Information sending method, information receiving method, communication node, and storage medium

Abstract

An information sending method, comprising: on the basis of the number of information bits in an information bit sequence, selecting, from at least two polynomials, a generator polynomial for performing CRC encoding on the information bit sequence, wherein the at least two polynomials correspond to different numbers of CRC bits; on the basis of the generator polynomial, performing CRC encoding on the information bit sequence, so as to obtain a CRC-encoded bit sequence; and sending the CRC-encoded bit sequence.

Description

Information transmission method, information reception method, communication node and storage medium TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, for example, to an information transmission method, an information reception method, a communication node and a storage medium. BACKGROUND

[0002] With the rapid development of big data, cloud computing, latency-sensitive network and other technologies, the number of user equipment in wireless communication networks is growing explosively, and wireless communication networks will carry diverse applications and massive data, which puts high requirements on data processing throughput, reliability, latency and the like. With the development of intelligent transportation, intelligent industrial control, intelligent logistics and the like, the communication requirements for ultra-low latency and ultra-high reliability are becoming more and more intense, that is, some large throughput data need to be transmitted and successfully received within a very short time.

[0003] In order to realize correct transmission of the information bit sequence, the sending end can add some redundant information in the information bit sequence, and the receiving end can detect whether the received data has an error code through the redundant information. The redundant information can be obtained by cyclic redundancy check (CRC) encoding. In CRC encoding, the redundant information is referred to as CRC check bits. The receiving end performs CRC check on the received data through the CRC check bits to detect whether the received data has an error code.

[0004] In the case that the communication system supports CRC check bits of different lengths, the false positive rate of CRC check of some length information bit sequences is high. SUMMARY

[0005] Embodiments of the present application provide an information transmission method applied to a first communication node, comprising:

[0006] selecting a generator polynomial for CRC encoding of the information bit sequence from at least two polynomials according to the number of information bits in the information bit sequence; wherein the at least two polynomials correspond to different numbers of CRC check bits;

[0007] performing CRC encoding on the information bit sequence according to the generator polynomial to obtain a CRC encoded bit sequence;

[0008] transmitting the CRC encoded bit sequence.

[0009] Embodiments of the present application provide an information reception method applied to a second communication node, comprising:

[0010] receiving a to-be-checked bit sequence;

[0011] selecting a generator polynomial for CRC decoding the to-be-verified bit sequence from at least two polynomials according to the number of information bits, wherein the at least two polynomials correspond to different numbers of CRC check bits;

[0012] performing CRC decoding on the to-be-verified bit sequence according to the generator polynomial to obtain an information bit sequence.

[0013] An embodiment of the present application provides a communication node, comprising: a processor; the processor is configured to implement the information sending method of any of the above embodiments or implement the information receiving method of any of the above embodiments when executing a computer program.

[0014] An embodiment of the present application further provides a computer readable storage medium storing a computer program, and the computer program is configured to implement the information sending method or the information receiving method of any of the above embodiments when executed by a processor. BRIEF DESCRIPTION OF DRAWINGS

[0015] FIG. 1 is a schematic diagram of an implementation environment for implementing an information sending method according to an embodiment of the present application;

[0016] FIG. 2 is a flowchart of an information sending method according to an embodiment of the present application;

[0017] FIG. 3 is a flowchart of another information sending method according to an embodiment of the present application;

[0018] FIG. 4 is a simulation diagram of a false alarm rate according to an embodiment of the present application;

[0019] FIG. 5 is a diagram of redundancy information overhead according to an embodiment of the present application;

[0020] FIG. 6 is a flowchart of an information receiving method according to an embodiment of the present application;

[0021] FIG. 7 is a diagram of a circuit corresponding to a first generator polynomial according to an embodiment of the present application;

[0022] FIG. 8 is a diagram of a circuit corresponding to a second generator polynomial according to an embodiment of the present application;

[0023] FIG. 9 is a structural diagram of an information sending device according to an embodiment of the present application;

[0024] FIG. 10 is a structural diagram of an information receiving device according to an embodiment of the present application;

[0025] FIG. 11 is a structural diagram of a communication node according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] It is to be understood that the specific embodiments described herein are merely exemplary and do not limit the application. The embodiments of the present application will be described in detail hereinafter with reference to the attached drawings.

[0027] In a wireless communication system, a transmitter encodes data to be transmitted by a channel coding method to obtain sub-coding blocks, and then maps the sub-coding blocks into constellation modulation symbols and transmits the constellation modulation symbols to a receiver. In a data processing channel, data processing errors can occur due to factors such as multipath, noise, and interference. The transmitter adds some redundant information to the data to be transmitted by channel coding, and the receiver can recover the original data to be transmitted by using the redundant information, that is, eliminate the distortion of the data in the transmission process. The receiver needs to perform channel decoding on the received constellation modulation symbols to recover the data to be transmitted. Channel coding methods can include Low Density Parity Check Code (LDPC) encoding, polar encoding, turbo encoding, convolutional encoding, and the like.

[0028] In addition to the need for channel coding, the receiver also needs some redundant information to determine whether the data after channel decoding is correct. The transmitter adds some redundant information to the information bit sequence, and the receiver can detect whether the received data has an error code by using the redundant information. If the received data is correct by using the redundant information, the receiver can continue the transmission of the next frame of data. If the received data itself is incorrect, but is judged to be correct by using the redundant information (that is, a false alarm occurs, or is called a false alarm), it will affect the communication of the entire system, and even need to be retransmitted by high-level data, which will inevitably bring a very large transmission delay.

[0029] In addition, although various channel coding methods can eliminate the distortion of the data in the transmission process, it is still relatively difficult to achieve a relatively low false alarm rate (False Alarm Rate, FAR) and a relatively small redundant overhead. In general, CRC check can be used to check the received data to determine whether it is correct.

[0030] It should be noted that the CRC check bits can be described in various ways. For example, a generator polynomial can be used for description, such as the generator polynomial of a CRC check code with 16 CRC check bits (i.e., the length of the redundant bits in the CRC check code is 16 bits) is g CRC16 (x)=x 16 +x 12 +x 5 +1. For another example, a register can be used for description, such as the generator polynomial of a CRC check code with 16 CRC check bits is described by a register as g CRC16 (D)=D16 +D 12 +D 5 +1, where "x" in the polynomial is replaced by "D" and the exponent of each term indicates the number of clocks (i.e., the number of shift registers) that need to be delayed. For example, a binary representation can be used. In a binary representation of a CRC generator polynomial, the first bit value (leftmost) corresponds to the coefficient of the highest power of the generator polynomial and the last bit value (rightmost) corresponds to the coefficient of the lowest power of the generator polynomial. For example, the CRC generator polynomial for the 16-bit CRC described above in binary is {1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1}. For example, a hexadecimal representation can be used. The CRC generator polynomial for the 16-bit CRC described above in hexadecimal is {1 1 0 2 1} or 0x11021. For example, a non-zero coefficient term power representation can be used. The CRC generator polynomial for the 16-bit CRC described above can be represented as {16, 12, 5, 0}. 16

[0031] The degree of a generator polynomial is represented as the power of the term with the highest power (i.e., the highest power) in the generator polynomial, g CRC16 (x) = x 16 +x 12 +x 5 +1. The degree of a generator polynomial is equal to the number of CRC check bits that the generator polynomial corresponds to. The order of the terms in a generator polynomial does not affect its description. For example, a generator polynomial can be written with the lower power terms first and then the higher power terms, g CRC16 (x) = x 16 +x 12 +x 5 +1, can be written as g CRC16 (x) = 1 + x 5 +x 12 +x 16 . Also, g CRC16 (D) = D 16 +D 12 +D 5 +1, can be written as g CRC16 (D) = 1 + D 5 + D 12 +D 16 .

[0032] ​FIG. 1 is a schematic diagram of an implementation environment for performing an information sending method according to an embodiment of the present application. As shown in FIG. 1, the implementation environment includes a base station 210, a plurality of types of user equipment (including 120, 130 and 140 in FIG. 1) and a core network 300. The plurality of types of user equipment (UE) can be Internet of Things (IoT) devices, which are used to collect a plurality of types of data and then send the collected data to the base station 210 after forward error correction encoding. The base station 210 communicates with the plurality of UEs and is connected to the core network 300. The core network 300 can provide access authorization, user authentication, Internet protocol connectivity, tracking and other access, routing or mobility management functions. The plurality of types of UEs can be distributed throughout the implementation environment, and each UE can be fixed or mobile. The plurality of types of UEs can communicate with a plurality of types of base stations 210 and network devices (including macro evolved Node Bs (eNBs), small cell eNBs and relay base stations, etc.).

[0033] It can be understood that application examples of the IoT devices include smart metering, inventory monitoring, water level monitoring, temperature monitoring, device monitoring, medical monitoring, wildlife monitoring, weather and geographical event monitoring, vehicle fleet management and tracking, remote security sensing, physical access control and transaction-based business charging, etc., which are not limited herein.

[0034] In an implementation, the base station 210 can include, but is not limited to, one of a base station (BS), a reader, an interrogator, an access point (AP), a node B, a g node B (generalized node B), a radio network controller (RNC), an evolved Node B (eNB), a base station controller (BSC), a base transceiver station (BTS), a transceiver function (TF), a radio router, a radio transceiver, a basic service set (BSS), an extended service set (ESS), or a radio base station (RBS). The implementation of the base station is not specifically limited in the present embodiment.

[0035] In an embodiment, a UE can be referred to as an access terminal, a tag, a passive tag, an ambient tag, a subscriber unit, a subscriber station, a mobile station, a mobile, a remote station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent, or a user device. For example, it can be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device with wireless communication function, a computing device, or other processing device connected to a wireless modem, an in-vehicle device, a wearable device, a terminal device in a 5th-Generation (5G) network or a future 6th-Generation (6G) network, etc. The embodiments are not limited to a specific implementation of a UE.

[0036] In an embodiment, the implementation environment for performing the information transmission method of the embodiments can be, but is not limited to, a network that can automatically adapt wireless communication devices, such as IoT. It can also be used in ambient IoT communication, in which the base station 210 in FIG. 1 corresponds to a reader, an interrogator, and various types of UEs correspond to tags (or labels), devices, or transponders. Data communication from the base station 210 to the UE is referred to as an R2D link or downlink, and data communication from the UE to the base station 210 is referred to as a D2R link or uplink. The information transmission method can be used for data communication of the R2D link or the D2R link. The transmitting end and the receiving end can be devices that communicate through IoT (e.g., machine type communication devices), and can include various types of sensors, water meters, electricity meters, product labels, article data labels, etc.

[0037] In some scenarios, the devices in the IoT need to store energy in a battery, but the battery has a small amount of power. These devices can have very low throughput or data volume applications, and require very little energy consumption to facilitate communication for a very long time without replacing the battery. In other scenarios, the devices in the IoT do not need to store energy in a battery, but directly transmit signals to the receiving end (for example, a base station) through backscattering. In the case of a tag (Tap) collecting energy and transmitting signals to the receiving end through backscattering, the device can be a passive IoT device at this time, which can be used in the licensed spectrum, for example, to send signals to a base station (for example, a node B or a G node B) of mobile communication, or to access an existing cellular mobile network.

[0038] In some scenarios, the IoT device can also communicate in the unlicensed spectrum. In some scenarios, the IoT device transmits data using an impedance network, and different data signals are indicated according to different impedance network parameters.

[0039] In the related art, when transmitting information in the implementation environment shown in FIG. 1, for example, transmitting data from a user equipment to a base station 210, CRC check bits can be generated by CRC encoding, and the CRC check bits are added to the information bit sequence and transmitted to the base station 210. After the base station 210 receives the data, the received data is CRC checked according to the CRC check bits. However, in the related art, the false positive rate of CRC checking of a partial length information bit sequence is high.

[0040] In an embodiment of the present application, an information sending method, an information receiving method, a communication node, and a storage medium are provided. The number of information bits in an information bit sequence can be used to select a generating polynomial for CRC encoding of the information bit sequence, and the information bit sequence is CRC encoded according to the generating polynomial to obtain a CRC encoded bit sequence, and the CRC encoded bit sequence is transmitted. The CRC encoding is based on a generating polynomial that matches the number of information bits in the information bit sequence, thereby reducing the false positive rate of data reception and increasing the robustness of data communication.

[0041] In the following, the information sending method, the information receiving method, the communication node, and the technical effects thereof are described.

[0042] FIG. 2 is a flow diagram of an information sending method according to an embodiment of the present application. The information sending method provided in the embodiment can be applied to a first communication node. The first communication node in the embodiment is a sending end. The first communication node in the embodiment can be a UE or a base station in FIG. 1, etc. As shown in FIG. 2, the information sending method provided in the embodiment includes the following operations.

[0043] 201: selecting a generator polynomial for CRC encoding of the information bit sequence from at least two polynomials according to a number of information bits in the information bit sequence.

[0044] The at least two polynomials correspond to different numbers of CRC check bits.

[0045] The information bit sequence in the embodiment refers to valid information to be sent, which is a bit sequence composed of at least one bit. The number of information bits in the embodiment refers to the number of bits included in the information bit sequence.

[0046] The at least two polynomials in the embodiment are polynomials for CRC encoding. The at least two polynomials correspond to different numbers of CRC check bits.

[0047] In an optional embodiment, the at least two polynomials in the embodiment include two generator polynomials, which are a first generator polynomial and a second generator polynomial. Among the two generator polynomials, the number of CRC check bits corresponding to the first generator polynomial is less than the number of CRC check bits corresponding to the second generator polynomial. Optionally, the number obtained by dividing the number of CRC check bits corresponding to the second generator polynomial by the number of CRC check bits corresponding to the first generator polynomial is greater than 2.

[0048] In an optional example, the number of CRC check bits corresponding to the first generator polynomial is equal to 6, and the number of CRC check bits corresponding to the second generator polynomial is equal to 16. In an optional example, the first generator polynomial with the number of CRC check bits equal to 6 is g CRC6 (D) = [D 6 + D 5 + 1]. The second generator polynomial with the number of CRC check bits equal to 16 is g CRC16 (D) = [D 16 + D 12 + D 5 + 1 ] . Alternatively, in another optional example, the second generator polynomial with the number of CRC check bits equal to 16 is g CRC16 (D) = [D 16 + D 11 + D 6 + D 5 + 1

[0049] In an optional example, the numbers of CRC check bits of the first generator polynomial and the second generator polynomial can be equal to any two different numbers of the following: 4, 5, 6, 8, 10, 11, 12, 14, 16, 18, 20, 24, 32.

[0050] In an optional example, the first generator polynomial corresponds to a CRC check bit number of 6, and the second generator polynomial corresponds to a CRC check bit number of 16; or, the first generator polynomial corresponds to a CRC check bit number of 5, and the second generator polynomial corresponds to a CRC check bit number of 16; or, the first generator polynomial corresponds to a CRC check bit number of 7, and the second generator polynomial corresponds to a CRC check bit number of 16.

[0051] In an optional example, the first generator polynomial corresponds to a CRC check bit number of 8, and the second generator polynomial corresponds to a CRC check bit number of 16; or, the first generator polynomial corresponds to a CRC check bit number of 5, and the second generator polynomial corresponds to a CRC check bit number of 10; or, the first generator polynomial corresponds to a CRC check bit number of 6, and the second generator polynomial corresponds to a CRC check bit number of 11.

[0052] In one implementation, in 201, if the number of information bits is less than or equal to a first threshold, the first generator polynomial is determined as a generator polynomial for CRC encoding the sequence of information bits. The first threshold can be an integer greater than 1. Exemplarily, the first generator polynomial can correspond to a CRC check bit number of 6, and the first generator polynomial can be g CRC6 (D) = [D 6 + D 5 + 1].

[0053] In an optional example, the first threshold is an integer greater than 0 and less than or equal to 2 L1 L1, where L1 is a CRC check bit number corresponding to the first generator polynomial. Exemplarily, L1 is equal to 6. In an optional example, the first threshold is an integer greater than 2 L1 - Δ and less than or equal to 2 L1 L1, where Δ is equal to 8 or 16. Exemplarily, the first threshold is one of 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 64.

[0054] In another optional example, the first threshold is an integer greater than 2 L1 and less than or equal to 2 L1 C', where C' is determined by a CRC check bit number L1 corresponding to the first generator polynomial and a CRC check bit number L2 corresponding to the second generator polynomial. In one example, Exemplarily, L1 can be equal to 6, and L2 can be equal to 16. Wherein, the operation formula represents the largest integer less than or equal to the real number x.

[0055] In an optional example, the first threshold is greater than or equal to 2 L1 • an integer of C'-Δ and less than or equal to 2 L1 • an integer of C', wherein Δ is equal to 16 or equal to 32. Exemplarily, L1 can be equal to 6 and L2 can be equal to 16. The first threshold is equal to one of: 114, 96, 98, 100, 102, 104, 106, 108, 110, 111, 112, 113, 115, 116, 117, 118, 120, 122, 124, 126, 128.

[0056] In yet another optional example, the first threshold is greater than 0 and less than or equal to 2 L1 • an integer of C'. In one example, Exemplarily, L1 can be equal to 6 and L2 can be equal to 16. In an optional example, the first threshold is greater than or equal to 2 L1 • an integer of C'-Δ and less than or equal to 2 L1 • an integer of C', wherein Δ is equal to 32 or equal to 16. The first threshold is equal to one of: 96, 98, 100, 102, 104, 106, 108, 110, 111, 112, 113, 114, 115, 116, 117, 118, 120, 122, 124, 126, 128.

[0057] It should be noted that the selection of the first threshold will affect the false positive rate. If the first threshold is too large, the first generator polynomial will be used to perform CRC encoding on the information bit sequence with a large number of information bits. It can be understood that in this scenario, the number of CRC check bits corresponding to the first generator polynomial is smaller compared to the number of information bits, which will cause the false positive rate to increase.

[0058] In another implementation, in 201, if the number of information bits is greater than or equal to a second threshold, a second generator polynomial is determined as the generator polynomial for performing CRC encoding on the information bit sequence. The second threshold is greater than or equal to the first threshold. Exemplarily, the number of CRC check bits corresponding to the second generator polynomial can be 16, and the second generator polynomial can be: CRC16 (D) = [D 16 + D 12 + D 5 + 1] or g CRC16 (D) = [D 16 + D 11 + D 6 + D 5 + 1].

[0059] In an optional example, the second threshold value is equal to one of: 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 64.

[0060] In another optional example, the second threshold value is equal to one of: 114, 96, 98, 100, 102, 104, 106, 108, 110, 111, 112, 113, 115, 116, 117, 118, 120, 122, 124, 126, 128.

[0061] It should be noted that the selection of the second threshold value will affect the redundancy overhead. If the second threshold value is too small, the second generator polynomial will be used to perform CRC encoding on the information bit sequence with a smaller number of information bits. It can be understood that in this scenario, the number of CRC check bits corresponding to the second generator polynomial is larger compared to the number of information bits, which will result in a larger redundancy overhead.

[0062] If the first threshold value and the second threshold value are equal, the selection of the first threshold value and the second threshold value will simultaneously affect the use of the first generator polynomial and the second generator polynomial, i.e., simultaneously affect the false positive rate and the redundancy overhead.

[0063] In yet another implementation, in 201, if the number of information bits is less than or equal to a third threshold value, it is determined that the number of CRC check bits corresponding to the generator polynomial used to perform CRC encoding on the information bit sequence is equal to 0. The third threshold value is smaller than the first threshold value.

[0064] In this embodiment, the number of CRC check bits equal to 0 corresponds to no cyclic redundancy encoding.

[0065] In an optional example, the third threshold value is equal to one of: 11, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18.

[0066] In yet another implementation, if the second threshold value is greater than the first threshold value, in 201, if the number of information bits is greater than the first threshold value and smaller than the second threshold value, the second generator polynomial is determined as the generator polynomial used to perform CRC encoding on the information bit sequence, or the first generator polynomial is determined as the generator polynomial used to perform CRC encoding on the information bit sequence.

[0067] It can be seen that in 201, the generator polynomial matching the number of information bits of the information bit sequence is determined according to the number of information bits of the information bit sequence.

[0068] 202: Perform CRC encoding on the information bit sequence according to the generator polynomial to obtain a CRC encoded bit sequence.

[0069] In 202, the information bit sequence is CRC encoded according to the determined generation polynomial to obtain a CRC encoded bit sequence. The encoding process is similar to the CRC encoding process in the related art, and thus is not described herein.

[0070] It can be understood that the CRC encoded bit sequence includes the information bit sequence and the CRC check bits.

[0071] 203: transmitting the CRC encoded bit sequence.

[0072] The CRC encoded bit sequence is transmitted in 203. For example, the CRC encoded bit sequence can be transmitted to a second communication node.

[0073] The information transmission method provided in this embodiment selects a generation polynomial for CRC encoding of the information bit sequence according to the number of information bits in the information bit sequence, and then performs CRC encoding of the information bit sequence according to the generation polynomial to obtain a CRC encoded bit sequence, and transmits the CRC encoded bit sequence. Thus, the false positive rate of data reception is reduced, and the robustness of data communication is increased.

[0074] FIG. 3 is a flowchart of another information transmission method provided in an embodiment of the present application. This embodiment describes in detail how to perform CRC encoding of an information bit sequence according to a generation polynomial to obtain a CRC encoded bit sequence, based on the embodiment shown in FIG. 2 and various optional implementation manners. As shown in FIG. 3, the information transmission method provided in this embodiment includes the following operations.

[0075] 301: selecting a generation polynomial for CRC encoding of an information bit sequence from at least two polynomials according to the number of information bits in the information bit sequence.

[0076] The at least two polynomials correspond to different numbers of CRC check bits.

[0077] The implementation process and technical principles of 301 are similar to those of 201, and thus are not described herein.

[0078] 302: segmenting the information bit sequence to obtain C information bit subsequences.

[0079] C is an integer greater than 0.

[0080] For example, C is equal to 2.

[0081] In an implementation manner, the information bit sequence can be segmented according to a preset number C of information bit subsequences to obtain C information bit subsequences.

[0082] In another implementation, the information bit sequence can be segmented according to the number of information bits in the information bit sequence to obtain the C information bit subsequences.

[0083] In another implementation, the information bit sequence can be segmented according to the segmentation rule indicated in the control signaling to obtain the C information bit subsequences.

[0084] In another implementation, the information bit sequence can be segmented according to the CRC encoding maximum information length, which is a positive integer.

[0085] Optionally, in the embodiment, C is any positive integer less than or equal to the number obtained by dividing the number of CRC check bits corresponding to the second generator polynomial by the number of CRC check bits corresponding to the first generator polynomial. For example, assuming that the number obtained by dividing the number of CRC check bits corresponding to the second generator polynomial by the number of CRC check bits corresponding to the first generator polynomial is 2.7, C is any positive integer less than or equal to 2.7, that is, C is 1 or C is 2.

[0086] Optionally, the implementation process of 302 can be: if the number of information bits is less than or equal to the first threshold and greater than the third threshold, segmenting the information bit sequence to obtain the C information bit subsequences.

[0087] Optionally, the implementation process of 302 can be: if the number of information bits is greater than the first threshold and less than the second threshold, segmenting the information bit sequence to obtain the C information bit subsequences.

[0088] In an optional example, the CRC encoding maximum information length is an integer greater than 0 and less than or equal to 2 L1 L1, where L1 is the number of CRC check bits corresponding to the first generator polynomial. In an optional example, the CRC encoding maximum information length takes a value of an integer greater than or equal to 2 L1 -Δ and less than or equal to 2 L1 , where Δ is equal to 8 or 16. In an optional example, the CRC encoding maximum information length takes a value of one of the following: 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 64.

[0089] In another optional example, the CRC encoding maximum information length is determined by the number of information bits. Optionally, if the number of information bits is less than or equal to a first threshold, the CRC encoding maximum information length is Kmax1. Where Kmax1 is a positive integer. If the number of information bits is greater than or equal to a second threshold, the CRC encoding maximum information length is Kmax2. Where Kmax2 is a positive integer, and Kmax2 is greater than Kmax1. The second threshold is an integer greater than or equal to the first threshold.

[0090] In another optional example, the first threshold is equal to E times Kmax1, where E is a positive integer.

[0091] Optionally, the E is a maximum integer less than or equal to a value obtained by dividing the number of CRC check bits corresponding to the second generator polynomial by the number of CRC check bits corresponding to the first generator polynomial. The E is equal to floor(L2 / L1), where L1 is the number of CRC check bits corresponding to the first generator polynomial, L2 is the number of CRC check bits corresponding to the second generator polynomial, and the formula floor(x) represents the integer part of a real number x, or rounding down a real number x, or taking a maximum integer less than or equal to a real number x.

[0092] In another optional example, the Kmax2 is equal to a preset maximum number of information bits.

[0093] Optionally, the first threshold in the embodiment is greater than 2 L1 and less than or equal to 2 L1 times the number of CRC check bits corresponding to the first generator polynomial and the number of CRC check bits corresponding to the second generator polynomial.

[0094] Optionally, the maximum value of C is equal to C'.

[0095] 303: According to the generator polynomial, the C information bit subsequences are respectively CRC encoded to obtain C CRC encoded bit subsequences.

[0096] In 303, according to the generator polynomial determined in 301, the C information bit subsequences are respectively CRC encoded to obtain C CRC encoded bit subsequences.

[0097] 304: The C CRC encoded bit subsequences are combined to obtain a CRC encoded bit sequence.

[0098] In 304, the C CRC encoded bit subsequences can be combined according to the segmentation order to obtain a CRC encoded bit sequence.

[0099] 305: transmit the CRC encoded bit sequence.

[0100] The implementation process of 305 is similar to that of 203, and thus is not described herein.

[0101] The information sending method provided in this embodiment can implement segmentation of an information bit sequence, obtain C information bit subsequences, perform CRC encoding on the C information bit subsequences respectively according to a generation polynomial, obtain C CRC encoded bit subsequences, and combine the C CRC encoded bit subsequences to obtain a CRC encoded bit sequence, thereby improving the CRC encoding efficiency and further improving the communication efficiency.

[0102] The information sending method provided in this embodiment is described below through several examples.

[0103] Example 1

[0104] In this example, the at least two polynomials include a first generation polynomial and a second generation polynomial. The CRC check bit numbers corresponding to the two generation polynomials are equal to 6 and 16. In an optional example, the first generation polynomial with the CRC check bit number equal to 6 is g CRC6 (D) = [D 6 + D 5 + 1]. The second generation polynomial with the CRC check bit number equal to 16 is g CRC16 (D) = [D 16 + D 12 + D 5 + 1].

[0105] In this example, the implementation of 201 is as follows: if the information bit number is less than or equal to a first threshold, the first generation polynomial is determined as the generation polynomial for CRC encoding of the information bit sequence. The value of the first threshold is 57.

[0106] In this example, the information bit number K = 48. The generation polynomial for CRC encoding is determined according to the information bit number. Since the information bit number K = 48 is less than the first threshold (57), the generation polynomial for cyclic redundancy check encoding is g CRC6 (D) = [D 6 + D 5 + 1].

[0107] The information bit sequence is set as a0, a1, a2, …, a K-1 , where K = 48. The information bit sequence a0, a1, a2, …, a K-1 is subjected to cyclic redundancy check encoding, and the corresponding CRC check bit number is equal to 6. The CRC check bits are p0, p1, p2, …, p L-1where L = 6. The information bit sequence a0, a1, a2, …, a K-1 and the CRC check bits p0, p1, p2, …, p L-1 The CRC encoded bit sequence can be obtained by concatenating the information bit sequence and the CRC check bit sequence, and the total length is 48 + 6 = 54 bits.

[0108] Fig. 4 is a simulation diagram of the false alarm rate according to an embodiment of the present application. As shown in Fig. 4, it shows the FAR performance of the first generator polynomial with CRC check bit number equal to 6 (denoted as CRC6 in Fig. 4). In Fig. 4, the horizontal axis corresponds to the block error rate (BLER), and the vertical axis corresponds to the false alarm rate (FAR). At the same block error rate, the smaller the false alarm rate is, the better. In Fig. 4, the FAR performance of the first generator polynomial with CRC check bit number equal to 6 is given when the information bit number is equal to 52 (denoted as K52 in Fig. 4), 56 (denoted as K56 in Fig. 4), 57 (denoted as K57 in Fig. 4), 58 (denoted as K58 in Fig. 4), 59 (denoted as K59 in Fig. 4), and 60 (denoted as K60 in Fig. 4), respectively. It can be seen that when the information bit number K is equal to 52, 56, and 57, respectively, the FAR performance is basically the same, and when the information bit number K is greater than 57, the FAR performance gradually deteriorates. Therefore, when the first threshold is equal to 57, the beneficial effect is that when the information bit number K is less than or equal to 57, the receiving end can have a lower false alarm rate, effectively preventing the spread of errors, and the robustness of the communication system can be enhanced.

[0109] In the present example, in 203, the CRC encoded bit sequence can be transmitted to the receiving end by directly modulating the CRC encoded bit sequence. Alternatively, the CRC encoded bit sequence can be channel encoded, and then modulated and transmitted to the receiving end, where the channel encoding method can be convolutional encoding, polar encoding, low-density parity check encoding, Turbo encoding, line coding, or a concatenated code of convolutional encoding and line coding, and the line coding can be Manchester coding, Bi-Phase Space (FM0) coding, or Miller coding.

[0110] In some other examples, the first threshold can also be equal to other values, for example, the first threshold can be equal to 56, and when the information bit number is less than or equal to 56, the CRC check bit number corresponding to the generator polynomial of the cyclic redundancy check encoding is equal to 6, i.e., the generator polynomial g CRC6 (D) = [D 6 + D 5+1] to perform the cyclic redundancy check encoding. Alternatively, the first threshold value can be equal to 55. Alternatively, the first threshold value can be equal to 54. Alternatively, the first threshold value can be equal to 53. Alternatively, the first threshold value can be equal to 52. Alternatively, the first threshold value can be equal to 51. Alternatively, the first threshold value can be equal to 50. Alternatively, the first threshold value can be equal to 49. Alternatively, the first threshold value can be equal to 48. Alternatively, the first threshold value can be equal to 58. Alternatively, the first threshold value can be equal to 59. Alternatively, the first threshold value can be equal to 60. Alternatively, the first threshold value can be equal to 61. Alternatively, the first threshold value can be equal to 62. Alternatively, the first threshold value can be equal to 63. Alternatively, the first threshold value can be equal to 64.

[0111] Example 2

[0112] The difference between this example and Example 1 is that the cyclic redundancy check encoding is performed using a generator polynomial with CRC check bit number equal to 16.

[0113] In this example, the at least two generator polynomials include a first generator polynomial and a second generator polynomial. The CRC check bit numbers corresponding to the two generator polynomials are equal to 6 and 16. In an optional example, the first generator polynomial with CRC check bit number equal to 6 is: CRC6 (D) = [D 6 + D 5 + 1]. The second generator polynomial with CRC check bit number equal to 16 is: CRC16 (D) = [D 16 + D 12 + D 5 + 1].

[0114] In this example, 201 is implemented as follows: if the information bit number is greater than or equal to a second threshold value, the second generator polynomial is determined as the generator polynomial for CRC encoding of the information bit sequence. The second threshold value is greater than or equal to the first threshold value. The second threshold value is equal to 57.

[0115] Based on the FAR performance simulation of the first generator polynomial with CRC check bit number equal to 6 shown in FIG. 4, it can be seen that when the information bit number is greater than 57, the FAR performance of the first generator polynomial deteriorates. At this time, if the cyclic redundancy encoding is still performed using the first generator polynomial, a large false alarm rate will occur at the receiving end. Therefore, when the information bit number is greater than 57, the generator polynomial for cyclic redundancy encoding needs to be switched to the second generator polynomial with CRC check bit number equal to 16, so as to improve the false alarm rate at the receiving end and enhance the stability and robustness of the communication system.

[0116] In this example, the number of information bits is equal to K = 96. The generator polynomial of the cyclic redundancy check coding is determined according to the number of information bits, and since the number of information bits K = 96 is greater than the second threshold value (57), the generator polynomial of the cyclic redundancy check coding is g CRC16 (D) = [D 16 + D 12 + D 5 + 1].

[0117] The information bit sequence is set to a0, a1, a2, …, a K-1 , where K = 96. The information bit sequence a0, a1, a2, …, a K-1 is cyclic redundancy check coded, and the corresponding number of CRC check bits is equal to 16. The CRC check bits are p0, p1, p2, …, p L-1 , where L = 16. The information bit sequence a0, a1, a2, …, a K-1 and the CRC check bits p0, p1, p2, …, p L-1 are concatenated to obtain a CRC-encoded bit sequence, and the total length is 96 + 16 = 112 bits.

[0118] In some other examples, the second threshold value can be equal to 64, and when the number of information bits is greater than or equal to 64, the number of CRC check bits corresponding to the generator polynomial of the cyclic redundancy check coding is equal to 16, that is, the generator polynomial g CRC16 (D) = [D 16 + D 12 + D 5 + 1] is used for cyclic redundancy check coding. Alternatively, the second threshold value can be equal to 55. Alternatively, the second threshold value can be equal to 54. Alternatively, the second threshold value can be equal to 53. Alternatively, the second threshold value can be equal to 52. Alternatively, the second threshold value can be equal to 51. Alternatively, the second threshold value can be equal to 50. Alternatively, the second threshold value can be equal to 49. Alternatively, the second threshold value can be equal to 48. Alternatively, the second threshold value can be equal to 58. Alternatively, the second threshold value can be equal to 59. Alternatively, the second threshold value can be equal to 60. Alternatively, the second threshold value can be equal to 61. Alternatively, the second threshold value can be equal to 62. Alternatively, the second threshold value can be equal to 63. Alternatively, the second threshold value can be equal to 64.

[0119] Example 3

[0120] The difference between this example and Example 1 is that the number of CRC check bits is equal to 0, that is, no cyclic redundancy check coding is performed.

[0121] In this example, the at least two polynomials include a first generator polynomial and a second generator polynomial. The CRC check bit numbers corresponding to the two generator polynomials are equal to 6 and 16. In an optional example, the first generator polynomial with the CRC check bit number equal to 6 is: CRC6 (D) = [D 6 + D 5 + 1]. The second generator polynomial with the CRC check bit number equal to 16 is: CRC16 (D) = [D 16 + D 12 + D 5 + 1].

[0122] In this example, the implementation of 201 is: if the information bit number is less than or equal to a third threshold, it is determined that the CRC check bit number corresponding to the generator polynomial for CRC encoding of the information bit sequence is equal to 0. The third threshold is equal to 14.

[0123] In this example, the information bit number is equal to K = 8. According to the information bit number, the generator polynomial for cyclic redundancy check encoding is determined. Since the information bit number K = 8 is less than the third threshold (14), the CRC check bit number for cyclic redundancy check encoding is equal to 0, i.e., corresponding to no cyclic redundancy check encoding. Since the proportion of CRC check bits (6 bits) is high in the case of a small number of information bits, the redundancy overhead of communication is greatly increased, which can lead to the occupation of more resources for transmitting CRC check bits. In the case of a small number of information bits, no cyclic redundancy check encoding (i.e., the CRC check bit number is equal to 0) can greatly reduce the communication overhead, and if the resource or energy is the same, a larger reception gain can be obtained, thereby improving the transmission reliability of the communication system.

[0124] The information bit sequence is set to a0, a1, a2,..., a K-1 , where K = 8. The information bit sequence a0, a1, a2,..., a K-1 is cyclic redundancy check encoded, and the corresponding CRC check bit number is equal to 0, i.e., the bit sequence after CRC encoding is the same as the information bit sequence, and the total length is 8 + 0 = 8 bits.

[0125] When the third threshold is equal to 14, i.e., the information bit number is less than or equal to 14, no cyclic redundancy check encoding is needed, and the shortest information bit number for cyclic redundancy check encoding using the first generator polynomial with the CRC check bit number equal to 6 is equal to 15. At this time, the maximum redundancy overhead is 6 / 15 = 40%, which also means that the maximum redundancy overhead of the communication system is 40%, so that the redundancy overhead is within a normal and reasonable range, thereby avoiding the waste of transmission resources and improving the information transmission efficiency.

[0126] In another example, the third threshold value is equal to 11, the minimum number of information bits encoded by cyclic redundancy check coding with the first generator polynomial with the number of CRC check bits equal to 6 is equal to 12, and the maximum redundancy overhead is 6 / 12=50%, which is moderate.

[0127] In some examples, the third threshold value can be equal to 16. Alternatively, the third threshold value can be equal to 15. Alternatively, the third threshold value can be equal to 11. Alternatively, the third threshold value can be equal to 13. Alternatively, the third threshold value can be equal to 12. Alternatively, the third threshold value can be equal to 10. Alternatively, the third threshold value can be equal to 9. Alternatively, the third threshold value can be equal to 8. Alternatively, the third threshold value can be equal to 7. Alternatively, the third threshold value can be equal to 6. Alternatively, the third threshold value can be equal to 5. Alternatively, the third threshold value can be equal to 17. Alternatively, the third threshold value can be equal to 18.

[0128] Example 4

[0129] This example implements information sending in the application scenarios of examples 1 to 3.

[0130] In this example, the at least two generator polynomials include a first generator polynomial and a second generator polynomial. The number of CRC check bits corresponding to the two generator polynomials is equal to 6 and 16. In an optional example, the first generator polynomial with the number of CRC check bits equal to 6 is g CRC6 (D) = [D 6 + D 5 + 1]. The second generator polynomial with the number of CRC check bits equal to 16 is g CRC16 (D) = [D 16 + D 12 + D 5 + 1].

[0131] In this example, the implementation of 201 is as follows: if the number of information bits is less than or equal to the third threshold value, the number of CRC check bits corresponding to the generator polynomial used for CRC encoding of the information bit sequence is determined to be equal to 0. The number of CRC check bits equal to 0 corresponds to no CRC encoding. In this example, the value of the third threshold value is 14.

[0132] In this example, the implementation of 201 can also be as follows: if the number of information bits is greater than the third threshold value and less than or equal to the first threshold value, the first generator polynomial is determined as the generator polynomial used for CRC encoding of the information bit sequence. In this example, the value of the first threshold value is 57.

[0133] In this example, the implementation of 201 can also be: if the number of information bits is greater than or equal to the second threshold, the second generator polynomial is determined as the generator polynomial for CRC encoding the information bit sequence. Wherein the second threshold is greater than or equal to the first threshold. Wherein the value of the second threshold is 57. That is, in this example, the second threshold is equal to the first threshold.

[0134] In an optional example, the information bit sequence is set as a0, a1, a2,..., a K-1 . Wherein if K = 6, since K is less than the third threshold (14), the corresponding number of CRC check bits is equal to 0, and the CRC encoded bit sequence obtained by performing cyclic redundancy check encoding on the information bit sequence a0, a1, a2,..., a K-1 is the same as the information bit sequence, and the total length is 6 + 0 = 6 bits.

[0135] If K = 40, since K is greater than the third threshold (14) and less than or equal to the first threshold (57), the corresponding number of CRC check bits is equal to 6, and the CRC check bits obtained by performing cyclic redundancy check encoding on the information bit sequence a0, a1, a2,..., a K-1 using the generator polynomial g CRC6 (D) = [D 6 + D 5 + 1] are p0, p1, p2,..., p L-1 , L = 6. Concatenating the information bit sequence a0, a1, a2,..., a K-1 and the CRC check bits p0, p1, p2,..., p L-1 can obtain the CRC encoded bit sequence, and the total length is 40 + 6 = 46 bits.

[0136] If K = 512, since K is greater than the second threshold (57), the corresponding number of CRC check bits is equal to 16, and the CRC check bits obtained by performing cyclic redundancy check encoding on the information bit sequence a0, a1, a2,..., a K-1 using the generator polynomial g CRC16 (D) = [D 16 + D 12 + D 5 + 1] are p0, p1, p2,..., p L-1 , L = 16. Concatenating the information bit sequence a0, a1, a2,..., a K-1 and the CRC check bits p0, p1, p2,..., p L-1 can obtain the CRC encoded bit sequence, and the total length is 512 + 16 = 528 bits.

[0137] In some other examples, the first threshold value can be set as in example 1; the second threshold value can be set as in example 2; and the third threshold value can be set as in example 3.

[0138] Example 5

[0139] The difference between this example and example 4 is that the values of the first threshold value, the second threshold value and the third threshold value are different.

[0140] In this example, the value of the third threshold value can be equal to 11, the value of the first threshold value can be equal to 114, and the value of the second threshold value can be equal to 114, i.e. the second threshold value is equal to the first threshold value. In an optional example, the information bit sequence is set as a0, a1, a2,..., a K-1 , the number of CRC check bits is L, K is a positive integer, and L is a non-negative integer. In one optional example, K = 4, at this time K is less than the third threshold value (11), so L is equal to 0, and the CRC check encoding is directly performed on the information bit sequence a0, a1, a2,..., a K-1 to obtain the CRC encoded bit sequence. If K = 88, at this time K is greater than the third threshold value (11) and less than or equal to the first threshold value (114), then L is equal to 6, and the information bit sequence a0, a1, a2,..., a CRC6 is cyclic redundancy check encoded by using the generator polynomial g 6 (D) = [D 5 + D K-1 + 1]. CRC16 If K = 1024, at this time K is greater than the second threshold value (114), then L is equal to 16, and the information bit sequence a0, a1, a2,..., a 16 is cyclic redundancy check encoded by using the generator polynomial g 12 (D) = [D 5 + D K-1 + D CRC6 + 1].

[0141] In some other examples, in the implementation of 201, if the number of information bits is less than or equal to the third threshold value, then L is equal to 0, and no cyclic redundancy check encoding is needed, i.e. the generator polynomial thereof can be considered as a generator polynomial with all zero coefficients; otherwise, if the number of information bits is less than or equal to the first threshold value, then L is equal to 6, and the generator polynomial for cyclic redundancy check encoding is g 6 (D) = [D 5 + D CRC16 + 1]; otherwise, if the number of information bits is greater than the second threshold value, then L is equal to 16, and the generator polynomial for cyclic redundancy check encoding is g 16 (D) = [D + D + D + D + 1].12 +D 5 +1]。

[0142] The first threshold value can be equal to 113. Alternatively, the first threshold value can be equal to 112. Alternatively, the first threshold value can be equal to 111. Alternatively, the first threshold value can be equal to 110. Alternatively, the first threshold value can be equal to 115. Alternatively, the first threshold value can be equal to 116. Alternatively, the first threshold value can be equal to 117. Alternatively, the first threshold value can be equal to 118. Alternatively, the first threshold value can be equal to 108. Alternatively, the first threshold value can be equal to 120. Alternatively, the first threshold value can be equal to 106. Alternatively, the first threshold value can be equal to 122. Alternatively, the first threshold value can be equal to 104. Alternatively, the first threshold value can be equal to 124. Alternatively, the first threshold value can be equal to 102. Alternatively, the first threshold value can be equal to 126. Other values of the third threshold value can refer to Example 3.

[0143] Example 6

[0144] The difference between this example and Examples 1 to 5 is that, when performing CRC encoding, the information bit sequence is segmented to obtain C information bit subsequences, the C information bit subsequences are respectively subjected to CRC encoding according to a generation polynomial to obtain C CRC-encoded bit subsequences, and the C CRC-encoded bit subsequences are combined to obtain a CRC-encoded bit sequence.

[0145] In this example, a first generation polynomial with a CRC check bit number equal to 6 is used for cyclic redundancy check encoding, where the first generation polynomial is: CRC6 (D) = [D 6 +D 5 +1]。

[0146] In this example, the information bit sequence is segmented according to a CRC encoding maximum information length.

[0147] In an optional example, the CRC encoding maximum information length is set as Kmax, the information bit number is set as K, and the number of information bit subsequences is calculated according to the following formula: Wherein, the operation formula represents the smallest integer greater than or equal to the real number x.

[0148] In an optional example, the bit number of the 0th to (g-1)th information bit subsequences is G+1, and the bit number of the gth to (C-1)th information bit subsequences is G. Wherein, g = mod(K, G), where mod(K, G) represents the remainder obtained by dividing K by G. It should be noted that if g = 0, it means that the number of bits of all information bit subsequences is G.

[0149] In an optional example, the CRC encoding maximum information length is equal to 57. In an optional example, the number of bits of the information bit sequence is less than or equal to a first threshold, where the first threshold is equal to 114. In this example, the first threshold is E times the CRC encoding maximum information length Kmax, where E is equal to 2. In an optional example, the number of bits of the information bit sequence is greater than a third threshold, where the third threshold is equal to 11.

[0150] FIG. 5 is a diagram of redundancy information overhead according to an embodiment of the present application. FIG. 5 shows redundancy information overheads in cases of using the first generator polynomial and the second generator polynomial, respectively. The right graph in FIG. 5 is an enlarged view of the dashed area in the left graph. In FIG. 5, the horizontal axis corresponds to the number of information bits K, and the vertical axis corresponds to the overhead of CRC check bits (indicated as overhead in the graph). The overhead of CRC check bits in this embodiment refers to the ratio of the number of CRC check bits to the number of information bits. In general, the smaller the overhead, the better, i.e., the closer the curve in the graph to the lower boundary, the smaller the overhead.

[0151] Kmax in FIG. 5 represents the CRC encoding maximum information length. When the number of CRC check bits is 6, Kmax is 57. When the number of CRC check bits is 16, Kmax is 1024. It can be understood that when CRC6 is used for encoding, the information bit sequence is segmented and encoded (i.e., encoded using the manner of 302 to 304) when the horizontal axis is greater than 57. The value of C and the number of bits of each information bit subsequence are as shown above. When the second generator polynomial with the number of CRC check bits equal to 16 (indicated as CRC16 in FIG. 5) is used for encoding, the information bit sequence is segmented and encoded when the horizontal axis is greater than 1024.

[0152] As can be seen from the right graph in FIG. 5, compared with CRC encoding using CRC16, when the number of information bits is less than or equal to 114, after the information bit sequence is segmented, CRC encoding is performed on the information bit subsequences using the first generator polynomial with the number of CRC check bits equal to 6, which has a lower overhead.

[0153] In an optional example, the information bit sequence is set to a0, a1, a2,..., a K-1 When K = 108, K is greater than the third threshold (11), the corresponding number of CRC check bits is equal to L = 6, and the corresponding generator polynomial of CRC is g CRC6(D) = [D 6 + D 5 + 1]. The information bit sequence is segmented according to the CRC encoding maximum information length Kmax=57 to obtain C=2 information bit subsequences, and the lengths of the 2 information bit subsequences are both equal to 54. Then the C=2 information bit subsequences are respectively subjected to cyclic redundancy check encoding using the generator polynomial g CRC6 (D) = [D 6 + D 5 + 1] to obtain C CRC-encoded bit subsequences, and the lengths of the C CRC-encoded bit subsequences are respectively 60 bits. Finally, the combination of the C=2 CRC-encoded bit subsequences is used to form a CRC-encoded bit sequence, and the length of the CRC-encoded bit sequence is 120 bits.

[0154] In this example, the CRC-encoded bit sequence is transmitted by performing 305 in the following manner: the CRC-encoded bit sequence can be directly subjected to On-Off Keying (OOK) modulation or Binary Phase Shift Keying (BPSK) modulation to obtain a modulation symbol sequence. Then the modulation symbol sequence is transmitted to the receiving end. Alternatively, the CRC-encoded bit sequence is subjected to Manchester encoding, FM0 encoding or Miller encoding to obtain an encoded bit sequence, and then the encoded bit sequence is subjected to OOK modulation or BPSK modulation to obtain a modulation symbol sequence, and then the modulation symbol sequence is transmitted to the receiving end. Alternatively, the CRC-encoded bit sequence is subjected to convolutional encoding to obtain a convolutional encoded bit sequence, and then the convolutional encoded bit sequence is subjected to Manchester encoding, FM0 encoding or Miller encoding to obtain an encoded bit sequence, and then the encoded bit sequence is subjected to OOK modulation or BPSK modulation to obtain a modulation symbol sequence, and then the modulation symbol sequence is transmitted to the receiving end.

[0155] In this example, the first threshold is equal to one of the following: 114, 113, 112, 111, 110, 115, 116, 117, 118, 108, 120, 106, 122, 104, 124, 102, 126, 100, 96. The third threshold in this example is equal to one of the following: 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5.

[0156] Example 7

[0157] In this example, the at least two polynomials include a first generator polynomial and a second generator polynomial. The CRC check bit numbers corresponding to the 2 generator polynomials are equal to 6 and 16. In an optional example, the first generator polynomial with a CRC check bit number equal to 6 is g CRC6 (D) = [D6 +D 5 +1]. The second generator polynomial with 16 CRC check bits is: g CRC16 (D)=[D 16 +D 12 +D 5 +1].

[0158] In this example, the implementation process of 201 includes: if the number of information bits is less than or equal to the third threshold, then the number of CRC check bits corresponding to the generator polynomial used for CRC encoding of the information bit sequence is determined to be 0. In this example, the value of the third threshold is 11.

[0159] In this example, the implementation process of 201 may further include: if the number of information bits is greater than a third threshold and less than or equal to a first threshold, then the first generator polynomial is determined as the generator polynomial for CRC encoding of the information bit sequence. The first threshold is set to 114. In this case, a generator polynomial g with a CRC check bit count of 6 is used. CRC6 (D)=[D 6 +D 5 +1] When performing cyclic redundancy check encoding, the process shown in Example 6 is used for CRC encoding, that is: the information bit sequence is divided according to the maximum information length of CRC encoding to obtain C information bit subsequences, and CRC encoding is performed on the C information bit subsequences according to the generator polynomial (the first generator polynomial in this example) to obtain C CRC encoded bit subsequences. The C CRC encoded bit subsequences are combined to obtain the CRC encoded bit sequence.

[0160] The maximum information length of this CRC encoding is set to Kmax, and the number of information bits is set to K. The number of information bit subsequences is calculated using the following formula: In an optional example, the number of bits in the information bit subsequence from 0 to g-1 is G+1, and the number of bits in the information bit subsequence from g to C-1 is G. g = mod(K, G). In an optional example, the maximum information length of the CRC encoding is set to Kmax, which is equal to 57.

[0161] In this example, the implementation process of 201 may further include: if the number of information bits is greater than or equal to a second threshold, then the second generator polynomial is determined as the generator polynomial for CRC encoding of the information bit sequence. The second threshold is greater than or equal to the first threshold. In this example, the second threshold is 114.

[0162] In an optional example, the information bit sequence is set to a0, a1, a2, ..., a K-1If K=6, since K is less than the third threshold value (11), the corresponding number of CRC check bits is equal to 0. The information bit sequence a0, a1, a2,..., a K-1 The CRC encoded bit sequence obtained by performing cyclic redundancy check encoding is the same as the information bit sequence, and the total length is 6+0=6 bits.

[0163] If K=112, since K is greater than the third threshold value (11) and less than or equal to the first threshold value (114), the corresponding number of CRC check bits is equal to 6. The information bit sequence a0, a1, a2,..., a K-1 is first segmented according to the maximum information length (Kmax=57) of CRC encoding to obtain C=2 information bit subsequences, the lengths of which are equal to 56 respectively. The 0th information bit subsequence is equal to a0, a1, a2,..., a 55 The 1st information bit subsequence is equal to a 56 , 57 , 58 , 111 Then, the C=2 information bit subsequences are respectively subjected to cyclic redundancy check encoding to obtain C=2 CRC encoded bit subsequences, the lengths of which are 62 bits respectively. The combination of the C=2 CRC encoded bit subsequences constitutes the CRC encoded bit sequence, the length of which is 124 bits. Among them, the cyclic redundancy check encoding (using the generator polynomial g CRC6 (D)=[D 6 +D 5 +1]) obtains CRC check bits p0, p1, p2,..., p L-1 , and L=6.

[0164] If K=800, since K is greater than the second threshold value (114), the corresponding number of CRC check bits is equal to 16. The information bit sequence a0, a1, a2,..., a K-1 is subjected to cyclic redundancy check encoding (using the generator polynomial g CRC16 (D)=[D 16 +D 12 +D 5 +1]) to obtain CRC check bits p0, p1, p2,..., p L-1 , and L=16. The information bit sequence a0, a1, a2,..., a K-1 and the CRC check bits p0, p1, p2,..., p L-1 are concatenated to obtain a CRC encoded bit sequence, the total length of which is 800+16=816 bits.

[0165] In some other examples, other values of the first threshold can refer to Example 5; and other values of the third threshold can refer to Example 3.

[0166] Example 8

[0167] This example is different from Example 6 and Example 7 in that code block segmentation is performed on all information bit sequences, and the CRC encoding maximum information length is determined by the number of information bits.

[0168] In this example, when performing CRC encoding, the information bit sequence is segmented according to the CRC encoding maximum information length to obtain C information bit subsequences, the C information bit subsequences are respectively CRC encoded according to the generator polynomial to obtain C CRC encoded bit subsequences, and the C CRC encoded bit subsequences are combined to obtain a CRC encoded bit sequence.

[0169] In an optional example, the CRC encoding maximum information length is determined by the number of information bits. For example, if the number of information bits is less than or equal to a first threshold, the CRC encoding maximum information length is equal to Kmax1; and if the number of information bits is greater than or equal to a second threshold, the CRC encoding maximum information length is Kmax2. Wherein, Kmax2 is greater than Kmax1. The second threshold is an integer greater than or equal to the first threshold.

[0170] In an optional example, the Kmax1 is an integer greater than 0, and the Kmax1 is less than or equal to 2L1power, L1 is a positive integer. Wherein, L1 is equal to the number of CRC check bits corresponding to the generator polynomial used when the number of information bits is less than or equal to the first threshold. In an optional example, L1 is the number of CRC check bits corresponding to the first generator polynomial, and L is equal to 6. In an optional example, the value of Kmax1 is greater than 2 L1 -Δ and less than or equal to 2 L1 power, and Δ is equal to 8 or 16. Alternatively, the value of Kmax1 is 57.

[0171] In an optional example, the first threshold is an integer greater than 2 L1 , and the first threshold is less than or equal to 2 L1 ·C', wherein L1 is the number of CRC check bits corresponding to the first generator polynomial, and C' is determined by the number of CRC check bits corresponding to the first generator polynomial and the number of CRC check bits corresponding to the second generator polynomial. In an example, wherein L1 is the number of CRC check bits corresponding to the first generator polynomial, and L2 is the number of CRC check bits corresponding to the second generator polynomial. Optionally, L1 can be equal to 6, and L2 can be equal to 16. In an optional example, the first threshold value is greater than or equal to 2 L1 • C' - Δ and less than or equal to 2 L1 • an integer of C', wherein Δ is equal to 16. In another optional example, the first threshold value is equal to 114.

[0172] In an optional example, the Kmax2 is an integer greater than Kmax1, and the Kmax2 is less than 2048. In this example, the Kmax2 is equal to 1024.

[0173] In this example, the specific process is shown as follows.

[0174] First, the number of information bits can be determined, denoted as K, wherein K is a positive integer.

[0175] Then, 301 is performed: according to the number of information bits in the information bit sequence, a generator polynomial for CRC encoding of the information bit sequence is selected from at least two polynomials. In this example, the at least two polynomials include a first generator polynomial and a second generator polynomial. The number of CRC check bits corresponding to the two generator polynomials is equal to 6 and 16. In an optional example, the first generator polynomial with the number of CRC check bits equal to 6 is: g CRC6 (D) = [D 6 + D 5 + 1]. The second generator polynomial with the number of CRC check bits equal to 16 is: g CRC16 (D) = [D 16 + D 12 + D 5 + 1].

[0176] If the number of information bits K is less than or equal to the first threshold value, the number of corresponding CRC check bits is equal to 6, that is, the generator polynomial of the cyclic redundancy check encoding is determined to be the first generator polynomial g CRC6 (D) = [D 6 + D 5 + 1]. If the number of information bits K is greater than or equal to the second threshold value, the number of corresponding CRC check bits is equal to 16, that is, the generator polynomial of the cyclic redundancy check encoding is determined to be the second generator polynomial g CRC16 (D) = [D 16 + D 12 + D 5 + 1]. Wherein the first threshold value and the second threshold value are both equal to 114.

[0177] Secondly, performing 302 to 304: segmenting the information bit sequence to obtain C information bit subsequences; performing CRC encoding on the C information bit subsequences respectively according to the generation polynomial to obtain C CRC encoded bit subsequences; and combining the C CRC encoded bit subsequences to obtain the CRC encoded bit sequence. Wherein, segmenting the information bit sequence according to the CRC encoding maximum information length.

[0178] The CRC encoding maximum information length in the present example is determined by the number of information bits. Exemplarily, if the number of information bits is less than or equal to a first threshold, the CRC encoding maximum information length is equal to Kmax1=57; otherwise, the CRC encoding maximum information length is equal to Kmax2=1024. Segmenting the information bit sequence according to the determined CRC encoding maximum information length to obtain C information bit subsequences, then performing cyclic redundancy check encoding on the C information bit subsequences respectively to obtain C CRC encoded bit subsequences, and the combination of the C CRC encoded bit subsequences constitutes the CRC encoded bit sequence.

[0179] Finally, modulating and transmitting the CRC encoded bit sequence.

[0180] In an optional example, the information bit sequence is set as a0, a1, a2,..., a K-1 . Wherein, K=72, since K is less than the first threshold (114), the corresponding CRC check bit number is equal to 6, and the cyclic redundancy check encoding adopts the first generation polynomial: g CRC6 (D)=[D 6 +D 5 +1]. And since K is less than the first threshold (114), the CRC encoding maximum information length is equal to Kmax1=57. Segmenting the information bit sequence according to the determined CRC encoding maximum information length (57) to obtain C=2 information bit subsequences, the length of each information bit subsequence is equal to 36; then performing cyclic redundancy check encoding on the C=2 information bit subsequences respectively to obtain C=2 CRC encoded bit subsequences, the length is 42 bits respectively; the combination of the C=2 CRC encoded bit subsequences constitutes the CRC encoded bit sequence, the length is 84 bits.

[0181] Wherein, if K=888, since K is greater than the first threshold (114), the corresponding CRC check bit number is equal to 16, and the cyclic redundancy check encoding adopts the second generation polynomial: g CRC16 (D)=[D 16 +D 12 +D 5+1]. And, since K is less than the first threshold (114), the CRC encoding maximum information length equals Kmax2 = 1024. The information bit sequence is segmented according to the determined CRC encoding maximum information length (1024) to obtain C = 1 information bit sub-sequences; and the C = 1 information bit sub-sequences are respectively subjected to cyclic redundancy check encoding with a length of 904 bits, i.e., the CRC encoded bit sequence.

[0182] In some other examples, the first threshold can be equal to one of the following: 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64.

[0183] In some other examples, the Kmax1 can be equal to one of the following: 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64.

[0184] In some other examples, the Kmax1 can be equal to 56. Or, the Kmax1 can be equal to 55. Or, the Kmax1 can be equal to 54. Or, the Kmax1 can be equal to 53. Or, the Kmax1 can be equal to 52. Or, the Kmax1 can be equal to 51. Or, the Kmax1 can be equal to 50. Or, the Kmax1 can be equal to 49. Or, the Kmax1 can be equal to 48. Or, the Kmax1 can be equal to 58. Or, the Kmax1 can be equal to 59. Or, the Kmax1 can be equal to 60. Or, the Kmax1 can be equal to 61. Or, the Kmax1 can be equal to 62. Or, the Kmax1 can be equal to 63. Or, the Kmax1 can be equal to 64.

[0185] Example 9

[0186] The difference between the present example and Examples 1 to 8 is that different polynomials are used.

[0187] In an optional example, the at least two polynomials include a first generator polynomial and a second generator polynomial. The CRC check bit numbers corresponding to the 2 generator polynomials are equal to 5 and 16. In an optional example, the first generator polynomial with the CRC check bit number equal to 5 is: CRC5 (D) = [D 5 + D 3 +1]. The second generator polynomial with the CRC check bit number equal to 16 is: CRC16 (D) = [D 16 + D 12 + D 5 +1].

[0188] In an optional example, the first threshold value is greater than or equal to 2 L1 - Δ and less than or equal to 2 L1 , where Δ is equal to 8. Wherein, L1 is equal to the number of CRC check bits corresponding to the generator polynomial used when the number of information bits is less than or equal to the first threshold value. L1 is the number of CRC check bits corresponding to the first generator polynomial, and in this example, L is equal to 5. Exemplarily, the first threshold value is one of the following: 24, 25, 26, 27, 28, 29, 30, 31, 32.

[0189] In an optional example, the first threshold value is greater than or equal to 2 L1 and the first threshold value is less than or equal to 2 L1 · C', where L1 is the number of CRC check bits corresponding to the first generator polynomial, and C' is determined by the number of CRC check bits corresponding to the first generator polynomial and the number of CRC check bits corresponding to the second generator polynomial. In one example, where L1 is the number of CRC check bits corresponding to the first generator polynomial, and L2 is the number of CRC check bits corresponding to the second generator polynomial. Exemplarily, L1 can be equal to 5, and L2 can be equal to 16. And in an optional example, the first threshold value is greater than or equal to 2 L1 · C' - Δ and less than or equal to 2 L1 · C' - Δ and less than or equal to 2

[0190] In the premise of ensuring that the overhead of using the first generator polynomial for segmented encoding is less than the overhead of using the second generator polynomial for non-segmented encoding (i.e. overall encoding), that is, C*L1 is less than L2. Then, C' can be considered as the maximum number of information bit subsequences obtained after segmenting the information bit sequence. Once the maximum number of information bit subsequences obtained after segmentation is greater than C', it will result in a larger CRC overhead, that is, the overhead of using the first generator polynomial to perform cyclic redundancy encoding on each information bit subsequence will be larger than the overhead of using the second generator polynomial to perform cyclic redundancy encoding on the information bit sequence.

[0191] In another optional example, the first threshold value is one of the following: 96, 95, 94, 93, 92, 91, 90, 89, 88.

[0192] Example 10

[0193] The difference between this example and examples 1 to 9 is that different polynomials are used.

[0194] In an optional example, the at least two polynomials include a first generator polynomial and a second generator polynomial. The two generator polynomials correspond to CRC check bit numbers equal to 6 and 16. In an optional example, the first generator polynomial with CRC check bit number equal to 6 is: CRC6 (D) = [D 6 + D 5 + 1]. The second generator polynomial with CRC check bit number equal to 16 is: CRC16 (D) = [D 16 + D 11 + D 6 + D 5 + 1].

[0195] In an optional example, the at least two polynomials include a first generator polynomial and a second generator polynomial. The two generator polynomials correspond to CRC check bit numbers equal to 6 and 24. In an optional example, the first generator polynomial with CRC check bit number equal to 6 is: CRC6 (D) = [D 6 + D 5 + 1]. The second generator polynomial with CRC check bit number equal to 24 is: CRC24 (D) = [D 24 + D 23 + D 18 + D 17 + D 14 + D 11 + D 10 + D 7 + D 6 + D 5 + D 4 + D 3 + D + 1].

[0196] In an optional example, the at least two polynomials include a first generator polynomial and a second generator polynomial. The two generator polynomials correspond to CRC check bit numbers equal to 5 and 11. In an optional example, the first generator polynomial with CRC check bit number equal to 5 is: CRC5 (D) = [D 5 + D 3 + 1]. The second generator polynomial with CRC check bit number equal to 11 is: CRC11 (D) = [D 11 + D 10 + D 9 + D 5 + 1].

[0197] In an optional example, the at least two polynomials include a first generator polynomial and a second generator polynomial. The CRC check bit number corresponding to the two generator polynomials is equal to 8 and 16. In an optional example, the first generator polynomial with the CRC check bit number equal to 8 is: g CRC8 (D) = [D 8 + D 7 + D 4 + D 3 + D + 1]. The second generator polynomial with the CRC check bit number equal to 16 is: g CRC16 (D) = [D 16 + D 11 + D 6 + D 5 + 1].

[0198] As can be seen from the above examples, the information sending method provided in the embodiment has lower data overhead than CRC16 alone, and has a lower false alarm rate of data transmission. The information sending method can be used for CRC data checking of future ultra-high passive Internet of Things.

[0199] FIG. 6 is a flow diagram of an information receiving method according to an embodiment of the present application. The information receiving method provided in the embodiment can be applied to a second communication node. The second communication node in the embodiment is a receiving end. The second communication node in the embodiment can be a base station or a UE, etc. in FIG. 1. As shown in FIG. 6, the information receiving method provided in the embodiment includes the following operations.

[0200] 601: receiving a to-be-checked bit sequence.

[0201] The to-be-checked bit sequence in the embodiment corresponds to the CRC-encoded bit sequence in the above information sending method embodiment. If there is an error in the reception, at least one bit in the to-be-checked bit sequence will be different from the CRC-encoded bit sequence, and when cyclic redundancy check decoding is performed, the check will fail, i.e., an error reception will be prompted. If the cyclic redundancy check decoding is passed, the CRC check bits in the to-be-checked bit sequence are removed, and the original transmitted information bit sequence can be obtained. However, there is a special reception state in communication: the received to-be-checked bit sequence is incorrect, but the cyclic redundancy check decoding is passed, i.e., it is considered as a legal CRC codeword and correct reception is prompted. This special reception state will affect the robustness of communication and should be avoided as much as possible in actual communication. The probability of the special reception state is the false alarm rate or false detection rate (FAR) of data transmission.

[0202] 602: selecting a generator polynomial for CRC decoding of the to-be-checked bit sequence from at least two polynomials according to the number of information bits.

[0203] The at least two polynomials correspond to different numbers of CRC check bits.

[0204] In an embodiment, the at least two polynomials include a first generator polynomial and a second generator polynomial, the first generator polynomial corresponding to a smaller number of CRC check bits than the second generator polynomial.

[0205] In an embodiment, the first generator polynomial corresponds to 6 CRC check bits, and the second generator polynomial corresponds to 16 CRC check bits. Alternatively, the first generator polynomial corresponds to 5 CRC check bits, and the second generator polynomial corresponds to 16 CRC check bits; or the first generator polynomial corresponds to 7 CRC check bits, and the second generator polynomial corresponds to 16 CRC check bits.

[0206] In an embodiment, the first generator polynomial corresponding to 6 CRC check bits is g CRC6 (D) = [D 6 + D 5 + 1], and the second generator polynomial corresponding to 16 CRC check bits is g CRC16 (D) = [D 16 + D 12 + D 5 + 1].

[0207] In an embodiment, the implementation of 602 is as follows: if the number of information bits is less than or equal to a first threshold, the first generator polynomial is determined as the generator polynomial for CRC decoding of the information bit sequence.

[0208] The first threshold is an integer greater than 0 and less than or equal to 2 L1 · L1, where L1 is the number of CRC check bits corresponding to the first generator polynomial. Alternatively, the first threshold is an integer greater than 2 L1 · L1 and less than or equal to 2 L1 · C', where C' is determined by the number of CRC check bits L1 corresponding to the first generator polynomial and the number of CRC check bits L2 corresponding to the second generator polynomial. In an example, where L1 is the number of CRC check bits corresponding to the first generator polynomial, and L2 is the number of CRC check bits corresponding to the second generator polynomial. By way of example, L1 can be equal to 6, and L2 can be equal to 16. Alternatively, the first threshold is an integer greater than 0 and less than or equal to 2 L1 · C'.

[0209] In an embodiment, the implementation of 602 is: if the number of information bits is greater than or equal to a second threshold, determining the second generator polynomial as the generator polynomial for CRC decoding of the sequence of information bits, wherein the second threshold is greater than or equal to the first threshold.

[0210] In an embodiment, the implementation of 602 is: if the number of information bits is less than or equal to a third threshold, determining that the number of CRC check bits corresponding to the generator polynomial for CRC decoding of the sequence of information bits is equal to 0, wherein the third threshold is less than the first threshold.

[0211] In an embodiment, the first threshold is equal to one of: 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 64; or the first threshold is equal to one of: 114, 96, 98, 100, 102, 104, 106, 108, 110, 111, 112, 113, 115, 116, 117, 118, 120, 122, 124, 126, 128.

[0212] In an embodiment, the second threshold is equal to one of: 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 64; or the second threshold is equal to one of: 114, 96, 98, 100, 102, 104, 106, 108, 110, 111, 112, 113, 115, 116, 117, 118, 120, 122, 124, 126, 128.

[0213] In an embodiment, the third threshold is equal to one of: 11, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18.

[0214] In an embodiment, the number of CRC check bits corresponding to the second generator polynomial is greater than 2 times the number of CRC check bits corresponding to the first generator polynomial.

[0215] In an optional example, the number of CRC check bits of the first generator polynomial and the second generator polynomial can be equal to any two different numbers of: 4, 5, 6, 8, 10, 11, 12, 14, 16, 18, 20, 24, 32.

[0216] In an optional example, the first generator polynomial corresponds to 6 CRC check bits, and the second generator polynomial corresponds to 16 CRC check bits. Alternatively, the first generator polynomial corresponds to 5 CRC check bits, and the second generator polynomial corresponds to 16 CRC check bits; or the first generator polynomial corresponds to 7 CRC check bits, and the second generator polynomial corresponds to 16 CRC check bits.

[0217] In an optional example, the first generator polynomial corresponds to 8 CRC check bits, and the second generator polynomial corresponds to 16 CRC check bits; or the first generator polynomial corresponds to 5 CRC check bits, and the second generator polynomial corresponds to 10 CRC check bits; or the first generator polynomial corresponds to 6 CRC check bits, and the second generator polynomial corresponds to 11 CRC check bits.

[0218] In an embodiment, the first threshold value is equal to 57, and the second threshold value is equal to 57. In an embodiment, the first threshold value is equal to 114, and the second threshold value is equal to 114. In an embodiment, the third threshold value is equal to 14. In an embodiment, the third threshold value is equal to 11.

[0219] 603: performing CRC decoding on the to-be-checked bit sequence according to the generator polynomial to obtain an information bit sequence.

[0220] Optionally, the implementation process of 603 comprises: if the generator polynomial is the first generator polynomial, inputting the to-be-checked bit sequence into a circuit corresponding to the first generator polynomial to obtain the information bit sequence; and if the generator polynomial is the second generator polynomial, inputting the to-be-checked bit sequence into a circuit corresponding to the second generator polynomial to obtain the information bit sequence.

[0221] FIG. 7 is a schematic diagram of a circuit corresponding to the first generator polynomial according to an embodiment of the present application. As shown in FIG. 7, the hardware circuit corresponding to the first generator polynomial comprises 6 registers (D0, D1, …, D5) and 2 XOR gates. All bits of the received to-be-checked bit sequence are sequentially input into the circuit shown in FIG. 7, and the bits remaining in the last register satisfy a certain state, which indicates correct reception, otherwise, it indicates error reception. For example, if all bits remaining in the last register are equal to 0, it indicates correct reception, and the CRC check bits can be removed to obtain the transmitted information bit sequence.

[0222] Figure 8 is a schematic diagram of a circuit corresponding to a second generator polynomial according to an embodiment of the present application. As shown in Figure 8, the hardware circuit corresponding to the second generator polynomial includes 16 registers (D0, D1,..., D15) and 3 XOR gates. All the bits of the received bit sequence to be checked are sequentially input into the circuit shown in Figure 8, and the bits remaining in the last registers satisfy a certain state, which indicates correct reception, otherwise, it indicates error reception. For example, if all the bits remaining in the last registers are equal to 0, it indicates correct reception, and the CRC check bits can be removed to obtain the transmitted information bit sequence.

[0223] In the embodiment, the information bit sequence can also be segmented for CRC encoding. In an optional example, the information bit sequence is encoded according to a generator polynomial of cyclic redundancy check to obtain a CRC encoded bit sequence, including: segmenting the information bit sequence according to a maximum information length of CRC encoding to obtain C information bit subsequences, and then encoding the C information bit subsequences respectively according to the generator polynomial of cyclic redundancy check to obtain C CRC encoded bit subsequences, and the combination of the C CRC encoded bit subsequences constitutes the CRC encoded bit sequence. Wherein, C is an integer greater than 0.

[0224] In an optional example, the C is any positive integer less than or equal to a value obtained by dividing the number of CRC check bits corresponding to the second generator polynomial by the number of CRC check bits corresponding to the first generator polynomial.

[0225] In an optional example, the maximum information length of CRC encoding is an integer greater than 0, and the value of the maximum information length of CRC encoding is less than or equal to 2 L1 -Δand less than or equal to 2 L1 power of 2, and L1 is a positive integer. In an optional example, L1 is the number of CRC check bits corresponding to the first generator polynomial, and L1 is equal to 6. In an optional example, the value of the maximum information length of CRC encoding is an integer greater than or equal to 2

[0226] In an optional example, the number of bits of the information bit sequence is less than or equal to a first threshold. In an optional example, the first threshold is an integer greater than 0, and the first threshold is less than or equal to 2 L1• C', where L1 is the number of CRC check bits corresponding to the first generator polynomial, and C' is determined by the number of CRC check bits corresponding to the first generator polynomial and the number of CRC check bits corresponding to the second generator polynomial. In one optional example, where L1 is the number of CRC check bits corresponding to the first generator polynomial, and L2 is the number of CRC check bits corresponding to the second generator polynomial. Exemplarily, L1 can be equal to 6, and L2 can be equal to 16. In one optional example, the first threshold value is one of: 96, 98, 100, 102, 104, 106, 108, 110, 111, 112, 113, 114, 115, 116, 117, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136.

[0227] The implementation process of 603 can include: segmenting the to-be-verified bit sequence to obtain a to-be-verified bit sub-sequence; performing CRC decoding on the to-be-verified bit sub-sequence according to the generator polynomial to obtain an information bit sub-sequence; and obtaining the information bit sequence according to the information bit sub-sequence, corresponding to the encoding mode of 302 to 304.

[0228] The information receiving method provided in this embodiment includes: receiving a to-be-verified bit sequence; selecting a generator polynomial for performing CRC decoding on the to-be-verified bit sequence from at least two polynomials according to the number of information bits, where the at least two polynomials correspond to different numbers of CRC check bits; and performing CRC decoding on the to-be-verified bit sequence according to the generator polynomial to obtain an information bit sequence. The information receiving method has a lower data transmission false positive rate and increases the robustness of data communication.

[0229] FIG. 9 is a structural schematic diagram of an information sending device provided in an embodiment of the present application. As shown in FIG. 9, the information sending device provided in this embodiment can be arranged in a first communication node. As shown in FIG. 9, the information sending device provided in this embodiment includes the following modules: a first selection module 91, an encoding module 92, and a sending module 93.

[0230] The first selection module 91 is configured to select a generator polynomial for performing CRC encoding on the information bit sequence from at least two polynomials according to the number of information bits in the information bit sequence.

[0231] The at least two polynomials correspond to different numbers of CRC check bits.

[0232] The encoding module 92 is configured to perform CRC encoding on the information bit sequence according to the generator polynomial to obtain a CRC encoded bit sequence.

[0233] The sending module 93 is configured to send the CRC encoded bit sequence.

[0234] In an embodiment, the at least two polynomials include a first generator polynomial and a second generator polynomial, the first generator polynomial corresponding to a number of CRC check bits being less than the number of CRC check bits corresponding to the second generator polynomial.

[0235] In an embodiment, the number of CRC check bits corresponding to the first generator polynomial is 6, and the number of CRC check bits corresponding to the second generator polynomial is 16; or, the number of CRC check bits corresponding to the first generator polynomial is 5, and the number of CRC check bits corresponding to the second generator polynomial is 16; or, the number of CRC check bits corresponding to the first generator polynomial is 7, and the number of CRC check bits corresponding to the second generator polynomial is 16.

[0236] In an embodiment, the first generator polynomial is g CRC6 (D) = [D 6 + D 5 + 1], and the second generator polynomial is g CRC16 (D) = [D 16 + D 12 + D 5 + 1].

[0237] In an embodiment, the first selection module 91 is configured to, in response to the number of information bits being less than or equal to a first threshold, determine the first generator polynomial as the generator polynomial for CRC encoding the information bit sequence.

[0238] In an embodiment, the first threshold is an integer greater than 0 and less than or equal to 2 L1 · L1, where L1 is the number of CRC check bits corresponding to the first generator polynomial; or, the first threshold is an integer greater than 2 L1 · L1 and less than or equal to 2 L1 · C', where C' is determined by the number of CRC check bits L1 corresponding to the first generator polynomial and the number of CRC check bits L2 corresponding to the second generator polynomial; or, the first threshold is an integer greater than 0 and less than or equal to 2 L1 · C'.

[0239] In an embodiment, the first selection module 91 is configured to, in response to the number of information bits being greater than or equal to a second threshold, determine the second generator polynomial as the generator polynomial for CRC encoding the information bit sequence; and the second threshold is greater than or equal to the first threshold.

[0240] In an embodiment, the first selecting module 91 is configured to determine that the number of CRC check bits corresponding to the generation polynomial for CRC encoding the information bit sequence is equal to 0 in response to the number of information bits being less than or equal to a third threshold value, wherein the third threshold value is less than the first threshold value.

[0241] In an embodiment, the encoding module 92 is configured to divide the information bit sequence to obtain C information bit subsequences, wherein C is an integer greater than 0; perform CRC encoding on the C information bit subsequences respectively according to the generation polynomial to obtain C CRC encoded bit subsequences; and combine the C CRC encoded bit subsequences to obtain the CRC encoded bit sequence.

[0242] In an embodiment, in the aspect of dividing the information bit sequence to obtain C information bit subsequences, the encoding module 92 is configured to divide the information bit sequence to obtain C information bit subsequences in response to the number of information bits being less than or equal to the first threshold value and greater than the third threshold value, or divide the information bit sequence to obtain C information bit subsequences in response to the number of information bits being greater than the first threshold value and less than the second threshold value.

[0243] In an embodiment, the C is equal to 2.

[0244] In an embodiment, the C is an arbitrary positive integer less than or equal to a value obtained by dividing the number of CRC check bits corresponding to the second generation polynomial by the number of CRC check bits corresponding to the first generation polynomial.

[0245] In an embodiment, in the aspect of dividing the information bit sequence, the encoding module 92 is configured to divide the information bit sequence according to a CRC encoding maximum information length, wherein the CRC encoding maximum information length is a positive integer.

[0246] In an embodiment, the CRC encoding maximum information length is an integer greater than 0 and less than or equal to 2 L1 , wherein L1 is the number of CRC check bits corresponding to the first generation polynomial.

[0247] In an embodiment, the CRC encoding maximum information length is determined by the number of information bits.

[0248] In an embodiment, in the case that the number of information bits is less than or equal to the first threshold value, the CRC encoding maximum information length is Kmax1, wherein Kmax1 is a positive integer.

[0249] In an embodiment, the CRC encoding maximum information length is Kmax2 when the number of information bits is greater than or equal to the second threshold; wherein Kmax2 is a positive integer, and Kmax2 is greater than Kmax1, and the second threshold is an integer greater than or equal to the first threshold.

[0250] In an embodiment, the Kmax1 is equal to one of: 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 64.

[0251] In an embodiment, the Kmax2 is equal to a preset maximum number of information bits. For example, in a communication system, the preset maximum number of information bits is equal to 1000, and the Kmax2 is equal to 1000. If the CRC encoding maximum information length is equal to Kmax2, and the Kmax2 is equal to the preset maximum number of information bits, it means that the information bit sequence does not need to be segmented, and the CRC encoding can be directly performed on the information bit sequence.

[0252] In another optional example, the first threshold is equal to E times of Kmax1, wherein E is a positive integer.

[0253] Optionally, the E is a maximum integer less than or equal to a value obtained by dividing the number of CRC check bits corresponding to the second generator polynomial by the number of CRC check bits corresponding to the first generator polynomial. The E is equal to floor(L2 / L1), wherein L1 is the number of CRC check bits corresponding to the first generator polynomial, L2 is the number of CRC check bits corresponding to the second generator polynomial, and the formula floor(x) represents an integer part of a real number x, or rounding down a real number x, or taking a maximum integer less than or equal to a real number x.

[0254] In an embodiment, the CRC encoding maximum information length is equal to one of: 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 64.

[0255] In an embodiment, the first threshold is equal to one of: 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 64; or the first threshold is equal to one of: 114, 96, 98, 100, 102, 104, 106, 108, 110, 111, 112, 113, 115, 116, 117, 118, 120, 122, 124, 126, 128.

[0256] In an embodiment, the second threshold value is equal to one of: 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 64; or, the second threshold value is equal to one of: 114, 96, 98, 100, 102, 104, 106, 108, 110, 111, 112, 113, 115, 116, 117, 118, 120, 122, 124, 126, 128.

[0257] In an embodiment, the third threshold value is equal to one of: 11, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18.

[0258] In an embodiment, a value obtained by dividing the number of CRC check bits corresponding to the second generator polynomial by the number of CRC check bits corresponding to the first generator polynomial is greater than 2.

[0259] In an embodiment, the first threshold value is equal to 57, and the second threshold value is equal to 57. In an embodiment, the first threshold value is equal to 114, and the second threshold value is equal to 114. In an embodiment, the third threshold value is equal to 14. In an embodiment, the third threshold value is equal to 11.

[0260] The information sending device provided in the embodiment can implement the information sending method executed by the first communication node in the above-mentioned embodiments, and the implementation principle and technical effects are similar to those of the above-mentioned embodiments, which will not be described herein again.

[0261] FIG. 10 is a structural schematic diagram of an information receiving device according to an embodiment of the present application. As shown in FIG. 10, the information receiving device provided in the embodiment can be arranged in a second communication node. As shown in FIG. 10, the information receiving device provided in the embodiment includes the following modules: a receiving module 101, a second selecting module 102, and a decoding module 103.

[0262] The receiving module 101 is arranged to receive a to-be-verified bit sequence.

[0263] The second selecting module 102 is arranged to select, according to the number of information bits, a generator polynomial for performing CRC decoding on the to-be-verified bit sequence from at least two polynomials.

[0264] The at least two polynomials correspond to different numbers of CRC check bits.

[0265] The decoding module 103 is arranged to perform CRC decoding on the to-be-verified bit sequence according to the generator polynomial to obtain an information bit sequence.

[0266] In an embodiment, the at least two polynomials include a first generator polynomial and a second generator polynomial, the first generator polynomial corresponding to a number of CRC check bits smaller than a number of CRC check bits corresponding to the second generator polynomial.

[0267] In an embodiment, the number of CRC check bits corresponding to the first generator polynomial is 6, and the number of CRC check bits corresponding to the second generator polynomial is 16; or the number of CRC check bits corresponding to the first generator polynomial is 5, and the number of CRC check bits corresponding to the second generator polynomial is 16; or the number of CRC check bits corresponding to the first generator polynomial is 7, and the number of CRC check bits corresponding to the second generator polynomial is 16.

[0268] In an embodiment, the first generator polynomial is g CRC6 (D) = [D 6 + D 5 + 1], and the second generator polynomial is g CRC16 (D) = [D 16 + D 12 + D 5 + 1].

[0269] In an embodiment, the decoding module 103 is configured to, in response to the generator polynomial being the first generator polynomial, input the to-be-verified bit sequence into a circuit corresponding to the first generator polynomial to obtain the information bit sequence; and in response to the generator polynomial being the second generator polynomial, input the to-be-verified bit sequence into a circuit corresponding to the second generator polynomial to obtain the information bit sequence.

[0270] The information receiving apparatus provided in the embodiment can implement the information receiving method performed by the second communication node in the above-mentioned embodiments, and the implementation principle and technical effects are similar to those of the above-mentioned embodiments, which will not be described herein again.

[0271] The embodiments of the present application further provide a communication node, including: a processor, the processor being configured to implement the method provided in any of the embodiments of the present application when executing computer instructions. Illustratively, the communication node can be the first communication node or the second communication node. The first communication node includes: a processor, the processor being configured to implement the information sending method provided in any of the embodiments of the present application when executing computer instructions; and the second communication node includes: a processor, the processor being configured to implement the information receiving method provided in any of the embodiments of the present application when executing computer instructions.

[0272] Figure 11 is a schematic diagram of a structure of a communication node according to an embodiment of the present application. As shown in Figure 11, the communication node comprises a processor 60, a memory 61 and a communication interface 62; the number of processors 60 in the communication node can be one or more, and Figure 11 takes one processor 60 as an example; the processor 60, the memory 61 and the communication interface 62 in the communication node can be connected through a bus or other means, and Figure 11 takes the connection through a bus as an example. The bus represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor or a local bus using any of a variety of bus structures.

[0273] The memory 61 is a computer readable storage medium, which can be configured to store software programs, computer executable programs and modules, such as program instructions / modules corresponding to the method in the embodiments of the present application. The processor 60 executes at least one function application and data processing of the communication node by running the software programs, instructions and modules stored in the memory 61, that is, implements the method described above.

[0274] The memory 61 can include a program storage area and a data storage area, wherein the program storage area can store an operating system and at least one application required by a function; the data storage area can store data created according to the use of the communication node, etc. In the present application, the memory 61 can realize local caching of information bit sequences, to-be-verified bit sequences, generating polynomials, and the number of CRC check bits, etc.

[0275] In addition, the memory 61 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state memory device. In some examples, the memory 61 can include a memory disposed remotely with respect to the processor 60, and these remote memories can be connected to the communication node through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0276] The communication interface 62 can be configured to receive and send data. The communication interface 62 can be used to send the encoded bit sequence to the receiving end, or receive the to-be-verified bit sequence. The communication interface 62 in the embodiment of the present application can include a single antenna or a plurality of antennas.

[0277] The embodiments of the present application further provide a communication system comprising the first communication node and the second communication node.

[0278] The embodiments of the present application further provide a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the method provided by any of the embodiments of the present application.

[0279] The computer storage medium of the embodiments of the present application can adopt any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination thereof. The computer readable storage medium includes, but is not limited to, a non-exhaustive list: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an electrically erasable, programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present application, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus.

[0280] The computer readable signal medium can include a data signal propagated in a baseband or as a part of a carrier wave propagating through transmission media, and the data signal bears computer readable program code. Such a propagated data signal can take through various forms, including but not limited to electro-magnetic signal, optical signal or any suitable combination thereof. The computer readable signal medium can also be any computer readable medium that can send, propagate or transfer program for use by or in connection with an instruction execution system, device or apparatus, other than the computer readable storage medium.

[0281] The program code contained on the computer readable medium can be transmitted by any suitable medium, including but not limited to wireless, wire, cable, radio frequency (RF), or any suitable combination thereof.

[0282] Computer program code for carrying out operations of the present disclosure can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++, Ruby, Go, or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0283] Those skilled in the art will appreciate that the term user terminal encompasses any appropriate type of wireless user equipment, such as a mobile phone, a portable data processing apparatus, a portable web browser, or a vehicle mounted mobile station.

[0284] In general, the various embodiments of the application can be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects can be implemented in hardware, while other aspects can be implemented in

[0285] Embodiments of the application can be implemented by the data processor of a mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. Computer program instructions can be in assemblies, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or in any combination of one or more programming languages, executed on one or more computing devices.

[0286] The block diagrams of any logical flow of the present application in the drawings can represent program operations, or can represent interconnecting logical circuits, modules and functions, or can represent a combination of program operations and logical circuits, modules and functions. The computer program can be stored on a memory. The memory can have any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as, but not limited to, read only memory (ROM), random access memory (RAM), optical storage devices, and systems such as digital versatile disc (DVD) or CD-ROM, and the like. The computer readable media can include non-transitory storage media. The data processor can be of any type suitable for the local technical environment, and can include, but is not limited to, general purpose computers, special purpose computers, microprocessors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), and processors based on multi-core processor architectures, as examples.

Claims

1. A method for transmitting information, applied to a first communication node, comprising: selecting a generator polynomial for cyclic redundancy check (CRC) encoding of an information bit sequence from at least two polynomials according to a number of information bits in the information bit sequence, wherein the at least two polynomials correspond to different numbers of CRC check bits; CRC encoding the information bit sequence according to the generator polynomial to obtain a CRC encoded bit sequence; and transmitting the CRC encoded bit sequence.

2. The method of claim 1, wherein, The at least two polynomials comprise a first generator polynomial and a second generator polynomial, and the first generator polynomial corresponds to a smaller number of CRC check bits than the second generator polynomial.

3. The method of claim 2, wherein, The first generator polynomial corresponds to 6 CRC check bits, and the second generator polynomial corresponds to 16 CRC check bits; or the first generator polynomial corresponds to 5 CRC check bits, and the second generator polynomial corresponds to 16 CRC check bits; or the first generator polynomial corresponds to 7 CRC check bits, and the second generator polynomial corresponds to 16 CRC check bits.

4. The method of claim 2, wherein, The first generator polynomial is: g CRC6 (D) = [D 6 +D 5 +1], and the second generator polynomial is: g CRC16 (D) = [D 16 +D 12 +D 5 +1].

5. The method of claim 2, wherein, The selecting a generator polynomial for CRC encoding of an information bit sequence from at least two polynomials according to a number of information bits in the information bit sequence comprises: in response to the number of information bits being less than or equal to a first threshold, determining the first generator polynomial as the generator polynomial for CRC encoding of the information bit sequence.

6. The method of claim 5, wherein, the first threshold is greater than 0 and less than or equal to 2 L1 an integer, wherein L1 is a number of CRC check bits corresponding to the first generator polynomial; or, the first threshold is greater than 2 L1 and less than or equal to 2 L1 • an integer of C', wherein C' is determined by a CRC check bit number L1 corresponding to the first generator polynomial and a CRC check bit number L2 corresponding to the second generator polynomial; or, the first threshold value is greater than 0 and less than or equal to 2 L1 • an integer of C'.

7. The method of claim 5, wherein, The selecting a generator polynomial for CRC encoding of an information bit sequence from at least two polynomials according to a number of information bits in the information bit sequence comprises: in response to the number of information bits being greater than or equal to a second threshold, determining the second generator polynomial as the generator polynomial for CRC encoding of the information bit sequence, wherein the second threshold is greater than or equal to the first threshold.

8. The method of claim 5, wherein, The selecting a generator polynomial for CRC encoding of an information bit sequence from at least two polynomials according to a number of information bits in the information bit sequence comprises: in response to the number of information bits being less than or equal to a third threshold, determining that the generator polynomial for CRC encoding of the information bit sequence corresponds to 0 CRC check bits, wherein the third threshold is less than the first threshold.

9. The method of claim 2, wherein, The CRC encoding the information bit sequence according to the generator polynomial to obtain a CRC encoded bit sequence comprises: segmenting the information bit sequence to obtain C information bit subsequences, wherein C is an integer greater than 0; CRC encoding the C information bit subsequences according to the generator polynomial to obtain C CRC encoded bit subsequences; and combining the C CRC encoded bit subsequences to obtain the CRC encoded bit sequence.

10. The method of claim 9, wherein, The segmenting the information bit sequence to obtain C information bit subsequences comprises: In response to the number of information bits being less than or equal to a first threshold and greater than a third threshold, the information bit sequence is segmented to obtain C information bit subsequences; or In response to the number of information bits being greater than a first threshold and less than a second threshold, the information bit sequence is segmented to obtain C information bit subsequences.

11. The method of claim 9 or 10, wherein, The C is equal to 2.

12. The method of claim 9 or 10, wherein, The C is any positive integer less than or equal to a value obtained by dividing a number of CRC check bits corresponding to the second generator polynomial by a number of CRC check bits corresponding to the first generator polynomial.

13. The method of claim 9, wherein, The segmentation of the information bit sequence comprises segmenting the information bit sequence according to a CRC encoding maximum information length, the CRC encoding maximum information length being a positive integer.

14. The method of claim 13, wherein, The CRC encoding maximum information length is greater than 0 and less than or equal to 2 L1 , wherein L1 is the number of CRC check bits corresponding to the first generator polynomial.

15. The method of claim 13, wherein, The CRC encoding maximum information length is determined by the number of information bits.

16. The method of claim 15, wherein, In a case where the number of information bits is less than or equal to a first threshold, the CRC encoding maximum information length is Kmax1, where Kmax1 is a positive integer.

17. The method of claim 16, wherein, In a case where the number of information bits is greater than or equal to a second threshold, the CRC encoding maximum information length is Kmax2, where Kmax2 is a positive integer and Kmax2 is greater than Kmax1, and the second threshold is an integer greater than or equal to the first threshold.

18. The method of claim 13, wherein, The CRC encoding maximum information length is equal to one of 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, and 64.

19. The method of claim 5 or 10, wherein, The first threshold is equal to one of 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, and 64; or the first threshold is equal to one of 114, 96, 98, 100, 102, 104, 106, 108, 110, 111, 112, 113, 115, 116, 117, 118, 120, 122, 124, 126, and 128.

20. The method of claim 7, 10, or 17, wherein, The second threshold is equal to one of 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, and 64; or the second threshold is equal to one of 114, 96, 98, 100, 102, 104, 106, 108, 110, 111, 112, 113, 115, 116, 117, 118, 120, 122, 124, 126, and 128.

21. The method of claim 8 or 10, wherein, The third threshold is equal to one of 11, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, and 17.

22. The method of claim 16, wherein, The Kmax1 is equal to one of 57, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, and 64.

23. The method of claim 16, wherein, The first threshold is equal to E times the Kmax1, where E is a positive integer.

24. The method of claim 23, wherein, The E is the largest integer less than or equal to a value obtained by dividing the number of CRC check bits corresponding to the second generator polynomial by the number of CRC check bits corresponding to the first generator polynomial.

25. The method of claim 17, wherein, The Kmax2 is equal to a preset maximum number of information bits.

26. The method of claim 2, wherein, The value obtained by dividing the number of CRC check bits corresponding to the second generator polynomial by the number of CRC check bits corresponding to the first generator polynomial is greater than 2.

27. An information receiving method applied to a second communication node, the method comprising: receiving a bit sequence to be checked; selecting a generator polynomial for cyclic redundancy check (CRC) decoding of the bit sequence to be checked from at least two polynomials according to a number of information bits, wherein the at least two polynomials correspond to different numbers of CRC check bits; performing CRC decoding of the bit sequence to be checked according to the generator polynomial to obtain a bit sequence of information.

28. The method of claim 27, wherein, The at least two polynomials include a first generator polynomial and a second generator polynomial, and the number of CRC check bits corresponding to the first generator polynomial is less than the number of CRC check bits corresponding to the second generator polynomial.

29. The method of claim 28, wherein, The number of CRC check bits corresponding to the first generator polynomial is 6, and the number of CRC check bits corresponding to the second generator polynomial is 16; or the number of CRC check bits corresponding to the first generator polynomial is 5, and the number of CRC check bits corresponding to the second generator polynomial is 16; or the number of CRC check bits corresponding to the first generator polynomial is 7, and the number of CRC check bits corresponding to the second generator polynomial is 16.

30. The method of claim 28, wherein, The first generator polynomial is: g CRC6 (D) = [D 6 + D 5 + 1], and the second generator polynomial is: g CRC16 (D) = [D 16 + D 12 + D 5 + 1].

31. The method of claim 28, wherein, The performing of the CRC decoding of the bit sequence to be checked according to the generator polynomial to obtain the bit sequence of information comprises: in response to the generator polynomial being the first generator polynomial, inputting the bit sequence to be checked into a circuit corresponding to the first generator polynomial to obtain the bit sequence of information; in response to the generator polynomial being the second generator polynomial, inputting the bit sequence to be checked into a circuit corresponding to the second generator polynomial to obtain the bit sequence of information.

32. A communication node, comprising: a processor; The processor is configured to implement the information sending method in any one of claims 1 to 26 or the information receiving method in any one of claims 27 to 31 when executing a computer program.

33. A computer readable storage medium storing a computer program, the computer program being configured to implement the information sending method in any one of claims 1 to 26 or the information receiving method in any one of claims 27 to 31 when executed by a processor.

Images