LDPC-based encoding method and LDPC-based decoding method

Abstract

An LDPC code-based encoding method and an LPDC-based decoding method. On the basis of a first LDPC matrix, an encoding apparatus performs LDPC encoding on an acquired information bit sequence to obtain a codeword sequence. A decoding apparatus decodes the codeword sequence on the basis of the first LDPC matrix. The first LDPC matrix comprises a first region. Non-zero elements comprised in the first region satisfy a first rule. The first rule is used for indicating the density of the non-zero elements comprised in the first region. According to the encoding method and decoding method, the encoding performance and decoding performance of an LDPC code can be improved by means of designing the density of non-zero elements in a certain region comprised in an LDPC matrix.

Description

An encoding method and a decoding method based on LDPC

[0001] The present application claims priority to the Chinese patent application No. 202411076165.7, filed on August 6, 2024, and entitled "An encoding method and a decoding method based on LDPC", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of channel coding. More particularly, it relates to an encoding method and a decoding method based on LDPC. BACKGROUND

[0003] A spatially coupled low density parity check (SC-LDPC) code connects multiple low density parity check (LDPC) block codes together by spatial coupling to form a coupling chain. This coupling structure enables the SC-LDPC code to utilize the information of adjacent block codes during decoding, thereby achieving excellent decoding performance. In actual use, a part of the check matrix of the SC-LDPC code needs to be intercepted according to the service code rate for encoding and decoding, which may cause a loss in the encoding or decoding performance of the SC-LDPC code. SUMMARY

[0004] The present application provides an encoding method and a decoding method based on LDPC code, which can guarantee the encoding and decoding performance of multiple LDPC codes by designing the matrix characteristics of the LDPC code.

[0005] In a first aspect, an encoding method based on LDPC code is provided, which can be executed by a first device. In the absence of special description, the "first device" in the present application can refer to the first device itself (e.g., a terminal device or a network device), a component (e.g., a communication module, a processor, a circuit, a chip or a chip system, etc.) in the first device, or a logic module or software capable of realizing all or part of the functions of the first device. For ease of understanding, the following description is made by taking the first device as an example.

[0006] The method comprises: the first device acquires an information bit sequence; and the first device performs LDPC encoding on the information bit sequence according to a first LDPC matrix to obtain a codeword sequence. The first LDPC matrix comprises a first region, and the non-zero elements included in the first region satisfy a first rule, which is used to indicate the density of the non-zero elements included in the first region.

[0007] The density of non-zero elements of a certain region included in the LDPC matrix is designed by the method, and the coding performance and decoding performance of the LDPC code can be improved.

[0008] In some implementations of the first aspect, the first LDPC matrix is coupled by L groups of sub-matrices, each group of the L groups of sub-matrices is identical, each group of the L groups of sub-matrices includes w+1 sub-matrices, and each of the w+1 sub-matrices is a M*N matrix. The first LDPC matrix includes a first matrix composed of S groups of sub-matrices, the S groups of sub-matrices are any S groups of continuous sub-matrices in the L groups of sub-matrices, and the first matrix is a [M*(w+S)]*(N*S) matrix. In one implementation, the first region is composed of the 1st to M*S rows and the 1st to N*S columns of the first matrix. In another implementation, the first region is composed of any M*A rows and the 1st to N*S columns of the first matrix.

[0009] wherein A

[0010] For example, the first region can be composed of the first M*S rows of the first matrix or the first region can be composed of any M*A rows of the first matrix.

[0011] For example, the first LDPC matrix can be an SC-LDPC matrix.

[0012] The method provides a selection method for the first region of the first LDPC matrix, and the density of non-zero elements of the first region selected by the method satisfies a certain rule, so that the coding performance and decoding performance of the LDPC code can be improved.

[0013] In some implementations of the first aspect, the first rule is any one of the following:

[0014] d(H)-d(H')≤θ*d(H), d(H)-d(H')≤θ*d(H'), or d(H)-d(H')≤α.

[0015] For example, d(H) represents the number of non-zero elements included in the first matrix, and d(H') represents the number of non-zero elements included in the first region.

[0016] For another example, d(H) represents the sum of non-zero elements included in the first matrix, and d(H') represents the sum of non-zero elements included in the first region.

[0017] For another example, d(H) represents the average row weight of the first matrix, and d(H') represents the average row weight of the first region.

[0018] In another example, d(H) represents the average column weight of the first matrix, and d(H') represents the average column weight of the first region.

[0019] The method provides a plurality of first rules and a plurality of representations of the density of non-zero elements of the first region, and the density of non-zero elements of the first region included in the LDPC matrix for encoding can be flexibly designed according to actual needs.

[0020] With reference to the first aspect, in some implementations of the first aspect, the column weight of each column of each group of sub-matrices in the L groups of sub-matrices is equal.

[0021] Alternatively, each group of sub-matrices in the L groups of sub-matrices has a column-regular form.

[0022] It can also be understood that the column weight of each column of the first LDPC matrix is equal.

[0023] The method can reduce the complexity of constructing the first LDPC matrix by designing the form of the first LDPC matrix to be column-regular, and still obtain excellent encoding performance and decoding performance.

[0024] With reference to the first aspect, in some implementations of the first aspect, the first sub-matrix to the i-th sub-matrix in the w+1 sub-matrices each include non-zero elements, or the number of non-zero elements included in the first sub-matrix to the i-th sub-matrix in the w+1 sub-matrices is greater than or equal to t.

[0025] wherein 1≤i≤w+1, and t>1.

[0026] The method can reduce the loss of encoding performance and decoding performance as much as possible by designing the distribution density of non-zero elements of each group of sub-matrices of the first LDPC matrix in the low-coupling-width region.

[0027] With reference to the first aspect, in some implementations of the first aspect, the first LDPC matrix is an X*Y matrix, the first region is composed of the first row to the X-th row and the y-th column of the first LDPC matrix, and the first rule is: min ≤d(H')≤J max

[0028] wherein d(H') represents the number of non-zero elements included in the first region, 2≤J min ≤J max , 1≤y≤Y, and y, Y, and X are positive integers.

[0029] The method provides a selection method of the first area for any LDPC matrix, that is, any column of the first LDPC matrix can be selected as the first area, and the number of non-zero elements in the column meets a certain rule, so that the encoding performance and decoding performance of the LDPC code are improved.

[0030] With reference to the first aspect, in some implementations of the first aspect, the first area can also be composed of part of elements in the yth column of the first LDPC matrix.

[0031] The method provides another selection method of the first area for any LDPC matrix, that is, part of elements in any column of the first LDPC matrix can be selected as the first area, and the number of non-zero elements in the first area meets a certain rule, so that the encoding performance and decoding performance of the LDPC code are improved.

[0032] With reference to the first aspect, in some implementations of the first aspect, the first LDPC matrix is an X*Y matrix, the first area is composed of the xth row and the 1st to Yth columns of the first LDPC matrix, and the first rule is K min ≤d(H')≤K max

[0033] wherein d(H') represents the number of non-zero elements included in the first area, 3≤K min ≤K max , 1≤x≤X, and x, X and Y are positive integers.

[0034] The method provides still another selection method of the first area for any LDPC matrix, that is, any row of the first LDPC matrix can be selected as the first area, and the number of non-zero elements in the row meets a certain rule, so that the encoding performance and decoding performance of the LDPC code are improved.

[0035] With reference to the first aspect, in some implementations of the first aspect, the first area can also be composed of part of elements in the xth row of the first LDPC matrix.

[0036] The method provides still another selection method of the first area for any LDPC matrix, that is, part of elements in any row of the first LDPC matrix can be selected as the first area, and the number of non-zero elements in the first area meets a certain rule, so that the encoding performance and decoding performance of the LDPC code are improved.

[0037] In a second aspect, a decoding method based on an LDPC code is provided. The method can be performed by a second device. Unless specifically stated, the "second device" in the present application can refer to the second device itself (e.g., a terminal device or a network device), a component (e.g., a communication module, a processor, a circuit, a chip, or a chip system) in the second device, or a logic module or software capable of realizing all or part of the functions of the second device. For ease of understanding, the following description is made with the second device performing as an example.

[0038] The method includes: obtaining, by the second device, a codeword sequence; and performing, by the first device, LDPC decoding on the codeword sequence according to a first LDPC matrix. The first LDPC matrix includes a first region, and the non-zero elements included in the first region satisfy a first rule. The first rule is used to indicate the density of the non-zero elements included in the first region.

[0039] By the above method, the density of the non-zero elements in a certain region of the LDPC matrix is designed, which can improve the encoding performance and decoding performance of the LDPC code.

[0040] Other implementation manners of the second aspect can refer to the other implementation manners of the first aspect, and the technical effects thereof can refer to the technical effects of the other implementation manners of the first aspect, which will not be described herein again.

[0041] In a third aspect, a communication device is provided. The communication device is configured to perform the method provided in any of the above aspects or possible implementation manners thereof. Specifically, the communication device can include units and / or modules for performing the method provided in any of the above aspects or possible implementation manners thereof, such as a processing unit and / or a transceiving unit.

[0042] In an implementation manner, the communication device is the first device or the second device. When the communication device is the first device or the second device, the transceiving unit can be a transceiver, or an input / output interface, or a communication interface; and the processing unit can be at least one processor. Optionally, the transceiver is a transceiving circuit. Optionally, the input / output interface is an input / output circuit.

[0043] In another implementation manner, the communication device is a chip, a chip system, or a circuit for the first device or the second device. When the communication device is a chip, a chip system, or a circuit for the first device or the second device, the transceiving unit can be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin, or a related circuit on the chip, the chip system, or the circuit; and the processing unit can be at least one processor, a processing circuit, or a logic circuit.

[0044] In a fourth aspect, a communication apparatus is provided, which comprises a memory configured to store a computer program or instructions; and at least one processor configured to execute the computer program or instructions stored in the memory to implement the method in any one of the aspects or the implementation manners thereof.

[0045] In an implementation manner, the apparatus is the first apparatus or the second apparatus.

[0046] In another implementation manner, the apparatus is a chip, a chip system or a circuit used in the first apparatus or the second apparatus.

[0047] In a fifth aspect, a communication apparatus is provided, which comprises at least one processor and a communication interface, the at least one processor configured to acquire, through the communication interface, a computer program or instructions stored in a memory, to implement the method in any one of the aspects or the implementation manners thereof. The communication interface can be implemented by hardware or software.

[0048] In an implementation manner, the apparatus further comprises the memory.

[0049] In a sixth aspect, a processor is provided, which is configured to implement the method in any one of the aspects.

[0050] For the sending and acquiring / receiving operations of the processor, if no special description is made, or if it is not contrary to the actual role or inherent logic in the related description, it can be understood as the output and receiving, input operations of the processor, or the sending and receiving operations performed by the radio frequency circuit and the antenna, which are not limited in the present application.

[0051] In a seventh aspect, a computer readable storage medium is provided, which stores program codes for execution by an apparatus, and the program codes comprise codes for implementing the method in any one of the aspects or the implementation manners thereof.

[0052] In an eighth aspect, a computer program product is provided, which comprises instructions, and when the computer program product is run on a computer, the computer is caused to implement the method in any one of the aspects or the implementation manners thereof.

[0053] In a ninth aspect, a chip is provided, which comprises a processor and a communication interface, the processor is configured to read instructions stored in a memory through the communication interface, and implement the method in any one of the aspects or the implementation manners thereof. The communication interface can be implemented by hardware or software.

[0054] Optionally, as an implementation manner, the chip further comprises the memory, the memory stores the computer program or instructions, and the processor is configured to execute the computer program or instructions stored in the memory, and when the computer program or instructions are executed, the processor is configured to implement the method in any one of the aspects or the implementation manners thereof.

[0055] When the method provided by the application is executed by a chip, the application does not limit the number of chips for implementing the method of the application, for example, the method can be executed by one chip, or two or more chips. When the number of chips for implementing the method of the application is two or more, the chip manufacturers are not limited, and can be the same manufacturer or different manufacturers.

[0056] In a tenth aspect, a communication system is provided, comprising at least one of the first device or the second device described above.

[0057] In an eleventh aspect, a computer program is provided, which, when running on a computer, causes the method provided by any one of the above aspects or the implementation manners thereof to be executed. BRIEF DESCRIPTION OF DRAWINGS

[0058] FIG. 1 is a schematic diagram of a check matrix H of an LDPC.

[0059] FIG. 2 is a Tanner graph of a check matrix H of an LDPC.

[0060] FIG. 3 is a schematic diagram of the structure of an LDPC base matrix.

[0061] FIG. 4 is a schematic diagram of an information transmission process.

[0062] FIG. 5 is a schematic diagram of a system architecture 100 suitable for the embodiments of the application.

[0063] FIG. 6 is a schematic flowchart of a communication method 200 provided by the embodiments of the application.

[0064] FIG. 7 is a schematic diagram of an example of a first area included in a first LDPC matrix provided by the embodiments of the application.

[0065] FIG. 8 is another schematic diagram of a first area included in a first LDPC matrix provided by the embodiments of the application.

[0066] FIG. 9 is a schematic diagram of window decoding using a first LDPC matrix.

[0067] FIG. 10 is an example performance comparison diagram of a first LDPC matrix and other LDPC matrices provided by the embodiments of the application.

[0068] FIG. 11 is another example performance comparison diagram of a first LDPC matrix and other LDPC matrices provided by the embodiments of the application.

[0069] FIG. 12 is a schematic diagram of a structure of a device provided by the embodiments of the application.

[0070] FIG. 13 is another schematic diagram of a structure of a device provided by the embodiments of the application.

[0071] FIG. 14 is a schematic diagram of a chip system according to an embodiment of the present application. DETAILED DESCRIPTION

[0072] The technical solutions in the present application will be described below with reference to the drawings.

[0073] In order to facilitate understanding of the solutions of the present application, the terms involved in the present application will be introduced first.

[0074] 1. Low density parity check (LDPC) code

[0075] An LDPC code is a kind of linear block code, and its check matrix is a kind of sparse matrix. In the case of a long code length, the number of zero elements in the check matrix of the LDPC code is much larger than the number of non-zero elements, or in other words, the row weight and the column weight of the check matrix are very small numbers compared with the code length of the LDPC code. An LDPC code with an information bit sequence of a length equal to k and a code length equal to n can be uniquely determined by its check matrix or its generator matrix. The information bit sequence can be a payload bit sequence or a bit sequence after adding a cyclic redundancy check (CRC) bit sequence, and the present application does not limit this.

[0076] Tanner represented the code word of the LDPC in the form of a graph in 1981, and this kind of graph is now called a Tanner graph, which is in one-to-one correspondence with the check matrix. The Tanner graph is composed of two types of vertices, one type of vertices represents code word bits and is called a variable node, and the other type of vertices is a check node representing a check constraint relationship. Each check node represents a check constraint relationship, which will be described below in combination with FIG. 1 and FIG. 2.

[0077] FIG. 1 is a schematic diagram of a check matrix H of an LDPC.

[0078] In FIG. 1, {Vi} represents a set of variable nodes, and {Ci} represents a set of check nodes. Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, each column represents a code word bit, and each code word bit corresponds to a variable node. In FIG. 1, there are 8 variable nodes and 4 check nodes. If a code word bit is contained in the corresponding check equation, a connecting line is used to connect the variable node and the check node involved, and a Tanner graph is obtained.

[0079] FIG. 2 is a Tanner graph of the check matrix H of the LDPC.

[0080] As shown in FIG. 2, the Tanner graph represents the check matrix of the LDPC. For example, for a check matrix H of size M rows by N columns, the Tanner graph contains two types of nodes, N variable nodes and M check nodes. The N variable nodes correspond to the N columns of the check matrix H, and the M check nodes correspond to the M rows of the check matrix H. A cycle in the Tanner graph is a group of vertices connected together, with one vertex in the group serving as both a start point and an end point, and passing through each node only once. The variable nodes in the Tanner graph correspond to each column of the check matrix H, i.e., each code bit of the LDPC; and the check nodes in the Tanner graph correspond to each row of the check matrix H, i.e., each check bit of the LDPC. The connection between the two types of nodes corresponds to the value of the element in the H matrix. For example, if there is a connection between the ith check node and the jth variable node, it means that the value of the element (i, j) in the H matrix is 1, and if there is no connection, the corresponding element is 0. The connection between the variable nodes and the check nodes can also be referred to as an edge. The connection between the check nodes and the variable nodes can also be described as: the check nodes and the variable nodes have a connection relationship.

[0081] 2. Quasi-cyclic low density parity check (QC-LDPC) code

[0082] The QC-LDPC code is a structured LDPC code. Due to the unique structure of the check matrix, the encoding can be implemented by using a simple feedback shift register, which reduces the encoding complexity of the LDPC. In the case of a long code length, the check matrix H of the LDPC is very large, so H is usually represented by multiple Z c ×Z c submatrices. Specifically, the complete check matrix H can be represented by an exponential matrix H b , where each element in H b corresponds to a Z c ×Z c submatrix, and each submatrix can be represented by a cyclic shift of a number of bits. Thus, the storage space required by the complete check matrix H is greatly reduced. The elements in the exponential matrix H b can also be referred to as quasi-cyclic (QC) blocks.

[0083] Based on the exponential matrix H b and the lifting size Z c , the exponential matrix H b can be expanded to a complete check matrix H for encoding or decoding. Zc The lifting size can also be referred to as an expansion factor, a lifting factor, a lifting value, an expansion value, an expansion coefficient, etc., and is described as a lifting value in the present application.

[0084] For example, an exponent matrix H of a QC-LDPC with a size of m*n b As shown below:

[0085] As can be seen, the exponent matrix H b has a size of 4 rows and 24 columns, and the elements represents a circulant permutation matrix, and i represents a cyclic shift value, where 0≤i≤Z c -1, and i is an integer. In addition, the "-1" in the exponent matrix H b represents an all-zero matrix, and "0" represents an identity matrix.

[0086] Here, Z c =4, i=0 / 1 / 2 / 3 are taken as examples to illustrate the cyclic shift. , respectively, as shown below:

[0087] Exemplarily, the zero elements in the exponent matrix H b may be represented in other forms in addition to "-1", such as using "-" or a null value to represent an all-zero matrix.

[0088] 3. Spatially coupled low density parity check (SC-LDPC) code

[0089] The check matrix H of the SC-LDPC sc is shown below:

[0090] where H sc is constructed by coupling L groups of submatrices, each group of submatrices in the L groups of submatrices is the same, and each group of submatrices in the L groups of submatrices includes w+1 submatrices, which can be represented as H0, H1, …, H w Each submatrix H i is an M*N matrix, and thus the matrix size of H sc is [M*(w+L)]*(N*L). Here, L is referred to as a coupling length, and w is referred to as a coupling width.

[0091] Exemplarily, the construction of each submatrix H i may refer to the check matrix H shown in FIG. 1.

[0092] Specifically, if the w+1 sub-matrices in each of the L groups of sub-matrices are the same, the SC-LDPC code is referred to as a time-invariant SC-LDPC code; if the w+1 sub-matrices in each of the L groups of sub-matrices are different, the SC-LDPC code is referred to as a time-varying SC-LDPC code.

[0093] 4. Quasi-cyclic spatial-coupled low density parity check (QC SC-LDPC) code

[0094] The check matrix B of the QC SC-LDPC is shown as follows:

[0095] The B is constructed by coupling L groups of sub-matrices, each of the L groups of sub-matrices is the same, and each of the L groups of sub-matrices includes w+1 sub-matrices, which can be represented as B0, B1, …, B w Each of the sub-matrices B i is an m*n matrix, and thus the matrix H sc has a matrix size of [m*(w+L)]*(n*L). The L here is referred to as a coupling length, and the w is referred to as a coupling width.

[0096] Exemplarily, the construction of each of the sub-matrices B i can refer to the exponent matrix H b of the QC-LDPC shown above, which has a size of m*n.

[0097] Specifically, if the w+1 sub-matrices in each of the L groups of sub-matrices are the same, the QC SC-LDPC code is referred to as a time-invariant QC SC-LDPC code; if the w+1 sub-matrices in each of the L groups of sub-matrices are different, the QC SC-LDPC code is referred to as a time-varying QC SC-LDPC code.

[0098] 5. Non-zero elements and zero elements

[0099] In this application, the zero element in the check matrix represents that there is no connection between the variable node and the check node. The non-zero element in the check matrix represents that there is a connection between the variable node and the check node.

[0100] This application does not limit the specific forms of the zero element and the non-zero element. For example, in the exponent matrix H b , "-1" can be used to represent the zero element, and "non-negative value" can be used to represent the non-zero element. For another example, in the check matrix H, "0" can be used to represent the zero element, and "1" can be used to represent the non-zero element.

[0101] For the convenience of description, "0" is uniformly used to represent the zero element, and "1" is uniformly used to represent the non-zero element in the following.

[0102] 6. Column weight and row weight

[0103] For a column of a matrix, the column weight can refer to the number of non-zero elements contained in the column. For a row of a matrix, the row weight can refer to the number of non-zero elements contained in the row. For example, as shown in FIG. 1, the column weight of the first column of the check matrix H is 2, and the row weight of the first row is 4. For another example, the column weight of the first column of the parity check matrix H b as described above is 4, and the row weight of the first row is 20.

[0104] 7. Basic structure of check matrix

[0105] As shown in (a) of FIG. 3, the check matrix can include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region can include the A part and the B part shown in (b) of FIG. 3, where the A part corresponds to information bits, and the B part is a square matrix and corresponds to core check bits, and the B part can also be a region corresponding to a check column with a column weight greater than 1. The all-zero region can correspond to the C part of (b) of FIG. 3, which is an all-zero matrix. The incremental redundancy region can correspond to the D part of (b) of FIG. 3. The raptor-like region can correspond to the E part of (b) of FIG. 3, which can be a unit matrix or a lower triangular matrix, and corresponds to check bits for low rate extension.

[0106] The base matrix of the LDPC code shown in FIG. 3 adopts a "raptor-like" structure, and can be gradually extended to a low rate from a high rate core matrix, so that various code rates can be flexibly supported. In actual use, as shown in (a) of FIG. 3, the first X rows and the first Y columns of the check matrix can be intercepted, and as the code rate gradually decreases from high to low, X and Y gradually increase, and the region of the matrix used also gradually expands. The difference between X and Y is the number of information columns.

[0107] 8. Information transmission process

[0108] Figure 4 is a schematic diagram of an information transmission process. As shown in Figure 4, information is transmitted from a source to a destination through source encoding, channel encoding, modulation, air interface transmission, demodulation, channel decoding, and source recovery. The upper layer processes (including source encoding, channel encoding, and modulation) are performed at the transmitting end (i.e., the encoding device described below), and the lower layer processes (including demodulation, channel decoding, and source recovery) are performed at the receiving end (i.e., the decoding device described below).

[0109] Embodiments of the present application mainly relate to source encoding, channel encoding, channel decoding, and source recovery as shown in Figure 4.

[0110] Figure 5 is a schematic diagram of a system architecture 100 suitable for embodiments of the present application. As shown in Figure 5, the system architecture 100 can include an encoding device and a decoding device. The encoding device is not limited to one or more, and the decoding device is not limited to one or more. For example, one of the encoding device and the decoding device can be a network device as shown in Figure 5, and the other can be a terminal device 1 or a terminal device 2 as shown in Figure 5.

[0111] The terminal device in the embodiments of the present application includes various communication kits (which can include, for example, an antenna, a power supply template, a cable, a wireless fidelity (WiFi) module, and the like) having a wireless communication function, a handheld device, a vehicle-mounted device, or other processing devices connected to a wireless modem, and can specifically refer to a user equipment (UE), a user, an access terminal, a user unit, a user station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, a user device, a wireless modem, a machine type communication device, or other processing devices connected to a wireless modem. It can also be a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a terminal in self driving, a terminal in remote medical, a terminal in smart grid, a terminal in transportation safety, a terminal in smart city, a terminal in smart home, or a terminal device in future communication network, and the like. Of course, the terminal device in the present application can also refer to a chip, a modem, a system on a chip (SoC), or a communication platform that can include a radio frequency (RF) part, etc. mainly responsible for the relevant communication function in the device, etc.

[0112] The network device in the embodiments of the present application can include, but is not limited to, a next-generation base station (gNodeB, gNB) in a 5th generation (5th generation, 5G) communication system, a base station in a future mobile communication system, an access point (access point, AP) in a wireless fidelity (wireless fidelity, WiFi) system, a wireless relay node, a wireless backhaul node, a transmission point (transmission point, TP) or a transmission reception point (transmission reception point, TRP), an evolved node B (evolved node B, eNB) in a long term evolution (long term evolution, LTE) system, a network device in a non-terrestrial network (non-terrestrial network, NTN) communication system, and the like. The network device can also be one or a group (i.e., multiple) of antenna panels of a base station. In addition, the network device can also be a network node constituting a gNB or a TP, such as a baseband processing unit (base band unit, BBU), a centralized unit (centralized unit, CU), a distributed unit (distributed unit, DU), or a radio unit (radio unit, RU), and the like. Alternatively, the network device can also be a device in a device-to-device (device-to-device, D2D) communication system, a machine-to-machine (machine to machine, M2M) communication system, an Internet of Things (Internet of Things, IoT), a vehicle-to-vehicle communication system, or other communication systems that perform network side functions, and the like, without limitation.

[0113] In the embodiments of the present application, the device for implementing the function of the terminal device can be a terminal device, or a device capable of supporting the terminal device to implement the corresponding function, such as a chip (or chip system) or circuit, which can be installed in the terminal device. In addition, the device for implementing the function of the network device can be a network device, or a device capable of supporting the network device to implement the corresponding function, such as a chip (or chip system) or circuit, which can be installed in the network device. Alternatively, the chip system can include a chip, or include a chip and other discrete devices.

[0114] In the system architecture shown in FIG. 5, in uplink communication, the encoding device is terminal device 1 or terminal device 2, and the decoding device is the network device. In downlink communication, the encoding device is the network device, and the decoding device is terminal device 1 or terminal device 2.

[0115] SC-LDPC codes connect multiple LDPC block codes together through spatial coupling, forming a coupled chain. This coupling structure allows SC-LDPC codes to utilize information from adjacent block codes during decoding, resulting in excellent decoding performance. In practical applications, a portion of the SC-LDPC code's parity-check matrix needs to be truncated for encoding and decoding based on the service code rate, which may cause a loss in the encoding or decoding performance of the SC-LDPC code.

[0116] In view of the above-mentioned technical problems, this application aims to provide an LDPC-based encoding and decoding method. By designing the matrix features of LDPC codes, the encoding and decoding performance of various LDPC codes can be guaranteed.

[0117] Figure 6 is a schematic flowchart of the LDPC-based communication method 200 provided in this application. Steps 210 to 214 in the communication method 200 can be executed by an encoding device. Unless otherwise specified, "encoding device" in this application can refer to the encoding device itself (e.g., a terminal device or network device), a component within the encoding device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the encoding device. Step 216 can be executed by a decoding device. Unless otherwise specified, "decoding device" in this application can refer to the decoding device itself (e.g., a terminal device or network device), a component within the decoding device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the decoding device.

[0118] Step S210: The encoding device acquires the information bit sequence.

[0119] In step S212, the encoding device performs LDPC encoding on the information bit sequence according to the first LDPC matrix to obtain the codeword sequence.

[0120] Specifically, the first LDPC matrix includes a first region, the non-zero elements of which satisfy a first rule, which is used to indicate the density of the non-zero elements included in the first region.

[0121] For example, the first LDPC matrix can be the parity check matrix H of the SC-LDPC code. sc The parity-check matrix B of the QC-LDPC code, the parity-check matrix H of the LDPC code, and the exponent matrix H of the QC-LDPC code. b This application does not limit this to such matters.

[0122] The first LDPC matrix is ​​used as the parity check matrix H of the SC-LDPC code in the following text. scThe first region and the first rule are described by taking the parity check matrix H of the LDPC code as an example.

[0123] The first LDPC matrix is the parity check matrix H of the SC-LDPC code. sc

[0124] The first LDPC matrix includes a first matrix composed of S groups of sub-matrices, and the S groups of sub-matrices are the parity check matrix H of the SC-LDPC code. sc Any S groups of consecutive sub-matrices in the first matrix, so it can be concluded that the first matrix is a matrix of [M*(w+S)]*(N*S).

[0125] FIG. 7 shows a first matrix included in the H sc and the H sc of the coupling length L=8 and the coupling width w=3. The first matrix shown in FIG. 7 is composed of the 1st group of sub-matrices to the Sth group of sub-matrices of the L groups of sub-matrices. The first matrix can also be composed of the 2nd group of sub-matrices to the S+1th group of sub-matrices of the L groups of sub-matrices, or the first matrix can also be composed of the 3rd group of sub-matrices to the S+2th group of sub-matrices of the L groups of sub-matrices, and the present application does not limit this. FIG. 7 is only an example, and the coupling length L and the coupling width w can also have other values, which are not limited by the present application.

[0126] For example, the value range of S can be associated with the value of the coupling width w, for example, 2w≤S≤5w, 5≤w≤20. Or, 8≤S≤55.

[0127] Specifically, the first region can be composed of the 1st to M*Sth rows and the 1st to N*Sth columns of the first matrix. For example, the first region in FIG. 7 can be composed of the 1st to M*5th rows and the 1st to N*5th columns of the first matrix.

[0128] FIG. 8 shows another example of a first matrix included in the H sc and the H sc of the coupling length L=8 and the coupling width w=3. The first matrix shown in FIG. 8 is composed of the 1st group of sub-matrices to the Sth group of sub-matrices of the L groups of sub-matrices. The first matrix can also be composed of the 2nd group of sub-matrices to the S+1th group of sub-matrices of the L groups of sub-matrices, or the first matrix can also be composed of the 3rd group of sub-matrices to the S+2th group of sub-matrices of the L groups of sub-matrices, and the present application does not limit this. FIG. 8 is only an example, and the coupling length L and the coupling width w can also have other values, which are not limited by the present application.

[0129] For example, the value range of S can be associated with the value of the coupling width w, for example, 2w≤S≤5w, 5≤w≤20. Or, 8≤S≤55.

[0130] Specifically, the first region can be composed of any M*A rows and 1~N*S columns of the first matrix, A

[0131] Exemplarily, the first rule applicable to the first region shown in the above Fig. 7 or the above Fig. 8 can be any of the following:

[0132] d(H)-d(H')≤θ*d(H), d(H)-d(H')≤θ*d(H'), d(H)-d(H')≤α,

[0133] wherein d(H) represents the number of non-zero elements included in the first matrix, d(H') represents the number of non-zero elements included in the first region; or d(H) represents the sum of non-zero elements included in the first matrix, d(H') represents the sum of non-zero elements included in the first region; or d(H) represents the average row weight of the first matrix, d(H') represents the average row weight of the first region; or d(H) represents the average column weight of the first matrix, d(H') represents the average column weight of the first region; 0<θ<1, α≥1.

[0134] Exemplarily, θ≤1 / 4, 1 / 3, 1 / 2, 1 / 5 or 1 / 10, which are not limited in the present application.

[0135] Optionally, the first region further includes a second matrix. Exemplarily, the second matrix can be composed of part of rows in the first region or the second matrix can be composed of part of columns in the first region, etc., which are not limited in the present application. The non-zero elements included in the second matrix satisfy a second rule, which is used to indicate the density of the non-zero elements included in the second matrix. Exemplarily, the second rule applicable to the second matrix can be any of the following: d(H')-d(H”)≤θ*d(H'), d(H')-d(H”)≤θ*d(H”), d(H')-d(H”)≤α,

[0136] wherein d(H”) represents the number of non-zero elements included in the second matrix, d(H') represents the number of non-zero elements included in the first region; or d(H”) represents the sum of non-zero elements included in the second matrix, d(H') represents the sum of non-zero elements included in the first region; or d(H”) represents the average row weight of the second matrix, d(H') represents the average row weight of the first region; or d(H”) represents the average column weight of the second matrix, d(H') represents the average column weight of the first region; 0<θ<1, α≥1.

[0137] For example, θ ≤ 1 / 4, 1 / 3, 1 / 2, 1 / 5 or 1 / 10, and this application does not limit it.

[0138] It should be noted that the above embodiments illustrate the characteristics of the first LDPC matrix by taking as an example the first LDPC matrix including a first matrix, the first matrix including a first region, the first region including a second matrix, a first rule applicable to the first region, and a second rule applicable to the second matrix. This application is not limited to this. For example, the second matrix may also include a third matrix, etc., and the density of non-zero elements included in the third matrix also satisfies certain rules.

[0139] One example is using the parity-check matrix H of the SC-LDPC code. sc Decoding can be performed using window decoding, as shown in Figure 9. Figure 9 shows H with coupling length L = 8 and coupling width w = 3. sc The window decoding process. Each decoding operation occurs in H... sc A decoding window of length S' is selected for decoding, meaning the size of the decoding window is (M*S')*(N*S'). After the current decoding window reaches its maximum iteration count or completes decoding, the decoding window will be moved to H... sc The decoder moves M rows down and N rows to the right, and continues the decoding process in the new decoding window. The S shown above can be equal to the decoding window length S', meaning the first region shown above can be any decoding window. This method ensures that the density of non-zero elements in the decoding window satisfies the first rule mentioned above, resulting in better decoding performance.

[0140] In another example, the column weights of each column in each of the L submatrices used to couple the construction of the first LDPC matrix are equal.

[0141] For example, each submatrix in L submatrixes can be denoted as Each column has the same column weight, that is... It has the form of a column regular expression.

[0142] For example, for H with coupling length L=8 and coupling width w=3 as shown in Figures 7, 8, and 9 above... sc , Each column of the submatrix composed of H0, H1, H2, and H3 has the same column weight, which can also be understood as H sc Each column has the same weight.

[0143] In another example, each of the L submatrices in the first LDPC matrix comprises w+1 submatrices, which can be represented as H0, H1, ..., H w, the elements of the first sub-matrix to the i-th sub-matrix in the w+1 sub-matrices are non-zero elements, specifically, the elements of H0, H1, …, H w , the elements of H0, H1, …, H p are non-zero elements, 0≤p≤w. Exemplarily, for the H sc with the coupling length L=8 and the coupling width w=3 shown in FIG. 7, FIG. 8, and FIG. 9, the elements of H0, H1, H2 in H0, H1, H2, H3 or the elements of H0, H1 in H0, H1, H2, H3 are non-zero elements, etc., which are not limited in the present application.

[0144] Alternatively, the number of non-zero elements included in the first sub-matrix to the i-th sub-matrix in the w+1 sub-matrices is greater than or equal to t. Specifically, the number of non-zero elements included in H0, H1, …, H w , H1, …, H p is ≥t, 0≤p≤w, t>1. Exemplarily, for the H sc with the coupling length L=8 and the coupling width w=3 shown in FIG. 7, FIG. 8, and FIG. 9, the number of non-zero elements included in H0, H1, H2 in H0, H1, H2, H3 or the number of non-zero elements included in H0, H1 in H0, H1, H2, H3 is ≥t, etc., which are not limited in the present application.

[0145] It should be noted that the case that the first LDPC matrix is the check matrix B of the QC SC-LDPC code can refer to the case that the first LDPC matrix is the check matrix H sc of the SC-LDPC code, which will not be described herein again.

[0146] (II) The first LDPC matrix is the check matrix H

[0147] In an example, the first LDPC matrix is an X*Y matrix, and the first region can be composed of the first 1~X rows and the y-th column of the first LDPC matrix. Exemplarily, the first rule applicable to the first region can be: J min ≤d(H')≤J max

[0148] wherein d(H') represents the number of non-zero elements included in the first region, 2≤J min ≤J max , 1≤y≤Y, y, Y, X are positive integers.

[0149] In another example, the first LDPC matrix is an X*Y matrix, and the first region can be composed of part of the elements in the y-th column of the first LDPC matrix. Exemplarily, the first rule applicable to the first region can be: J min≤ d(H') ≤ J max

[0150] wherein d(H') represents the number of non-zero elements included in the first region, 2≤J min ≤ J max , 1≤y≤Y, y, Y, X are positive integers.

[0151] In another example, the first LDPC matrix is an X*Y matrix, and the first region is composed of part of elements in the xth row of the first LDPC matrix. Exemplarily, the first rule applicable to the first region can be: K min ≤ d(H') ≤ K max

[0152] wherein d(H') represents the number of non-zero elements included in the first region, 3≤K min ≤ K max , 1≤x≤X, x, X, Y are positive integers.

[0153] In another example, the first LDPC matrix is an X*Y matrix, and the first region is composed of part of elements in the xth row of the first LDPC matrix. Exemplarily, the first rule applicable to the first region can be: K min ≤ d(H') ≤ K max

[0154] wherein d(H') represents the number of non-zero elements included in the first region, 3≤K min ≤ K max , 1≤x≤X, x, X, Y are positive integers.

[0155] It should be noted that the case that the first LDPC matrix is a check matrix H b of a QC-LDPC code can refer to the case that the first LDPC matrix is a check matrix H of an LDPC code, which will not be described herein again.

[0156] Exemplarily, the encoding device can divide the information bit sequence to be encoded into groups in units of a bits, and then perform linear operation on the a information bits by the encoder to obtain g check bits, and then combine the a information bits and the g check bits to obtain a codeword with a length of v=a+g. The mapping relationship from the information bits with a length of a bits to the codeword with a length of v bits can be represented by the above first LDPC check matrix. The codeword sequence can be generated according to the above first LDPC check matrix to complete the encoding process.

[0157] In step S214, the encoding device sends the above codeword sequence. Correspondingly, the decoding device acquires the codeword sequence.

[0158] Step S222, the decoding device decodes the code word sequence according to the first LDPC check matrix.

[0159] Specifically, the characteristics of the first LDPC check matrix can refer to the first LDPC check matrix of S212 described above, which will not be repeated here.

[0160] FIG. 10 is an example performance comparison diagram of the first LDPC matrix and other LDPC matrices provided by the embodiments of the present application, which is obtained under the scenario of code rate = 3 / 4, decoding window length S' = 15, and coupling width w = 6. The performance of the first LDPC matrix having the form of column regularity and the density of non-zero elements in the first region satisfying the first rule is shown by the dashed line in FIG. 10, and the performance of the LDPC matrix having the form of column regularity but the density of non-zero elements in the first region not satisfying the first rule is shown by the solid line in FIG. 10. The abscissa of FIG. 10 represents the iteration round number within the decoding window, and the ordinate represents the threshold. It can be seen that the threshold of the first LDPC matrix provided by the embodiments of the present application, whose density of non-zero elements in the first region satisfies the first rule, is significantly lower than that of the LDPC matrix whose density of non-zero elements in the first region does not satisfy the first rule, that is, under the requirement of a given bit error rate (BER), the first LDPC matrix provided by the embodiments of the present application can reduce the minimum channel condition (such as signal to noise ratio (SNR)) under which the system can work reliably, and can achieve efficient and reliable communication under a wider range of channel conditions.

[0161] FIG. 11 is another example performance comparison diagram of the first LDPC matrix and other LDPC matrices provided by the embodiments of the present application, which is obtained under the scenario of code rate = 3 / 4, decoding window length S' = 15, and coupling width w = 6. The performance of the first LDPC matrix whose elements of H0, H1, H2, and H3 in H0, H1, …, H6 are non-zero elements and the density of non-zero elements in the first region satisfies the first rule is shown by the dashed line in FIG. 11, and the performance of the LDPC matrix whose elements of H0, H1, H2, and H3 in H0, H1, …, H6 are non-zero elements but the density of non-zero elements in the first region does not satisfy the first rule is shown by the solid line in FIG. 11. The abscissa of FIG. 11 represents the iteration round number within the decoding window, and the ordinate represents the threshold. It can be seen that the threshold of the first LDPC matrix provided by the embodiments of the present application, whose density of non-zero elements in the first region satisfies the first rule, is significantly lower than that of the LDPC matrix whose density of non-zero elements in the first region does not satisfy the first rule, that is, under the requirement of a given BER, the first LDPC matrix provided by the embodiments of the present application can reduce the minimum channel condition (such as SNR) under which the system can work reliably, and can achieve efficient and reliable communication under a wider range of channel conditions.

[0162] As can be seen from the performance comparison charts of FIG. 10 and FIG. 11, the first LDPC matrix obtained by the communication method 200 of the embodiments of the present application can improve the encoding and decoding performance of various types of LDPC codes.

[0163] The method embodiments provided by the present application are described in detail above in combination with FIG. 1 to FIG. 11, and the device embodiments of the present application will be described below in combination with FIG. 12 to FIG. 14.

[0164] It can be understood that, in order to implement the functions in the above embodiments, the devices in FIG. 12 to FIG. 14 include the hardware structure and / or software module for performing the respective functions. Those skilled in the art should easily realize that, in combination with the units and method steps of the examples described in the embodiments disclosed in the present application, the present application can be implemented in the form of hardware or a combination of hardware and computer software.

[0165] FIG. 12 and FIG. 13 are structural schematic diagrams of possible devices provided by the embodiments of the present application. These devices can be used to implement the functions of the encoding device or the decoding device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0166] As shown in FIG. 12, the device 10 includes a transceiver unit 11 and a processing unit 12.

[0167] When the device 10 is used to implement the functions of the encoding device in the above method embodiments, the transceiver unit 11 is configured to perform the transceiving steps of the encoding device, such as step S214, and the processing unit 12 is configured to perform the processing steps of the encoding device, such as steps S210 and S212. When the device 10 is used to implement the functions of the decoding device in the above method embodiments, the transceiver unit 11 is configured to perform the transceiving steps of the decoding device, such as step S214, and the processing unit 12 is configured to perform the processing steps of the decoding device, such as step S216.

[0168] For more detailed description of the transceiver unit 11 and the processing unit 12, reference can be made to the related description in the above method embodiments, which will not be described herein.

[0169] As shown in FIG. 13, the device 20 includes a processor 21. The processor 21 is coupled with a memory 23, and the memory 23 is configured to store instructions. When the device 20 is used to implement the above method, the processor 21 is configured to execute the instructions in the memory 23 to implement the functions of the above processing unit 12.

[0170] Optionally, the device 20 further includes the memory 23. The memory 23 can be integrated in the processor 21 (in the case of cache, the relevant part of the data instructions is read and written), and in addition, can include a separate memory (to store the protocol stack).

[0171] Optionally, the apparatus 20 further includes an interface circuit 22. The interface circuit can be referred to as a communication interface. The processor 21 and the interface circuit 22 are coupled to each other. It can be understood that the interface circuit 22 can be a transceiver or an input / output interface. When the apparatus 20 is configured to implement the method described above, the processor 21 is configured to execute instructions to implement the functions of the processing unit 12 described above, and the interface circuit 22 is configured to implement the functions of the transceiver unit 11 described above.

[0172] Optionally, the apparatus 20 can be an encoding apparatus or a decoding apparatus, and the interface circuit can be a transceiver.

[0173] Optionally, the apparatus 20 can be a chip applied to an encoding apparatus or a decoding apparatus, and the interface circuit can be an input / output interface.

[0174] For example, when the apparatus 20 is a chip applied to an encoding apparatus or a decoding apparatus, the chip implements the functions of the encoding apparatus or the decoding apparatus in the method embodiments described above. The chip receives information from other modules (such as a radio frequency module or an antenna) in the encoding apparatus or the decoding apparatus, and the information is sent by other devices to the encoding apparatus or the decoding apparatus; or the chip sends information to other modules (such as a radio frequency module or an antenna) in the encoding apparatus or the decoding apparatus, and the information is sent by the encoding apparatus or the decoding apparatus to other devices.

[0175] FIG. 14 is a schematic diagram of a chip system 30 provided by an embodiment of the present application. The chip system 30 (or also referred to as a processing system) includes a logic circuit 31 and an input / output interface 32.

[0176] The logic circuit 31 can be a processing circuit in the chip system 30. The logic circuit 31 can be coupled to a storage unit, call instructions in the storage unit, so that the chip system 30 can implement the methods and functions of the embodiments of the present application. The input / output interface 32 can be an input / output circuit in the chip system 30, output information processed by the chip system 30, or input data or signaling information to be processed by the chip system 30 for processing.

[0177] As a solution, the chip system 30 is configured to implement the operations performed by the encoding apparatus or the decoding apparatus in the various method embodiments described above.

[0178] For example, the logic circuit 31 is configured to implement processing-related operations performed by the encoding apparatus or the decoding apparatus in the method embodiments described above; and the input / output interface 32 is configured to implement sending and / or receiving-related operations performed by the encoding apparatus or the decoding apparatus in the method embodiments described above.

[0179] The application further provides a communication device, comprising a processing circuit coupled with a memory, the memory being configured to store computer programs or instructions and / or data, and the processing circuit being configured to execute the computer programs or instructions stored in the memory or read the data stored in the memory to perform the method in any of the above method embodiments. Optionally, the processing circuit is one or more. Optionally, the communication device comprises the memory. Optionally, the memory is one or more. Optionally, the memory is integrated with the processing circuit or is separately arranged.

[0180] The application further provides a chip, comprising a processing circuit coupled with a memory, the memory being configured to store computer programs or instructions, and the processing circuit being configured to execute the computer programs or instructions stored in the memory to implement the method performed by the encoding device or the decoding device in any of the above method embodiments. The memory can be located in the chip or outside the chip, and is not limited herein.

[0181] The application further provides a computer readable storage medium, which stores computer instructions for implementing the method performed by the encoding device or the decoding device in any of the above method embodiments.

[0182] The application further provides a computer program product, comprising instructions which, when executed by a computer, implement the method performed by the encoding device or the decoding device in any of the above method embodiments.

[0183] The application further provides a communication system, comprising at least one of the encoding device or the decoding device in any of the above embodiments.

[0184] The explanations and beneficial effects of the related contents in any of the above devices can refer to the corresponding method embodiments provided above, and will not be repeated here.

[0185] It can be understood that the processing circuit in the embodiments of the application can be a processor or a circuit in the processor for performing processing operations, and the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0186] The method steps in the embodiments of the present application can be realized by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, a register, a hard disk, a mobile hard disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in the sending end device or the receiving end device. Of course, the processor and the storage medium can also exist as discrete components in the sending end device or the receiving end device.

[0187] In the above embodiments, the implementation can be wholly or partially realized by software, hardware, firmware or any combination thereof. When realized by software, the implementation can be wholly or partially realized in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When loaded and executed by a computer, the computer programs or instructions perform the flow or function described in the embodiments of the present application. The computer can be a general purpose computer, a special purpose computer, a computer network, a network device, a user equipment or other programmable apparatus. The computer programs or instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another, for example, the computer programs or instructions can be transferred from one website site, computer, server or data center to another website site, computer, server or data center through a wired or wireless manner. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center and the like integrated with one or more available media. The available media can be a magnetic medium, for example, a floppy disk, a hard disk, a magnetic tape; an optical medium, for example, a digital video disc; and a semiconductor medium, for example, a solid state disk.

[0188] In various embodiments of the present application, the terms and / or descriptions of different embodiments are consistent and can be mutually referred to if there is no special description and no logical conflict. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0189] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the application is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present application. It will be understood that the examples given are intended to be illustrative only and that the following examples are to be construed as merely setting forth typical embodiments of the application and that no limitation to the scope of the application is intended.

Claims

1. An encoding method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain the information bit sequence; The information bit sequence is LDPC encoded according to the first LDPC matrix to obtain a codeword sequence; The first LDPC matrix includes a first region, and the non-zero elements in the first region satisfy a first rule, which is used to indicate the density of the non-zero elements in the first region.

2. A decoding method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain the codeword sequence; LDPC decoding is performed on the codeword sequence according to the first LDPC matrix; The first LDPC matrix includes a first region, and the non-zero elements in the first region satisfy a first rule, which is used to indicate the density of the non-zero elements in the first region.

3. The method according to claim 1 or 2, characterized in that, The first LDPC matrix is ​​constructed by coupling L groups of submatrices. Each group of submatrices in the L groups of submatrices is the same. Each group of submatrices in the L groups of submatrices includes w+1 submatrices, and each submatrice in the w+1 submatrices is an M*N matrix. The first LDPC matrix includes a first matrix, which is composed of S groups of sub-matrices. The S groups of sub-matrices are any S groups of consecutive sub-matrices in the L groups of sub-matrices. The first matrix is ​​a matrix of [M*(w+S)]*(N*S). The first region is composed of rows 1 to M*S and columns 1 to N*S of the first matrix, or the first region is composed of any M*A rows and columns 1 to N*S of the first matrix; Where A < w + S, S < L, and M, N, L, S, and w are all integers.

4. The method according to claim 3, characterized in that, The first rule is any of the following: d(H)-d(H')≤θ*d(H), d(H)-d(H')≤θ*d(H'), d(H)-d(H')≤α, Wherein, d(H) represents the number of non-zero elements in the first matrix, and d(H') represents the number of non-zero elements in the first region; or, d(H) represents the sum of the non-zero elements in the first matrix, and d(H') represents the sum of the non-zero elements in the first region; or, d(H) represents the average row weight of the first matrix, and d(H') represents the average row weight of the first region; or, d(H) represents the average column weight of the first matrix, and d(H') represents the average column weight of the first region; 0 < θ < 1, α ≥ 1.

5. The method according to claim 3 or 4, characterized in that, The column weight of each column in each submatrix of the L submatrixes is equal.

6. The method according to any one of claims 3 to 5, characterized in that, All elements in the first to the ith submatrix of the w+1 submatrixes are non-zero elements, or the number of non-zero elements in the first to the ith submatrixes of the w+1 submatrixes is greater than or equal to t, 1≤i≤w+1, t>1.

7. The method according to claim 1 or 2, characterized in that, The first LDPC matrix is ​​an X*Y matrix, and the first region consists of rows 1 to X and column y of the first LDPC matrix. The first rule is: J min ≤d(H')≤J max Where d(H') represents the number of non-zero elements in the first region, 2≤J min ≤J max , 1≤y≤Y, where y, Y, and X are all positive integers.

8. The method according to claim 7, characterized in that, The first region is composed of a subset of elements in the y-th column of the first LDPC matrix.

9. The method according to claim 1 or 2, characterized in that, The first LDPC matrix is ​​an X*Y matrix, and the first region consists of the x-th row and columns 1 to Y of the first LDPC matrix. The first rule is: K min ≤d(H')≤K max Where d(H') represents the number of non-zero elements in the first region, 3≤K min ≤K max , 1≤x≤X, where x, X, and Y are all positive integers.

10. The method according to claim 9, characterized in that, The first region consists of a subset of elements from the x-th row of the first LDPC matrix.

11. A communication device, characterized in that, Including processor and interface circuitry, The interface circuit is used to receive signals and transmit the signals to the processor or send signals processed by the processor to cause the processor to perform the method as described in any one of claims 1 to 10.

12. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed by a communication device, enable the method as described in any one of claims 1 to 10 to be implemented.

13. A computer program product, characterized in that, Includes a computer program, which, when run, enables the method as described in any one of claims 1 to 10 to be implemented.

14. A chip, characterized in that, The chip includes a processor and a communication interface. The processor reads instructions stored in the memory through the communication interface to implement the method as described in any one of claims 1 to 10.

15. A communication device, characterized in that, Includes units or modules for implementing the method as described in any one of claims 1 to 10.

16. A processor, characterized in that, Used to perform the method as described in any one of claims 1 to 10.

17. A communication system, characterized in that, Includes means for performing the method as claimed in any one of claims 1, 3-10, and means for performing the method as claimed in any one of claims 2-10.

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