Three-dimensional semiconductor memory and electronic device comprising same

Abstract

Embodiments of the present disclosure provide a three-dimensional semiconductor memory, comprising a substrate, a plurality of active layers arranged in an array on the substrate, a plurality of bit lines, and a shielding structure. Each of the plurality of bit lines is connected to one end of the corresponding active layer, and the plurality of bit lines extend in a second direction and are stacked on the substrate in a third direction. Each of a plurality of memory cells is connected to the other end of the corresponding active layer. The shielding structure comprises a main body portion and a plurality of shielding portions. The shielding portions extend in the second direction, the main body portion and the shielding portions are made of a conductive material, and the main body portion is electrically connected to the shielding portions. In the third direction, at least one shielding portion is arranged between adjacent bit lines. In the embodiments of the present disclosure, by forming the shielding portions between the stacked bit lines, the shielding portions are electrically connected to the main body portion, and are connected to a fixed potential terminal by means of the main body portion, reducing the parasitic capacitance between the bit lines.

Description

Three-dimensional semiconductor memory and electronic device thereof

[0001] The present application claims priority to the Chinese patent application No. 202411099297.1, filed on August 9, 2024, and entitled "Three-dimensional semiconductor memory and electronic device thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, in particular to a three-dimensional semiconductor memory structure and an electronic device thereof. BACKGROUND

[0003] With the development of the integration density of dynamic memory towards higher direction, higher requirements are put forward for the arrangement mode of transistors in the dynamic memory array structure and the size of the transistors. However, due to the limitations of lithography machines and various electrical parasitic effects and other manufacturing factors, there is a limit to the reduction of the critical dimension, therefore, how to make a chip with higher storage density on a wafer is the research direction of many researchers and semiconductor practitioners.

[0004] The emergence of three-dimensional dynamic random memory (3D DRAM), especially 3D DRAM including multilayer horizontal cell (MHC), generally includes a plurality of horizontally extending bit line structures stacked on a substrate. In the vertical direction, the parasitic capacitance exists between the stacked bit line structures. When the number of layers is large, the existence of parasitic capacitance easily affects the overall electrical performance of the storage structure, and in severe cases, causes the storage structure to deviate or fail to work. Therefore, how to eliminate the parasitic capacitance in the stacked structure has been a problem to be solved in the field. SUMMARY

[0005] Embodiments of the present disclosure provide a three-dimensional semiconductor memory, which at least helps to reduce the parasitic capacitance in the stacked structure, prevent mutual influence between different cells, and improve the overall electrical performance of the storage cell.

[0006] In an aspect, embodiments of the present disclosure provide a three-dimensional semiconductor memory, comprising:

[0007] a substrate;

[0008] a plurality of active layers arranged in an array on the substrate along a second direction and a third direction;

[0009] a plurality of bit lines respectively connected to one end of the active layers along a first direction, the plurality of bit lines extending along the second direction, and the plurality of bit lines being stacked on the substrate along the third direction;

[0010] a plurality of storage units respectively connected to another end of the active layer away from the bit line along a first direction; the first direction, the second direction and the third direction intersect with each other;

[0011] a shielding structure including a main body portion and a plurality of shielding portions extending along the second direction, the main body portion and the shielding portions being made of a conductive material, the main body portion and the shielding portions being electrically connected;

[0012] wherein along the third direction, at least one shielding portion is provided between adjacent bit lines.

[0013] In some embodiments, a projection of the shielding portion on the substrate overlaps with a projection of the bit line on the substrate, along the first direction, a length of the overlapping portion is d1, a length of the bit line along the first direction is d2, wherein the d1 is greater than or equal to d2 / 2.

[0014] In some embodiments, a thickness of the shielding portion along the third direction is less than or equal to a thickness of the bit line along the third direction.

[0015] In some embodiments, along the second direction, a length of the shielding portion is greater than or equal to a length of the bit line.

[0016] In some embodiments, along the second direction, a length of the main body portion is less than or equal to a length of the bit line.

[0017] In some embodiments, a plurality of the shielding portions are respectively located on opposite sides of the main body portion along the first direction.

[0018] In some embodiments, along a cross section of the first direction and the third direction, the main body portion has a "U" shaped cross section.

[0019] In some embodiments, the main body portion and the plurality of shielding portions are an integral structure.

[0020] In some embodiments, a second dielectric layer is provided between the bit line and the main body portion, a first dielectric layer and the second dielectric layer are provided between the bit line and the shielding portion.

[0021] In some embodiments, a material of the first dielectric layer and / or the second dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material.

[0022] In some embodiments, the conductive material includes one or more of Ti, Ta, W, Cu, Al, TiN, TaN.

[0023] In some embodiments, the main body portion comprises a plurality of sub-main body portions, the plurality of sub-main body portions extend along the third direction and are arranged at intervals along the second direction.

[0024] In some embodiments, an insulating medium layer is further arranged between the main body portion and the substrate.

[0025] In some embodiments, the storage unit comprises one or more of a capacitive storage unit, a phase change storage unit, and a resistive switching storage unit.

[0026] In some embodiments, the three-dimensional semiconductor memory further comprises a plurality of word lines, the plurality of word lines respectively extend along the third direction and correspond to the plurality of active layers stacked along the third direction.

[0027] Another aspect of the embodiments of the present disclosure further provides an electronic device, comprising: a processor; and

[0028] a memory, wherein the memory is coupled to the processor, and at least one of the memory and the processor comprises the three-dimensional semiconductor memory according to any of the embodiments of the present disclosure.

[0029] The technical scheme provided by the embodiments of the present disclosure has at least the following advantages: the three-dimensional semiconductor memory provided by the embodiments of the present disclosure comprises a substrate, a plurality of active layers located on the substrate, the plurality of active layers being arranged in an array on the substrate, a plurality of bit lines respectively connected to one end of the active layers, the plurality of bit lines extending along a second direction and being stacked on the substrate along a third direction, and a shielding structure comprising a main body portion and a plurality of shielding portions, the shielding portions extending along the second direction, the main body portion and the shielding portions being composed of a conductive material, and the main body portion being electrically connected to the shielding portions, wherein at least one shielding portion is arranged between adjacent bit lines along the third direction. In the embodiments of the present disclosure, the shielding portions are formed between the stacked bit lines, the shielding portions are electrically connected to the main body portion, and the main body portion is connected to a fixed potential end, so as to realize electrical isolation between the stacked bit lines, reduce parasitic capacitance between the bit lines, and further reduce signal interference between adjacent bit lines, thereby improving the overall electrical performance of the stacked device. BRIEF DESCRIPTION OF DRAWINGS

[0030] One or more embodiments are illustrated by way of example in the drawings that are not intended to be limiting of the embodiments so far as they are in conformity with the patent statutes. In the drawings:

[0031] Fig. 1 is a three-dimensional schematic view of a three-dimensional semiconductor memory according to an embodiment of the present disclosure;

[0032] Fig. 2 is a three-dimensional schematic view of a partial structure of a three-dimensional semiconductor memory according to an embodiment of the present disclosure;

[0033] Fig. 3 is a partial cross-sectional schematic view of the three-dimensional schematic view shown in Fig. 1;

[0034] Fig. 4 is an enlarged schematic view of a dashed portion in the cross-sectional schematic view shown in Fig. 3;

[0035] Fig. 5 is a three-dimensional schematic view of a three-dimensional semiconductor memory according to another embodiment of the present disclosure;

[0036] Fig. 6 is a partial cross-sectional schematic view of a three-dimensional semiconductor memory according to another embodiment of the present disclosure;

[0037] Figs. 7-18 are schematic views of respective steps in a method of manufacturing a three-dimensional semiconductor memory according to an embodiment of the present disclosure;

[0038] Fig. 19 is a schematic block diagram of a structure of an electronic device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] The technical solutions of the present disclosure will be described in further detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0040] The present disclosure will be described in greater detail in the following paragraphs with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. The advantages and features of the present disclosure will become more apparent from the following description and the claims. It should be noted that the accompanying drawings are simplified and use non-precise proportions only to facilitate, clarify and assist in the explanation of the embodiments of the present disclosure.

[0041] It can be understood that the meanings of "on", "over", and "above" in the present disclosure should be interpreted in the broadest way, such that "on" not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes "on" something with intervening features or layers therebetween.

[0042] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects, and do not necessarily mean a specific order or sequence.

[0043] In the embodiments of the present disclosure, the term "layer" refers to a material portion including a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Furthermore, the layer can be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0044] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0045] As known from the background, the three-dimensional dynamic random access memory includes a plurality of layers of horizontal storage structures. In some structures, the bit lines extend in a horizontal direction parallel to the substrate. The bit lines of different layers of storage structures are stacked in a vertical direction. The stacked bit lines are connected to the peripheral circuit through the lead structure of the step structure to realize input or output of electrical signals. When the number of stacked storage structures increases, the number of stacked bit lines also increases, so that the parasitic capacitance between the stacked bit lines accumulates. The existence of the parasitic capacitance interferes with the signal transmission on the bit lines. In severe cases, signal loss or signal error occurs, thereby affecting the overall electrical stability of the storage structure.

[0046] The embodiments of the present disclosure provide a three-dimensional semiconductor memory. By providing a shielding structure, the parasitic capacitance between the stacked bit lines is effectively reduced, and the electrical performance and electrical stability of the three-dimensional semiconductor memory are improved. In the embodiments of the present disclosure, the bit line not only includes the bit line part of the storage array region, but also includes the bit line part of the step region. The shielding structure is provided between adjacent bit lines to reduce the parasitic capacitance between adjacent bit lines and improve the signal transmission of the bit line signal.

[0047] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the reader to better understand the embodiments of the present disclosure. However, the technical solutions claimed in the embodiments of the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0048] Embodiment of the present disclosure provides a three-dimensional semiconductor memory, which will be described in detail below in combination with the accompanying drawings. FIG. 1 is a schematic diagram of a three-dimensional structure of a three-dimensional semiconductor memory provided by an embodiment of the present disclosure, FIG. 2 is a schematic diagram of a partial structure of a three-dimensional semiconductor memory provided by an embodiment of the present disclosure, FIG. 3 is a partial sectional view along a first direction X and a third direction Z of the schematic diagram of the three-dimensional structure of the three-dimensional semiconductor memory shown in FIG. 1, and FIG. 4 is an enlarged schematic diagram of a dashed portion in the sectional view shown in FIG. 3.

[0049] Referring to FIGS. 1-4, the three-dimensional semiconductor memory includes a substrate 110, a plurality of active layers 106 which are respectively arranged in an array on the substrate 110 along a second direction Y and a third direction Z, a plurality of bit lines 103 which are respectively connected to one end of the plurality of active layers 106 at the same layer and electrically connected to the active layers 106, a plurality of storage nodes 105 which are respectively connected to the other end of the plurality of active layers 106 away from the bit lines 103 along a first direction X, and a shielding structure 100 which includes a main body 101 and a plurality of shielding portions 102, the plurality of shielding portions 102 extend along the second direction Y and are electrically connected to the main body 101, and at least one shielding portion 102 is arranged between adjacent bit lines 103 along the third direction Z.

[0050] As shown in FIG. 1, the three-dimensional semiconductor memory forms a stacked structure on the substrate 110, i.e., arranged in an array along the second direction Y and the third direction Z respectively. In the embodiment of the present disclosure, the first direction X, the second direction Y and the third direction Z are perpendicular to each other, wherein the plane determined by the first direction X and the second direction Y is parallel to the surface of the substrate 110. In some embodiments, the first direction X, the second direction Y and the third direction Z can be perpendicular to each other, and in actual applications, the included angle between any two of the first direction X, the second direction Y and the third direction Z is not 0° or 180°. For ease of description, the first direction X, the second direction Y and the third direction Z are perpendicular to each other as an example for detailed description. The substrate 110 can be selected from materials suitable for semiconductor processing, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, germanium silicon, germanium on insulator (GOI) or silicon on insulator (SOI), etc.

[0051] The bit line 103 extends along a second direction Y parallel to the surface of the substrate 110, and the same bit line 103 is electrically connected to a plurality of active layers 106 located at the same layer. In some embodiments, the bit line 103 is in direct contact with and electrically connected to the active layer 106. In other embodiments, an interconnection layer such as a metal silicide is formed between the bit line 103 and the active layer 106 to reduce the contact resistance, which is not specifically limited in the embodiments of the present disclosure. It can be understood that the bit line 103 can be formed of a conductive material commonly used in the art, such as doped Si, doped Ge, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten silicide (WSi), cobalt silicide (CoSi), titanium silicide (TiSi), or a combination thereof.

[0052] As shown in FIGS. 1-2, the plurality of active layers 106 are arranged in an array structure along the second direction Y and the third direction Z, and the active layer 106 is located at one side of the bit line 103 along the first direction X. In the embodiments of the present disclosure, the active layer 106 has a columnar or cylindrical structure extending along the first direction X, and it can be understood that the active layer 106 can have any other shape, which is not specifically limited in the embodiments of the present disclosure. As shown in FIG. 2, the active layer 106 includes a source region 1061, a channel region 1062, and a drain region 1063 arranged in sequence along the first direction X. In some embodiments, the source region 1061 and the drain region 1063 include a first type of doped element, and the channel region 1062 can include a second type of doped element. The first type and / or the second type of doped element can be an N-type element or a P-type element. The N-type element can be a group V element such as a phosphorus (P) element, a bismuth (Bi) element, an antimony (Sb) element, or an arsenic (As) element. The P-type element can be a group III element such as a boron (B) element, an aluminum (Al) element, a gallium (Ga) element, or an indium (In) element. It can be understood that the doping type of the source region 1061 and the drain region 1063 can be different from (i.e., forming a junction structure) or the same as (i.e., forming a junction-less structure) the doping type of the channel region 1062, which is not specifically limited in the embodiments of the present disclosure. The material of the active layer 106 includes single crystal silicon, polycrystalline silicon, single crystal silicon germanium (SiGe), or an oxide semiconductor material, wherein the oxide semiconductor material is any one of In2O3 (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), ZnON (zinc oxynitride), or a combination of two or more thereof.

[0053] As shown in FIGS. 1-3, the storage node 105 is located at the other end of the active layer 106 away from the bit line 103 in the first direction, and the storage node 105 is electrically connected to the other end of the active layer 106, i.e., electrically connected to the drain region 1063. Each storage node 105 corresponds to one active layer 106. In some embodiments, the storage node 105 includes a capacitor storage node, which includes a columnar capacitor storage node or a cylindrical capacitor storage node. The capacitor storage node includes a capacitor lower electrode, a capacitor dielectric layer, and a capacitor upper electrode. The capacitor lower electrode is electrically connected to the drain region 1063 of the active layer 106, and the capacitor dielectric layer is located between the capacitor lower electrode and the capacitor upper electrode. The material of the capacitor lower electrode or the capacitor upper electrode includes a metal material, such as Ti, Ta, W, Cu, Al, TiN, TaN, or a combination thereof. The capacitor dielectric layer can be a high dielectric constant material, such as hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate, etc. In some embodiments, the storage node 105 can also be other types of storage nodes, such as a phase change storage node, a resistive switching storage node, etc.

[0054] As shown in FIG. 1, the three-dimensional semiconductor memory further includes a plurality of word lines 104 extending in a third direction Z. Each word line 104 corresponds to a plurality of active layers 106 stacked in the third direction Z. Specifically, the channel region 1062 in each active layer 106 corresponds to a word line 104, and a gate dielectric layer (not shown in the figure) is provided between the channel region 1062 and the corresponding word line 104. As shown in FIGS. 1-2, the word line 104 extends in the third direction and is located on one side of the channel region 1062. In some embodiments, a word line structure is also formed on the other side of the channel region, i.e., a double word line structure is formed, or the word line surrounds the outside of the channel region 1062, forming a gate-all-around transistor (GAA). In some embodiments, the word line 104 can also penetrate the stacked channel regions 1062, forming a channel-all-around transistor (CAA). The material of the word line 104 is any one of tungsten, tantalum, molybdenum, titanium nitride, or tantalum nitride, forming a metal gate line. In other embodiments, the material of the word line is doped polysilicon. Since the energy gap of the polysilicon is close to the energy gap of the material of the active layer as the channel, and the work function of the polysilicon can be changed by controlling the doping concentration, which is beneficial to reduce the threshold voltage between the gate and the active layer of the channel region. The type of the doping element of the doped polysilicon is the same as or different from the type of the doping element of the active layer of the channel region.

[0055] In the embodiments of the present disclosure, the shielding structure 100 includes a main body 101 and a plurality of shielding portions 102 made of conductive material, and the plurality of shielding portions 102 extend along the second direction Y. In the third direction Z, at least one shielding portion 102 is arranged between adjacent bit lines 103, that is, the shielding portion 102 made of conductive material is inserted between the two bit lines 103, so as to shield the two bit lines 103, thereby reducing the parasitic capacitance between the bit lines 103 and the bit lines 103. Although the parasitic capacitance between the bit lines 103 and the shielding portion 102 is increased, in fact, the gain of the parasitic capacitance reduction between the bit lines 103 and the bit lines 103 by inserting the shielding portion 102 is greater than the parasitic capacitance between the bit lines 103 and the shielding portion 102, that is, the gain of the parasitic capacitance reduction between the bit lines 103 and the bit lines 103 is more significant.

[0056] As shown in FIGS. 1-3, the shielding structure 100 includes a main body 101 and a plurality of shielding portions 102, the plurality of shielding portions 102 are electrically connected with the main body 101 respectively, and the shielding portions 102 extend along the second direction Y. As shown in FIG. 3, the projection of the shielding portion 102 on the substrate 110 overlaps with the projection of the bit line 103 on the substrate 110, wherein the length of the overlapping portion along the first direction X is d1, and in addition, the length of the bit line 103 along the first direction X is d2. Wherein d1 is greater than or equal to d2 / 2, that is, the shielding portion 102 covers at least half of the length of the bit line 103 along the first direction X. In the embodiments of the present disclosure, in order to realize effective electrical isolation between the stacked bit lines and reduce the parasitic capacitance between the bit lines, the effective coverage length of the bit line covered by the shielding portion 102 is greater than or equal to half of the actual length of the bit line. When the coverage length is less than half of the actual length of the bit line, a relatively large parasitic capacitance can still be formed between adjacent bit lines, and the shielding portion cannot realize effective electrical isolation. In some actual examples, d1 is greater than or equal to d2, that is, the effective coverage length of the bit line covered by the shielding portion 102 is greater than or equal to the actual length of the bit line, that is, complete electrical isolation can be realized, thereby improving the electrical performance of the three-dimensional semiconductor memory. It can be understood that there is a relative part between the shielding portion 102 and the bit line 103, and both the shielding portion 102 and the bit line 103 are made of conductive material, so there is also parasitic capacitance between the shielding portion 102 and the bit line 103. In order to effectively reduce the parasitic capacitance between the bit lines and prevent the parasitic capacitance between the shielding portion 102 and the bit line 103 from affecting the three-dimensional semiconductor memory, in the embodiments of the present disclosure, d1 can be selected to be greater than or equal to d2 / 2 and less than d2.

[0057] In some embodiments, an insulating medium layer 109 is further arranged between the main body 101 and the substrate 110, as shown in FIG. 3, and the main body 101 and the substrate 110 are electrically isolated by the insulating medium layer 109. When the main body 110 is electrically connected to the fixed potential end, the potential of the substrate 110 will not be affected, thereby avoiding interference with the working potential of the three-dimensional storage structure. The material of the insulating medium layer 109 is one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric material.

[0058] In some embodiments, the thickness of the shielding portion 102 along the third direction Z is less than or equal to the thickness of the bit line 103 along the third direction Z. In order to improve the storage density of the three-dimensional semiconductor memory, the spacing thickness between the stacked storage structures is less than the thickness of the storage structure itself, and the shielding portion 102 is arranged between the bit lines 103 (i.e., between the storage structures) along the third direction Z. Therefore, the thickness of the shielding portion 102 along the third direction Z is less than or equal to the thickness of the bit line 103 along the third direction Z, which can improve the storage density of the three-dimensional semiconductor memory and improve the integration density of the memory device.

[0059] In some embodiments, along the second direction Y, the length of the shielding portion 102 is greater than or equal to the length of the bit line 103, as shown in FIGS. 1-2. In order to achieve effective electrical isolation between adjacent bit lines 103, the shielding portion 102 can cover the entire length of the bit line extending along the second direction Y. The bit line 103 is connected to the peripheral circuit through the stepped structure (not shown) electrically connected thereto, thereby achieving input or output of signals. The stepped structure can extend along the first direction X or the second direction Y, and the present disclosure does not make specific limitations thereto.

[0060] As shown in FIG. 1, the main body 101 extends along the second direction Y and the third direction Z to form a flat plate structure, a plurality of shielding portions 102 are arranged on one side of the main body 101, and the main body 101 is connected to a fixed potential end through a wire (not shown). The shielding portion 102 is electrically connected to the main body 101 and connected to the fixed potential end through the main body 101, for example, can be grounded, thereby achieving electrical shielding of the stacked bit lines 103. As shown in FIG. 1-2, the main body 101 extends along the second direction Y, and there is a large relative area between the main body 101 and the stacked bit lines 103, so it is easy to generate a large parasitic capacitance. In some embodiments, as shown in FIG. 5, along the second direction Y, the length of the main body 101 is less than the length of the bit line 103. By shortening the length of the main body 101 along the second direction Y, the parasitic capacitance between the main body 101 and the bit line 103 can be effectively reduced, and the influence on the electrical performance of the memory can be reduced. In some embodiments, as shown in FIG. 5, a plurality of sub-main bodies 101-1, 101-2 can be included, the plurality of sub-main bodies 101-1, 101-2 extend along the third direction Z and are arranged at intervals along the second direction Y, and each sub-main body 101-1, 101-2 is electrically connected to the plurality of shielding portions 102. In some embodiments, when a plurality of sub-main bodies are included, each sub-main body is arranged to be staggered with the word line 104 in the first direction X. In this way, the parasitic capacitance between the main body and the word line can be reduced, the electrical signal on the word line can be prevented from being affected by the main body grounded to the ground potential, and the stability of the electrical signal on the word line can be improved.

[0061] As shown in FIG. 6, in some embodiments, the plurality of shielding portions 102 are respectively located on opposite sides of the main body 101 along the first direction X. It can be understood that the plurality of shielding portions 102 located on the two sides of the main body 101 can be mirror symmetric about the symmetry axis S, that is, the three-dimensional semiconductor storage structure is mirror symmetric about the symmetry axis S, and the mirror symmetric three-dimensional semiconductor storage structure shares the same main body 101, that is, the main body 101 has a "U" shaped cross section in the cross section along the first direction X and the third direction Z. In some embodiments, separate main bodies 101 can also be formed, which are respectively connected to different three-dimensional semiconductor storage structures, or an integral main body 101 is formed, and different three-dimensional semiconductor storage structures share the same main body 101. The embodiments of the present disclosure do not make specific limitations on this.

[0062] In some embodiments, the main body 101 and the plurality of shielding portions 102 are an integral structure, that is, they are formed in the same process step. The main body 101 and the plurality of shielding portions 102 are formed of a conductive material, wherein the conductive material includes one or more of Ti, Ta, W, Cu, Al, TiN, TaN. In the embodiments of the present disclosure, the conductive material is selected as TiN. In some embodiments, the material of the bit line 103 and the material of the shielding portion 102 can be the same, for example, both are TiN.

[0063] In some embodiments, the second dielectric layer 108 is further arranged between the bit line 103 and the body part 101, and the first dielectric layer 107 and the second dielectric layer 108 are further arranged between the bit line 103 and the shielding part 102. FIG. 4 is an enlarged schematic view of the dashed portion in the cross-sectional view shown in FIG. 3. As shown in FIG. 4, along the third direction, the first dielectric layer 107 and the second dielectric layer 108 are further arranged in a stacked structure between the bit line 103 and the shielding part 102. The material of the first dielectric layer 107 and / or the second dielectric layer 108 is one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric material. In the embodiments of the present disclosure, in order to reduce the parasitic capacitance between the bit line 103 and the body part 101 and the parasitic capacitance between the bit line 103 and the shielding part 102, optionally, the second dielectric layer 108 is low-k dielectric material, for example, the low-k dielectric constant material can be, but is not limited to, one or a combination of two or more of SiOH, SiOCH, FSG (fluorosilicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass).

[0064] In summary, the three-dimensional semiconductor memory provided by the embodiments of the present disclosure includes a substrate, a plurality of active layers arranged in an array on the substrate, a plurality of bit lines respectively connected to one end of the active layers, the plurality of bit lines extending along a second direction and stacked on the substrate along a third direction, and a shielding structure including a body part and a plurality of shielding parts, the shielding parts extending along the second direction, the body part and the shielding parts being composed of conductive material and electrically connected to each other. In the embodiments of the present disclosure, the shielding parts are formed between the stacked bit lines, the shielding parts are electrically connected to the body part, and the body part is connected to a fixed potential end, thereby realizing electrical isolation between the stacked bit lines, reducing the parasitic capacitance between the bit lines, further reducing signal interference between adjacent bit lines, and improving the overall electrical performance of the stacked device.

[0065] An embodiment of the present disclosure further provides a preparation method of a three-dimensional semiconductor memory. The preparation method of the three-dimensional semiconductor memory provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. FIGS. 7-18 are partial schematic views of respective steps in the preparation method of the semiconductor structure provided by an embodiment of the present disclosure. The preparation method of the semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to FIGS. 7-18.

[0066] As shown in FIG. 7, a substrate 201 is provided, and a multi-layer stack structure 200 is formed on the substrate 201 and stacked along a third direction Z. The stack structure 200 includes a first stack layer 202 and a second stack layer 203 stacked in sequence along the third direction Z. The substrate 201 can be made of monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanium, germanium on insulator (GOI), or silicon on insulator (SOI), etc. In some embodiments, the substrate material is selected as monocrystalline silicon material, and the N-type or P-type substrate 201 is formed by performing N-type or P-type doping treatment and annealing treatment on the monocrystalline silicon material. The N-type element can be a group V element such as phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, or arsenic (As) element. The P-type element can be a group III element such as boron (B) element, aluminum (Al) element, gallium (Ga) element, or indium (In) element. In the embodiments of the present disclosure, the surface of the substrate 201 can be pretreated to remove impurities or natural oxide layer on the surface before the stack structure 200 is formed on the substrate 201. The first stack layer 202 can be formed of or include at least one of silicon, germanium, silicon germanium, silicon oxide, silicon nitride, and silicon oxynitride, such as silicon oxide. The second stack layer 203 can be formed of or include at least one of silicon, germanium, silicon germanium, silicon oxide, silicon nitride, and silicon oxynitride, such as silicon nitride. In some embodiments, the first stack layer 202 and the second stack layer 203 can be formed by epitaxy or deposition process. It can be understood that the first stack layer 202 and the second stack layer 203 have a high etching selectivity, such as greater than or equal to 10:1, under the same etching condition, so as to facilitate the formation of the three-dimensional stack structure. In addition, as shown in FIG. 7, the stack structure 200 includes a first region I and a second region II distributed along a first direction X. The first region is used for forming transistors and storage nodes of the three-dimensional memory, and the second region II is used for forming bit line structures and shielding structures.

[0067] The stack structure 200 is patterned to remove the stack structure in the second region II to form an opening 204 exposing the upper surface of the substrate 201. As shown in FIG. 8, a mask layer (not shown) is formed above the stack structure 200, and the stack structure 200 is patterned by a patterning process including dry etching, wet etching or a combination of both. After the patterning process, the stack structure in the second region II is removed to form the opening 204 exposing the upper surface of the substrate 201. As shown in FIG. 9, the stack structure 200 in the first region I is laterally etched through the opening 204 to remove part of the first stack layer 202 to form a plurality of first grooves 205 between the second stack layers 203 or between the second stack layers 203 and the substrate 201, and the first grooves 205 are in communication with the opening 204. FIG. 10 is a cross-sectional view of FIG. 9 along the direction of A-A'. As shown in FIG. 10, part of the first stack layer 202 is removed by the lateral etching process. It can be understood that the first stack layer 202 and the second stack layer 203 and / or the substrate 201 have a high etching selectivity (e.g., greater than or equal to 10:1), so that when the first stack layer 202 is removed by etching, the amount of etching of the second stack layer 203 and / or the substrate 201 is small or substantially no etching.

[0068] As shown in FIG. 11, a first dielectric material layer 206 is deposited in the opening 204 and the plurality of first recesses 205 in communication with the opening 204 by a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and the first dielectric material layer 206 can also cover the upper surface of the exposed substrate 201, wherein the first dielectric material layer 206 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric material. As shown in FIG. 11, the first dielectric material layer 206 in the first recesses 205 covers the exposed surfaces of the first stack layer 202 and the second stack layer 203, respectively, and the first dielectric material layer 206 in the first recesses 205 forms a second recess 207 in communication with the opening 204. As shown in FIG. 11, a sacrificial layer 208 is filled in the second recess 207, for example, the sacrificial layer can be formed by a chemical vapor deposition process, and the sacrificial layer outside the second recess 207 is removed by a dry or wet etching process, so that the sacrificial layer 208 fills the second recess 207. In some embodiments, the sacrificial layer 208 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, and polysilicon. In the embodiments of the present disclosure, the sacrificial layer 208 has a high etching selectivity (e.g., greater than or equal to 10:1) with the first stack layer 202, the second stack layer 203, and the first dielectric material layer 206, for example, the sacrificial layer 208 is made of polysilicon. As shown in FIG. 12, a patterning process is used to remove the first dielectric material layer 206 on one side of the second stack layer 203 along the first direction X, and the remaining first dielectric material layer forms a first dielectric layer 2061. In some embodiments, as shown in FIG. 13, part of the sacrificial layer 208 can also be removed along the first direction X, so that the sacrificial layer 208 is flush with the formed first dielectric layer 2061 in the vertical direction, and optionally, the first dielectric material layer and the sacrificial layer can be removed in different removal steps, respectively.

[0069] As shown in FIG. 14, the second stack layer 203 is laterally etched along the first direction X through the opening 204, such as a wet etching process, to remove part of the second stack layer and form a plurality of third grooves 209 between the adjacent first dielectric layers 2061, which are in communication with the opening 204. In some embodiments, the length of the third groove 209 along the first direction can be less than or equal to the length of the first dielectric layer 2061 along the first direction. It can be understood that the time of the lateral etching process and the length of the third groove 209 formed by etching can be determined according to how much the bit line is covered by the finally formed shielding part. As shown in FIG. 15, the bit line material layer is filled in the third groove 209 to form a bit line layer 210. For example, the sacrificial layer can be formed by a chemical vapor deposition process, and the bit line layer 210 is formed by removing the bit line layer outside the third groove 209 through a dry or wet etching process, so that the bit line layer 210 fills the third groove 209. In some embodiments, the bit line layer 210 can be formed by using a conductive material commonly used in the art, such as doped Si, doped Ge, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten silicide (WSi), cobalt silicide (CoSi), titanium silicide (TiSi), or a combination thereof.

[0070] After the bit line layer 210 is formed, the sacrificial layer 208 is removed by a selective etching process. As shown in FIG. 16, the sacrificial layer 208 is selectively etched through the opening 204 to expose the second groove 207. A wet etching process can be used to laterally etch the sacrificial layer 208. Since the etching selectivity between the sacrificial layer 208 and the first dielectric layer 206 and the bit line layer 210 is high (such as greater than or equal to 10:1), when the sacrificial layer 208 is etched and removed, the first dielectric layer 2061 and the bit line layer 210 are not etched or have a small amount of etching. As shown in FIG. 17, a second dielectric material layer 211 is deposited in the opening 204 and the plurality of second grooves 207 in communication with the opening 204 by a process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, wherein the material of the second dielectric material layer 211 is one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric material. In the embodiments of the present disclosure, in order to reduce the parasitic capacitance of the bit line between the shielding structures, the low-k dielectric material can be selected as the second dielectric material layer. As shown in FIG. 18, a shielding material layer 213 is formed on the surface of the formed second dielectric layer 211, and the material of the shielding material layer 213 includes one or more of Ti, Ta, W, Cu, Al, TiN, and TaN.

[0071] The electronic device provided by the embodiments of the present disclosure can be a mobile phone, a tablet computer, a smart bracelet, a wearable electronic device, a virtual reality device, an augmented reality device, a vehicle-mounted device, a server, a workstation, or the like.

[0072] The processor 20 can include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), or the like. The memory 10 can be configured to store data to be processed by the processor 20 and / or data processed by the processor.

[0073] The electronic device 1 can include, but is not limited to, a mobile phone, a tablet computer, a smart bracelet, a wearable electronic device, a virtual reality device, an augmented reality device, a vehicle-mounted device, a server, a workstation, or the like.

[0074] The three-dimensional semiconductor memory provided by the embodiments of the present disclosure includes a substrate, a plurality of active layers on the substrate, the plurality of active layers arranged in an array on the substrate, a plurality of bit lines respectively connected to one end of the active layers, the plurality of bit lines extending along a second direction, and the plurality of bit lines stacked on the substrate along a third direction, and a shielding structure including a main body and a plurality of shielding parts, the shielding parts extending along the second direction, the main body and the shielding parts being made of a conductive material, and the main body being electrically connected to the shielding parts, wherein at least one shielding part is arranged between adjacent bit lines along the third direction. In the embodiments of the present disclosure, the shielding parts are formed between the stacked bit lines, the shielding parts are electrically connected to the main body, and the main body is connected to a fixed potential end, so as to realize electrical isolation between the stacked bit lines, reduce the parasitic capacitance between the bit lines, and further reduce the signal interference between adjacent bit lines, thereby improving the overall electrical performance of the stacked device.

[0075] The above merely provides a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims

Claims

1. A three-dimensional semiconductor memory, characterized by, The three-dimensional semiconductor memory comprises: a substrate (110); a plurality of active layers (106) arranged in an array on the substrate (110) along a second direction (Y) and a third direction (Z); a plurality of bit lines (103) respectively connected to one end of the active layers (106) along a first direction (X), the plurality of bit lines (103) extending along the second direction (Y), and the plurality of bit lines (103) being stacked on the substrate (110) along the third direction (Z); a plurality of storage nodes (105) respectively connected to the other end of the active layers (106) away from the bit lines (103) along the first direction (X); the first direction (X), the second direction (Y) and the third direction (Z) intersecting with each other; a shielding structure (100) comprising a main body (101) and a plurality of shielding parts (102), the plurality of shielding parts (102) extending along the second direction (Y), the main body (101) and the shielding parts (102) being made of conductive material, and the main body (101) and the shielding parts (102) being electrically connected; wherein at least one shielding part (102) is arranged between adjacent bit lines (103) along the third direction (Z).

2. The three-dimensional semiconductor memory according to claim 1, wherein The projection of the shielding part (102) on the substrate (110) overlaps with the projection of the bit line (103) on the substrate (110), and the length of the overlapping part along the first direction (X) is d1, and the length of the bit line (103) along the first direction (X) is d2, wherein d1 is greater than or equal to d2 / 2.

3. The three-dimensional semiconductor memory according to claim 1, wherein The thickness of the shielding part (102) along the third direction (Z) is less than or equal to the thickness of the bit line (103) along the third direction (Z).

4. The three-dimensional semiconductor memory according to any one of claims 1 to 3, wherein The length of the shielding part (102) along the second direction (Y) is greater than or equal to the length of the bit line (103).

5. The three-dimensional semiconductor memory according to any one of claims 1 to 4, wherein The length of the main body (101) along the second direction (Y) is less than or equal to the length of the bit line (103).

6. The three-dimensional semiconductor memory according to any one of claims 1 to 5, wherein The plurality of shielding parts (102) are respectively located on opposite sides of the main body (101) along the first direction (X).

7. The three-dimensional semiconductor memory according to any one of claims 1-6, in a cross section along the first direction (X) and the third direction (Y), the main body (101) has a "U" type cross section.

8. The three-dimensional semiconductor memory according to any one of claims 1 to 7, wherein The main body (101) and the plurality of shielding parts (102) are an integral structure.

9. The three-dimensional semiconductor memory according to any one of claims 1 to 8, wherein A second dielectric layer is arranged between the bit line (103) and the main body (101), and a first dielectric layer (107) and the second dielectric layer (108) are arranged between the bit line and the shielding part.

10. The three-dimensional semiconductor memory according to claim 9, wherein, The material of the first dielectric layer (107) and / or the second dielectric layer (108) is one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric material.

11. The three-dimensional semiconductor memory according to any one of claims 1 to 10, wherein The conductive material includes one or more of Ti, Ta, W, Cu, Al, TiN, TaN.

12. The three-dimensional semiconductor memory of claim 5, wherein, The main body part (101) includes a plurality of sub-main body parts (101-1, 101-2, …), which extend along the third direction (Z) and are arranged at intervals along the second direction (Y).

13. The three-dimensional semiconductor memory according to any one of claims 1 to 12, wherein An insulating medium layer (109) is further arranged between the main body part (101) and the substrate.

14. The three-dimensional semiconductor memory according to any one of claims 1 to 13, wherein The storage node (105) includes one or more of a capacitive storage node, a phase change storage node, and a resistive change storage node.

15. The three-dimensional semiconductor memory according to any one of claims 1 to 14, wherein The three-dimensional semiconductor memory further includes: A plurality of word lines (104) respectively extend along the third direction (Z) and correspond to the plurality of active layers (106) stacked along the third direction (Z).

16. An electronic device (1) characterized in that Comprise: a processor (10); and a memory (20), wherein the memory (20) is coupled with the processor (10), and at least one of the memory (20) and the processor (10) comprises the three-dimensional semiconductor memory according to any one of claims 1-15.

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