Method for producing a piezoelectrically actuatable membrane, piezoelectrically actuatable membrane, and use of the piezoelectrically actuatable membrane

Abstract

The present disclosure relates to a method for producing a piezoelectrically actuatable membrane (1), comprising the steps of a) providing a substrate (2), c) applying a first electrode layer (20), d) applying a piezoelectric layer stack (22), e) applying a second electrode layer (24), wherein applying the piezoelectric layer stack (22) in step d) comprises d-1) applying a seed layer (28), d-2) applying a cover layer (44), d-3) thermal annealing or d-I) applying a dielectric layer (30), d-II) applying a piezoelectric layer (26) having decreasable layer thickness (38). The disclosure additionally relates to a piezoelectrically actuatable membrane (1). The disclosure furthermore relates to the use of the piezoelectrically actuatable membrane (1) in a device having a front volume and a back volume.

Description

[0001] R.414120

[0002] - 1 -

[0003] Description

[0004] title

[0005] Method for producing a piezoelectrically actuated membrane, piezoelectrically actuated membrane and use of the piezoelectrically actuated membrane

[0006] Technical field

[0007] The present invention relates to a method for producing a piezoelectrically actuated membrane comprising the steps a) providing a substrate, c) applying a first electrode layer, d) applying a piezoelectric layer stack, e) applying a second electrode layer, wherein the application of the piezoelectric layer stack in step d) comprises d-1) applying a seed layer, d-2) applying a cover layer, d-3) thermal curing or dl) applying a dielectric layer, d-2) applying a piezoelectric layer with a removable thickness. The invention further relates to a piezoelectrically actuated membrane. The invention further relates to the use of the piezoelectrically actuated membrane in a device with a front volume and a back volume.

[0008] State of the art

[0009] Piezoelectrically actuated membranes are components of micro-scale loudspeakers and microphones and are also referred to as MEMS transducers (microelectromechanical systems). These preferably have a 3D folded-sheet structure or a lamellar structure and can be excited to horizontal oscillations by applying a voltage between an upper and lower electrode. Such systems are known from the prior art; see WO 2021 / 144400 A1.

[0010] The membranes in the prior art comprise, in addition to the upper and lower electrode layers, a piezoelectric layer, which usually comprises AIN or doped AIN and is deposited by chemical vapor deposition (CVD), in particular by atomic layer deposition (R.414120).

[0011] - 2 -

[0012] ALD = atomic layer deposition), or applied by means of physical vapor deposition (PVD = physical vapor deposition), in particular cathode deposition (sputtering).

[0013] Although the ALD process offers the advantage that the individual layers are deposited in a conformal manner, the deposition rate in the ALD process is relatively low, which leads to long deposition times.

[0014] Since the production of a piezoelectric layer also requires a certain degree of crystallinity and quality, meaning as free as possible from impurities, of the deposited material, it is necessary to expose the resulting AIN layer to direct ion bombardment in the plasma, which further reduces the deposition rate.

[0015] Sputtering, on the other hand, is known to produce thin material layers with high piezoelectric coefficients, but it is rather unsuitable for substrates with cavities of a certain depth. The layers are usually not formed uniformly, which can lead to holes in the layers, potentially causing an electrical short circuit or breakdown, rendering the MEMS component unusable.

[0016] Alternatively, metal-organic vapor deposition (MOCVD) is also possible in the field of chemical vapor deposition. While this also yields highly crystalline layers, the high deposition temperature results in high layer stress. Furthermore, the conformity of the resulting layers is significantly lower with the MOCVD process than with the ALD process.

[0017] Accordingly, there is immense demand for methods for manufacturing MEMS membranes, particularly for depositing the piezoelectric layer. These methods should be applicable even to substrates with cavities of a certain depth and should produce uniform piezoelectric layers with the required crystallinity, free from impurities. Ideally, the methods should be cost-effective and allow for batch-scale production of MEMS membranes.

[0018] Disclosure of invention R.414120

[0019] - 3 -

[0020] According to the invention, a method for producing a piezoelectrically actuated membrane is found, comprising the steps, in particular in this order: a) providing a substrate with a substrate top and at least one cavity, wherein the at least one cavity comprises a first side wall and an opposing second side wall as well as a cavity bottom, and a depth measured from the substrate top to the cavity bottom and a width measured from the first side wall to the second side wall, c) applying a first electrode layer, d) applying a piezoelectric layer stack, e) applying a second electrode layer.wherein the application of the piezoelectric layer stack in step d) comprises the following steps: d-1) application of a seed layer; d-2) application of a cover layer; d-3) thermal curing of the seed layer from d-1) and the cover layer from d-2) to obtain the piezoelectric layer stack; or dl) application of a dielectric layer; d-ll) application of a piezoelectric layer such that the piezoelectric layer extends from the substrate top towards the cavity bottom with a removable layer thickness at the first and second side walls, wherein the dielectric layer from dl) and the piezoelectric layer from d-ll) form the piezoelectric layer stack.

[0021] According to the invention, the piezoelectrically actuated membrane is a membrane with a 3D folded structure, as described above. In this case, vertical sections of the membrane run almost parallel to the side walls of the structure and thus in the direction of fluid flow, with the vertical sections being connected to each other via horizontal sections.

[0022] In suitable embodiments of the method according to the invention, this further comprises a step: b) Application of a passivation layer R.414120

[0023] - 4 -

[0024] Preferably, the passivation layer is applied to the substrate before the first electrode layer, which means that step b) of the inventive method preferably takes place between steps a) and c).

[0025] The substrate according to the present invention comprises at least one cavity, but preferably a plurality of cavities, which form the basis for the 3D folded structure of the membrane. In suitable embodiments, the substrate is a silicon substrate into which the cavities are introduced by reactive ion etching or by KOH etching. The resulting cavities have a depth-to-width ratio greater than 5:1, preferably greater than 10:1, and particularly preferably greater than 20:1. In some embodiments, the resulting cavities can be even deeper.

[0026] The optional passivation layer in step b) is formed according to the invention by thermal oxidation; however, other deposition methods, e.g., LPCVD, are also possible. The first electrode layer in step c) is preferably made of microcrystalline silicon or polysilicon. If the membrane is connected to a voltage source, the first electrode layer, together with the voltage source, functions as the bottom electrode. The first electrode layer is preferably obtained via a CVD process, as this provides fast deposition times. The CVD process can be selected from metal-organic vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD), but is not limited to these methods.

[0027] The second electrode layer in step e) functions as the top electrode when applied to a voltage source and, in suitable embodiments, comprises platinum, tungsten, tin oxide, monocrystalline silicon, polysilicon, molybdenum, titanium, tantalum, metal silicide, aluminum, graphite, copper, or mixtures thereof. The second electrode layer is also preferably obtained via a CVD process, but, just like the first electrode layer, is not limited to this process.

[0028] The piezoelectric layer stack in step d) can be obtained according to the invention via two variants. R.414120

[0029] - 5 -

[0030] In a first embodiment of the invention, the piezoelectric layer stack in step d) can be obtained by first applying a seed layer according to d-1) to the first electrode layer, followed by a cover layer according to d-2) and the subsequent thermal curing of the seed layer and the cover layer in step d-3), so that a piezoelectric layer stack is formed.

[0031] Alternatively, the piezoelectric layer stack in step d) can be obtained by first applying a dielectric layer according to step dl) to the first electrode layer, followed by the application of a piezoelectric layer in step dl I). In contrast to the first embodiment, this piezoelectric layer is not applied continuously with a constant thickness, but rather starting from the substrate surface and extending towards the cavity bottom, with a removable thickness at the first and second side walls. In this variant, the piezoelectric layer stack comprises the dielectric layer from dl) and the piezoelectric layer from dl I). The piezoelectric layer may or may not be formed at the cavity bottom.In a further embodiment of this alternative application of the piezoelectric layer stack, the piezoelectric layer can first be applied according to step dl I) and then the dielectric layer according to step dl). In this case, too, the piezoelectric layer, in contrast to the first embodiment, would not be continuous with a constant layer thickness, but would be applied from the substrate top towards the cavity bottom with a removable layer thickness at the first and second side walls.

[0032] The piezoelectric layer comprises AIN, doped AIN, PZT (lead zirconate titanate), KNN (potassium sodium niobate), ZnO, PVDF, or mixtures thereof. Doped AIN can have the formula Ali- x Sc xexhibit N, where 0 <x<0,4, wobei auch andere Dotierstoffe als Sc oder Kombinationen von Dotierstoffen eingesetzt werden können. Erfindungsgemäß wird die piezoelektrische Schicht dabei mittels metallorganischer Gasphasenepitaxie (MOCVD), ALD, LPCVD oder Katho- denzerstäubung (Sputtern) aufgetragen.

[0033] In a preferred embodiment of the invention, the cover layer according to the first alternative comprises a piezoelectric layer as described above, in particular, this layer is designed as a piezoelectric layer. However, the cover layer can also be a layer that is not yet piezoelectric during deposition, made of the materials AIN, doped AIN, PZT (lead zirconate titanate), R.414120

[0034] - 6 -

[0035] The coating may consist of KNN (potassium sodium niobate), ZnO, PVDF, or mixtures thereof; in particular, the coating layer can be deposited amorphously. The coating layer is preferably deposited using a highly conformal deposition process, e.g., atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0036] The dielectric layer comprises AIN, doped AIN, Al₂O₃-X, SiCh, SisN^x, HfCh-x, ZrCh-x, TiOa-x, SrTiOa, BaTiOs, or mixtures thereof. According to the invention, the dielectric layer is deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD), in particular by atomic layer deposition (ALD) or LPCVD.

[0037] The nucleation layer according to the first variant can be configured as a piezoelectric layer or as a dielectric layer, as described in the previous paragraphs, and is applied in particular by atomic layer deposition (ALD). If the surface layer is not configured as a piezoelectric layer, the nucleation layer is either configured as a piezoelectric layer or is at least crystalline, so that a piezoelectric surface layer can form during subsequent thermal annealing. If both the surface layer and the nucleation layer are configured as piezoelectric layers, they can differ in their composition. For example, the nucleation layer can comprise AIN and the piezoelectric layer Ali- x Sc xN. Alternatively, the top layer and the nucleation layer can also be designed as piezoelectric layers with the same composition; for example, both can be made of AIN. In the case of a non-piezoelectric nucleation layer, the nucleation layer essentially only functions as a growth template during the healing process. Materials that are crystalline and lattice-adapted to the piezoelectric layer, such as NbN, HfN, ZrN, or TiN, are preferred.

[0038] The nucleation layer can be deposited using a plasma ALD process, preferably with ion bombardment. Since the nucleation layer only needs to be very thin, deposition using MOCVD is also possible, although not preferred, as the layer stress does not have a significant negative impact. Sputtering is less preferred for depositing the nucleation layer, but is fundamentally possible. However, this can lead to less conformally formed layers; in particular, the nucleation layer would not be fully formed in the cavities, which is related to R.414120.

[0039] - 7 - would result in no fully piezoelectric layer being present after thermal curing in step d-3).

[0040] The thermal annealing of the nucleation layer and the piezoelectric layer can include heat treatment in a heating oven, rapid thermal annealing (RTA), flash lamp annealing (FLA), or laser annealing, wherein the temperature in step d-3) is between 350°C and 1100°C, in particular between 500°C and 1000°C.

[0041] In suitable embodiments of the method according to the invention, the layer thickness of the nucleation layer is 1 A, in particular 1 / 6, particularly preferably 1 / 10, of the layer thickness of the entire piezoelectric layer stack. This has the advantage that the overall process time can be minimized.

[0042] The following example is intended to illustrate the formation of a highly crystalline piezoelectric layer stack via a seed layer, whereby the example is to be understood merely as a possible embodiment and not as limiting to the disclosure of the invention:

[0043] Trimethylaluminium is introduced into a reaction chamber containing the pre-cavified substrate, along with a protective gas (Ar or N₂). The trimethylaluminium reacts with the substrate surface within milliseconds. In a subsequent step, the reaction chamber is purged with a protective gas for a few seconds to remove unreacted trimethylaluminium and any byproducts. An N₂ / H₂ or N₂ or NH₃ plasma treatment is then performed to detach poorly bonded atoms of Al or N from the substrate surface. This treatment typically lasts between a few seconds and several tens of seconds. Longer treatment duration results in higher crystalline quality. A further purge with protective gas is then carried out before another layer of Al is deposited by repeating the procedure until the desired seed layer thickness is reached.The top layer is then deposited using a thermal ALD process. Compared to the plasma ALD process, this has the advantage that it can also be carried out in batches. In this process, a precursor, e.g., trimethylaluminum, is introduced into a reaction chamber containing the already cavity-filled substrate, along with a protective gas such as argon or nitrogen. The trimethylaluminum reacts with R.414120 within a few milliseconds.

[0044] - 8 -

[0045] Substrate surface. In a subsequent step, the reaction chamber is purged with a protective gas for a few seconds to remove unreacted trimethylaluminum and any byproducts. Then, for example, NH3, N2H4, or N2 / H2 is introduced into the reaction chamber, with the treatment typically lasting between a few milliseconds and several seconds. A further purging step with protective gas is then performed before another layer of AIN is deposited by repeating the procedure until the desired nucleation layer thickness is reached. Alternatively, a pulsed CVD process can be used, in which the precursors are introduced in pulses, but no separate purging step is performed. In both methods, TMA / N2H4 or TMA / NH3 are conceivable precursor combinations.

[0046] In the second embodiment of the method according to the invention, i.e., the application of a dielectric layer and a piezoelectric layer with decreasing layer thickness, the order in which the layers are applied (dielectric and piezoelectric) is essentially irrelevant. Industrially, the layer order is also determined by the application methods used. For example, when using a MOCVD process to apply the piezoelectric layer, it is advantageous to first apply the piezoelectric layer at high temperatures and then, in a subsequent step, to apply the conformal dielectric layer using an ALD process at lower temperatures.

[0047] The deposition of the piezoelectric layer with decreasing layer thickness on the side walls can be achieved by depositing it using physical vapor deposition (PVD) or metal-organic vapor phase epitaxy (MOCVD).

[0048] When depositing the dielectric layer and the piezoelectric layer with removable thickness, it is preferred to select the materials and deposition parameters such that any potential layer stress between the two layers is at least partially compensated. For example, Al₂O₃ deposited by ALD typically suffers tensile stress, while AIN deposited by sputtering is known to suffer from tensile stress. By ion bombardment during sputtering, the layer stress of AIN can be changed from tensile to compressive stress, which simultaneously offers the advantage that compressively stressed AIN typically has higher piezoelectric coefficients. Therefore, a combination of Al₂O₃ as the dielectric layer is R.414120

[0049] - 9 -

[0050] The layer applied using the ALD process and the sputtered AIN as a piezoelectric layer represent an advantageous combination, as the overall stress on the membrane is minimized.

[0051] In suitable methods according to the invention, the following applies to the ratio of the layer thicknesses of the piezoelectric layer and the dielectric layer: dpiezo » d diei -r, piezo ^r,diel where dpi eZ o, ddtei = layer thicknesses of the piezoelectric / dielectric layer and E r , piezo, r ,diei = relative permittivities of the piezoelectric / dielectric layer.

[0052] In a suitable embodiment of the method according to the invention, dpiezo £ r, piezo at least 2 times larger than ddiel , preferably at least 5 times larger and especially £r,diel preferably at least 10 times larger.

[0053] Actuating the piezoelectric membrane requires a voltage source that applies an electrical voltage to the membrane. The strength of the actuation is proportional to this voltage. Therefore, to ensure that a large proportion of the voltage drops across the piezoelectric layer, it is advantageous for the dielectric layer to be made of a material with high relative permittivity, such as ZrÜ2, HfCh, TiC>2, SrTiOa, or BaTiOa, and to have a small layer thickness.

[0054] In a further suitable embodiment of the method according to the invention, this method comprises the additional steps f) application of a middle electrode layer g) application of a second piezoelectric layer stack, wherein steps f) and g) are carried out between steps d) and e), wherein the application of the second piezoelectric layer stack in step g) comprises steps d-1) to d-3) or dl) to d-ll).

[0055] In one possible embodiment of the method according to the invention, the first piezoelectric layer stack can comprise steps d-1) to d-3) and the second piezoelectric layer stack can comprise steps dl) to d-ll) or vice versa.

[0056] In this embodiment with a second piezoelectric layer stack and a middle electrode layer, either the first electrode layer / middle electrode layer or the middle electrode layer / second R.414120

[0057] - 10 -

[0058] The electrode layer can be used as a sensor layer, meaning that a deflection of the membrane (vibration) can be converted into an electrical signal. However, it is also possible to use both the first electrode layer / middle electrode layer and the middle electrode layer / second electrode layer for actuation.

[0059] According to the invention, a piezoelectrically actuated membrane, manufactured according to the inventive method, is further proposed, comprising

[0060] A) a first electrode layer

[0061] B) a piezoelectric layer stack

[0062] C) a second electrode layer

[0063] In an alternative embodiment, the piezoelectrically actuated membrane comprises

[0064] A) a first electrode layer

[0065] B) a piezoelectric layer stack

[0066] D) a middle electrode layer

[0067] E) a second piezoelectric layer stack

[0068] C) a second electrode layer

[0069] According to the invention, the use of the piezoelectrically actuated membrane in one of the above embodiments in a device with a front volume and back volume, in particular in a loudspeaker or in a microphone, is further proposed.

[0070] Advantages of the invention

[0071] The inventive method for producing a piezoelectrically actuated membrane, as well as the piezoelectrically actuated membrane comprising at least one piezoelectric layer stack, enables the creation of layers with piezoelectric properties and the required crystallinity. Furthermore, it is possible to apply these layers into the cavities of substrates with cavities of a certain depth.

[0072] By depositing the piezoelectric layer and the dielectric layer or nucleation layer using different methods, the aforementioned disadvantages of the individual methods, such as low deposition rates, can be overcome. R.414120

[0073] - 11 - rates, long deposition times, low piezoelectric coefficients, electrical breakdowns or short circuits, are reduced to a minimum and in some cases completely avoided.

[0074] Furthermore, the selection of suitable combinations of materials for the piezoelectric layer and the dielectric layer or nucleation layer allows the layer stress between the two layers to be compensated, resulting in a more reliable and mechanically stable membrane.

[0075] The production of thin films, for example via a thermal ALD process, also allows deposition to be carried out on a batch scale, which makes the production of MEMS membranes significantly more cost-effective and efficient.

[0076] Brief description of the drawings

[0077] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

[0078] They show:

[0079] Figure 1 shows a schematic cross-sectional view of a first part of a method according to the invention;

[0080] Figure 2 shows a schematic cross-sectional view of a second part of a method according to the invention;

[0081] Figure 3 shows a schematic cross-sectional view of a method according to the invention, in particular for applying a piezoelectric layer stack according to a first variant;

[0082] Figure 4a shows a schematic cross-sectional view of a method according to the invention, in particular for applying a piezoelectric layer stack according to a second variant and R.414120

[0083] - 12 -

[0084] Figure 4b shows a schematic cross-sectional view of a method according to the invention, in particular for applying a piezoelectric layer stack according to a second alternative variant.

[0085] Embodiments of the invention

[0086] In the following description of embodiments of the invention, identical or similar elements are designated by the same reference numerals, and repeated descriptions of these elements are omitted in individual cases. The figures represent the subject matter of the invention only schematically.

[0087] Figure 1 shows a substrate 2 with a substrate surface 4 and a plurality of cavities 6, one of which is shown in detail. According to the invention, the cavities 6 are produced by reactive ionic deep etching or KOH etching, as described above. The cavity 6 has a first side wall 8 and an opposing second side wall 10, as well as a cavity bottom 16. The depth 12 of the cavity 6 is therefore measured from the substrate surface 4 to the cavity bottom 16, and the width 14 of the cavity 6 is measured from the first side wall 8 to the second side wall 10. In the embodiment shown, a passivation layer 18 is already applied continuously to the substrate surface 4, preferably by thermal oxidation according to the invention.

[0088] Figure 2 shows the substrate 2 with the applied passivation layer 18 according to Figure 1. In further steps of the inventive method, a first electrode layer 20, a piezoelectric layer stack 22 (further shown in Figures 3 and 4), and a second electrode layer 24 were applied to the passivation layer 18.

[0089] The first electrode layer 20 is preferably made of microcrystalline silicon or polysilicon and is obtained according to the invention by a CVD process, e.g. LPCVD. The second electrode layer 24 preferably comprises platinum, tungsten, tin oxide, monocrystalline silicon, polysilicon, molybdenum, titanium, tantalum, metal silicide, aluminum, graphite, copper or mixtures thereof and is preferably also deposited by a CVD process, e.g. LPCVD or ALD.

[0090] Figure 3 shows an enlarged section of Figure 2 and illustrates the method according to the invention in a first embodiment, in particular the formation of a piezoelectric layer stack 22 according to a first variant. R.414120

[0091] - 13 -

[0092] Figure A shows substrate 2, specifically a section of the first sidewall 8 of substrate 2. The passivation layer 18 and a first electrode layer 20 are already applied. Figure B shows a nucleation layer 28 applied using a plasma ALD process. This nucleation layer can be configured as a piezoelectric layer 26, a dielectric layer 30, or alternatively, an electrically conductive layer (not shown here for simplicity). The thickness 34 of the nucleation layer 28 is chosen such that it has a maximum thickness of 34 mm. 1The core layer 28 is 32 mm thick, representing the thickness of the piezoelectric stack 22 (see E). In C, a piezoelectric layer 26, which here functions as a cover layer 44 (for simplicity, still referred to as piezoelectric layer 26), preferably made of AIN or doped AIN and deposited using thermal ALD or CVD processes, is deposited onto this core layer 28. The thickness 38 mm of the piezoelectric layer 26 is significantly greater than the thickness 34 mm of the core layer 28. In D, the core layer 28 and the piezoelectric layer 26 are then thermally cured at 350°C to 1100°C, resulting in the piezoelectric stack 22 with a thickness 32 mm. Finally, in E, the second electrode layer 24 is deposited.

[0093] Figure 4a) shows the section from Figure 2 enlarged and depicts the method according to the invention in a second embodiment, in particular the formation of a piezoelectric layer stack 22 according to a second variant in its first alternative.

[0094] In A, as shown in Figure 3, the first side wall 8 of the substrate 2 is depicted, with a passivation layer 18 and a first electrode layer 20 already applied. In B, a dielectric layer 30 is now applied uniformly, i.e., with a constant layer thickness 36. The dielectric layer 30 is preferably applied using ALD or LPCVD. The piezoelectric layer 26 is then applied such that the layer thickness 38 of the piezoelectric layer 26 decreases continuously from the substrate top 4 (not shown) to the cavity bottom 16 (not shown). The dielectric layer 30 and the piezoelectric layer 26 together form the piezoelectric layer stack 22 with a layer thickness 32. In D, as already shown for Figures 2 and 3, the second electrode layer 24 is applied.

[0095] Figure 4b) shows the section from Figure 2 in a second alternative to Figure 4a). Starting from substrate 2 with a passivation layer 18 and an R.414120

[0096] - 14 - In contrast to Figure 4a), in b, the first electrode layer 20 in a) is now first coated with the piezoelectric layer 26 such that the thickness 38 of the piezoelectric layer 26 decreases continuously from the substrate top 4 (not shown) to the cavity bottom 16 (not shown). In c), the dielectric layer 30 is now coated uniformly with a constant thickness 36, so that the piezoelectric layer 26 and the dielectric layer 30 form a piezoelectric layer stack 22 with a thickness 32. In d, the second electrode layer 24 is now coated analogously to the variant already shown in Figure 4a).

[0097] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, within the scope specified by the claims, a multitude of modifications are possible that fall within the bounds of what is considered skilled in the art.

Claims

R.414120 - 15 - Claims 1. Method for producing a piezoelectrically actuated membrane (1) comprising the steps, in particular in this order: a) providing a substrate (2) having a substrate top (4) and at least one cavity (6), wherein the at least one cavity (6) comprises a first side wall (8) and an opposing second side wall (10) and a cavity bottom (16), and a depth (12) measured from the substrate top (4) to the cavity bottom (16) and a width (14) measured from the first side wall (8) to the second side wall (10), c) applying a first electrode layer (20), d) applying a piezoelectric layer stack (22), e) applying a second electrode layer (24).wherein the application of the piezoelectric layer stack (22) in step d) comprises the following steps: d-1) application of a seed layer (28); d-2) application of a cover layer (44); d-3) thermal curing of the seed layer (28) from d-1) and the cover layer (44) from d-2) to obtain a piezoelectric layer stack (22); or dl) application of a dielectric layer (30); d-11) application of a piezoelectric layer (26) such that the piezoelectric layer (26) is present at the first (8) and second side walls (10) extending from the substrate top (4) towards the cavity bottom (16) with a removable layer thickness (38), wherein the dielectric layer (30) from dl) and the piezoelectric layer (26) from d-11) form the piezoelectric layer stack (22).

2. Method according to claim 1 , R.414120 - 16 - furthermore encompassing the following step, in particular between the Steps a) and c): b) Application of a passivation layer (18).

3. Method according to claim 1 or 2, wherein the at least one cavity (6) of the substrate (2) is produced in step a) by reactive ion deep etching or KOH etching, such that the ratio depth (12):width (14) of the at least one cavity (6) is greater than 5:1, preferably greater than 10:1 and particularly preferably greater than 20:

1.

4. Method according to at least one of the preceding claims, wherein the piezoelectric layer (26) comprises AIN, doped AIN, PZT (lead zirconate titanate), KNN (potassium sodium niobate), ZnO or PVDF, wherein the piezoelectric layer (26) is applied by means of ALD, in particular thermal ALD, LPCVD, metal-organic vapor phase epitaxy (MOCVD) or cathode sputtering.

5. Method according to at least one of the preceding claims, wherein the cover layer (44) comprises an at least partially piezoelectric layer (26) according to claim 4 or wherein the cover layer (44) comprises AIN, doped AIN, PZT (lead zirconate titanate), KNN (potassium sodium niobate), ZnO or PVDF, wherein the latter is in at least a partially amorphous state.

6. Method according to at least one of the preceding claims, wherein the dielectric layer (30) is AIN, doped AIN, Al2O3-X, SiO2, Si3N4-x, HfO 2-x , ZrO2- x , TiO2- x , SrTiO3, BaTiO3 comprising, wherein the dielectric layer (30) is applied by atomic layer deposition (ALD) or chemical vapor deposition (CVD), in particular by atomic layer deposition (ALD).

7. Method according to at least one of the preceding claims, wherein the seed layer (28) is configured as a piezoelectric layer (26) according to claim 4 or as a dielectric layer (30) according to claim 6, in particular wherein the seed layer (28) is applied by means of atomic layer deposition (ALD), in particular by means of plasma-enhanced atomic layer deposition (ALD). R.414120 - 17 - 8. Method according to at least one of the preceding claims, wherein the thermal annealing comprises heat treatment in a heating furnace, rapid thermal annealing (RTA), flash lamp annealing (FLA) or laser annealing, wherein the temperature in step d-3) is between 350°C and 1100°C, in particular between 500°C and 1000°C.

9. Method according to at least one of the preceding claims, wherein the layer thickness (34) of the nucleation layer (28) 1A, in particular 1 / 6, particularly preferably 1 / 10, of the layer thickness (32) of the piezoelectric layer stack (22).

10. Method according to at least one of the preceding claims, wherein the following applies to the ratio of the layer thicknesses (38, 36) of the piezoelectric layer (26) and the dielectric layer (30): where dpiezo, ddiei = layer thicknesses (38, 36) of the piezoelectric (26) / dielectric layer (30) £ r , piezo, r, diel = relative permittivities of the piezoelectric (26) / dielectric layer (30) 11. Method according to at least one of the preceding claims, wherein the method comprises the additional steps f) application of a middle electrode layer (40) g) application of a second piezoelectric layer stack (42), wherein steps f) and g) are performed between steps d) and e), wherein the application of the second piezoelectric layer stack (42) in step g) comprises steps d-1) to d-3) or dl) to d-ll).

12. Piezoelectrically actuated membrane (1), manufactured according to a method according to any one of claims 1 to 11, comprising A) a first electrode layer (20) B) a piezoelectric layer stack (22) C) a second electrode layer (24). R.414120 - 18 - 13. Piezoelectrically actuated membrane (1) according to claim 12 further comprising D) a middle electrode layer (40) E) a second piezoelectric layer stack (42) wherein layers D) and E) are arranged between layers B) and C) 14. Use of the piezoelectrically actuated membrane (1) according to claim 12 or 13 in a device with front volume and back volume, in particular in a loudspeaker or in a microphone.

Images