Semiconductor device

Abstract

This semiconductor device improves the efficiency of arithmetic. In the semiconductor device, one of the source and the drain of a first transistor is connected to the gate of a second transistor and the gate of a third transistor, one of the source and the drain of the second transistor is connected to one of the source and the drain of the third transistor, a first signal line is connected to the other of the source and the drain of the second transistor, the second signal line is connected to the other of the source and the drain of the third transistor, the first signal line has a function of supplying an arithmetic signal, the second signal line has a function of supplying an inverted signal of the arithmetic signal, the third transistor has a polarity different from a polarity of the second transistor, and the first transistor has an oxide semiconductor in the channel formation region thereof.

Description

Semiconductor Devices

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] Electronic devices including semiconductor devices such as a central processing unit (CPU) are becoming widespread. To process large amounts of data at high speed, technological developments aimed at improving the performance of semiconductor devices are actively underway. One example of a technology that achieves high performance is the so-called system-on-chip (SoC) approach, in which an accelerator such as a graphics processing unit (GPU) is tightly coupled with a CPU. With semiconductor devices that achieve high performance through SoC implementation, increased heat generation and power consumption become problems.

[0004] In AI (Artificial Intelligence) technology, the amount of calculations and the number of parameters become enormous, resulting in an increase in the amount of calculations. Since an increase in the amount of calculations leads to increased heat generation and power consumption, architectures for reducing the amount of calculations have been actively proposed. Representative architectures include the Binary Neural Network (BNN) and the Ternary Neural Network (TNN), which are particularly effective for reducing circuit size and power consumption (see, for example, Patent Document 1). For example, in a BNN, data originally expressed with 32-bit or 16-bit precision can be compressed into two values, "+1" or "-1," thereby significantly reducing the amount of calculations and the number of parameters. For example, in a TNN, data originally expressed with 32-bit or 16-bit precision can be compressed into three values, "+1," "0," or "-1," thereby significantly reducing the amount of calculations and the number of parameters. BNNs and TNNs are effective in reducing circuit size or power consumption, and are therefore considered to be well suited to applications requiring low power consumption in limited hardware resources, such as embedded chips.

[0005] International Publication No. 2019 / 078924

[0006] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0007] An object of one embodiment of the present invention is to improve the operational efficiency of a semiconductor device. Another object of one embodiment of the present invention is to miniaturize a semiconductor device. Another object of one embodiment of the present invention is to reduce the power consumption of a semiconductor device. Another object of one embodiment of the present invention is to suppress heat generation from a semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure.

[0008] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc.

[0009] One embodiment of the present invention is a semiconductor device including a first signal line, a second signal line, a first transistor, a second transistor, and a third transistor, in which one of a source and a drain of the first transistor is connected to a gate of the second transistor and a gate of the third transistor, one of the source and the drain of the second transistor is connected to one of the source and the drain of the third transistor, the first signal line is connected to the other of the source and the drain of the second transistor, and the second signal line is connected to the other of the source and the drain of the third transistor, the first signal line has a function of supplying an arithmetic signal, the second signal line has a function of supplying an inverted signal of the arithmetic signal, the third transistor has a polarity different from that of the second transistor, and the first transistor has an oxide semiconductor in a channel formation region.

[0010] In the above structure, the third transistor preferably has silicon in a channel formation region.

[0011] In the above structure, the third transistor is preferably a p-channel transistor.

[0012] In the above structure, it is preferable that the semiconductor device has an arithmetic circuit and a fourth transistor, one of a source and a drain of the fourth transistor is connected to one of a source and a drain of the second transistor, and the arithmetic circuit is connected to the other of the source and drain of the fourth transistor.

[0013] In the above structure, the other of the source and the drain of the first transistor is preferably connected to a first signal line.

[0014] Alternatively, one embodiment of the present invention includes a plurality of memory circuits, a first signal line, a second signal line, and an arithmetic circuit, each of the plurality of memory circuits having a function of holding data in a first node, each of the plurality of memory circuits including a first transistor, a second transistor, a third transistor, and a fourth transistor, the third transistor having a polarity different from that of the second transistor, the first node being connected to one of a source and a drain of the first transistor, a gate of the second transistor, and a gate of the third transistor, one of the source and a drain of the second transistor being connected to one of the source and a drain of the third transistor, and one of the source and a drain of the fourth transistor being connected to one of the source and a drain of the second transistor. a first signal line connected to the other of the source and drain of the second transistor in each of the plurality of memory circuits, a second signal line connected to the other of the source and drain of the third transistor in each of the plurality of memory circuits, an arithmetic circuit connected to the other of the source and drain of the fourth transistor in each of the plurality of memory circuits, the first signal line having a function of supplying an arithmetic signal, and the second signal line having a function of supplying an inverted signal of the arithmetic signal, each of the plurality of memory circuits having a function of holding a first potential at a first node and a function of outputting an arithmetic result using the arithmetic signal, an inverted signal of the arithmetic signal, and the first potential, and the arithmetic circuit having a function of adding up the arithmetic results output from each of the plurality of memory circuits.

[0015] In the above structure, the first transistor preferably includes an oxide semiconductor in a channel formation region, and the third transistor preferably includes silicon in a channel formation region.

[0016] In the above structure, the third transistor is preferably a p-channel transistor.

[0017] In the above structure, it is preferable that the first transistor has an oxide semiconductor in a channel formation region, the third transistor has silicon in a channel formation region, the arithmetic circuit has a fifth transistor having silicon in a channel formation region and a sixth transistor having silicon in a channel formation region, and the sixth transistor has a polarity different from that of the fifth transistor.

[0018] In the above structure, the third transistor and the sixth transistor are preferably p-channel transistors.

[0019] According to one embodiment of the present invention, the computing efficiency of a semiconductor device can be improved. According to another embodiment of the present invention, the semiconductor device can be miniaturized. According to another embodiment of the present invention, the power consumption of a semiconductor device can be reduced. According to another embodiment of the present invention, heat generation by a semiconductor device can be suppressed. Furthermore, a semiconductor device with a novel structure can be provided.

[0020] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification.

[0021] FIGS. 1A, 1B, and 1C are diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 2A and 2B are diagrams illustrating an example of the configuration of a semiconductor device. FIG. 3 is a diagram illustrating an example of the configuration of a semiconductor device. FIG. 4 is a diagram illustrating an example of the configuration of a semiconductor device. FIG. 5 is a diagram illustrating an example of the configuration of a semiconductor device. FIGS. 6A and 6B are diagrams illustrating an example of the operation of a semiconductor device. FIGS. 7A and 7B are diagrams illustrating an example of the operation of a semiconductor device. FIGS. 8A, 8B, 8C, 8D, and 8E are diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 9A, 9B, and 9C are diagrams illustrating an example of the configuration of a semiconductor device. FIG. 10A is a diagram illustrating a hierarchical neural network. FIG. 10B is a diagram illustrating an example of the configuration of a semiconductor device. FIGS. 11A and 11B are diagrams illustrating an example of the configuration of a semiconductor device. FIG. 12 is a diagram illustrating an example of the configuration of a semiconductor device. FIGS. 13A and 13B are diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 14A, 14B, and 14C are diagrams illustrating an example of the configuration of a semiconductor device. 15A and 15B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 15C is a cross-sectional view illustrating an indium oxide film. FIGS. 16A, 16B, and 16C are diagrams illustrating an example of an electronic component. FIG. 17 is a diagram illustrating an example of an information processing system. FIG. 18 is a diagram illustrating an example of space equipment. FIG. 19 is a diagram illustrating an example of a storage system applicable to a data center.

[0022] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0023] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0024] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0025] Furthermore, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "[n]", or "[m, n]" may be added to the reference numeral. For example, the second wiring GL is described as wiring GL[2].

[0026] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0027] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0028] Furthermore, the positional relationships of components shown in the drawings are relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" indicating the positional relationships may be used for convenience. The positional relationships of components are not limited to the content described in this specification, and can be rephrased appropriately depending on the situation.

[0029] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0030] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0031] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0032] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0033] Embodiment 1 A structure, operation, and the like of a semiconductor device that is one embodiment of the present invention will be described.

[0034] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0035] FIG. 1A illustrates a configuration example of a memory circuit of one embodiment of the present invention.

[0036] The memory circuit 24 shown in FIG. 1A includes transistors 31A, 32A, 32B, and a capacitance element 34A (also referred to as a capacitor). As shown in FIG. 1A, each element is connected to a write word line WWL, a write bit line WBL, a read bit line RBL, an operation signal line IN, and an operation inversion signal line INb. Mutually inverted signals are applied to the operation signal line IN and the operation inversion signal line INb. Note that each transistor may have a backgate electrode.

[0037] The gate of the transistor 31A is connected to the write word line WWL, one of the source and drain is connected to the write bit line WBL, and the other is connected to a node SN. One electrode of the capacitance element 34A is connected to the node SN, and the other electrode is supplied with a ground potential. Note that although the other electrode of the capacitance element 34A is supplied with a ground potential in the example shown in FIG. 1A, a constant potential signal or the like may also be supplied.

[0038] The gates of the transistors 32A and 32B are connected to the node SN. One of the source and drain of the transistor 32A is connected to the operation signal line IN. One of the source and drain of the transistor 32B is connected to the operation inverted signal line INb. The other of the source and drain of the transistor 32A and the other of the source and drain of the transistor 32B are connected to each other. The other of the source and drain of the transistor 32A and the other of the source and drain of the transistor 32B are connected to the output node X. The output node X is connected to the read bit line RBL.

[0039] Data can be written to node SN from write bit line WBL via transistor 31 A. By turning off transistor 31 A, the written data can be held.

[0040] The memory circuit 24 shown in FIG. 1A is a three-transistor (3T) gain cell. A transistor having an oxide semiconductor in a channel formation region (hereinafter referred to as an OS transistor) is preferably used as the transistor 31A. Because an OS transistor has extremely low leakage current, using an OS transistor as the transistor 31A allows data to be retained at the node SN for a long time. Here, the transistor 31A may be referred to as an access transistor. By using an OS transistor as the access transistor, the memory circuit 24 can be used as a nonvolatile memory with excellent retention characteristics. Furthermore, because OS transistors have excellent radiation resistance, using an OS transistor as the transistor 31A can prevent erroneous data rewriting due to exposure to radiation such as cosmic rays. Therefore, the reliability of data retained in the memory circuit can be improved. Furthermore, the three-transistor gain cell is characterized by high rewrite endurance.

[0041] Furthermore, the memory circuit 24 shown in FIG. 1A is capable of reading data without destroying it (non-destructive reading), and is therefore suitable for parallel processing of product-sum operations in a neural network, which involves repeating a large number of data read operations.

[0042] The transistor 32B has a polarity different from that of the transistor 32A. By using transistors with polarities different from each other as the transistors 32A and 32B, a circuit that performs operations such as exclusive OR and exclusive NOR can be configured with a small number of transistors.

[0043] Here, an n-channel transistor is used as the transistor 32A, and a p-channel transistor is used as the transistor 32B. As the p-channel transistor, for example, a transistor having silicon in a channel formation region (hereinafter referred to as a Si transistor) can be used.

[0044] The transistor 32A may be an OS transistor or a Si transistor.

[0045] The memory circuit 24 can output to the output node X output data based on the exclusive OR (or exclusive NOR) of the data (e.g., weight data) stored in the node SN and the input data provided to the calculation signal line IN.

[0046] The truth table of the memory circuit 24 in FIG. 1A can be expressed as shown in Table 1. In Table 1, H-level and L-level voltages are represented by logic "1" and logic "0," respectively. "IN" corresponds to the logic according to the voltage of the operation signal line IN given as input data. "SN" corresponds to the logic according to the voltage given from the write bit line WBL to the node SN. "X" corresponds to the logic according to the voltage given to the output node X as output data.

[0047]

[0048] The semiconductor device of one embodiment of the present invention can be used as a binary neural network (BNN) by performing an operation using values ​​output to the output nodes X of each of the memory circuits 24. A logic "1" and a logic "0" are data expressed by two values, "+1" or "-1," used in a BNN.

[0049] 1B shows, as an example of a semiconductor device, a memory section 22 having a plurality of memory circuits 24, and an arithmetic circuit 23 connected to the memory section 22. Note that, as an example, the configuration shown in FIG. 1A is used as the memory circuit 24 in FIG. 1B, and the memory sections 22 arranged in one row and N columns (N is a natural number of 2 or more) are connected to the arithmetic circuit 23.

[0050] The write word line WWL is shared by a plurality of memory circuits 24 arranged in one row. Each of the write bit lines WBL_1 to WBL_N, each of the operation signal lines IN_1 to IN_N, each of the operation inverted signal lines INb_1 to INb_N, and each of the read bit lines RBL_1 to RBL_N are connected to the memory circuits 24 in different columns.

[0051] The operation result of memory circuit 24 is output to operation circuit 23 from read bit line RBL.

[0052] The arithmetic circuit 23 has a function of performing one of processes such as integer arithmetic, single-precision floating-point arithmetic, and double-precision floating-point arithmetic using the digital value data held in each of the memory circuits 24 of the memory unit 22. The arithmetic circuit 23 has a function of repeatedly executing the same process such as a multiply-and-accumulate operation.

[0053] The memory circuit 24 shown in FIG. 2A differs from that shown in FIG. 1A in that it includes a transistor 33A and a read word line RWL. The memory circuit 24 shown in FIG. 2A can output a signal from an output node X to a read bit line RBL via the transistor 33A. The gate of the transistor 33A is connected to the read word line RWL, and one of the source and drain of the transistor 33A is connected to the output node X, and the other is connected to the read bit line RBL. The transistor 33A may be an OS transistor or a Si transistor. The transistors 32A and 33A may each be an OS transistor or a Si transistor, examples of which will be described later with reference to FIGS. 9A to 9C .

[0054] 2B shows an example in which the write bit line WBL and the operation signal line IN are shared in FIG. 2A. In the memory circuit 24 shown in FIG. 2B, the write bit line WBL can also function as the operation signal line IN. One of the source and drain of the transistor 32A is connected to the write bit line WBL.

[0055] The memory circuit 24 shown in FIG. 2A and the memory circuit 24 shown in FIG. 2B are each four-transistor (4T) gain cells.

[0056] 2A, by providing the write bit line WBL and the operation signal line IN separately, it is possible to independently perform writing to the node SN of the memory circuit 24 and an operation based on the exclusive OR in the memory circuit 24. Therefore, for example, among different memory circuits 24 connected to the same write bit line WBL, it is possible to perform writing in the memory circuit 24 of one row and perform an operation in the memory circuit 24 of a different row and output the operation result.

[0057] On the other hand, in the configuration shown in FIG. 2B, the write bit line WBL and the operation signal line IN are shared, thereby reducing the number of wirings and the circuit area of ​​the memory section 22.

[0058] In the configuration shown in FIG. 2B, when data is written to node SN, a voltage corresponding to the data to be written is applied to write bit line WBL, and when an operation based on exclusive OR is performed, a voltage corresponding to an operation signal is applied to write bit line WBL.

[0059] The transistor 33A functions as a switch that controls the output of data from the output node X to the read bit line RBL. The switching of the switch can be controlled by a signal on the read word line RWL.

[0060] 3 shows, as an example of a semiconductor device, a memory section 22 having a plurality of memory circuits 24 and an arithmetic circuit 23 connected to the memory section 22. In the memory section 22, the plurality of memory circuits 24 are arranged in a matrix. Note that in FIG. 3, the configuration shown in FIG. 2B is used as the memory circuit 24 as an example.

[0061] 3 illustrates write word lines WWL_1 to WWL_M, read word lines RWL_1 to RWL_M, write bit lines WBL_1 to WBL_N, operation inversion signal lines INb_1 to INb_N, and read bit lines RBL_1 to RBL_N, which are arranged in a matrix of M rows and N columns (M and N are natural numbers of 2 or greater). Also illustrated are a plurality of memory circuits 24 connected to each word line and bit line.

[0062] The memory circuits 24 arranged in the same column are connected to the same read bit line RBL. Which memory circuit 24 is selected among the memory circuits 24 arranged in the same column can be controlled by a signal to the read word line RWL. That is, by applying a selection signal to the read word line RWL, a memory circuit 24 is selected, and the operation result is output from the selected memory circuit 24 to the read bit line RBL.

[0063] Among the memory circuits 24 connected to the same read bit line RBL, the operation results of the memory circuits 24 from the first row to the Mth row can be sequentially output to the arithmetic circuit 23. The arithmetic circuit 23 has a function of adding the operation results sequentially output.

[0064] The data held in node SN can be, for example, data W, which is weight data used in product-sum calculations of a neural network. The memory unit 22 can hold weight data and generate a signal based on an exclusive NOR (ExNOR) with input data, and can be configured as shown in FIG.

[0065] As shown in FIG. 4, weight data W １１ Data W ＭＮ is stored in the memory unit 35, and input data is provided to the exclusive NOR unit 36 ​​(ExNOR) via the operation signal lines IN_1 to IN_N, so that output data based on the exclusive NOR of the weight data and the input data can be output to the read bit lines RBL_1 to RBL_N.

[0066] Although the exclusive NOR operation has been described here, it is also possible to make the memory circuit 24 function as an exclusive OR (ExOR) operation circuit by swapping the operation signal line IN and the inverted operation signal line INb. For example, in Fig. 1A, the operation signal line IN is connected to one of the source and drain of the transistor 32A, and the inverted operation signal line INb is connected to one of the source and drain of the transistor 32B. However, if the inverted operation signal line INb is connected to one of the source and drain of the transistor 32A, and the operation signal line IN is connected to one of the source and drain of the transistor 32B, as shown in Fig. 1C, the truth table of the memory circuit 24 can be expressed as shown in Table 2.

[0067]

[0068] 5 is a schematic diagram illustrating a memory unit 22 having a plurality of memory circuits 24 and an arithmetic circuit 23 connected to the memory unit 22. As described above, each of the memory circuits 24 in the memory unit 22 includes a storage unit 35 and a multiplication unit 40. The weight data W １ Data W ｋ (k is a natural number of 2 or more) is stored in the storage unit 35, and is input via the calculation signal line IN (write bit line WBL) and the calculation inversion signal line INb. １ Data A ｋ and an output signal Y, which is a 1-bit digital signal corresponding to the multiplication １ (=A １ ×W １ ) to output signal Y ｋ (=A ｋ ×W ｋ ) is given to the arithmetic circuit 23.

[0069] The output signals of the memory circuits 24 of the memory unit 22 for each row are sequentially output to the arithmetic circuit 23 via the read bit line RBL. For example, if the memory circuit 24 of the first row (data W １ When the calculation result of the memory circuit 24 having ｋ = A １ ×W １is applied to the read bit line RBL, and the memory circuit 24 in the kth row (data W ｋ When the calculation result of the memory circuit 24 having ｋ = A ｋ ×W ｋ is given.

[0070] 5 includes an accumulator 49 and an encoding circuit 45. The arithmetic circuit 23 can generate a signal Q that has been subjected to a product-sum operation by adding together the multiplied output signals.

[0071] 6A and 6B, an example of the method of operation of the memory circuit 24 shown in FIG. 2B will be described.

[0072] Fig. 6A is a timing chart corresponding to the operation of memory circuit 24 shown in Fig. 2B, and Fig. 6B shows an example of the state of memory circuit 24 corresponding to period T13 in Fig. 6A. In Fig. 2B, write bit line WBL can also function as operation signal line IN.

[0073] 6B , the “x” marks shown for transistors 31A and 32A indicate a state in which transistors 31A and 32A are off and a potential corresponding to logic “0” is held at node SN. The arrow from write bit line WBL to transistor 32A indicates a state in which a potential corresponding to logic “0” is applied to write bit line WBL, which functions as operation signal line IN, but is not output to node X because transistor 32A is off. The arrow from operation inversion signal line INb to node X indicates a state in which a potential corresponding to logic “1” is applied to operation inversion signal line INb and is output to node X via transistor 32B. The arrow from node X to read bit line RBL indicates a state in which the potential applied to node X is further output from node X to read bit line RBL via transistor 33A.

[0074] During period T11, a signal H is applied to the write word line WWL. Here, signal H is a high potential signal. Furthermore, data to be written to node SN is applied to the write bit line WBL. Either logic "1" or logic "0" data is applied to node SN. Here, for example, a high potential signal is applied as a signal corresponding to logic "1," and for example, a low potential signal is applied as a signal corresponding to logic "0." An inverted signal of the write bit line WBL is applied to the operation inversion signal line INb. That is, when logic "1" data is applied to the write bit line WBL, logic "0" data is applied to the operation inversion signal line INb, and when logic "0" data is applied to the write bit line WBL, logic "1" data is applied to the operation inversion signal line INb. During period T11, transistor 31A is turned on, and the potential of node SN changes in accordance with the data applied to the write bit line WBL.

[0075] During the period T11, the read word line RWL is supplied with a signal L. Here, the signal L is a low-potential signal. Since the transistor 33A is in the off state during the period T11, the operation of the memory circuit 24 during the period T11 does not affect the potential of the read bit line RBL.

[0076] After the data is written to the node SN, a signal L is applied to the write word line WWL before the period T11 switches to the next period T12, thereby turning off the transistor 31A and holding the data written to the node SN.

[0077] Next, in period T12, the signal L continues to be applied to the write word line WWL and the read word line RWL. Before the period T12 switches to the next period T13, the signal L is applied to the write bit line WBL. An inverted signal of the write bit line WBL is applied to the operation inversion signal line INb.

[0078] Period T12 is a period for preventing erroneous writing. Before switching from period T11 to the next period T12, the signal supplied to the write word line WWL is changed from signal H to signal L, turning off the transistor 31A. If the signal supplied to the write bit line WBL is changed before this operation is performed, the potential of the node SN will fluctuate, causing erroneous writing. By separating the period in which the write word line WWL is changed to signal L (period T11) from the period in which the signal supplied to the write bit line WBL is changed (period T12), erroneous writing can be prevented.

[0079] Next, in period T13, an exclusive OR operation is performed using the logic corresponding to the signal applied to the write bit line WBL (IN in Table 1 described above) and the logic corresponding to the signal held at node SN (SN in Table 1 described above). When applying a signal corresponding to logic "1" to the write bit line WBL, for example, a high potential signal is applied, and when applying a signal corresponding to logic "0", for example, a low potential signal is applied. An inverted signal of the write bit line WBL is also applied to the operation inversion signal line INb.

[0080] During period T13, the read word line RWL is supplied with a signal H. During period T13, the transistor 33A is turned on, and the operation result is output to the read bit line RBL via the transistor 33A.

[0081] 3, a plurality of memory circuits 24 arranged in the column direction can be connected to the read bit line RBL. At this time, in a memory circuit 24 selected by the read word line RWL, i.e., a memory circuit 24 to which a signal H is applied to the read word line RWL, the operation result is output to the read bit line RBL. In an unselected memory circuit 24, the transistor 33A is turned off by applying a signal L to the read word line RWL. Therefore, even in an unselected memory circuit 24, when a signal is applied to the write bit line WBL and the operation inversion signal line INb, an operation is performed within the memory circuit 24, but the operation result is not output to the read bit line RBL.

[0082] 6B shows, as an example, the operation of memory circuit 24 when logic "0" is applied as "SN" and logic "0" is applied as "IN". When data corresponding to logic "0", here signal L, is applied to node SN, transistor 31A is turned off and transistor 32A is turned on. When transistor 32A is turned on, a signal applied to operation inversion signal line INb via transistor 32A, here logic "1" as the inverse of logic "0" of "IN", is output to read bit line RBL. In other words, logic "1" is output to read bit line RBL as the operation result.

[0083] When logic "0" is given as "SN" and logic "1" is given as "IN", the signal given to the operation inversion signal line INb via transistor 32A, in this case logic "0", is output to the read bit line RBL as the inverse of the logic "1" of "IN".

[0084] Furthermore, when logic "1" is applied as "SN" and logic "0" is applied as "IN", transistor 31A is turned on and transistor 32A is turned off. When transistor 31A is turned on, the signal applied to operation signal line IN via transistor 31A, in this case logic "0", is output to read bit line RBL. That is, logic "0" is output to read bit line RBL as the operation result.

[0085] When logic "1" is given as "SN" and logic "1" is given as "IN", the signal given to the operation signal line IN via transistor 31A, in this case the logic "1" of "IN", is output to the read bit line RBL.

[0086] By the above operation, data can be held and calculations can be performed using the memory circuit 24 shown in FIG. 2A.

[0087] Next, an example of the operation method of the memory circuit 24 shown in FIG. 1A will be described with reference to FIGS. 7A and 7B.

[0088] FIG. 7A is a timing chart corresponding to the operation of the memory circuit 24 shown in FIG. 1A, and FIG. 7B shows an example of the state of the memory circuit 24 corresponding to a period T23 in FIG. 7A.

[0089] During a period T21, a signal H is applied to the write word line WWL, and data to be written to the node SN is applied to the write bit line WBL. During the period T21, the transistor 31A is turned on, the potential of the node SN changes in accordance with the applied data, and data corresponding to either a logic "1" or a logic "0" is applied to the node SN.

[0090] Furthermore, period T21 is a write period for node SN, and no calculation using "IN" and "SN" is performed yet. Therefore, certain signals are applied to the calculation signal line IN and the calculation inversion signal line INb, respectively, and data is accordingly output to the read bit line, but during period T21 and the following period T22, the data output to the read bit line is not used for calculation processing in the calculation circuit 23. When data corresponding to a logic "1" is applied to node SN, transistor 31A is turned on, and the signal of the calculation signal line IN is output to the read bit line RBL during period T21. When data corresponding to a logic "0" is applied to node SN, transistor 32A is turned on, and the signal of the calculation inversion signal line INb is output to the read bit line RBL during period T21.

[0091] 1A shows a configuration in which the write bit line WBL and the operation signal line IN are independent, but if the write bit line WBL and the operation signal line IN are configured to serve as a combined line, the signal on the operation signal line IN corresponds to the signal on the write bit line WBL. In this case, when data corresponding to a logic "1" is applied to the node SN, the transistor 31A is turned on, and the signal on the write bit line WBL, i.e., the signal H, is output to the read bit line RBL during the period T21. When data corresponding to a logic "0" is applied to the node SN, the transistor 32A is turned on, and the signal on the operation inverted signal line INb, i.e., the signal H which is the inverted signal of the write bit line WBL, is output to the read bit line RBL during the period T21.

[0092] After the data is written to the node SN, a signal L is applied to the write word line WWL before the period T21 switches to the next period T22, thereby turning off the transistor 31A and holding the data written to the node SN.

[0093] Next, in period T22, the write word line WWL continues to be supplied with the signal L. Before the period T22 switches to the next period T23, the signal L is supplied to the write bit line WBL.

[0094] In the memory circuit 24 shown in FIG. 1A, the write bit line WBL and the operation signal line IN are independent, and therefore, unlike the memory circuit shown in FIG. 2B, the write bit line WBL is not used as a signal line in the operation performed in the next period T23. Therefore, even in the period T23, the signal on the write bit line WBL can be varied independently of the operation performed in the memory circuit 24. Therefore, the period T22 does not need to be provided. In such a case, the signal supplied to the write bit line WBL in the next period T23 may remain as signal H. Alternatively, signal L may be supplied.

[0095] Next, during period T23, an exclusive OR operation is performed using the logic corresponding to the signal applied to operation signal line IN (IN in Table 1 described above) and the logic corresponding to the signal held at node SN (SN in Table 1 described above). An inverted signal of operation signal line IN is applied to operation inverted signal line INb. The operation result is applied as output data to operation circuit 23 via read bit line RBL, and operation circuit 23 performs an operation using the output data.

[0096] 7B shows an example of the operation of memory circuit 24 when logic "0" is applied as "SN" and logic "0" is applied as "IN." As a result of the operation, logic "1" is output to read bit line RBL.

[0097] By the above operation, data can be held and calculations can be performed using the memory circuit 24 shown in FIG. 1A.

[0098] 8A is a diagram illustrating a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 includes a CPU 10, an accelerator 20, and a bus 30. The accelerator 20 includes an arithmetic processing unit 21 and a memory unit 22. The arithmetic processing unit 21 includes an arithmetic circuit 23. The memory unit 22 includes a memory circuit 24. The memory unit 22 may also be referred to as a device memory or a shared memory.

[0099] The CPU 10 has a function of performing general-purpose processing, such as executing an operating system, controlling data, and executing various calculations and programs. The CPU 10 has one or more CPU cores. Each CPU core has a data retention circuit that can retain data even when the supply of power voltage is stopped. The supply of power voltage can be controlled by electrically disconnecting it from a power domain using a power switch or the like. The power voltage may also be referred to as a drive voltage. For example, a memory including a transistor (OS transistor) having an oxide semiconductor in a channel formation region is suitable as the data retention circuit. The oxide semiconductor is also called a metal oxide.

[0100] The accelerator 20 has a function of executing a program (also called a kernel or kernel program) called from a host program. The accelerator 20 can perform, for example, parallel processing of matrix operations in graphics processing, parallel processing of product-sum operations in neural networks, and parallel processing of floating-point operations in scientific and technological calculations.

[0101] The bus 30 connects the CPU 10 and the accelerator 20. That is, the CPU 10 and the accelerator 20 can transmit data via the bus 30.

[0102] The memory unit 22 has a function of storing and generating data to be processed by the accelerator 20. Specifically, it has a function of storing weight data (also referred to as a first data signal) used in parallel processing of product-sum operations of the neural network. The memory unit 22 also has a function of generating output data (a third data signal) according to the result of multiplication by input data (also referred to as a second data signal). The memory unit 22 has a function of inputting the generated output data to the arithmetic processing unit 21.

[0103] The memory circuit 24 is connected to the arithmetic circuit 23 of the arithmetic processing unit 21 and has the function of storing weight data expressed in binary, that is, a 1-bit digital signal. The memory circuit 24 also has the function of generating a signal obtained by exclusive ORing the result of multiplying the weight data by the input data.

[0104] As shown in Fig. 8B, the accelerator 20 can have a stacked structure of a layer 910 and a layer 920 over the layer 910. The layer 910 is, for example, a layer including a Si transistor. The layer 920 is, for example, a layer including an OS transistor. Fig. 8C shows an enlarged view of a portion of Fig. 8B.

[0105] The arithmetic circuit 23 of the arithmetic processing unit 21 is preferably provided using Si transistors in the layer 910. By configuring the arithmetic circuit 23 as a CMOS circuit including n-channel Si transistors and p-channel Si transistors in the layer 910, the speed of the arithmetic processing can be increased.

[0106] A part of the memory circuit 24 included in the memory portion 22 (shown as a region 24b in FIG. 8B ) can be provided in the layer 920. In particular, a transistor having a function of retaining data written to the node SN (for example, the transistor 31A in FIG. 1A ) is preferably provided in the layer 920.

[0107] A part of the memory circuit 24 included in the memory portion 22 (shown as a region 24a in FIG. 8B ) can be provided in the layer 910. For example, a p-channel transistor having a polarity different from that of an OS transistor can be formed in the layer 910. The transistor 32B shown in FIG. 1A and the like is preferably provided in the layer 910.

[0108] The region 24b of the layer 920 can be stacked with the arithmetic circuit 23 and the region 24a of the layer 910. This allows the region 24a and the region 24b to be arranged without increasing the circuit area. The region 24a and the region 24b are connected via a wiring 39 that extends in a direction substantially perpendicular to the surface of the substrate on which the layer 910 is arranged. Here, "substantially perpendicular" refers to a state in which the region 24a and the region 24b are arranged at an angle of 85 degrees or more and 95 degrees or less.

[0109] Although FIGS. 8B and 8C show an example in which the region 24a and the region 24b are connected via the wiring 39, the arithmetic circuit 23 and the region 24b may be connected via the wiring 39 as shown in FIG. 8D.

[0110] As shown in FIG. 8E, regions 24a and 24b, and arithmetic circuit 23 and region 24b may both be connected by wiring (shown here as wiring 39a and wiring 39b) extending in a direction approximately perpendicular to the substrate surface on which layer 910 is provided.

[0111] 9A to 9C show examples of a configuration in which the arithmetic circuit 23 and the transistors and capacitors included in the memory circuit 24 are arranged in layers 910 and 920. FIG.

[0112] The operational circuitry 23 is preferably located on layer 910 .

[0113] The memory circuit 24 includes a region 24a arranged in the layer 910 and a region 24b arranged in the layer 920. An OS transistor is preferably used as the transistor 31A included in the memory circuit 24. A Si transistor, for example, can be used as the transistor 32B. Therefore, the transistor 32B can be provided in the region 24a, and the transistor 31A can be provided in the region 24b.

[0114] The transistors 32A and 33A may each be an OS transistor or a Si transistor.

[0115] 9A illustrates an example in which an OS transistor is used as the transistor 32A and a Si transistor is used as the transistor 33A. The transistor 32A can be provided in the region 24b, and the transistor 33A can be provided in the region 24a.

[0116] In the configuration example shown in FIG. 9A, two wirings 39 are arranged to connect between the layer 910 and the layer 920, one of which connects the gate of the transistor 32B to the other of the source and drain of the transistor 31A, and the other of which connects the source and drain of the transistor 33A to the other of the source and drain of the transistor 32A.

[0117] 9B illustrates an example in which OS transistors are used as the transistors 32A and 33A. The transistors 32A and 33A can be provided in the region 24b.

[0118] In the configuration example shown in Figure 9B, three wirings 39 are arranged to connect between layer 910 and layer 920, and compared to Figure 9A, an additional wiring 39 is arranged to connect the other of the source and drain of transistor 33A to the arithmetic circuit 23.

[0119] 9C shows an example in which Si transistors are used as the transistors 32A and 33A. The transistors 32A and 33A can be provided in the region 24a. By using a Si transistor with a high operating speed as the transistor 32A, the speed of operations based on exclusive OR in the memory circuit 24 may be increased.

[0120] In the configuration example shown in Figure 9C, two wirings 39 are arranged to connect between layer 910 and layer 920, one of which connects one of the source and drain of transistor 31A to one of the source and drain of transistor 32A, and the other of which connects the gate of transistor 32B to the other of the source and drain of transistor 31A.

[0121] 9A and 9C , the transistor 33A can be provided in the layer 910 where the arithmetic circuit 23 is provided, so that the wiring connecting the arithmetic circuit 23 to the other of the source and drain of the transistor 33A does not need to be elevated up to the layer 920. This increases the degree of freedom in arranging the transistors and wiring in the circuit, which may increase the degree of circuit integration. Furthermore, the shorter wiring length may reduce the delay time of the circuit. In such cases, the speed of circuit operation can be increased.

[0122] 9B, the number of transistors arranged in layer 910 of memory circuit 24 can be reduced, so the area of ​​region 24a is smaller and the area of ​​region 24b is larger than in other configurations. Region 24b can be arranged to overlap arithmetic circuit 23 and region 24a, so the effect of reducing the circuit area by stacking layer 910 and layer 920 may be even greater.

[0123] 9A to 9C show an example in which the capacitance element 34A is arranged on the layer 920, the capacitance element 34A may be arranged on a layer above the layer 920, or may be arranged on a layer between the layers 910 and 920.

[0124] Metal oxides suitable for oxide semiconductors have a wide band gap, and OS transistors have extremely small off-state current. A memory using an OS transistor has an extremely small amount of charge leaking from a storage node through the OS transistor. Therefore, the memory can function as a nonvolatile memory circuit, enabling power gating of an accelerator.

[0125] High-density integrated semiconductor devices may generate heat due to circuit operation. This heat increases the temperature of a transistor, which can change the characteristics of the transistor, resulting in a change in field-effect mobility or a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so their field-effect mobility is less likely to change with temperature, and their operating frequency is less likely to decrease. Furthermore, OS transistors tend to maintain the characteristic that their drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, OS transistors can operate stably even in high-temperature environments.

[0126] In order to improve the reliability and electrical characteristics of an OS transistor, a metal oxide used for a semiconductor layer preferably has crystallinity.

[0127] Metal oxides have a wide band gap, electrons are less likely to be excited, and the effective mass of holes is large. Therefore, avalanche breakdown and the like may be less likely to occur in OS transistors than in general Si transistors. Therefore, for example, hot carrier degradation and the like caused by avalanche breakdown can be suppressed. By suppressing hot carrier degradation, the OS transistor can be driven at a high drain voltage.

[0128] An OS transistor is an accumulation-type transistor in which electrons serve as majority carriers. Therefore, the OS transistor is less susceptible to drain-induced barrier lowering (DIBL), which is one of the short-channel effects, compared to an inversion-type transistor (typically, a Si transistor) having a pn junction. That is, an OS transistor has higher resistance to the short-channel effect than a Si transistor.

[0129] Since OS transistors have high resistance to the short-channel effect, their channel lengths can be reduced without deteriorating their reliability, and therefore, the use of OS transistors can increase the degree of circuit integration. Although the drain electric field increases with the reduction in channel length, as described above, OS transistors are less susceptible to avalanche breakdown than Si transistors.

[0130] Furthermore, because OS transistors have high resistance to short-channel effects, their gate insulating films can be thicker than those of Si transistors. For example, even for minute transistors with a channel length and a channel width of 100 nm or less, a thick gate insulating film of about 10 nm can be provided. By thickening the gate insulating film, parasitic capacitance can be reduced, thereby improving the operating speed of the circuit. Furthermore, by thickening the gate insulating film, leakage current through the gate insulating film can be reduced, leading to a reduction in static current consumption.

[0131] The accelerator 20 can retain data even when the supply of power supply voltage is stopped by having the memory circuit 24. This enables power gating of the accelerator 20, thereby enabling a significant reduction in power consumption.

[0132] The arithmetic processing unit 21 includes an arithmetic circuit 23. The arithmetic processing unit 21 has a function of performing arithmetic processing using digital values. Digital values ​​are less susceptible to noise. Therefore, the accelerator 20 is suitable for performing arithmetic processing that requires highly accurate calculation results. The arithmetic processing unit 21 is preferably configured using a Si CMOS. With this configuration, the arithmetic processing unit 21 can be stacked with an OS transistor.

[0133] The arithmetic circuits 23 may be configured (column-parallel calculation) in which one arithmetic circuit 23 is provided for each read bit line of the memory circuit 24, i.e., for each column. This configuration allows parallel arithmetic processing of data for one row of the memory circuit 24 (up to all bit lines). Compared to multiply-and-accumulate operations using the CPU 10, column-parallel calculation is not limited by the data bus size (e.g., 32 bits) between the CPU and memory. This significantly increases the parallelism of calculations, thereby improving the efficiency of computations required for massive computations, such as deep neural network learning (AI technology) and scientific and engineering calculations using floating-point arithmetic. Additionally, because data output from the memory circuit 24 can be read after calculations are completed, the power consumed during memory access (data transfer between the CPU and memory, and calculations by the CPU) can be reduced, suppressing increases in heat generation and power consumption. Furthermore, by shortening the physical distance between the arithmetic circuit 23 and the memory circuit 24, for example by stacking the layers, the parasitic capacitance generated in the signal lines can be reduced, thereby making it possible to reduce power consumption.

[0134] One embodiment of the present invention can reduce the size of a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. Another embodiment of the present invention can reduce the power consumption of a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. Another embodiment of the present invention can suppress heat generation in a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. Another embodiment of the present invention can reduce the number of data transfers between a CPU and a semiconductor device that functions as a memory in a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. In other words, a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters, has a non-von Neumann architecture, and can perform parallel processing with significantly less power consumption than a von Neumann architecture, which consumes more power as the processing speed increases.

[0135] FIG. 10A illustrates a hierarchical neural network based on a binary neural network (BNN) architecture. This diagram illustrates a fully connected neural network with a neuron 50, one input layer (I1), three hidden layers (M1 to M3), and one output layer (O1). If the number of neurons in the input layer I1 is 786, the number of neurons in the hidden layers M1 to M3 is 256, and the number of neurons in the output layer O1 is 10, the number of connections in each layer (layers 51, 52, 53, and 54) is (784 × 256) + (256 × 256) + (256 × 256) + (256 × 10), or a total of 334,336. In other words, the weight parameters required for neural network calculations are approximately 330 Kbits in total, providing a memory capacity sufficient for implementation even in a small-scale system.

[0136] Next, FIG. 10B shows a detailed block diagram of a semiconductor device 100 capable of performing the neural network calculations shown in FIG. 10A.

[0137] FIG. 10B illustrates an example of the configuration of the memory section 22 and memory circuit 24 described in FIGS. 8A and 8B, as well as peripheral circuits for driving each component.

[0138] 10B shows a controller 61, a row decoder 62, a word line driver 63, a column decoder 64, a write driver 65, a precharge circuit 66, a sense amplifier 67, a selector 68, an input buffer 71, and an arithmetic control circuit 72.

[0139] 11A is a diagram illustrating blocks that control the memory unit 22 for each configuration illustrated in FIG. 10B. In FIG. 11A, a controller 61, a row decoder 62, a word line driver 63, a column decoder 64, a write driver 65, a precharge circuit 66, a sense amplifier 67, and a selector 68 are illustrated.

[0140] The controller 61 processes externally input signals and generates control signals for the row decoder 62 and the column decoder 64. The externally input signals are control signals such as a write enable signal and a read enable signal for controlling the memory unit 22. The controller 61 also inputs and outputs data to be written to or read from the memory unit 22 to and from the CPU 10 via a bus.

[0141] The row decoder 62 generates signals for driving the word line driver 63. The word line driver 63 generates signals to be applied to the write word line WWL and the read word line RWL. The column decoder 64 generates signals for driving the sense amplifier 67 and the write driver 65. The sense amplifier 67 amplifies the potential of the read bit line RBL. The write driver 65 generates signals for controlling the read bit line RBL and the write bit line WBL. The precharge circuit 66 has the function of precharging the read bit line RBL and the like. Signals read from the memory circuit 24 of the memory unit 22 can be input to the arithmetic circuit 23 and can also be output via the selector 68. The selector 68 sequentially reads data corresponding to the bus width and outputs the required data to the CPU 10, etc. via the controller 61.

[0142] FIG. 11B is a diagram illustrating the blocks that control the arithmetic processing unit 21 extracted from the configurations shown in FIG. 10B.

[0143] The controller 61 processes an external input signal and generates a control signal for the arithmetic control circuit 72. The controller 61 also generates various signals for controlling the arithmetic circuit 23 of the arithmetic processing unit 21. The controller 61 also inputs and outputs data related to the arithmetic results via an input buffer 71. By using the input buffer 71, parallel calculations with a number of bits greater than the data bus width of the CPU become possible. Furthermore, the number of times a huge number of weight parameters are transferred between the CPU 10 can be reduced, thereby achieving low power consumption.

[0144] One embodiment of the present invention can reduce the size of a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. Another embodiment of the present invention can reduce the power consumption of a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. Another embodiment of the present invention can suppress heat generation in a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. Another embodiment of the present invention can reduce the number of data transfers between a CPU and a semiconductor device that functions as a memory in a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. In other words, a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters, has a non-von Neumann architecture, and can perform parallel processing with significantly less power consumption than a von Neumann architecture, which consumes more power as the processing speed increases.

[0145] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0146] Embodiment 2 In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described.

[0147] <Structure Example of Semiconductor Device> FIG. 12 illustrates an example of a cross-sectional view of a semiconductor device of one embodiment of the present invention.

[0148] 12 includes a layer 801 and a layer 802 on the layer 801. In addition, in Fig. 12, wiring, plugs, etc. are disposed between the layer 801 and the layer 802. Furthermore, wiring, semiconductor elements, etc. are disposed on the layer 802.

[0149] 12 , a layer 801 has transistors Tr11 and Tr12, a layer 802 has transistors Tr21 and Tr22, and a capacitance element CA is provided on the layer 802. The configuration of the layer 801 and the configuration of the layer 802 can be applied to the previously described layers 910 and 920, respectively, the transistor Tr12 can be applied to the previously described transistor 32B, the transistor Tr21 can be applied to the previously described transistor 31A, and the capacitance element CA can be applied to the previously described capacitance element 34A.

[0150] The configuration of transistor Tr11 can be applied to the previously described transistors 33A and 32A. Transistor Tr22 has a configuration similar to that of transistor Tr21, for example. Transistor Tr22 can also be applied to the previously described transistors 33A and 32A. The configuration shown in FIG. 12 can be applied to the connection of a memory circuit in which, for example, transistor Tr11 corresponds to transistor 33A and transistor Tr22 corresponds to transistor 32A.

[0151] The layer 801 preferably includes a transistor using silicon, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. In particular, the layer 801 preferably includes a transistor using silicon.

[0152] The layer 802 preferably includes a transistor using a metal oxide, and preferably includes a transistor including a metal oxide that functions as an oxide semiconductor.

[0153] The layer 801 includes a transistor Tr12. The layer 801 may include a transistor Tr11 in addition to the transistor Tr12. The transistor Tr11 has a polarity different from that of the transistor Tr12. Here, as an example, a p-channel transistor is used as the transistor Tr12, and an n-channel transistor is used as the transistor Tr11.

[0154] The transistor Tr12 is provided on a substrate 311 and has a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313a that is part of the substrate 311, and a low-resistance region 314a1 and a low-resistance region 314a2 that function as a source region or a drain region.

[0155] The transistor Tr11 is provided on a substrate 311 and has a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313b that is a part of the substrate 311, and a low-resistance region 314b1 and a low-resistance region 314b2 that function as a source region or a drain region.

[0156] The semiconductor region 313a and its neighboring region, the semiconductor region 313b and its neighboring region, the low-resistance region 314a1, the low-resistance region 314a2, the low-resistance region 314b1, and the low-resistance region 314b2 can each be formed using silicon, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. Formation using single-crystal silicon is particularly preferable. Alternatively, a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistors Tr11 and Tr12 may be, for example, HEMTs (High Electron Mobility Transistors) using gallium arsenide and aluminum gallium arsenide.

[0157] Here, in the transistor Tr11 and the transistor Tr12 shown in FIG. 12, the semiconductor regions 313b and 313a in which channels are formed have convex shapes.

[0158] FIG. 13A shows a cross section of the transistor Tr11 perpendicular to the cross section shown in FIG. 12 . As shown in FIG. 13A , a conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313b via an insulating layer 315. As described above, the transistors Tr11 and Tr12 are also called FIN-type transistors because they utilize the convex portions of the semiconductor substrate. An insulating layer may be provided in contact with the top of the convex portions and function as a mask for forming the convex portions. While the case where the convex portions are formed by processing a portion of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate. The conductive layer 316 may be made of a material that adjusts the work function.

[0159] Adjacent transistors in the layer 801 are electrically isolated from each other by an isolation region 321. The isolation region can be formed by a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or the like.

[0160] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0161] On the transistors Tr11 and Tr12, insulating layers 320, 326, 342, 344, 350, and 351 are stacked in this order as interlayer films. Conductive layers such as conductive layers 328a, 328b, 328c, and 328d are embedded in the insulating layer 320. Conductive layers such as conductive layers 330a, 330b, and 330c are embedded in the insulating layer 326. Conductive layers such as conductive layers 332a, 332b, and 332c are embedded in the insulating layer 342. Conductive layers such as conductive layers 334a, 334b, and 334c are embedded in the insulating layer 344. Conductive layers such as conductive layers 336a and 336b are embedded in the insulating layers 350 and 351. These conductive layers function as plugs or wiring.

[0162] The low resistance region 314a2 of transistor Tr12, the low resistance region 314b1 of transistor Tr11, and the conductive layer 220 of transistor Tr22 are connected to each other via conductive layers 328c, 330b, 328b, 332b, 334b, 336a, etc.

[0163] The conductive layer 316 of the transistor Tr12 and the conductive layer 220 of the transistor Tr21 are connected to each other via the conductive layer 328d, the conductive layer 330c, the conductive layer 332c, the conductive layer 334c, the conductive layer 336b, and the like.

[0164] The low-resistance region 314b2 of the transistor Tr11 can be connected to a circuit provided in the layer 801 via the conductive layers 328a, 330a, 332a, and 334a. For example, it can be connected to the aforementioned arithmetic circuit 23. At least a part of these conductive layers can be made to function as the aforementioned read bit line RBL.

[0165] A layer 802 is provided over the insulating layer 351 .

[0166] The layer 802 includes a transistor Tr21. The layer 802 may also include a transistor Tr22 in addition to the transistor Tr21.

[0167] In FIG. 12, a transistor Tr21, a transistor Tr22, and an insulating layer 280 are provided on an insulating layer 351.

[0168] 12 shows an example of the configuration of vertical channel transistors, with transistors Tr21 and Tr22. A vertical channel transistor has a structure in which the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction).

[0169] The vertical channel transistor may also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, or a vertical channel transistor.

[0170] In this specification, in a vertical channel transistor, one of the source electrode and the drain electrode located at the bottom may be referred to as a bottom electrode, and the other of the source electrode and the drain electrode located at the top may be referred to as an top electrode.

[0171] The structure of the vertical channel transistor will be described below. Note that the transistor Tr22 can have the same structure as the transistor Tr21, so the structure of the transistor Tr21 will be described here.

[0172] FIG. 13B shows a cross section of the transistor Tr21 perpendicular to the cross section shown in FIG.

[0173] The transistor Tr21 includes a conductive layer 220 that functions as at least one of a wiring and an electrode, a conductive layer 240 that functions as at least one of a wiring and an electrode, a semiconductor layer 230, an insulating layer 250 that functions as a gate insulating film, and a conductive layer 260 that functions as a gate.

[0174] The conductive layer 220 is provided over the insulating layer 351 which functions as an interlayer film. The conductive layer 220 also functions as a wiring. The conductive layer 220 may be provided to extend over a plurality of transistors provided in the layer 802.

[0175] An insulating layer 280 functioning as an interlayer film and a conductive layer 240 are formed in this order over the insulating layer 351 and the conductive layer 220. Note that the conductive layer 240 also functions as a wiring. Therefore, the conductive layer 240 may be provided to extend over a plurality of transistors provided in the layer 802.

[0176] Furthermore, openings reaching the conductive layer 220 are formed in the insulating layer 280 and the conductive layer 240 in regions overlapping with the conductive layer 220. A semiconductor layer 230 is formed on the side surfaces and bottom of the openings. That is, the semiconductor layer 230 is formed so as to fit along the top surface of the conductive layer 220, the side surfaces of the insulating layer 280, and the side surfaces of the conductive layer 240. The semiconductor layer 230 is also formed so as to fit along part of the top surface of the conductive layer 240. The insulating layer 250 is provided inside the openings so as to be in contact with the semiconductor layer 230. A conductive layer 260 is formed on the top surface and side surfaces of the insulating layer 250 so as to fill the openings.

[0177] The semiconductor layer 230 preferably includes a metal oxide. For example, a metal oxide that functions as an oxide semiconductor can be used as the semiconductor layer 230. The semiconductor layer 230 includes a channel formation region. The semiconductor layer 230 further includes a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The semiconductor layer 230 may have a stacked structure of two or more metal oxide layers.

[0178] A part of the conductive layer 220 functions as one of the source electrode and the drain electrode of the transistor Tr21. A part of the conductive layer 240 functions as the other of the source electrode and the drain electrode of the transistor Tr21. A part or the whole of the conductive layer 260 functions as the gate electrode of the transistor Tr21.

[0179] As described above, by forming the insulating layer, the conductive layer, and the semiconductor layer, a vertical channel transistor can be formed in which the channel length direction has a component in the height direction (vertical direction). Furthermore, the channel length of the transistor Tr21 depends on the film thickness of the insulating layer 280. The thinner the insulating layer 280, the shorter the channel length, and therefore the larger the on-current of the transistor Tr21 can be. On the other hand, the thicker the insulating layer 280, the longer the channel length, and therefore the smaller the off-current of the transistor Tr21 can be.

[0180] Furthermore, the wirings connecting the vertical channel transistors are not formed in the same process but in different processes. As a result, the wirings connecting the vertical channel transistors have overlapping regions in a plan view. Because the wirings connecting the vertical channel transistors are provided at different heights, parasitic capacitances generated in the wirings can be reduced. This allows the driving frequency of the transistor Tr21 to be increased, and the driving speed of the semiconductor device of one embodiment of the present invention can be increased.

[0181] An insulating layer 286 and an insulating layer 287 are provided in this order over the transistor Tr21 and the transistor Tr22. A conductive layer 246a is provided in a portion overlapping with the conductive layer 260 of the transistor Tr22 so as to fill the openings of the insulating layer 286 and the insulating layer 287. A conductive layer 246c is provided in a portion overlapping with the conductive layer 260 of the transistor Tr21 so as to fill the openings of the insulating layer 286 and the insulating layer 287.

[0182] A conductive layer 248a and a conductive layer 248b are provided over the insulating layer 287. The conductive layer 248a partially overlaps with the conductive layer 246a, and the conductive layer 248b partially overlaps with the conductive layer 246c.

[0183] The conductive layer 260 of the transistor Tr21 and the conductive layer 248b are connected via the conductive layer 246c, and the conductive layer 260 of the transistor Tr22 and the conductive layer 248a are connected via the conductive layer 246a.

[0184] An insulating layer 288 is provided over the insulating layer 287, the conductive layer 248a, and the conductive layer 248b.

[0185] The capacitor CA is provided to have a portion overlapping with the conductive layer 248a. The capacitor CA includes a conductive layer 110, a conductive layer 120, and an insulating layer .

[0186] The conductive layer 110 is provided on the conductive layer 248a so that a portion of the conductive layer 110 is embedded in the insulating layer 288. The conductive layer 110 has a convex portion protruding from the insulating layer 288, and the insulating layer 130 and the conductive layer 120 are provided in this order to cover the convex portion. The conductive layer 110 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 120 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric.

[0187] In a portion overlapping with the conductive layer 220 of the transistor Tr21, a conductive layer 246b is provided so as to fill openings in the insulating layer 280, the insulating layer 250, the insulating layer 286, and the insulating layer 287. The conductive layer 220 of the transistor Tr21 is connected to the conductive layer 110 via the conductive layer 246b and the conductive layer 248a.

[0188] An inorganic insulating film can be used as an insulating layer included in a semiconductor device according to one embodiment of the present invention. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film may be used for an insulating layer included in a semiconductor device.

[0189] By using insulating layers having a function of suppressing diffusion of impurities as the insulating layer 351 and the insulating layer 287, diffusion of impurities from the lower layer of the insulating layer 351 and the upper layer of the insulating layer 287 into the semiconductor layer 230 can be suppressed.

[0190] The insulating layer 351 and the insulating layer 287 may be an insulating layer having a function of suppressing diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). For example, an insulating layer having lower hydrogen permeability than the insulating layer 286 and the insulating layer 350 may be used. The insulating layer 351 and the insulating layer 287 may be an insulating layer having a function of suppressing diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, an insulating layer having lower oxygen permeability than the insulating layer 286 and the insulating layer 350 may be used.

[0191] Alternatively, the insulating layers 280, 286, and the like can have a stacked structure, and an insulating layer having a function of suppressing diffusion of impurities such as hydrogen and oxygen can be used as one of the stacked layers.

[0192] Examples of materials for the insulating layer having the function of suppressing hydrogen diffusion include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0193] Examples of materials for the insulating layer having the function of suppressing oxygen diffusion include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, silicon nitride oxide, etc. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0194] The conductive layer 110 has a pillar-shaped protrusion, and is therefore sometimes called a pillar-type capacitance element.

[0195] The configuration of the capacitance element CA is not limited to the configuration shown in Fig. 12. For example, various configurations such as a parallel plate type, a trench type, or a cylinder type can be used.

[0196] The structure of the layer 801 can be applied to, for example, the layer 910 described above, and the structure of the layer 802 can be applied to, for example, the layer 920 described above.

[0197] The conductive layer provided between the layer 801 and the layer 802 can be applied to, for example, the wiring 39 described above. For example, the wiring 39 described above can be formed using at least a part of the conductive layer 330c, the conductive layer 332c, the conductive layer 334c, and the conductive layer 336b included in the portion 39A surrounded by the dashed dotted line. Furthermore, the wiring 39 described above can be formed using at least a part of the conductive layer 330b, the conductive layer 332b, the conductive layer 334b, and the conductive layer 336a included in the portion 39B surrounded by the dashed dotted line.

[0198] Note that the transistors illustrated in FIG. 12 are merely examples, and the structure is not limited thereto. Any appropriate transistor can be used depending on the circuit configuration or driving method.

[0199] It is preferable to use a material with a high relative dielectric constant for the insulating layer 250 functioning as a gate insulating layer and the insulating layer 130 functioning as a dielectric layer of the capacitor CA. Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0200] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0201] Ferroelectric materials may also be used for the insulating layer 250, which functions as a gate insulating layer, and the insulating layer 130, which functions as a dielectric layer of the capacitor element CA. Examples of ferroelectric materials include oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. It is also preferable to use materials in which a Group 3 (Group IIIa) element is added to these oxides. For example, it is preferable to include one or more elements selected from scandium, yttrium, and lanthanides. Yttrium, lanthanum, and scandium are particularly preferred because they are relatively easy to handle and have high compatibility with semiconductor manufacturing processes. Adding such elements not only enables stable expression of ferroelectricity, but also suppresses characteristic degradation during repeated rewriting, improving reliability. Furthermore, the withstand voltage of the insulating layer can be improved.

[0202] Alternatively, piezoelectric ceramics having a perovskite structure, such as barium titanate, lead titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), and bismuth ferrite (BFO), may be used.

[0203] Alternatively, organic ferroelectrics such as polyvinylidene fluoride (PVDF) or copolymers of vinylidene fluoride (VDF) and trifluoroethylene (TrFE) may be used.

[0204] The ferroelectric material may be, for example, a mixture or compound of multiple materials selected from the above-listed materials, or a laminate structure of multiple materials selected from the above-listed materials.

[0205] In addition, an oxide that releases oxygen by heating is preferably used as an insulating layer in contact with the semiconductor layer 230. This allows oxygen to be supplied to the semiconductor layer 230, and when a metal oxide is used for the semiconductor layer 230, oxygen vacancies in the metal oxide can be reduced. For example, silicon oxide, silicon oxynitride, or the like can be used.

[0206] Alternatively, the insulating layer in contact with the semiconductor layer 230 may be formed by stacking an oxide that releases oxygen when heated and an insulating layer that suppresses diffusion of impurities.

[0207] The conductive layers in contact with the semiconductor layer 230, for example, the conductive layers 220 and 240, each preferably have a low contact resistance with the semiconductor layer 230. For example, a conductive oxide or a conductive nitride can be used as the conductive layer having a low contact resistance.

[0208] For example, a stacked structure of a conductive layer with low contact resistance and a conductive layer with lower resistance than the conductive layer can be used as the conductive layer 220 and the conductive layer 240. For example, a structure can be used in which a metal and a metal nitride are used for the lower layer and a conductive oxide is used for the upper layer.

[0209] Examples of conductive oxides that can be used for the conductive layer of one embodiment of the present invention include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In—Sn oxide), indium tin oxide containing titanium oxide, indium tin oxide containing silicon (In—Si—Sn oxide), indium zinc oxide, and indium zinc oxide containing tungsten oxide.

[0210] Examples of metal elements that can be used for the conductive layer of one embodiment of the present invention include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. Alloys containing any of the above metal elements can also be used for the conductive layer of one embodiment of the present invention. Nitrides of the above metals or alloys, or oxides of the above metals or alloys can also be used.

[0211] <Modifications of Transistor> As a structural example of a transistor that can be used as the transistors Tr21 and Tr22 described above, a transistor 200D is shown in FIGS. 14A to 14C.

[0212] Fig. 14A is a top view of a transistor 200D that can be used in a semiconductor device of one embodiment of the present invention. Fig. 14B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in Fig. 14A. Fig. 14C is a cross-sectional view taken along the line A3-A4 indicated by a dashed dotted line in Fig. 14A. Note that Fig. 14B is a cross-sectional view of the transistor 200D in the channel length direction, and Fig. 14C is a cross-sectional view of the transistor 200D in the channel width direction.

[0213] 14A to 14C , the transistor 200D includes a semiconductor layer 520 disposed over a substrate 501, conductive layers 542a and 542b spaced apart from each other on the semiconductor layer 520, an insulating layer 580 disposed over the conductive layers 542a and 542b and having an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, and an insulating layer 550 disposed among the semiconductor layer 520, the conductive layers 542a and 542b, the insulating layer 580, and the conductive layer 560. Note that hereinafter, the conductive layers 542a and 542b may be collectively referred to as the conductive layer 542.

[0214] 14A to 14C , an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520, the conductive layer 542a, the conductive layer 542b, and the insulating layer 580. The insulating layer 554 is in contact with the top surface and side surfaces of the conductive layer 542a, the top surface and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520, and the side surfaces of the insulating layer 524.

[0215] Here, the conductive layer 560 functions as the gate electrode of the transistor 200D, and the conductive layers 542a and 542b function as a source electrode and a drain electrode, respectively. The conductive layer 560 is formed so as to be embedded in the opening of the insulating layer 580 and in the region sandwiched between the conductive layers 542a and 542b. Here, the conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening of the insulating layer 580. That is, in the transistor 200D, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 200D. This reduces the area occupied by the semiconductor device. Furthermore, the integration density of the semiconductor device can be increased.

[0216] 14A to 14C , the conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided to be embedded in the conductive layer 560a. Although the conductive layer 560 in the transistor 200D has a two-layer stacked structure, one embodiment of the present invention is not limited to this. For example, the conductive layer 560 may have a single-layer structure or a stacked structure of three or more layers.

[0217] The transistor 200D includes an insulating layer 502 disposed on a substrate 501, an insulating layer 514 disposed on the insulating layer 502, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. Furthermore, a semiconductor layer 520 is disposed on the insulating layer 524.

[0218] Further, insulating layers 574 and 581 functioning as interlayer films are provided over the transistor 200D. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, and the insulating layer 580.

[0219] For the insulating layer 550, it is preferable to use, for example, a material suitable for a gate insulating layer.

[0220] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layers 514, 522, 554, and 574 may be insulating layers having a function of suppressing hydrogen diffusion. For example, the insulating layers 514, 522, 554, and 574 may be insulating layers having a lower hydrogen permeability than the insulating layers 524, 550, and 580. The insulating layers 514, 522, and 554 may be insulating layers having a function of suppressing oxygen diffusion. For example, the insulating layers 514, 522, and 554 may be insulating layers having a lower oxygen permeability than the insulating layers 524, 550, and 580. When the conductive layer 505 functions as a gate electrode, the insulating layer 522 is preferably formed using a material suitable for a gate insulating layer.

[0221] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are separated from layers below the insulating layer 522 and layers above the insulating layer 574 by the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and excess oxygen contained in layers above the insulating layer 574 and below the insulating layer 522 can be prevented from mixing into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0222] 14B shows an example in which two conductive layers 545 are provided, each of which is connected to the transistor 200D and functions as a plug. Note that an example in which an insulating layer 541 is provided in contact with a side surface of the conductive layer 545 that functions as a plug is shown. That is, the insulating layer 541 is provided in contact with inner walls of openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581.

[0223] Here, the height of the top surface of the conductive layer 545 can be approximately the same as the height of the top surface of the insulating layer 581. Note that although the conductive layer 545 is a single layer in the transistor 200D, one embodiment of the present invention is not limited to this. For example, the conductive layer 545 may have a stacked structure of two or more layers.

[0224] Furthermore, the thickness of the semiconductor layer 520 in a region that does not overlap with the conductive layer 542 may be thinner than the thickness of the region that overlaps with the conductive layer 542. This is achieved by removing part of the top surface of the semiconductor layer 520 when forming the conductive layers 542a and 542b. When a conductive film that will become the conductive layer 542 is formed on the top surface of the semiconductor layer 520, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region located between the conductive layer 542a and the conductive layer 542b on the top surface of the semiconductor layer 520, it is possible to prevent a channel from being formed in the region.

[0225] The conductive layer 505 is disposed so as to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved. When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a backgate electrode.

[0226] The conductive layer 505 may be provided to be larger than the channel formation region in the semiconductor layer 520. In particular, as shown in Fig. 14C, the conductive layer 505 may extend to a region outside the end portion intersecting with the channel width direction of the semiconductor layer 520. In other words, the conductive layer 505 and the conductive layer 560 may overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0227] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0228] A conductive layer 542 (a conductive layer 542a and a conductive layer 542b) functioning as a source electrode and a drain electrode is provided over the semiconductor layer 520. When an oxide semiconductor is used for the semiconductor layer 520, the conductive layer 542 may be formed using a conductive material that is not easily oxidized or a conductive material that maintains its conductivity even when it absorbs oxygen.

[0229] A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 200D. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with the opening of the insulating layer 580. This allows the conductive layer 560 to be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0230] The insulating layer 550 functions as a gate insulating layer. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520.

[0231] Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, and the like can be suitably used as the gate insulating layer.

[0232] The insulating layers 524 and 550 preferably have a reduced concentration of impurities such as water or hydrogen.

[0233] Although the conductive layer 560 is shown as having a two-layer structure in FIGS. 14A to 14C, it may have a single-layer structure or a stacked structure of three or more layers.

[0234] The conductive layer 560a is formed of the above-mentioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ Alternatively, a conductive layer having a function of suppressing the diffusion of impurities such as copper atoms may be used, or a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) may be used.

[0235] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 550. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0236] The conductive layer 560b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 560 also functions as a wiring, a conductive layer with high conductivity may be used. For example, a conductive material containing tungsten, copper, or aluminum as a main component may be used. Furthermore, the conductive layer 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0237] 14B and 14C , in a region of the semiconductor layer 520 that does not overlap with the conductive layer 542, for example, in the channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is covered with the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 200D, to act on the side surface of the semiconductor layer 520. This increases the on-state current of the transistor 200D and improves its frequency characteristics.

[0238] Two conductive layers 545 are disposed in openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554. One of the two conductive layers 545 is provided over the conductive layer 542a and connected to the conductive layer 542a. The other of the two conductive layers 545 is provided over the conductive layer 542b and connected to the conductive layer 542b. The two conductive layers 545 are disposed opposite each other with the conductive layer 560 interposed therebetween. Note that the height of the top surface of the conductive layer 545 may be flush with the top surface of the insulating layer 581.

[0239] The conductive layer 545 may be made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0240] When the conductive layer 545 has a stacked-layer structure, a conductive layer having a function of suppressing diffusion of impurities such as water or hydrogen may be used as a conductive layer in contact with the conductive layer 542 and the insulating layer 541. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is used. By using such a conductive material, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layer 545. Furthermore, impurities such as water or hydrogen from above the insulating layer 581 can be prevented from entering the semiconductor layer 520 through the conductive layer 545.

[0241] The insulating layer 541 may be, for example, an insulating layer that can be used for the insulating layer 554. The insulating layer 541 is provided in contact with the insulating layer 554, and therefore can prevent impurities such as water or hydrogen from the insulating layer 580 or the like from being mixed into the semiconductor layer 520 through the conductive layer 545. Furthermore, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layer 545.

[0242] <Metal Oxide> A metal oxide suitable for an oxide semiconductor layer included in an OS transistor will be described.

[0243] The crystallinity of the metal oxide is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0244] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. ＯH) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to be normally on. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration in the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

[0245] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0246] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for an oxide semiconductor layer, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0247] For example, indium oxide can be used as a metal oxide for the semiconductor layer of an OS transistor.

[0248] Examples of the metal oxide that can be used for the semiconductor layer of an OS transistor include oxides containing one or more elements selected from In, Sn, Zn, Ga, Al, and Ti. In these oxides, the content of each of the elements selected from In, Sn, Zn, Ga, Al, and Ti is preferably 1 atomic % or more, for example.

[0249] Examples of the metal oxide include, in addition to the above-mentioned indium oxide, zinc oxide, tin oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as "GZO"), aluminum zinc oxide (Al-Zn oxide, also referred to as "AZO"), indium Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0250] Specifically, the composition of the In-Zn oxide can be In:Zn=1:1 (atomic ratio) or a composition close thereto, In:Zn=2:1 (atomic ratio) or a composition close thereto, or In:Zn=4:1 (atomic ratio) or a composition close thereto, where the term "nearby composition" includes a range of ±30% of the desired atomic ratio.

[0251] Specifically, the composition of the In-M-Zn oxide may be a metal oxide having an In:M:Zn=1:1:1 [atomic ratio] or a composition thereabout, an In:M:Zn=1:1:1.2 [atomic ratio] or a composition thereabout, an In:M:Zn=1:1:0.5 [atomic ratio] or a composition thereabout, an In:M:Zn=1:1:2 [atomic ratio] or a composition thereabout, an In:M:Zn=4:2:3 [atomic ratio] or a composition thereabout, an In:M:Zn=1:3:2 [atomic ratio] or a composition thereabout, or an In:M:Zn=1:3:4 [atomic ratio] or a composition thereabout. Alternatively, examples of a composition containing a trace amount of element M include a composition in which In:M:Zn=4:0.1:1 (atomic ratio) or a composition in the vicinity thereof, a composition in which In:M:Zn=2:0.1:1 (atomic ratio) or a composition in the vicinity thereof, or a composition in which In:M:Zn=1:0.1:1 (atomic ratio) or a composition in the vicinity thereof. Examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

[0252] Examples of the crystalline structure of metal oxides that function as semiconductors include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0253] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0254] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0255] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0256] The oxide semiconductor layer of one embodiment of the present invention includes, for example, a crystalline metal oxide. Examples of the structure of the crystalline metal oxide include a CAAC structure, a polycrystalline (polycrystalline) structure, and an nc structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0257] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0258] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0259] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned metal oxides are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0260] Hereinafter, an indium oxide film that can be used as the oxide semiconductor layer of one embodiment of the present invention will be described.

[0261] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0262] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 15B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 15A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 15A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 15A.

[0263] 15A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility can be reduced to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0264] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0265] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0266] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0267] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 15A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0268] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0269] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0270] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0271] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0272] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0273] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0274] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0275] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0276] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0277] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 15C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0278] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0279] Furthermore, as shown in FIG. 15C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２) or reacts with oxygen contained in the membrane and is released as water molecules.

[0280] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0281] Table 3 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 3, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 3, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0282]

[0283] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0284] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0285] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0286] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0287] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0288] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0289] In this embodiment, an electronic component that can use the semiconductor device described in the above embodiment will be described. An electronic component that uses the semiconductor device of one embodiment of the present invention is effective in achieving high performance, such as low power consumption.

[0290] [Electronic Component] Fig. 16A shows a perspective view of electronic component 1700. Electronic component 1700 shown in Fig. 16A has substrate 1701, semiconductor device 1710 on substrate 1701, and mold 1711. In particular, semiconductor device 1710 is sealed by mold 1711. Note that Fig. 16A omits some parts of electronic component 1700 in order to show the interior of electronic component 1700.

[0291] The substrate 1701 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0292] Electronic component 1700 is provided with, for example, lead frame 1712. A portion of lead frame 1712 located on substrate 1701 is covered with mold 1711, and another portion of lead frame 1712 is exposed to the outside of mold 1711. In particular, lead frame 1712 exposed to the outside of mold 1711 functions as, for example, a terminal for mounting electronic component 1700 on a printed circuit board.

[0293] Inside mold 1711, electrode pads 1713 are provided on lead frame 1712, and electrode pads 1713 are connected to semiconductor device 1710 via wires 1714. Electronic component 1700 is mounted on a printed circuit board, for example, by contacting lead frame 1712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and connecting them on the printed circuit board.

[0294] Next, a semiconductor device 1710 will be described. The semiconductor device described in the above embodiments can be used as the semiconductor device 1710. The semiconductor device 1710 includes, for example, a memory portion having a memory circuit, an arithmetic processing portion that performs arithmetic using the memory circuit, and peripheral circuits for driving the memory portion and the arithmetic processing portion. In a semiconductor device according to one embodiment of the present invention, a layer including the arithmetic processing portion and a layer including at least a part of the memory portion can be monolithically stacked. Furthermore, a layer including peripheral circuits for driving each component and a layer including at least a part of the memory portion can be monolithically stacked.

[0295] In a monolithic stacked structure, it is possible to connect each layer without using through-electrode technology (for example, TSV (Through Silicon Via)) or bonding technology such as Cu-Cu direct bonding. Therefore, for example, a configuration can be adopted in which a circuit for performing arithmetic processing and a memory circuit are formed on the same chip. This makes it possible to increase the speed of the operation of the interface between the circuit for performing arithmetic processing and the memory circuit. Note that the semiconductor device 1710 can also be configured so that a CPU is formed on the same chip in addition to peripheral circuits for driving the memory unit and arithmetic processing unit. This makes it possible to increase the speed of the operation of the interface between the CPU and the peripheral circuits for driving the memory unit and arithmetic processing unit.

[0296] Furthermore, by forming the CPU and peripheral circuits for driving the memory unit and the arithmetic processing unit on the same chip, it is possible to reduce the size of the connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).

[0297] The semiconductor device 1710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0298] Next, Fig. 16B shows a modified example of electronic component 1700. Electronic component 1700A shown in Fig. 16B differs from electronic component 1700 in that it does not use lead frame 1712, but has electrodes 1733 provided on the bottom of substrate 1701. Electrodes 1733 function as connection terminals for mounting electronic component 1700A on a printed circuit board.

[0299] 16B shows an example in which electrodes 1733 are formed using solder balls. By providing solder balls in a matrix on the bottom of substrate 1701, BGA (Ball Grid Array) mounting can be achieved. For this purpose, substrate 1701 is provided with through-hole vias, and conductive layers 1732 that function as wiring are provided in these vias. Electrode pads 1713 are provided above conductive layer 1732 on substrate 1701 so as to be in contact with them, and electrodes 1733 are provided below substrate 1701 so as to be in contact with them below conductive layer 1732.

[0300] Furthermore, the electrodes 1733 may be formed of conductive pins instead of solder balls. By providing conductive pins in a matrix on the bottom of the substrate 1701, PGA (Pin Grid Array) mounting can be achieved.

[0301] Furthermore, electronic component 1700A can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0302] The electronic component of one embodiment of the present invention may be in the form of a system in package (SiP) or a multi-chip module (MCM). For example, an electronic component 1700C illustrated in FIG. 16C includes an interposer 1731 over a package substrate 1734 (printed circuit board), and a semiconductor device 1735 and a plurality of semiconductor devices 1710 over the interposer 1731.

[0303] 16C , for example, the semiconductor device 1710 can be used as a high bandwidth memory (HBM). The semiconductor device 1735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, an accelerator, or a field programmable gate array (FPGA). The semiconductor device of one embodiment of the present invention can be applied to the semiconductor device 1710 and the semiconductor device 1735.

[0304] For example, an accelerator included in the semiconductor device of one embodiment of the present invention can be used as the semiconductor device 1710, and a CPU included in the semiconductor device of one embodiment of the present invention can be used as the semiconductor device 1735. By using the accelerator included in the semiconductor device of one embodiment of the present invention as the semiconductor device 1710, the semiconductor device 1710 can have a function as a memory that stores data and a function as an arithmetic circuit that performs calculations using the stored data. When the semiconductor device 1710 functions as an arithmetic circuit in addition to the semiconductor device 1735, the calculation efficiency of the electronic component 1700 can be improved. By improving the calculation efficiency, power consumption of the electronic component 1700 can be reduced, and heat generation by the electronic component 1700 can be suppressed.

[0305] The package substrate 1734 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, similar to the substrate 1701. The interposer 1731 may be, for example, a silicon interposer or a resin interposer.

[0306] The interposer 1731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 1731 also functions to connect the integrated circuits provided on the interposer 1731 to electrodes provided on the package substrate 1734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 1731, and the integrated circuits and the package substrate 1734 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0307] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0308] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0309] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 1700C, the width of the terminal pitch becomes an issue, and it may become difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. Furthermore, a structure that combines a memory cell array stacked using TSVs and a monolithic stacked memory cell array is sometimes called a hybrid structure.

[0310] Furthermore, if the temperature of the electronic component 1700C increases due to heat generated by electric current or the like, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 1700C may be degraded. Therefore, it is preferable to provide a heat sink (heat sink) on the electronic component 1700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 1731. For example, in the electronic component 1700C described in this embodiment, it is preferable to align the height of the semiconductor device 1710 and the semiconductor device 1735.

[0311] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0312] Fourth Embodiment In this embodiment, an electronic device using the electronic components described in the above embodiments and an information processing system using the electronic device will be described.

[0313] Fig. 17 is a diagram showing an example of the configuration of an information processing system 8000. The information processing system 8000 shown in Fig. 17 includes examples of electronic devices and a server located within a network.

[0314] Figure 17 shows, as examples of the electronic devices, a mobile information terminal 8200, a wearable information terminal 8300, a notebook personal computer 8400, an automobile 8500, an industrial robot 8600, and a camera 8700.

[0315] FIG. 17 also shows a network 8100 and a mainframe computer 8110 arranged within the network 8100 .

[0316] As an example, the mainframe computer 8110 may refer to multiple computers installed in a server room or the like. For example, the mainframe computer 8110 may be a rack-mounted computer in which multiple computers are stored in a rack. The mainframe computer 8110 may also be called a supercomputer. In the information processing system 8000, the mainframe computer 8110 may also be called a server or a cloud server.

[0317] Each of the multiple computers in the mainframe 8110 has a motherboard, and the motherboard is provided with multiple slots, multiple connection terminals, etc. As an example, one or multiple PC cards can be inserted into the slots.

[0318] The PC card is an example of a processing board equipped with a processing device such as a CPU, an accelerator, etc. For example, the electronic component 1700 can be used as the processing device.

[0319] The mainframe computer 8110 can also function as a parallel computer. By using the mainframe computer 8110 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0320] When wired communication is performed as the network 8100, specifications standardized by IEEE such as Ethernet (registered trademark) can be used. In addition, types of communication include electrical communication using electric wires such as twisted pair cables, and optical communication using optical fibers.

[0321] On the other hand, when wireless communication is performed as network 8100, communication standards such as the fourth generation mobile communication system (4G), fifth generation mobile communication system (5G), and sixth generation mobile communication system (6G), or specifications standardized by IEEE such as Wi-Fi (registered trademark) and Bluetooth (registered trademark), can be used as communication protocols or communication technologies.

[0322] The network 8100 may be, for example, a PAN (Personal Area Network), a LAN (Local Area Network), a CAN (Campus Area Network), a MAN (Metropolitan Area Network), a WAN (Wide Area Network), or a GAN (Global Area Network).

[0323] For example, by using a GAN for the network 8100, it is possible to use the Internet, which is the foundation of the World Wide Web (WWW).

[0324] If the information processing system 8000 is constructed on a LAN as the network 8100, the possibility of confidential information leaking can be reduced, for example, compared to when the Internet is used.

[0325] Furthermore, a company or individual managing the supercomputer 8110 can provide services using the information processing system 8000 to users of each electronic device, for example, using the network 8100. One example of such services is a form of use known as cloud computing. Cloud computing allows users of the above-mentioned electronic devices to utilize the functions of the supercomputer 8110, such as the ability to store large amounts of data, the ability to perform large-scale calculations, and other applications.

[0326] In particular, the semiconductor device according to one embodiment of the present invention can perform large-scale calculations such as an artificial neural network model by being provided in the above-described electronic devices and the mainframe computer 8110. This enables the information processing system 8000 to provide services to users in a usage form called cloud AI or edge AI.

[0327] Cloud AI is generally a form of service usage in which the supercomputer 8110 performs learning and inference of an artificial neural network. The supercomputer 8110 has previously learned collected data, and each electronic device sends input data to the artificial neural network to the supercomputer 8110, causing the supercomputer 8110 to perform inference on the input data. The supercomputer 8110 also sends the results of the inference to each electronic device, allowing each electronic device to use the results of the inference. Because learning and inference are performed by the supercomputer 8110, cloud AI is suitable for performing calculations on large amounts of data and processing including complex calculations.

[0328] On the other hand, edge AI generally refers to a service usage form in which each electronic device performs learning and inference of an artificial neural network. In this case, the mainframe 8110 provides each electronic device with an artificial neural network model, weight coefficients (sometimes referred to as weight data, coupling coefficients, etc.). The results of learning and inference performed on each electronic device are also transmitted to the mainframe 8110. A usage form in which the mainframe 8110 performs learning of an artificial neural network and each electronic device performs inference using the trained neural network may also be called edge AI.

[0329] Edge AI requires less communication time than cloud AI because each electronic device performs inference using an artificial neural network. In other words, edge AI is suitable for analyzing input data in real time. Furthermore, because the amount of data transmitted between each electronic device and the mainframe 8110 is reduced, data communication costs can be reduced, and the power consumption required for data communication can also be reduced. Furthermore, because the amount of data transmitted is reduced, security risks such as information leaks can be reduced. Therefore, edge AI is suitable for building small-scale systems, for example.

[0330] Note that the semiconductor device of one embodiment of the present invention can be suitably used for an edge AI because it consumes extremely little power during standby.

[0331] Below, we will explain an example of a specific edge AI system.

[0332] 17 is an electronic device in which a display device and a touch panel are integrated. The portable information terminal 8200 can include an electronic component 8201 as the electronic component 1700 described above, which allows the portable information terminal 8200 to perform large-scale calculations such as an artificial neural network. The portable information terminal 8200 can also include a camera.

[0333] By providing the mobile information terminal 8200 with a camera, image recognition by edge AI can be performed on images captured by the mobile information terminal 8200. Examples of objects to be recognized include humans, animals, plants, characters, pictograms, etc. In particular, image recognition can be used for biometric authentication by performing image recognition on images of human faces, fingerprints, palm prints, irises, veins, etc.

[0334] [Wearable Information Terminal] The wearable information terminal 8300 shown in Fig. 17 is an electronic device that can be worn on a human head. The wearable information terminal 8300 in Fig. 17 has a structure that covers the eyes, a display device, temples that are hooked onto the ears, and earphones, but other examples include an HMD (head-mounted display) and a glasses-type XR device. The wearable information terminal 8300 can also be equipped with a camera, similar to the portable information terminal 8200.

[0335] In addition, the wearable information terminal 8300 can be equipped with an electronic component 8301 as the electronic component 1700 described above, thereby enabling the wearable information terminal 8300 to perform large-scale calculations such as artificial neural networks.

[0336] By providing a camera in the wearable information terminal 8300, images captured by the wearable information terminal 8300 can be displayed on a display device in real time. Furthermore, by performing image recognition using edge AI, information about an object included in an image displayed on the display device can be additionally displayed on the display device. Furthermore, by performing image recognition of moving objects such as pedestrians, bicycles, cars, and trains displayed on the display device, risk prediction can be performed to determine whether or not there is a risk of contact.

[0337] 17 is an electronic device that is primarily used on a desk. The notebook personal computer 8400 can include an electronic component 8401 as the electronic component 1700 described above, which enables the notebook personal computer 8400 to perform large-scale calculations such as artificial neural networks.

[0338] For example, the notebook personal computer 8400 can use edge AI for its calculation processing when using an application, for example, for upconversion to increase the screen resolution of images (including still images and videos) displayed on a display device in real time, translation to convert text into another language, editing of text or images, etc.

[0339] 17 is an example of a moving body. The automobile 8500 can be equipped with an electronic component 8501 as the electronic component 1700 described above, and thus the automobile 8500 can be used as an electronic device for edge AI.

[0340] Edge AI in the automobile 8500 can be used for applications such as autonomous driving, hazard prediction during autonomous driving, and air conditioning management inside the vehicle.

[0341] In this specification, an automobile has been described as an example of a mobile object, but other mobile objects include, for example, trains, monorails, ships, and aircraft (for example, helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). The above-mentioned mobile objects can also be used as electronic devices for edge AI.

[0342] [Industrial Robot] The industrial robot 8600 shown in FIG. 17 can be deployed in, for example, a production factory. The industrial robot 8600 preferably has multiple drive axes to precisely control the drive range. The industrial robot 8600 may have one or more functions, such as gripping, cutting, welding, coating, and pasting an object. In order to detect the object, the industrial robot 8600 is preferably equipped with a sensor such as an image detection module or a camera. The industrial robot 8600 is also preferably equipped with a sensor that detects minute currents to determine whether or not the object has been gripped.

[0343] The industrial robot 8600 can be equipped with the electronic component 8601 as the above-described electronic component 1700, thereby allowing the industrial robot 8600 to be used as an edge AI electronic device. The edge AI in the industrial robot 8600 can be used for applications such as image recognition of objects, classification by type, classification by size, and inspection to determine whether an item is good or bad.

[0344] 17 can be used as, for example, a surveillance camera, a security camera, a pet camera, etc. The housing of the camera 8700 is not limited to a ceiling-mounted type as shown in FIG. 17 , and there are various types such as a tabletop type and a wall-mounted type.

[0345] Note that the terms surveillance camera, security camera, and pet camera are common names and do not limit the intended use to the name. For example, a pet camera may be used as a surveillance camera or security camera, or vice versa. The camera 8700 may also be called a video camera.

[0346] The camera 8700 can also be provided with the electronic component 8701 as the electronic component 1700 described above, thereby enabling the camera 8700 to be used as an edge AI electronic device. The edge AI in the camera 8700 can be used, for example, for security purposes to detect moving objects displayed in images (still images and videos) captured by the camera 8700. The edge AI can also be used for disaster prevention purposes to detect river flooding, tsunamis, and the like.

[0347] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0348] In this embodiment, a space equipment and a data center (also referred to as a Data Center: DC) in which the semiconductor device described in the above embodiment can be used will be described. Note that the space equipment and the data center are effective in achieving high performance, such as low power consumption.

[0349] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment (for example, equipment having a function of processing and storing information).

[0350] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in environments where radiation may be incident. For example, the OS transistor can be suitably used in outer space. The semiconductor device of one embodiment of the present invention includes an OS transistor, which can achieve excellent retention characteristics in a memory circuit even in outer space. Furthermore, the accuracy of calculations in an arithmetic circuit can be improved.

[0351] Fig. 18 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 18, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but outer space described in this specification includes the thermosphere, mesosphere, and stratosphere.

[0352] 18 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0353] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0354] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0355] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received, for example, by a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0356] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 includes, for example, one or more selected from a CPU, an accelerator, and a memory circuit. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0357] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0358] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0359] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0360] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. Data centers are required to perform long-term data management, such as ensuring data immutability. Managing long-term data requires large-scale buildings, such as the installation of storage and servers for storing huge amounts of data, ensuring a stable power supply for data retention, and ensuring cooling equipment required for data retention. In addition, the data center preferably has a function for performing data calculations, and more preferably, the calculation speed is high.

[0361] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, power required for operation can be reduced and the operation speed can be increased.

[0362] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0363] Fig. 19 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 19 has a plurality of servers 7001sb as hosts 7001. It also has a plurality of storage devices 7003md as storage 7003. The host 7001 and storage 7003 are shown connected via a storage area network 7004 and a storage control circuit 7002.

[0364] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0365] The host 7001 preferably includes one or more of a CPU and an accelerator. The semiconductor device of one embodiment of the present invention can have a structure including a CPU and an accelerator. When the host 7001 includes the semiconductor device of one embodiment of the present invention, the arithmetic efficiency of the host 7001 can be improved. Furthermore, the power consumption of the host 7001 can be reduced.

[0366] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0367] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0368] In the semiconductor device of one embodiment of the present invention, the arithmetic processing unit can include a memory unit. When the storage 7003 includes the semiconductor device of one embodiment of the present invention, the storage 7003 can store data and perform calculations using the stored data. This allows the storage 7003 to handle part of the enormous amount of calculations performed in the storage system 7000. Since the host 7001 can process the results of calculations performed by the storage 7003, the calculation efficiency of the storage system 7000 can be improved. This allows the volume of the storage system 7000 to be reduced. Furthermore, the power consumption of the storage system 7000 can be reduced. Furthermore, heat generation by the storage system 7000 can be suppressed.

[0369] Furthermore, by using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing can be reduced, and power consumption can be reduced.Furthermore, by using a stacked memory cell array, miniaturization is possible.

[0370] Note that by applying the semiconductor device of one embodiment of the present invention to one or more of the electronic components described in the above embodiments, the electronic devices described in the above embodiments, the large-scale computers, space equipment, and data centers described in the above embodiments, it is expected that power consumption can be reduced. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of the above-described components, equipment, data centers, and the like, by using the semiconductor device of one embodiment of the present invention, carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0371] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0372] CA: capacitance element, GL: wiring, IN: calculation signal line, INb: calculation inversion signal line, RBL: read bit line, RWL: read word line, SN: node, Tr11: transistor, Tr12: transistor, Tr21: transistor, Tr22: transistor, W １１ : data, WBL: write bit line, Wk: data, W ＭＮ: data, WWL: write word line, 10: CPU, 20: accelerator, 21: arithmetic processing unit, 22: memory unit, 23: arithmetic circuit, 24: memory circuit, 24a: area, 24b: area, 30: bus, 31A: transistor, 32A: transistor, 32B: transistor, 33A: transistor, 34A: capacitance element, 35: storage unit, 36: exclusive OR unit, 39: wiring, 39A: part, 39a: wiring, 39B: part, 39b: wiring, 40: multiplication unit, 45: encoding circuit, 49: accumulator, 50: neuron, 51: layer, 52: layer, 53: layer, 54: layer, 61: controller, 62: row decoder, 63: word line driver, 64: column decoder, 65: write driver, 66: precharge circuit, 67: sense amplifier, 68: selector, 71: input buffer, 72: arithmetic control circuit, 100: semiconductor device, 110: conductive layer, 120: conductive layer, 130: insulating layer, 200D: transistor, 220: conductive layer, 230: semiconductor layer, 240: conductive layer, 246a: conductive layer, 246b: conductive layer, 246c: conductive layer, 248a: conductive layer, 248b: conductive layer, 250: insulating layer, 260: conductive layer, 280: insulating layer, 286 : insulating layer, 287: insulating layer, 288: insulating layer, 311: substrate, 313a: semiconductor region, 313b: semiconductor region, 315: insulating layer, 316: conductive layer, 320: insulating layer, 321: element isolation region, 326: insulating layer, 328a: conductive layer, 328b: conductive layer, 328c: conductive layer, 328d: conductive layer, 330a: conductive layer, 330b: conductive layer, 330c: conductive layer, 332a: conductive layer, 332b: conductive layer, 332c: conductive layer, 334a: conductive layer, 334b: conductive layer, 334c: conductive layer, 336a: conductive layer, 336b: conductive layer, 342: insulating layer, 344: insulating layer, 350: Insulating layer, 351: insulating layer, 501: substrate, 502: insulating layer, 505: conductive layer, 514: insulating layer, 516: insulating layer, 520: semiconductor layer, 522: insulating layer, 524: insulating layer, 541: insulating layer, 542: conductive layer, 542a: conductive layer, 542b: conductive layer, 545: conductive layer, 550: insulating layer, 554: insulating layer, 560: conductive layer, 560a: conductive layer, 560b: conductive layer, 574: insulating layer, 580: insulating layer, 581: insulating layer, 801: layer, 802: layer, 910: layer, 920: layer, 1700: electronic component, 1700A: electronic component, 1700C: electronic component, 1701: substrate,1710: semiconductor device, 1711: mold, 1712: lead frame, 1713: electrode pad, 1714: wire, 1731: interposer, 1732: conductive layer, 1733: electrode, 1734: package substrate, 1735: semiconductor device, 6800: artificial satellite, 6801: airframe, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 700 2: storage control circuit, 7003: storage, 7003md: storage device, 8000: information processing system, 8100: network, 8110: mainframe computer, 8200: portable information terminal, 8201: electronic component, 8300: wearable information terminal, 8301: electronic component, 8400: notebook personal computer, 8401: electronic component, 8500: automobile, 8501: electronic component, 8600: industrial robot, 8601: electronic component, 8700: camera, 8701: electronic component,

Claims

a first signal line, a second signal line, a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is connected to the gate of the second transistor and the gate of the third transistor; one of a source and a drain of the second transistor is connected to one of a source and a drain of the third transistor; the first signal line is connected to the other of the source and the drain of the second transistor; the second signal line is connected to the other of the source and the drain of the third transistor, the first signal line has a function of supplying an operational signal; the second signal line has a function of supplying an inverted signal of the calculation signal, the third transistor has a polarity different from that of the second transistor; The semiconductor device includes the first transistor having an oxide semiconductor in a channel formation region. 　 In claim 1, The semiconductor device, wherein the third transistor has silicon in a channel formation region. 　 In claim 1 or claim 2, The semiconductor device, wherein the third transistor is a p-channel transistor.

2. The circuit according to claim 1, further comprising an arithmetic circuit and a fourth transistor, one of a source and a drain of the fourth transistor is connected to one of a source and a drain of the second transistor; the arithmetic circuit is connected to the other of the source and the drain of the fourth transistor. 　 In claim 1, the other of the source and the drain of the first transistor is connected to the first signal line. 　 a plurality of memory circuits, a first signal line, a second signal line, and an arithmetic circuit; each of the plurality of memory circuits has a function of holding data in a first node; each of the plurality of memory circuits includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the third transistor has a polarity different from that of the second transistor; the first node is connected to one of the source and drain of the first transistor, the gate of the second transistor, and the gate of the third transistor; one of a source and a drain of the second transistor is connected to one of a source and a drain of the third transistor; one of the source and the drain of the fourth transistor is connected to the other of the source and the drain of the second transistor; the first signal line is connected to the other of the source and the drain of the second transistor of each of the plurality of memory circuits; the second signal line is connected to the other of the source and the drain of the third transistor of each of the plurality of memory circuits; one of a source and a drain of the fourth transistor is connected to one of a source and a drain of the second transistor; the first signal line has a function of supplying an operational signal; the second signal line has a function of supplying an inverted signal of the calculation signal, each of the plurality of memory circuits has a function of holding a first potential at the first node and a function of outputting a result of an operation using the operation signal, the inverted signal of the operation signal, and the first potential; The arithmetic circuit has a function of adding together the arithmetic results output from the plurality of memory circuits. 　 In claim 6, the first transistor has an oxide semiconductor in a channel formation region; The semiconductor device, wherein the third transistor has silicon in a channel formation region. 　 In claim 6 or claim 7, The semiconductor device, wherein the third transistor is a p-channel transistor. 　 In claim 6, the first transistor has an oxide semiconductor in a channel formation region; the third transistor has silicon in a channel formation region; the arithmetic circuit includes a fifth transistor having silicon in a channel formation region and a sixth transistor having silicon in a channel formation region; The sixth transistor has a polarity different from that of the fifth transistor. 　 In claim 9, the third transistor and the sixth transistor are p-channel transistors.

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