Solid-state imaging element, light detection device, and method for manufacturing solid-state imaging element

Abstract

The present invention reduces variation in current in a solid-state imaging element in which a transistor serving as a current source is provided in each pixel.　A current source transistor, a switch circuit, a capacitive element, and a sample-and-hold switch are provided in each of a plurality of pixels. The current source transistor has a source connected to a ground node, and supplies a predetermined drain-source current. One end of the capacitive element is connected to a gate of the current source transistor. The switch circuit opens and closes a path between an amplifying transistor and the current source transistor in accordance with a predetermined control signal. The sample-and-hold switch has a different polarity from the transistor in the switch circuit, and samples and holds a predetermined bias voltage in the capacitive element in accordance with a control signal.

Description

Solid-state imaging device, photodetector, and method for manufacturing solid-state imaging device

[0001] The present technology relates to a solid-state imaging device, and more particularly to a solid-state imaging device provided with a current source transistor, a photodetector, and a method for manufacturing the solid-state imaging device.

[0002] Conventionally, CIS (CMOS Image Sensor) has used a global shutter method in which all pixels are exposed simultaneously to reduce rolling shutter distortion. For example, a solid-state imaging device has been proposed in which a capacitive element is provided for each pixel and a voltage is sampled and held in the capacitive element (see, for example, Non-Patent Document 1). In this solid-state imaging device, an n-channel metal oxide semiconductor (nMOS) transistor with a grounded source and a bias voltage applied to its gate is provided for each pixel as a current source.

[0003] Geunsook Park, et al., A 2.2μm stacked back side illuminated voltage domain global shutter CMOS image sensor, IEDM 2019.

[0004] In the above-mentioned conventional technology, a capacitive element is provided for each pixel, and a global shutter system is realized by sampling and holding the voltage. However, in the above-mentioned solid-state imaging device, the gate-source voltage of the nMOS transistor of the current source can vary from pixel to pixel due to factors such as ground bounce when the pixel is driven. As a result, there is a problem in that the current flowing through the nMOS transistor of the current source varies from pixel to pixel.

[0005] The present technology was developed in view of such circumstances, and aims to suppress variations in current in a solid-state imaging device in which a current source transistor is provided for each pixel.

[0006] The present technology has been made to solve the above-mentioned problems. A first aspect of the present technology is a solid-state imaging device including a plurality of pixels, each of which includes a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current, a capacitance element having one end connected to the gate of the current source transistor, a switch circuit that opens and closes a path between an amplifier transistor and the current source transistor in accordance with a predetermined control signal, and a sample-and-hold transistor having a polarity opposite to that of the transistor in the switch circuit and that samples and holds a predetermined bias voltage in the capacitance element in accordance with the control signal. This reduces current variations. Furthermore, the same control signal can be sent to the transistor in the switch circuit and the sample-and-hold transistor to operate them exclusively. This reduces the number of signal lines for transmitting the control signal compared to when separate control signals are sent to the transistor in the switch circuit and the sample-and-hold transistor.

[0007] In addition, in the first aspect, a sample-and-hold circuit may be further provided that holds a signal level corresponding to the exposure amount and a predetermined reset level, thereby achieving a global shutter.

[0008] In this first aspect, the switch circuit may include at least one of a switch transistor that opens and closes a path between the source of the amplifier transistor and a previous-stage node connected to the sample-and-hold circuit, and a precharge transistor that opens and closes a path between the previous-stage node and the drain of the current source transistor, thereby providing an effect of cutting off current by controlling the transistor.

[0009] In this first aspect, the amplifier may further include a mirror source transistor through which a predetermined reference current flows, and the sample-and-hold transistor may open and close a path between the gate and drain of the mirror source transistor and the gate of the current source transistor, thereby providing an effect of supplying a current according to the reference current.

[0010] In this first aspect, the current source transistor, the capacitance element, the switch circuit, and the sample and hold transistor may be arranged on any one of a plurality of stacked semiconductor chips, thereby providing an effect of facilitating miniaturization of pixels.

[0011] In this first aspect, each of the plurality of pixels may detect the presence or absence of an address event, thereby suppressing variations in current among pixels that detect an address event.

[0012] In the first aspect, the capacitance element may be a MOS (Metal-Oxide-Semiconductor) capacitor, a MIM (Metal-Insulator-Metal) capacitor, or an inter-wiring capacitance, thereby providing an effect that the capacitance element is formed by a semiconductor process.

[0013] A second aspect of the present technology is a solid-state imaging device including a plurality of pixels, each of which is provided with a P-type current source transistor having a source connected to a power supply voltage and supplying a predetermined drain-source current, a capacitance element inserted between the gate of the current source transistor and the power supply voltage, and a sample-and-hold switch that samples and holds a predetermined bias voltage in the capacitance element during a period when the drain-source current is not supplied, thereby suppressing current variations.

[0014] According to a third aspect of the present technology, there is provided a solid-state imaging device including: a plurality of pixels, each of which is provided with a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current; a capacitance element having one end commonly connected to the gate of the current source transistor of each of the plurality of pixels; and a sample-and-hold switch that samples and holds a predetermined bias voltage in the capacitance element during a period in which the drain-source current is not supplied. This suppresses current variations and improves area efficiency.

[0015] According to a third aspect of the present technology, there is provided a photodetector device including a plurality of pixels, each of which includes a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current, a capacitance element having one end connected to a gate of the current source transistor, a switch circuit that opens and closes a path between an amplification transistor and the current source transistor in accordance with a predetermined control signal, and a sample-and-hold transistor having a polarity opposite to that of the transistor in the switch circuit and that samples and holds a predetermined bias voltage in the capacitance element in accordance with the control signal, and a signal processing circuit that processes pixel signals from each of the plurality of pixels, thereby achieving the effect of reducing power consumption by suppressing variations in current.

[0016] 1 is a block diagram showing an example configuration of an imaging device according to a first embodiment of the present technology. FIG. 2 is a block diagram showing an example configuration of a solid-state imaging element according to the first embodiment of the present technology. FIG. 3 is a circuit diagram showing an example configuration of a pixel according to the first embodiment of the present technology. FIG. 4 is a circuit diagram showing an example configuration of an accessory according to the first embodiment of the present technology. FIG. 5 is a block diagram showing an example configuration of a load MOS (Metal Oxide Semiconductor) circuit block and a column signal processing circuit according to the first embodiment of the present technology. FIG. 6 is a timing chart showing an example operation of a solid-state imaging element according to the first embodiment of the present technology. FIG. 7 is a graph showing an example of characteristics of a current source transistor according to the first embodiment of the present technology. FIG. 8 is a circuit diagram showing an example state of a solid-state imaging element in a comparative example. FIG. 9 is a diagram showing an example state of a solid-state imaging element during sample and hold according to the first embodiment of the present technology. FIG. 10 is a diagram showing an example state of a solid-state imaging element after sample and hold of a pixel according to the first embodiment of the present technology. FIG. 11 is a diagram showing an example layout of a sample and hold switch, a capacitive element, and a current source transistor according to the first embodiment of the present technology. FIG. 12 is a flowchart showing an example operation of a solid-state imaging element according to the first embodiment of the present technology. FIG. 1 is a circuit diagram showing an example configuration of a pixel in which transistors are reduced in a first modified example of the first embodiment of the present technology. FIG. 2 is a diagram showing an example of a stacked structure of a solid-state imaging element in a second embodiment of the present technology. FIG. 3 is a circuit diagram showing an example configuration of a pixel in the second embodiment of the present technology. FIG. 4 is a block diagram showing an example configuration of a solid-state imaging element in a third embodiment of the present technology. FIG. 5 is a circuit diagram showing an example configuration of a pixel in the third embodiment of the present technology. FIG. 6 is a circuit diagram showing an example configuration of a pixel in a fourth embodiment of the present technology. FIG. 7 is a block diagram showing an example configuration of a pixel array unit in a fifth embodiment of the present technology. FIG. 8 is a circuit diagram showing an example configuration of a pixel in a sixth embodiment of the present technology. FIG. 9 is a block diagram showing a schematic example configuration of a vehicle control system. FIG. 10 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0017] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example of sampling and holding in a capacitive element while current is stopped) 2. Second embodiment (an example of sampling and holding in a capacitive element while current is stopped in a stacked structure) 3. Third embodiment (an example of sampling and holding in a capacitive element while current is stopped, and detecting an address event) 4. Fourth embodiment (an example of using a P-type current source transistor and sampling and holding in a capacitive element while current is stopped) 5. Fifth embodiment (an example of sharing a sample-and-hold switch that samples and holds in a capacitive element while current is stopped among multiple pixels) 6. Sixth embodiment (an example of a sample-and-hold transistor that samples and holds in a capacitive element with a different polarity from that of a transistor in a switch circuit) 7. Application example to a moving body

[0018] 1. First Embodiment [Configuration Example of Imaging Device] Fig. 1 is a block diagram showing a configuration example of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device that captures image data, and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130. The imaging device 100 is assumed to be a digital camera or an electronic device with an imaging function (such as a smartphone or a personal computer). Note that the imaging device 100 is an example of a light detection device as defined in the claims.

[0019] The solid-state imaging element 200 captures image data under the control of the imaging control unit 130. The solid-state imaging element 200 supplies the image data to the recording unit 120 via a signal line 209.

[0020] The imaging lens 110 focuses light and guides it to the solid-state imaging element 200. The imaging control unit 130 controls the solid-state imaging element 200 to capture image data. The imaging control unit 130 supplies an imaging control signal including, for example, a vertical synchronization signal VSYNC to the solid-state imaging element 200 via a signal line 139. The recording unit 120 records the image data.

[0021] Here, the vertical synchronization signal VSYNC is a signal that indicates the timing of imaging, and a periodic signal with a constant frequency (such as 60 Hz) is used as the vertical synchronization signal VSYNC.

[0022] It should be noted that although the imaging device 100 records image data, the image data may be transmitted to an external device. In this case, an external interface for transmitting the image data is further provided. Alternatively, the imaging device 100 may further display the image data. In this case, a display unit is further provided.

[0023] [Configuration Example of Solid-State Imaging Device] Fig. 2 is a block diagram showing a configuration example of a solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 is a CIS, and includes a vertical scanning circuit 211, an accessory 220, and a pixel array unit 230. The solid-state imaging device 200 further includes a timing control circuit 212, a digital-to-analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. A plurality of pixels 300 are arranged in a two-dimensional lattice pattern in the pixel array unit 230. Each circuit in the solid-state imaging device 200 is provided on, for example, a single semiconductor chip.

[0024] Hereinafter, a group of pixels 300 arranged in the horizontal direction will be referred to as a "row," and a group of pixels 300 arranged in a direction perpendicular to the rows will be referred to as a "column."

[0025] The timing control circuit 212 controls the operation timing of the vertical scanning circuit 211 , the DAC 213 , and the column signal processing circuit 260 in synchronization with a vertical synchronization signal VSYNC from the imaging control unit 130 .

[0026] The DAC 213 generates a sawtooth ramp signal by DA (Digital to Analog) conversion and supplies the generated ramp signal to the column signal processing circuit 260.

[0027] The vertical scanning circuit 211 sequentially selects and drives rows to output analog pixel signals. The pixels 300 photoelectrically convert incident light to generate analog pixel signals. The pixels 300 supply pixel signals to the column signal processing circuit 260 via the load MOS circuit block 250.

[0028] The accessory 220 includes a mirror source transistor that forms a current mirror circuit with a current source transistor (not shown) in the pixel.

[0029] In the load MOS circuit block 250, a MOS transistor that supplies a constant current is provided for each column.

[0030] The column signal processing circuit 260 performs signal processing such as AD (Analog to Digital) conversion processing and CDS (Correlated Double Sampling) processing on pixel signals for each column. The column signal processing circuit 260 supplies image data made up of the processed signals to the recording unit 120. The column signal processing circuit 260 is an example of a signal processing circuit as defined in the claims.

[0031] [Pixel Configuration Example] FIG. 3 is a circuit diagram showing a configuration example of a pixel 300 according to the first embodiment of the present technology. The pixel 300 includes a pre-stage circuit 310, a sample-and-hold circuit 350, and a post-stage circuit 360. The pre-stage circuit 310 includes a photoelectric conversion element 311, a transfer transistor 312, a pre-stage reset transistor 313, a floating diffusion (FD) 314, and a pre-stage amplification transistor 315. The pre-stage circuit 310 also includes a switch circuit 330, a current source transistor 317, a capacitance element 318, and a sample-and-hold switch 319. The switch circuit 330 includes a switch transistor 331. The pixel 300 also includes a conversion efficiency control transistor 320, a capacitance element 321, and a pre-charge transistor 332. A selector 308 is also added for each column. For example, an nMOS transistor is used as each transistor in the pre-stage circuit 310. Note that the pre-stage circuit 310 of each pixel may be configured to include multiple photoelectric conversion elements. Alternatively, a configuration may be adopted in which a plurality of pre-stage circuits are connected to one sample-and-hold circuit 350, in other words, a plurality of pixels share one sample-and-hold circuit 350. Alternatively, a configuration may be adopted in which a plurality of pre-stage circuits and a plurality of sample-and-hold circuits are connected to one post-stage circuit 360, in other words, a plurality of pixels share one post-stage circuit 360.

[0032] The photoelectric conversion element 311 photoelectrically converts incident light to generate electric charges. The transfer transistor 312 transfers electric charges from the photoelectric conversion element 311 to the FD 314 in accordance with a transfer signal TRG from the vertical scanning circuit 211. The previous-stage reset transistor 313 initializes the FD 314 in accordance with a reset signal RST from the vertical scanning circuit 211.

[0033] The FD 314 accumulates electric charge and generates a voltage according to the amount of electric charge. Hereinafter, the voltage when the FD 314 is initialized will be referred to as a "reset level," and the voltage when electric charge is transferred to the FD 314 will be referred to as a "signal level."

[0034] The pre-amplifying transistor 315 amplifies the voltage of the FD 314 and outputs it from its source. The pre-amplifying transistor 315 is an example of an amplifying transistor as defined in the claims.

[0035] The switch transistor 331 opens and closes a path between the source of the pre-amplification transistor 315 and the drain of the current source transistor 317 in accordance with a control signal SW from the vertical scanning circuit 211. A connection node between the switch transistor 331 and the current source transistor 317 is referred to as a pre-node 316.

[0036] The current source transistor 317 provides a constant drain-source current I depending on the voltage applied to its gate. ｄｓ The source of the current source transistor 317 is connected to the ground node.

[0037] The capacitance element 318 is inserted between the gate and source (in other words, the ground node) of the current source transistor 317. The sample-and-hold switch 319 opens and closes the path between the accessory 220 and the gate of the current source transistor 317 in accordance with a control signal SH from the vertical scanning circuit 211. The capacitance element 318 is, for example, a MOS (Metal-Oxide-Semiconductor) capacitor, a MIM (Metal-Insulator-Metal) capacitor, or an inter-wiring capacitance. In addition to these, the capacitance element 318 may be any capacitance created by a semiconductor process.

[0038] Here, a configuration in which the capacitive element 318 and the sample-and-hold switch 319 are not provided will be considered as a comparative example.

[0039] In the comparative example, when exposure is completed, the vertical scanning circuit 211 turns on the switch transistors 331 of all pixels using the control signal SW. As a result, the drain-source current I ｄｓ At this time, the gate-source voltage V of the current source transistor 317 ｇｓ This gate-source voltage V ｇｓThe variation is caused by the following two factors:

[0040] The first is ground bounce on the pixel side, which occurs due to IR drop caused by the DC current itself within the pixel. Although efforts are made to reduce the resistance of the ground power supply network as much as possible by using mesh wiring, bounce of around several tens of millivolts (mV) is still unavoidable.

[0041] The second is variation in the bias voltage VB due to ground bounce on the accessory 220 side. However, regarding the second factor, it is easy to take measures against the ground bounce because the accessory 220 is disposed outside the pixel array unit 230. Therefore, the influence of the first factor is large.

[0042] Therefore, a capacitance element 318 and a sample-and-hold switch 319 are provided, and the vertical scanning circuit 211 switches the sample-and-hold switch 319 from a closed state to an open state using a control signal SH during a period in which the switch transistor 331 is in an off state. As a result, the bias voltage VB is sampled and held by the capacitance element 318.

[0043] Thereafter, when the switch transistor 331 transitions to the on state, a ground bounce occurs. However, since the sample-and-hold switch 319 is in the open state, there is no place for the charge to escape on the voltage side of the capacitance element 318, and the voltage rises by the amount of the ground bounce. As a result, the potential difference between both ends of the capacitance element 318 (i.e., the gate-source voltage V ｇｓ As a result, the fluctuation of the drain-source current I ｄｓ Fluctuations in the

[0044] If the capacitance value of the parasitic capacitance is Cp and the capacitance value of the capacitive element 318 is Cs, then the gate-source voltage V ｇｓ Fluctuation ΔV ｇｓ is expressed by the following formula, for example: ｇｓ ∝Cs / (Cp+Cs)...Formula 1

[0045] For example, if Cp is about 1 femtofarad (fF), then ΔV ｇｓTo reduce by 90%, it is sufficient to set Cs to about 10 femtofarads (fF) according to the above formula. With a capacitance value of this level, it is possible to appropriately balance the area of ​​the capacitive element 318 and the ability of the power supply side potential to follow the bounce.

[0046] The sample-and-hold circuit 350 holds a signal level corresponding to the exposure dose and a predetermined reset level, and includes capacitance elements 351 and 352, selection transistors 353 and 354, and a subsequent reset transistor 355. Each transistor in the sample-and-hold circuit 350 is, for example, an nMOS transistor.

[0047] The capacitance elements 351 and 352 hold the voltage (reset level or signal level) output from the previous-stage circuit 310. For example, the capacitance element 351 holds the reset level, and the capacitance element 352 holds the signal level. For example, elements with an MIM (Metal Insulator Metal) structure are used as these capacitance elements. Furthermore, one end of each of the capacitance elements 351 and 352 is commonly connected to the previous-stage node 316.

[0048] The selection transistor 353 opens and closes a path between the other end of the capacitance element 351 and a subsequent node 356 in accordance with a selection signal S1 from the vertical scanning circuit 211. The selection transistor 354 opens and closes a path between the other end of the capacitance element 352 and a subsequent node 356 in accordance with a selection signal S2 from the vertical scanning circuit 211.

[0049] The subsequent reset transistor 355 initializes the voltage of the subsequent node 356 to a predetermined potential VREG in accordance with a subsequent reset signal RB from the vertical scanning circuit 211. The potential VREG is set to a potential different from the power supply voltage VDD (for example, a potential lower than VDD).

[0050] The post-stage circuit 360 includes a post-stage amplification transistor 361 and a post-stage selection transistor 362. These transistors are, for example, nMOS transistors.

[0051] The rear-stage amplification transistor 361 amplifies the voltage of the rear-stage node 356. The rear-stage selection transistor 362 outputs the voltage signal amplified by the rear-stage amplification transistor 361 to the vertical signal line 309 as a pixel signal in accordance with a selection signal SEL from the vertical scanning circuit 211.

[0052] The conversion efficiency control transistor 320 controls the conversion efficiency of converting charge into voltage in accordance with a control signal FDG from the vertical scanning circuit 211. When the conversion efficiency control transistor 320 is in the on state, the capacitance element 321 is connected to the FD 314, and the conversion efficiency is low. On the other hand, when the conversion efficiency control transistor 320 is in the off state, the charge is converted into voltage only by the FD 314, and the conversion efficiency is high. For example, an element with an MIM structure is used as the capacitance element 321.

[0053] The selector 308 selects either the power supply voltage VDD or the voltage Vread in accordance with a selection signal sel from the vertical scanning circuit 211, and supplies the selected voltage as a drain voltage VAMD to the drain of the pre-amplification transistor 315. The power supply voltage VDD is selected when the sample-and-hold circuit 350 samples and holds a voltage. On the other hand, the voltage Vread is selected when the voltage is read from the sample-and-hold circuit 350 and AD converted for each row.

[0054] Here, the voltage Vread is set to a value shown in the following formula: Vread=VDD-Vgs-Vft Formula 2 In the above formula, Vgs is the gate-source voltage of the previous-stage amplification transistor 315. Vft is the amount of fluctuation in the potential of the FD 314 due to reset feedthrough of the previous-stage reset transistor 313.

[0055] By switching to the voltage Vread during reading, the pre-amplification transistor 315 is turned off, and noise generated by the transistor can be reduced.

[0056] The precharge transistor 332 is disposed in the switch circuit 330 and opens and closes the path between the previous stage node 316 and the current source transistor 317 in accordance with a control signal PC from the vertical scanning circuit 211 .

[0057] Although both the switch transistor 331 and the precharge transistor 332 are disposed in the switch circuit 330, it is also possible to dispose only one of them.

[0058] The sample-and-hold switch 319 samples and holds the bias voltage VB while at least one of the two transistors in the switch circuit 330 is in the off state.

[0059] In the sample-and-hold circuit 350, the selection transistor 353, the selection transistor 354, and the subsequent reset transistor 355 are pMOS (p-channel Metal Oxide Semiconductor) transistors.

[0060] Furthermore, the vertical scanning circuit 211 can control the transfer signal TRG, reset signal RST, and control signal FDG to any of high level, middle level, and low level. The high level is set to a value higher than "0" volts (V). The middle level is set to a value lower than the high level, for example, "0" volts (V). The low level is set to a value lower than the middle level, for example, "-1" volts (V). In other words, the transfer transistor 312, the preceding reset transistor 313, and the conversion efficiency control transistor 320 corresponding to these signals are driven in three levels.

[0061] When the vertical scanning circuit 211 holds the reset level in the capacitive element 351, it can soft-reset the pre-amplification transistor 315 by changing the transfer signal TRG, the reset signal RST, and the control signal FDG from the middle level to the low level, thereby reducing kTC noise.

[0062] Furthermore, by using pMOS transistors in the sample-and-hold circuit 350, it is possible to reduce the loss of charge from the capacitance element 351 when the gate voltage of the pre-amplifying transistor 315 is returned from a low level to an intermediate level.

[0063] Although the conversion efficiency control transistor 320, the capacitance element 321, the selector 308, and the precharge transistor 332 are all provided, the present invention is not limited to this configuration, and some of these elements may be omitted. Furthermore, although the vertical scanning circuit 211 drives some of the transistors in three-value mode, if soft reset is not required, these transistors may also be driven in two-value mode. Furthermore, although three pMOS transistors are provided in the sample-and-hold circuit 350, some or all of these may be replaced with nMOS transistors.

[0064] 4 is a circuit diagram showing a configuration example of the accessory 220 according to the first embodiment of the present technology. The accessory 220 includes a reference current source 221 and a plurality of mirror-source transistors 222. If the mirror-source transistors 222 are arranged on a row-by-row basis and the number of rows is N (N is an integer), the number of mirror-source transistors 222 is N. For example, nMOS transistors are used as these mirror-source transistors 222.

[0065] The reference current source 221 generates a predetermined reference current I ｒｅｆ . The gate and drain of each mirror-source transistor 222 are connected to the reference current source 221, and the source is connected to the ground node. Furthermore, the sample-and-hold switch 319 opens and closes a path between the gate and drain of the mirror-source transistor 222 in the corresponding row and the gate of the current-source transistor 317. Note that in the figure, elements other than the current-source transistor 317, capacitance element 318, and sample-and-hold switch 319 are omitted in each pixel 300.

[0066] With the above circuit configuration, when the sample-and-hold switch 319 is in a closed state, the mirror source transistor 222 and the corresponding current source transistor 317 form a current mirror circuit. If the switch transistor 331 (not shown) is in an on state when the sample-and-hold switch 319 is in a closed state, the current source transistor 317 will receive a reference current I ｒｅｆ Drain-source current I according to ｄｓ is playing.

[0067] To suppress the influence of ground bounce, the vertical scanning circuit 211 uses the control signal SH to transition the sample-and-hold switch 319 from the on state to the off state while the switch transistor 331 is in the off state, so that the voltage of the gate of the mirror source transistor 222 is sampled and held in the capacitive element 318 as the bias voltage VB.

[0068] After the sample and hold, the vertical scanning circuit 211 turns on the switch transistor 331. At this time, since the bias voltage VB is held in the capacitance element 318, the current source transistor 317 receives the mirror source reference current I ｒｅｆ Drain-source current I according to ｄｓ is playing.

[0069] [Configuration Example of Column Signal Processing Circuit] FIG. 5 is a block diagram showing a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 according to the first embodiment of the present technology.

[0070] A vertical signal line 309 is wired for each column in the load MOS circuit block 250. If the number of columns is I (I is an integer), then I vertical signal lines 309 are wired. Furthermore, a load MOS transistor 251 that supplies a constant current is connected to each vertical signal line 309.

[0071] The column signal processing circuit 260 includes a plurality of ADCs (Analog to Digital Converters) 261 and a digital signal processing unit 262. An ADC 261 is provided for each column. If the number of columns is I, then I ADCs 261 are provided.

[0072] The ADC 261 converts analog pixel signals from the corresponding columns into digital signals using the ramp signal Rmp from the DAC 213. The ADC 261 supplies the digital signals to the digital signal processing unit 262. For example, a single-slope ADC including a comparator and a counter is disposed as the ADC 261.

[0073] The digital signal processing unit 262 performs predetermined signal processing such as CDS processing on each of the digital signals for each column. The digital signal processing unit 262 supplies image data made up of the processed digital signals to the recording unit 120.

[0074] [Operation Example of Solid-State Imaging Device] Fig. 6 is a timing chart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. The vertical scanning circuit 211 drives all pixels to simultaneously start exposure. That is, exposure is performed using a global shutter method. During a sample-and-hold period from timing T2 at the end of the exposure period to timing T20, the vertical scanning circuit 211 drives all pixels to hold voltages (reset levels and signal levels). Then, during a readout period from timing T20 to T30, the vertical scanning circuit 211 sequentially drives the rows to read out the voltages and perform A / D (Analog to Digital) conversion.

[0075] In the period before timing T2, the control signal SW is at a low level and the control signal SH is at a high level. At timing T1 within this period, the vertical scanning circuit 211 changes the control signal SH from a high level to a low level. This causes the bias voltage to be sampled and held in the capacitive element 318 in the pixel.

[0076] At timing T2, the vertical scanning circuit 211 sets the control signal FDG, the reset signal RST, the control signal SW, and the control signal PC to high level, thereby initializing the FD 314 and subsequent nodes.

[0077] At timing T3, the vertical scanning circuit 211 sets the control signal FDG and the reset signal RST to the middle level, thereby establishing the reset level state and setting the previous-stage node to a potential state buffered by the previous-stage amplification transistor 315.

[0078] At timing T4, the vertical scanning circuit 211 sets the selection signals S1 and S2 to low level, and immediately thereafter at timing T5, returns the selection signal S2 to high level, causing the reset level to be sampled in the capacitive element 351.

[0079] At timing T6, the vertical scanning circuit 211 changes the transfer signal TRG, the reset signal RST, and the control signal FDG from the middle level to the low level, and changes the control signal PC from the high level to the low level, causing the voltage of the FD 314 (the gate of the pre-amplification transistor 315) to drop, soft-resetting the pre-amplification transistor 315, and holding the reset level in the capacitance element 351.

[0080] At timing T7, the vertical scanning circuit 211 sets the subsequent reset signal RB to high level, which also turns off the subsequent reset transistor 355 on the right side of the capacitive element 351.

[0081] At timing T8, the vertical scanning circuit 211 sets the selection signal S1 to high level, which also turns off the selection transistor 353.

[0082] At timing T9, the vertical scanning circuit 211 returns the transfer signal TRG, the reset signal RST, and the control signal FDG to the middle level and returns the control signal PC to the high level, thereby recovering the charge lost at timing T6 and preventing the loss of the reset level information.

[0083] At timing T10, the vertical scanning circuit 211 sets the transfer signal TRG to high level and the selection signal S2 to low level, thereby transferring charge to the FD 314. At timing T11, the vertical scanning circuit 211 sets the transfer signal TRG to middle level, thereby causing the signal level to be sampled by the capacitive element 352.

[0084] At timing T12, the vertical scanning circuit 211 sets the subsequent reset signal RB to low level, and immediately thereafter sets the transfer signal TRG, the reset signal RST, and the control signal FDG to low level. At timing T13, the vertical scanning circuit 211 returns the subsequent reset signal RB to high level. This initializes the subsequent nodes.

[0085] At timing T14, the vertical scanning circuit 211 sets the selection signal S2 to a high level and returns the transfer signal TRG, the reset signal RST, and the control signal FDG to the middle level, thereby turning off the selection transistor 354 and holding the signal level in the capacitance element 352.

[0086] In the subsequent read period, the control signal SW is controlled to a middle level, and the selection signals S1 and S2 are controlled to a high level in turn, and the reset level and the signal level are read out in turn.

[0087] Although the vertical scanning circuit 211 keeps the switch transistor 331 on during the sample and hold period, the present invention is not limited to this control. For example, the vertical scanning circuit 211 can alternately turn on and off the switch transistor 331 and the precharge transistor 332 during the sample and hold period. This allows the previous-stage node to settle from a high level to a low level more quickly, improving responsiveness.

[0088] As shown in the figure, when the control signal SW is at a low level, the drain-source current I ｄｓ During the period when the bias voltage is not supplied, the control signal SH is controlled to change from high level to low level, whereby the bias voltage is sampled and held in the capacitance element 318 in the pixel.

[0089] 7 is a graph showing an example of the characteristics of the current source transistor 317 according to the first embodiment of the present technology. The vertical axis in the graph represents the drain-source current I ｄｓ The horizontal axis represents the gate-source voltage V ｇｓ Shows.

[0090] When a current source transistor 317 is provided for each pixel, the current value per pixel must be set to a few nanoamperes (nA) in order to reduce power consumption. ｔｈ In this weak inversion region, the drain-source current I ｄｓ is expressed by the following formula: ｄｓ =I０ ・exp{(V ｇｓ -V ｔｈ ) / ηV Ｔ} ...Equation 3 In the above equation, I ０ and η are coefficients, and V Ｔ is the thermal voltage.

[0091] From Equation 3, the drain-source current I ｄｓ is the gate-source voltage V ｇｓ The gate-source voltage V ｇｓ Variation ΔV ｇｓ The drain-source current I ｄｓ Variation ΔI ｄｓ is the same ΔV in the strong inversion region ｇｓ is much larger than when

[0092] 8 is a circuit diagram showing an example of the state of the solid-state imaging device 200 in the comparative example. In this comparative example, each pixel 300 does not have the capacitance element 318 and the sample-and-hold switch 319, and the gate and source of the mirror-source transistor 222 are directly connected to the gate of the mirror-target current-source transistor 317.

[0093] In the comparative example, all pixels are driven, and the drain-source current I ｄｓ When a current flows, the current causes ground bounce, causing the ground voltage to vary from pixel to pixel. For example, the ground voltage in the upper left pixel of the figure is 80 millivolts (mV), but the ground voltage in the upper right pixel is 100 millivolts (mV).

[0094] Although the bias voltage VB may vary due to ground bounce on the accessory side, for the sake of convenience, it is assumed that there is no variation in the bias voltage VB.

[0095] In the comparative example, the gate-source voltage of the current source transistor 317 varies due to variations in the ground voltage between pixels. For example, in the upper left pixel, the bias voltage VB is 180 millivolts (mV) and the ground voltage is 80 millivolts (mB), so the gate-source voltage is 100 millivolts (mV). On the other hand, in the upper right pixel, the bias voltage VB is 180 millivolts (mV) and the ground voltage is 100 millivolts (mB), so the gate-source voltage is 80 millivolts (mV). Due to this variation in the gate-source voltage, the drain-source current I of the current source transistor 317 varies between pixels. ｄｓ It becomes inconsistent.

[0096] In the comparative example shown in the same figure, the drain-source current I ｄｓ A sufficiently large reference current I is used so that the current value required for driving all pixels can be obtained even if the ｒｅｆ needs to be supplied.

[0097] 9 is a diagram showing an example of a state of the solid-state imaging element when a pixel is sampled and held according to the first embodiment of the present technology, in which "a" in the figure shows the state of the solid-state imaging element when sampled by the sample-and-hold switch 319, and "b" in the figure shows the state when held.

[0098] As shown in the example of "a" in the figure, the switch transistor 331 (not shown) is in the off state in all pixels, and the supply of the drain-source current Ids from the current source transistor 317 is stopped. The dotted arrow indicates that the supply of the drain-source current Ids is stopped. During this period, no ground bounce occurs in each pixel, and the ground voltage of all pixels is, for example, 0 millivolts (mV).

[0099] Although the bias voltage VB may vary due to ground bounce on the accessory side, for the sake of convenience, it is assumed that there is no variation in the bias voltage VB.

[0100] The vertical scanning circuit 211 closes the sample-and-hold switches 319 of all pixels, causing the bias voltage VB to be sampled in the capacitance elements 318.

[0101] Then, as shown in b in the figure, the vertical scanning circuit 211 closes the sample-and-hold switches 319 of all pixels during the period in which the switch transistors 331 are in the off state, thereby holding the bias voltage VB of the capacitive elements 318.

[0102] Subsequently, as illustrated in FIG. 10, the vertical scanning circuit 211 turns on the switch transistors 331 (not shown) of all pixels, and the drain-source current I ｄｓ This current causes ground bounce, which causes the ground voltage to vary from pixel to pixel. For example, the pixel in the upper left corner of the figure has a ground voltage of 80 millivolts (mV), while the pixel in the upper right corner has a ground voltage of 100 millivolts (mV).

[0103] At this time, since the sample-and-hold switch 319 is in an open state, there is no escape route for the charge on the voltage side of the capacitance element 318. Therefore, according to the formula Q=CV, the voltage on the voltage side of the capacitance element 318 rises by the amount of ground bounce. For example, in the upper left pixel, the voltage on the power supply side rises from 140 millivolts (mV) to 220 millivolts (mV), and in the upper right pixel, the voltage on the power supply side rises from 140 millivolts (mV) to 240 millivolts (mV). As a result, the gate-source voltage for each pixel becomes approximately the same, and as a result, the drain-source current I ｄｓ The variation in the

[0104] 9 and 10, variations in the drain-source current Ids can be suppressed by sampling and holding the bias voltage VB in the capacitive element 318. This makes it possible to adjust the current value of the reference current to the minimum value required for driving, thereby reducing power consumption compared to the comparative example.

[0105] 11 is a diagram showing an example of the layout of the sample-and-hold switch 319, the capacitive element 318, and the current source transistor 317 according to the first embodiment of the present technology. For example, a MOS transistor is used as the sample-and-hold switch 319. The gate of the transistor is connected to a signal line that supplies a control signal SH, and the source is connected to a signal line that supplies a bias voltage VB. "G," "D," and "S" in the diagram represent the gate, drain, and source of the MOS transistor.

[0106] Furthermore, for example, the gate capacitance of a MOS transistor is used as the capacitance element 318. The drain and source of this transistor are connected to a node of the ground voltage VSS, and the gate is connected to a signal line that supplies the bias voltage VB.

[0107] The gate of the current source transistor 317 is connected to the connection node between the sample-and-hold switch 319 and the capacitance element 318, and the source is connected to the node of the ground voltage VSS.

[0108] 12 is a flowchart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.

[0109] The vertical scanning circuit 211 starts exposure of all pixels with the control signals SW of all pixels at low level (step S901). Then, while the control signals SW remain at low level, the vertical scanning circuit 211 controls the sample-and-hold switches 319 of all pixels to sample and hold the bias voltage VB (step S902). The vertical scanning circuit 211 then sets the control signals SW of all pixels at high level, ending exposure of all pixels (step S903). Next, the solid-state imaging device 200 sequentially reads out all rows (step S904). After step S904, the solid-state imaging device 200 ends its imaging operation.

[0110] As described above, according to the first embodiment of the present technology, the sample-and-hold switch 319 samples and holds the bias voltage VB in the capacitance element 318 while the drain-source current is stopped, thereby making it possible to suppress variations in the gate-source voltage. This makes it possible to suppress variations in the drain-source current for each pixel.

[0111] [Modification] In the first embodiment described above, pixels 300 having the circuit configuration illustrated in Fig. 3 are arranged, but the circuit configuration of pixels 300 is not limited to that illustrated in Fig. 3. A solid-state imaging device 200 in this modification of the first embodiment differs from the first embodiment in that it uses a circuit configuration different from that in Fig. 3.

[0112] 13 is a circuit diagram showing a configuration example of a pixel 300 according to a modification of the first embodiment of the present technology. The pixel 300 according to the modification of the first embodiment differs from the first embodiment in that the subsequent circuit has two systems.

[0113] Subsequent circuits 360-1 and 360-2 are arranged in the pixel 300, and a subsequent amplification transistor 361-1 and a subsequent selection transistor 362-1 are arranged in the subsequent circuit 360-1, with the subsequent selection transistor 362-1 connected to a vertical signal line 309-1. A subsequent amplification transistor 361-2 and a subsequent selection transistor 362-2 are arranged in the subsequent circuit 360-2, with the subsequent selection transistor 362-2 connected to a vertical signal line 309-2. The circuit configuration illustrated in the figure makes it possible to suppress fluctuations in the level of the subsequent node.

[0114] 14, the selection transistors 354 and 353 can be connected in series between the previous-stage circuit 310 and the subsequent-stage circuit 360. In this case, the capacitance element 351 is inserted between the subsequent-stage node 356 and the ground node. The capacitance element 352 is inserted between the connection node of the selection transistors 354 and 353 and the ground node.

[0115] Regarding the circuit in the same figure, you can refer to the control described in, for example, "Chen Xu et al., A Stacked Global-Shutter CMOS Imager with SC-Type Hybrid-GS Pixel and Self-Knee Point Calibration Single-Frame HDR and On-Chip Binarization Algorithm for Smart Vision Applications ISSCC2019."

[0116] 15, a sampling transistor 357 can be arranged in place of the selection transistors 353 and 354 in the sample-and-hold circuit 350. In this case, the sampling transistor 357 and the capacitance element 351 are connected in series between the front-stage circuit 310 and the rear-stage circuit 360. The capacitance element 352 is inserted between the connection node of the sampling transistor 357 and the capacitance element 351 and the ground node. The circuit configuration illustrated in the figure makes it possible to reduce the number of transistors.

[0117] For the circuit shown in the figure, you can refer to the control described in "Jae-kyu Lee, et al., A 2.1e-Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3 μm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology, ISSCC 2020."

[0118] In this way, according to the modification of the first embodiment of the present technology, the subsequent circuit is divided into two systems, so that fluctuations in the level of the subsequent node can be suppressed.

[0119] 2. Second Embodiment In the first embodiment described above, the circuits in the solid-state imaging element 200 are arranged on a single semiconductor chip, but this configuration may make it difficult to miniaturize pixels. The solid-state imaging element 200 in this second embodiment differs from the first embodiment in that the solid-state imaging element 200 has a stacked structure.

[0120] 16 shows a solid-state imaging device 200 according to the second embodiment, which includes a lower chip 202 and an upper chip 201 stacked on the lower chip 202. These chips are electrically connected by, for example, Cu-Cu bonding. Note that, in addition to Cu-Cu bonding, they can also be connected by vias or bumps.

[0121] An upper pixel array unit 231 is arranged on the upper chip 201. A lower pixel array unit 232 and a column signal processing circuit 260 are arranged on the lower chip 202. For each pixel in the pixel array unit 230, a portion of the pixels is arranged in the upper pixel array unit 231, and the remainder is arranged in the lower pixel array unit 232. The upper chip 201 and the lower chip 202 are examples of the multiple semiconductor chips set forth in the claims.

[0122] The lower chip 202 also has arranged thereon a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250. These circuits are omitted in the figure.

[0123] 17 is a circuit diagram showing a configuration example of a pixel 300 according to the second embodiment of the present technology. Elements in the pre-stage circuit 310 other than the pre-charge transistor 332, the current source transistor 317, the capacitance element 318, and the sample and hold switch 319 are arranged on the upper chip 201. The pre-charge transistor 332, the current source transistor 317, the capacitance element 318, the sample and hold switch 319, and circuits subsequent to the sample and hold circuit 350 are arranged on the lower chip 202. As illustrated in the figure, by distributing and arranging the elements in the pixel 300 across the stacked upper chip 201 and lower chip 202, the area of ​​the pixel can be reduced, making it easier to miniaturize the pixel.

[0124] It is also possible to disperse elements and circuits among three or more stacked semiconductor chips.

[0125] As described above, according to the second embodiment of the present technology, the circuits and elements in the pixel 300 are distributed and arranged on two semiconductor chips, which facilitates miniaturization of the pixel.

[0126] 3. Third Embodiment In the first embodiment described above, the capacitive element 318 and the sample-and-hold switch 319 are disposed in the CIS, but these circuits may also be disposed in a sensor other than the CIS. This third embodiment differs from the first embodiment in that the capacitive element 318 and the sample-and-hold switch 319 are disposed in an EVS (Event-based Vision Sensor).

[0127] 18 is a block diagram showing a configuration example of a solid-state imaging element 200 according to the third embodiment of the present technology. The solid-state imaging element 200 is an EVS, and includes a column arbiter 271, a column AER (Address Event Representation) circuit 272, a column address encoder 273, a pixel array unit 400, and a state machine 277. The solid-state imaging element 200 also includes a row address encoder 274, a row AER circuit 275, and a row arbiter 276. A plurality of pixels 410 are arranged in the pixel array unit 400 in a two-dimensional lattice pattern.

[0128] Each pixel in the pixel array unit 400 generates a differential signal indicating the amount of change in voltage corresponding to the photocurrent, and compares the level of the signal with a predetermined threshold. The comparison result indicates the detection result of an address event. The thresholds for comparison with the differential signal include two different thresholds, the larger of which is the upper threshold and the smaller of which is the lower threshold. The address events include on events and off events, and the detection results include the detection result of a one-bit on event and the detection result of a one-bit off event. An on event is detected when the differential signal exceeds the upper threshold, and an off event is detected when the differential signal falls below the lower threshold.

[0129] When an address event is detected, the pixel 410 transmits and receives a request and a response (hereinafter referred to as a "handshake") to the row AER circuit 275 in order to output the detection result of the address event to the outside. Next, the pixel 410 transmits and receives a request and a response to the row AER circuit 275 in order to output the detection result of the address event to the outside. Next, the pixel 410 transmits and receives a handshake with the column AER circuit 272.

[0130] The column arbiter 271 arbitrates requests from the column AER circuit 272 and transmits a response to the column AER circuit 272 based on the arbitration result.

[0131] The column AER circuit 272 transmits and receives (handshakes) requests and responses requesting external output of address event detection results between each column, the column arbiter 271, and the state machine 277.

[0132] The column address encoder 273 encodes the address of the column in which the address event occurs and transmits it to the state machine 277 .

[0133] The row address encoder 274 encodes the address of the row in which the address event occurred and transmits it to the state machine 277 .

[0134] The row arbiter 276 arbitrates requests from the row AER circuit 275 and transmits a response to the row AER circuit 275 based on the arbitration result.

[0135] The row AER circuit 275 transmits and receives (handshakes) requests and responses requesting external output of address event detection results between each row, the row arbiter 276, and the state machine 277.

[0136] The state machine 277 performs handshake between the column AER circuit 272 and the row AER circuit 275. When the state machine 277 receives a request from the column AER circuit 272 and the row AER circuit 275, it decodes the data from the column address encoder 273 and the row address encoder 274 to identify the address at which the address event was detected. Image data is generated by arranging the address event detection results for each pixel in a two-dimensional grid. The state machine 277 supplies the image data to the recording unit 120.

[0137] 19 is a circuit diagram showing an example of a configuration of a pixel 410 according to the third embodiment of the present technology. The pixel 410 includes a logarithmic response unit 420, a buffer 430, a differentiation circuit 440, a comparator 450, and an AER logic circuit 460.

[0138] The logarithmic response unit 420 includes a photoelectric conversion element 421 , nMOS transistors 422 and 423 , and a pMOS transistor 424 .

[0139] The photoelectric conversion element 421 generates a photocurrent Ip as an electrical signal by photoelectric conversion of incident light.

[0140] The pMOS transistor 424 and the nMOS transistor 423 are connected in series between the power supply and the ground terminal. The gate of the nMOS transistor 422 is connected to the connection node between the pMOS transistor 424 and the nMOS transistor 423, its source is connected to the photoelectric conversion element 421, and its drain is connected to the power supply. A bias voltage Vblog is applied to the gate of the pMOS transistor 424. The gate of the nMOS transistor 423 is connected to the connection node between the nMOS transistor 422 and the photoelectric conversion element 421.

[0141] With the above-described circuit configuration, the logarithmic response unit 420 performs current-voltage conversion on the photocurrent Ip to generate the pixel voltage Vp.

[0142] The solid-state imaging device 200 has a structure in which an upper chip 201 and a lower chip 202 are stacked, and the photoelectric conversion element 421 and nMOS transistors 422 and 423 are arranged on the upper chip 201. On the other hand, the circuitry from the pMOS transistor 424 onwards is arranged on the lower chip 202.

[0143] Although the solid-state imaging device 200 has a layered structure, it may be formed as a single semiconductor chip instead of the layered structure.

[0144] The buffer 430 also includes pMOS transistors 431 and 432 connected in series between the power supply and ground nodes. The gate of the pMOS transistor 432 on the ground side is connected to the logarithmic response unit 420, and a bias voltage Vbsf is applied to the gate of the pMOS transistor 431 on the power supply side. The connection point of the pMOS transistors 431 and 432 is connected to a differentiating circuit 440. This connection performs impedance conversion on the pixel voltage Vp, and a signal of the converted voltage is output to the differentiating circuit 440 as an output signal Vp'.

[0145] The differentiating circuit 440 includes capacitive elements 318 , 441 , and 444 , pMOS transistors 442 , 443 , and 446 , an nMOS transistor 445 , and a sample-and-hold switch 319 .

[0146] One end of the capacitance element 441 is connected to the buffer 430, and the other end is connected to one end of the capacitance element 444 and the gate of the pMOS transistor 443. A reset signal xrst is input to the gate of the pMOS transistor 442, and the source and drain are connected to both ends of the capacitance element 444. The pMOS transistor 443 and the nMOS transistor 445 are connected in series between the power supply and the ground terminal. The other end of the capacitance element 444 is connected to the connection point of the pMOS transistor 443 and the nMOS transistor 445. This connection point is also connected to the comparator 450. The nMOS transistor 445 is an example of a current source transistor as defined in the claims.

[0147] The capacitance element 318 is inserted between the gate and source of the nMOS transistor 445. The pMOS transistor 446 supplies a power supply voltage to the gate of the pMOS transistor 443 in accordance with the initialization signal INI, turning the pMOS transistor 443 off. While the reset signal xrst is at a high level, the initialization signal INI periodically controls the pMOS transistor 446 to be turned off. The sample-and-hold switch 319 samples and holds the bias voltage VB in the capacitance element 318, for example, when the initialization signal INI turns the pMOS transistor 446 off and cuts off the current.

[0148] With this connection, a differential signal indicating the amount of change in the output signal Vp' is generated and output to the comparator 450. The differential signal is also initialized by the reset signal xrst.

[0149] The comparator 450 includes pMOS transistors 451 and 453 and nMOS transistors 452 and 454. The pMOS transistor 451 and the nMOS transistor 452 are connected in series between the power supply and the ground terminal, and the pMOS transistor 453 and the nMOS transistor 454 are also connected in series between the power supply and the ground terminal. The gates of the pMOS transistors 451 and 453 are connected to the differentiation circuit 440. A predetermined upper threshold Von is applied to the gate of the nMOS transistor 452, and a predetermined lower threshold Voff is applied to the gate of the nMOS transistor 454.

[0150] The connection point between pMOS transistor 451 and nMOS transistor 452 is connected to AER logic circuit 460, and the voltage at this connection point is output as comparison result VCH. The connection point between pMOS transistor 453 and nMOS transistor 454 is also connected to AER logic circuit 460, and the voltage at this connection point is output as comparison result VCL. With this connection, comparator 450 outputs a high-level comparison result VCH when the differentiated signal exceeds the upper threshold Von, and outputs a low-level comparison result VCL when the differentiated signal falls below the lower threshold Voff. This comparison result VCH indicates the detection result of an on-event, and comparison result VCL indicates the detection result of an off-event.

[0151] Although the comparator 450 detects both an ON event and an OFF event, it may detect only one of them. For example, when detecting only an ON event, only the corresponding pMOS transistor 451 and nMOS transistor 452 are arranged.

[0152] The AER logic circuit 460 performs a handshake based on the comparison results VCH and VCL. When an address event occurs, the AER logic circuit 460 performs a handshake with the column arbiter 271. Next, the AER logic circuit 460 performs a handshake with the row arbiter 276 and resets the differentiation circuit 440 with the reset signal xrst.

[0153] Note that the capacitance element 318 and the sample-and-hold switch 319 can also be arranged in a sensor other than an EVS or a CIS, as long as the sensor has a current source transistor for each pixel. For example, the capacitance element 318 and the sample-and-hold switch 319 can also be arranged in a sensor that performs photon counting using a SPAD.

[0154] As described above, according to the third embodiment of the present technology, the capacitance element 318 and the sample-and-hold switch 319 are arranged in the EVS, so that variations in current in the EVS can be suppressed.

[0155] 4. Fourth Embodiment In the first embodiment described above, an nMOS transistor is used as the current source transistor 317, but a pMOS transistor can also be used. The solid-state imaging device 200 in this fourth embodiment differs from the first embodiment in that a pMOS transistor is used as the current source transistor 317.

[0156] 20 is a circuit diagram showing a configuration example of a pixel 300 according to a fourth embodiment of the present technology. The pixel 300 according to the fourth embodiment differs from the pixel 300 according to the first embodiment in that a pMOS transistor is used as a current source transistor 317. The source of the current source transistor 317 and one end of the capacitance element 318 are connected to a power supply voltage VDD. PMOS transistors are also used for other transistors such as a switch transistor 331 and a precharge transistor 332.

[0157] Even when a pMOS transistor is used as the current source transistor 317, the current variation can be suppressed in the same manner as in the first embodiment.

[0158] The second and third embodiments can be applied to the fourth embodiment.

[0159] As described above, according to the fourth embodiment of the present technology, when a pMOS transistor is used as the current source transistor 317, it is possible to suppress variations in current.

[0160] 5. Fifth Embodiment In the first embodiment described above, the capacitance element 318 and the sample-and-hold switch 319 are provided for each pixel, but it is preferable to improve area efficiency. The solid-state imaging device 200 in this fifth embodiment differs from the first embodiment in that a plurality of pixels share the capacitance element 318 and the sample-and-hold switch 319.

[0161] 21 is a circuit diagram showing a configuration example of a pixel array unit 230 according to the fifth embodiment of the present technology. This pixel array unit 230 is divided into a plurality of shared areas 305. When it is necessary to consider IR bounce on an area-by-area basis, that area is set as the shared area 305. In each of these shared areas 305, a capacitive element 318, a sample-and-hold switch 319, and a plurality of pixels are arranged. In the example of the same figure, for example, six pixels, namely, pixels 300-1, 300-2, 300-3, 300-4, 300-5, and 300-6, are arranged. Note that the number of pixels in the shared area 305 is not limited to six, as long as it is two or more.

[0162] Pixel 300-1 includes a current source transistor 317-1, and pixel 300-2 includes a current source transistor 317-2. Pixel 300-3 includes a current source transistor 317-3, and pixel 300-4 includes a current source transistor 317-4. Pixel 300-5 includes a current source transistor 317-5, and pixel 300-6 includes a current source transistor 317-6. Note that, for convenience of illustration, circuits within the pixels other than the current source transistors are omitted in the figure.

[0163] One end of the capacitance element 318 is commonly connected to the gates of the current source transistors of each of the six pixels. The sample-and-hold switch 319 samples and holds the bias voltage VB in the capacitance element 318 in accordance with the control signal SH. In this way, the capacitance element 318 and the sample-and-hold switch 319 are shared by the six pixels. This allows the number of elements per pixel to be reduced and area efficiency to be improved compared to when they are not shared.

[0164] It should be noted that the second, third, and fourth embodiments can be applied to the fifth embodiment.

[0165] As described above, according to the fifth embodiment of the present technology, a plurality of pixels share the capacitance element 318 and the sample-and-hold switch 319, thereby improving area efficiency.

[0166] 6. Sixth Embodiment In the first embodiment described above, the vertical scanning circuit 211 controls the sample and hold switch 319 and the transistors in the switch circuit 330 using different control signals. It is preferable to reduce the number of signal lines that transmit these control signals. The solid-state imaging device 200 in this sixth embodiment differs from the first embodiment in that transistors in the switch circuit 330 that have a polarity different from that of the transistors are used as sample and hold switches.

[0167] 22 is a circuit diagram showing a configuration example of a pixel 300 according to a sixth embodiment of the present technology. In the sixth embodiment, a sample and hold transistor 319-1 is used as the sample and hold switch 319. The polarity of this sample and hold transistor 319-1 is different from that of the transistor in the switch circuit 330.

[0168] For example, if the switch transistor 331 and the precharge transistor 332 in the switch circuit 330 are nMOS transistors, the sample and hold transistor 319-1 is a pMOS transistor.

[0169] In addition, one of the control signals SW and PC to the switch circuit 330 is also supplied to the gate of the sample and hold transistor 319-1. For example, in the same figure, the control signal PC is supplied to the gate of the sample and hold transistor 319-1.

[0170] Since the polarity of the transistor in the switch circuit 330 and the sample and hold transistor 319-1 are different, these transistors can be operated exclusively by supplying the same control signal to them. This eliminates the need to transmit the control signal SH, and allows the number of signal lines for transmitting the control signal to be reduced.

[0171] It should be noted that the second, third, fourth, and fifth embodiments can each be applied to the sixth embodiment.

[0172] As described above, according to the sixth embodiment of the present technology, the polarity of the transistor in the switch circuit 330 and the polarity of the sample and hold transistor 319-1 are different, so that it is possible to reduce the number of signal lines for transmitting control signals.

[0173] 5. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0174] FIG. 23 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0175] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 23, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0176] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0177] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0178] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0179] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0180] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0181] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0182] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0183] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0184] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 23, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0185] FIG. 24 is a diagram showing an example of the installation position of the imaging unit 12031.

[0186] In FIG. 24, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0187] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0188] 24 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0189] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0190] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0191] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0192] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0193] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration. Specifically, for example, the image capturing device 100 of FIG. 1 can be applied to the image capturing unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, it is possible to suppress current variations and reduce power consumption.

[0194] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0195] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0196] The present technology may also be configured as follows: (1) A solid-state imaging device comprising a plurality of pixels, each of which is provided with: a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current; a capacitance element having one end connected to the gate of the current source transistor; a switch circuit that opens and closes a path between an amplification transistor and the current source transistor in accordance with a predetermined control signal; and a sample-and-hold transistor having a polarity opposite to that of the transistor in the switch circuit and that samples and holds a predetermined bias voltage in the capacitance element in accordance with the control signal. (2) The solid-state imaging device according to (1), further comprising a sample-and-hold circuit that holds a signal level corresponding to an exposure amount and a predetermined reset level. (3) The solid-state imaging device according to (2), wherein the switch circuit includes at least one of a switch transistor that opens and closes a path between the source of the amplification transistor and a previous-stage node connected to the sample-and-hold circuit, and a precharge transistor that opens and closes a path between the previous-stage node and the drain of the current source transistor. (4) The solid-state imaging device according to any one of (1) to (3), further comprising a mirror source transistor through which a predetermined reference current flows, wherein the sample and hold transistor opens and closes a path between a gate and a drain of the mirror source transistor and a gate of the current source transistor. (5) The solid-state imaging device according to any one of (1) to (4), wherein the current source transistor, the capacitance element, the switch circuit, and the sample and hold transistor are arranged on one of a plurality of stacked semiconductor chips. (6) The solid-state imaging device according to any one of (1) to (5), wherein each of the plurality of pixels detects the presence or absence of an address event. (7) The solid-state imaging device according to any one of (1) to (6), wherein the capacitance element is a MOS (Metal-Oxide-Semiconductor) capacitor, a MIM (Metal-Insulator-Metal) capacitor, or an inter-wiring capacitance.(8) A solid-state imaging device comprising a plurality of pixels, each of which is provided with a P-type current source transistor having a source connected to a power supply voltage and supplying a predetermined drain-source current, a capacitance element inserted between the gate of the current source transistor and the power supply voltage, and a sample-and-hold switch that samples and holds a predetermined bias voltage in the capacitance element during a period when the drain-source current is not supplied. (9) A solid-state imaging device comprising a plurality of pixels, each of which is provided with a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current, a capacitance element having one end commonly connected to the gates of the current source transistors of the plurality of pixels, and a sample-and-hold switch that samples and holds a predetermined bias voltage in the capacitance element during a period when the drain-source current is not supplied. (10) A photodetector comprising: a plurality of pixels, each of which is provided with a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current, a capacitance element having one end connected to the gate of the current source transistor, a switch circuit that opens and closes a path between an amplifying transistor and the current source transistor in accordance with a predetermined control signal, and a sample-and-hold transistor having a polarity different from that of the transistor in the switch circuit and that samples and holds a predetermined bias voltage in the capacitance element in accordance with the control signal; and a signal processing circuit that processes pixel signals from each of the plurality of pixels. (11) A control method for a solid-state imaging element, comprising: a current source transistor having a source connected to a ground node, supplying a predetermined drain-source current; a switch circuit that opens and closes the path between the amplifying transistor and the current source transistor in accordance with a predetermined control signal; and a sample-and-hold switch having a polarity different from that of the transistor in the switch circuit, sampling and holding a predetermined bias voltage in a capacitance element having one end connected to the gate of the current source transistor in accordance with the control signal.

[0197] 100 Imaging device 110 Imaging lens 120 Recording unit 130 Imaging control unit 200 Solid-state imaging element 201 Upper chip 202 Lower chip 211 Vertical scanning circuit 212 Timing control circuit 213 DAC 220 Accessory 221 Reference current source 222 Mirror source transistor 230, 400 Pixel array unit 231 Upper pixel array unit 232 Lower pixel array unit 250 Load MOS circuit block 251 Load MOS transistor 260 Column signal processing circuit 261 ADC 262 Digital signal processing unit 271 Column arbiter 272 Column AER circuit 273 Column address encoder 274 Row address encoder 275 Row AER circuit 276 Row arbiter 277 State machine 300, 300-1, 300-2, 300-3, 300-4, 300-5, 300-6, 410 Pixel 305 Shared area 308 Selector 310 Pre-stage circuit 311, 421 Photoelectric conversion element 312 Transfer transistor 313 Pre-stage reset transistor 314 FD 315 Pre-stage amplification transistor 316 Pre-stage node 317, 317-1, 317-2, 317-3, 317-4, 317-5, 317-6 Current source transistor 318, 321, 351, 352, 441, 444 Capacitor element 319 Sample and hold switch 319-1 Sample and hold transistor 320 Conversion efficiency control transistor 330 Switch circuit 331 Switch transistor 332 Pre-charge transistor 350 Sample and hold circuit 353, 354 Selection transistor 355 Subsequent stage reset transistor 356 Subsequent stage node 357 Sampling transistor 360, 360-1, 360-2 Subsequent stage circuit 361, 361-1, 361-2 Subsequent stage amplification transistor 362, 362-1, 362-2 Subsequent stage selection transistor 420 Logarithmic response unit 422, 423, 445, 452, 454 nMOS transistor 424, 431, 432, 442, 443, 446, 451, 453 pMOS transistor 430 Buffer 440 Differentiation circuit 450 Comparator 460 AER logic circuit12031 Imaging unit

Claims

1. A solid-state imaging device comprising a plurality of pixels, each of which is provided with: a current source transistor whose source is connected to a ground node and which supplies a predetermined drain-source current; a capacitance element whose one end is connected to the gate of the current source transistor; a switch circuit which opens and closes a path between an amplifying transistor and the current source transistor in accordance with a predetermined control signal; and a sample-and-hold transistor which has a polarity different from that of the transistor in the switch circuit and which samples and holds a predetermined bias voltage in the capacitance element in accordance with the control signal.

2. A solid-state imaging device according to claim 1, further comprising a sample-and-hold circuit for holding a signal level corresponding to the amount of exposure and a predetermined reset level.

3. A solid-state imaging device as described in claim 2, wherein the switch circuit comprises at least one of a switch transistor that opens and closes a path between the source of the amplification transistor and a previous node connected to the sample-and-hold circuit, and a precharge transistor that opens and closes a path between the previous node and the drain of the current source transistor.

4. A solid-state imaging device according to claim 1, further comprising a mirror source transistor through which a predetermined reference current flows, wherein the sample-and-hold transistor opens and closes a path between the gate and drain of the mirror source transistor and the gate of the current source transistor.

5. A solid-state imaging device according to claim 1, wherein the current source transistor, the capacitance element, the switch circuit, and the sample-and-hold transistor are arranged on any one of a plurality of stacked semiconductor chips.

6. The solid-state imaging device according to claim 1, wherein each of said plurality of pixels detects the presence or absence of an address event.

7. A solid-state imaging device according to claim 1, wherein said capacitive element is a MOS (Metal-Oxide-Semiconductor) capacitor, a MIM (Metal-Insulator-Metal) capacitor, or an inter-wiring capacitor.

8. A solid-state imaging device comprising a plurality of pixels, each of which is provided with a P-type current source transistor whose source is connected to a power supply voltage and which supplies a predetermined drain-source current, a capacitance element inserted between the gate of the current source transistor and the power supply voltage, and a sample-and-hold switch which samples and holds a predetermined bias voltage in the capacitance element during a period when the drain-source current is not supplied.

9. A solid-state imaging device comprising: a plurality of pixels, each of which is provided with a current source transistor whose source is connected to a ground node and which supplies a predetermined drain-source current; a capacitance element having one end commonly connected to the gate of each of the current source transistors of the plurality of pixels; and a sample-and-hold switch which samples and holds a predetermined bias voltage in the capacitance element during a period when the drain-source current is not supplied.

10. A photodetector comprising: a plurality of pixels, each of which is provided with a current source transistor whose source is connected to a ground node and which supplies a predetermined drain-source current; a capacitance element whose one end is connected to the gate of the current source transistor; a switch circuit that opens and closes a path between an amplifying transistor and the current source transistor in accordance with a predetermined control signal; and a sample-and-hold transistor whose polarity is opposite to that of the transistor in the switch circuit and which samples and holds a predetermined bias voltage in the capacitance element in accordance with the control signal; and a signal processing circuit that processes pixel signals from each of the plurality of pixels.

11. A method for controlling a solid-state imaging device, comprising: a step of: a current source transistor, the source of which is connected to a ground node, supplies a predetermined drain-source current; a step of: a switch circuit opening and closing a path between an amplifying transistor and the current source transistor in accordance with a predetermined control signal; and a step of: a sample-and-hold switch, the polarity of which is different from that of the transistor in the switch circuit, sampling and holding a predetermined bias voltage in a capacitance element, one end of which is connected to the gate of the current source transistor, in accordance with the control signal.

Images