Multilayer ceramic electronic component

Abstract

The present invention provides a multilayer ceramic electronic component that is capable of reducing ESR while suppressing the occurrence of cracks in a laminate.　Provided is a multilayer ceramic capacitor 1 comprising a laminate 10 and an external electrode 40, wherein the external electrode 40 has a conductive resin layer 60 and a plating layer 70 that is disposed on the conductive resin layer 60, the conductive resin layer 60 contains a metal filler F and a resin part R, the metal filler F contains a spherical-segment-shaped filler CF, and a cut surface CP of the spherical-segment-shaped filler CF is disposed at the boundary B between the conductive resin layer 60 and the plating layer 70.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] In recent years, multilayer ceramic capacitors as multilayer ceramic electronic components have been required to be durable in harsh environments, such as those exposed to bending stress due to thermal expansion. To address this demand, a technique using a thermosetting conductive resin paste for the external electrodes of a multilayer ceramic capacitor has been known. Patent Document 1 (JP-A-2003-102666) describes this type of technique. Patent Document 1 (JP-A-2003-1026666) describes a multilayer ceramic capacitor having external electrodes with a layered structure in which an electrode layer formed by applying a conductive paste by dipping and baking the paste, a conductive epoxy-based thermosetting resin layer, a nickel-plated layer, and a tin-based layer are sequentially laminated.

[0003] Japanese Patent Application Publication No. 11-162771

[0004] The multilayer ceramic capacitor of Patent Document 1 can suppress the occurrence of cracks in the laminate by sacrificial fracture of the resin layer and stress relaxation due to deformation. However, a challenge with multilayer ceramic capacitors having such resin layers is reducing the ESR.

[0005] An object of the present invention is to provide a multilayer ceramic electronic component that can reduce ESR while suppressing the occurrence of cracks in the laminate.

[0006] A multilayer ceramic electronic component according to the present invention is a multilayer ceramic electronic component comprising: a laminate including a plurality of laminated ceramic layers and a plurality of internal conductor layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height direction and the width direction; a first external electrode arranged on the first end surface; and a second external electrode arranged on the second end surface, wherein the first external electrode and the second external electrode have a conductive resin layer and a plating layer arranged on the conductive resin layer, the conductive resin layer including a metal filler and a resin portion, the metal filler including a spherical depletion-shaped filler, and a cut surface of the spherical depletion-shaped filler being arranged at the boundary between the conductive resin layer and the plating layer.

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can reduce ESR while suppressing the occurrence of cracks in the laminate.

[0008] 1 is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 1; FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 2; FIG. 4 is a cross-sectional view taken along line IV-IV of the multilayer ceramic capacitor shown in FIG. 2; FIG. 5 is an enlarged view of an external electrode cross section at part V of the multilayer ceramic capacitor shown in FIG. 2; FIG. 6 is a schematic diagram showing an example of the configuration of a multilayer ceramic capacitor with a double structure; FIG. 7 is a schematic diagram showing an example of the configuration of a multilayer ceramic capacitor with a triple structure; and FIG. 8 is a schematic diagram showing an example of the configuration of a multilayer ceramic capacitor with a quadruple structure.

[0009] <Embodiment> A multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to one embodiment of the present disclosure will now be described with reference to Figs. 1 to 4. Fig. 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. Fig. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 of Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor 1 of Fig. 2. Fig. 4 is a cross-sectional view taken along line IV-IV of the multilayer ceramic capacitor 1 of Fig. 2.

[0010] The drawings may be drawn in a simplified schematic form to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match those described in the specification. Furthermore, components described in the specification may be omitted from the drawings, or the number of components may be omitted. For example, the number of internal electrode layers shown in Figures 2 and 3 is 10 for the sake of convenience, but this does not indicate the actual number of internal electrode layers 30. Terms used in the present invention that specify shapes and geometric conditions, as well as their degrees of similarity, such as "parallel," "orthogonal," and "identical," as well as values ​​of length and angle, are not limited to their strict meanings but are interpreted to include a range within which similar functions can be expected.

[0011] The multilayer ceramic capacitor 1 includes a laminate 10 and external electrodes 40 .

[0012] 1 to 4 show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T as the height direction of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as the LT cross section. The cross section shown in FIG. 3 is also referred to as the WT cross section. The cross section shown in FIG. 4 is also referred to as the LW cross section.

[0013] As shown in Figures 1 to 4, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in a stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that is perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that is perpendicular to the stacking direction T and the width direction W.

[0014] As shown in FIG. 1 , the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness or the like may be formed on part or all of the surfaces constituting the laminate 10.

[0015] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, the T dimension is preferably 0.1 mm or more and 10 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0016] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first outer layer portion 12A as a first main surface side outer layer portion and a second outer layer portion 12B as a second outer layer portion arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0017] The internal layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The internal layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 in the stacking direction T to the internal electrode layer 30 located closest to the second main surface TS2. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0018] The dielectric layers 20 are made of a dielectric material, such as BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ The dielectric material may be a dielectric ceramic containing components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc., added to the above main components.

[0019] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 15 μm or less. The number of laminated dielectric layers 20 is preferably 10 or more and 700 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers in the inner layer portion 11 and the dielectric layers in the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0020] The multiple internal electrode layers 30 include first internal electrode layers 31 as multiple first internal conductor layers and second internal electrode layers 32 as multiple second internal conductor layers. The multiple first internal electrode layers 31 are arranged on the multiple dielectric layers 20. The multiple second internal electrode layers 32 are arranged on the multiple dielectric layers 20. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10, with the dielectric layers 20 interposed between them. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20 therebetween.

[0021] The first internal electrode layer 31 has a first opposing portion 31A opposing the second internal electrode layer 32, and a first lead portion 31B led from the first opposing portion 31A to the first end face LS1. The first lead portion 31B is exposed at the first end face LS1.

[0022] The second internal electrode layer 32 has a second opposing portion 32A opposing the first internal electrode layer 31 and a second lead portion 32B led from the second opposing portion 32A to the second end face LS2. The second lead portion 32B is exposed at the second end face LS2.

[0023] In this embodiment, the first opposing portion 31A and the second opposing portion 32A face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0024] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first draw-out portion 31B and the second draw-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.

[0025] The width direction W of the first opposing portion 31A and the width direction W of the first lead portion 31B may be the same, or one of the dimensions may be smaller. The width direction W of the second opposing portion 32A and the width direction W of the second lead portion 32B may be the same, or one of the dimensions may be smaller.

[0026] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 10 or more and 700 or less.

[0028] The first main surface side outer layer portion 12A is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12A is an assembly of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface side outer layer portion 12A may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0029] The second main surface side outer layer portion 12B is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 12B is an assembly of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface side outer layer portion 12B may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0030] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. Fig. 4 shows the range of the counter electrode portion 11E in the width direction W and the length direction L. The counter electrode portion 11E is also called the effective portion of the capacitor.

[0031] The laminate 10 has side surface outer layer portions. The side surface outer layer portions include a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side surface WS1. The second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side surface WS2. Figures 3 and 4 show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2. The side surface outer layer portions are also referred to as W gaps or side gaps.

[0032] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first end surface LS1. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second end surface LS2. Figures 2 and 4 show the ranges in the length direction L of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2. The end surface side outer layer portion is also referred to as an L gap or end gap.

[0033] The external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side and a second external electrode 40B arranged on the second end face LS2 side.

[0034] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] As described above, in the laminate 10, capacitance is formed by the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 facing each other via the dielectric layer 20. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0037] The layers constituting the first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to a WT cross section at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, when there is no need to particularly distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.

[0038] The first external electrode 40A has a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A. The first plating layer 70A has a first Ni plating layer 71A as a lower plating layer and a first Sn plating layer 72A as an upper plating layer.

[0039] The second external electrode 40B has a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B. The second plating layer 70B has a second Ni plating layer 71B as a lower plating layer and a second Sn plating layer 72B as an upper plating layer.

[0040] As shown in FIGS. 2 and 4, the first Ni plating layer 71A has a first end surface side Ni plating layer 71A1 and a first side surface side Ni plating layer 71A2.

[0041] As shown in FIGS. 2 and 4, the second Ni plating layer 71B has a second end surface side Ni plating layer 71B1 and a second side surface side Ni plating layer 71B2.

[0042] In addition, when there is no need to particularly distinguish between the first base electrode layer 50A and the second base electrode layer 50B, the first base electrode layer 50A and the second base electrode layer 50B may be collectively referred to as the base electrode layer 50.

[0043] Furthermore, when there is no need to particularly distinguish between the first conductive resin layer 60A and the second conductive resin layer 60B, the first conductive resin layer 60A and the second conductive resin layer 60B may be collectively referred to as the conductive resin layer 60.

[0044] Furthermore, when there is no need to particularly distinguish between the first plating layer 70A and the second plating layer 70B, the first plating layer 70A and the second plating layer 70B may be collectively referred to as plating layer 70.

[0045] Furthermore, when there is no need to particularly distinguish between the first Ni plating layer 71A and the second Ni plating layer 71B, the first Ni plating layer 71A and the second Ni plating layer 71B may be collectively referred to as the Ni plating layer 71.

[0046] Furthermore, when there is no need to particularly distinguish between the first Sn plating layer 72A and the second Sn plating layer 72B, the first Sn plating layer 72A and the second Sn plating layer 72B may be collectively referred to as the Sn plating layer 72.

[0047] Furthermore, when it is not necessary to particularly distinguish between the first end face LS1 and the second end face LS2, the first end face LS1 and the second end face LS2 may be collectively referred to as the end face LS. Furthermore, when it is not necessary to particularly distinguish between the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B, the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B may be collectively referred to as the outer layer portion 12.

[0048] Therefore, the external electrode 40 can be said to have a base electrode layer 50 arranged on the first end face LS1 and the second end face LS2, a conductive resin layer 60 arranged on the base electrode layer 50, and a plating layer 70 arranged on the conductive resin layer 60.

[0049] The base electrode layer 50 includes a first base electrode layer 50A and a second base electrode layer 50B.

[0050] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. The first base electrode layer 50A may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0051] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. The second base electrode layer 50B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0052] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. This improves the adhesion between the laminate 10 and the base electrode layers. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The presence of a glass component can help sinter the metal component in the base electrode layer and promote sintering. The ceramic component may be the same type of ceramic material as that of the dielectric layer 20, or a different type of ceramic material. The ceramic component may be, for example, BaTiO ３ , CaTiO ３, (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ It includes at least one selected from the following:

[0053] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate and baking it. The baked layer may be formed by simultaneously firing a laminated chip having internal electrodes and a dielectric layer with a conductive paste applied to the laminated chip, or by simultaneously firing a laminated chip having internal electrodes and a dielectric layer to obtain a laminate and then applying a conductive paste to the laminate and baking it. When simultaneously firing a laminated chip having internal electrodes and a dielectric layer with a conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a layer containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be formed in multiple layers.

[0054] The longitudinal thickness of the first base electrode layer 50A located on the first end surface LS1 is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.

[0055] The longitudinal thickness of the second base electrode layer 50B located on the second end surface LS2 is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.

[0056] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction T of the first base electrode layer 50A provided on this portion is preferably, for example, approximately 4 μm or more and 40 μm or less at the center in the length direction L and width direction W of the first base electrode layer 50A provided on this portion.

[0057] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness in the width direction W of the first base electrode layer 50A provided on this portion is, for example, approximately 4 μm or more and 40 μm or less at the center of the length direction L and stacking direction T of the first base electrode layer 50A provided on this portion.

[0058] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction T of the second base electrode layer 50B provided on this portion is preferably, for example, approximately 4 μm or more and 40 μm or less at the center in the length direction L and width direction W of the second base electrode layer 50B provided on this portion.

[0059] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness in the width direction W of the second base electrode layer 50B provided on this portion is, for example, approximately 4 μm or more and 40 μm or less at the center in the length direction L and stacking direction T of the second base electrode layer 50B provided on this portion.

[0060] The external electrode 40 has a conductive resin layer 60 containing a resin component and a metal component that is disposed on the base electrode layer 50. The conductive resin layer 60 has a first conductive resin layer 60A and a second conductive resin layer 60B.

[0061] The first conductive resin layer 60A is disposed so as to cover the first base electrode layer 50A. In this embodiment, the first conductive resin layer 60A is disposed so as to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. Preferably, the end of the first conductive resin layer 60A is in contact with the laminate 10. The end of the first conductive resin layer 60A refers to a portion of the first conductive resin layer 60A that is closer to the second end surface LS2 than the first base electrode layer 50A in the longitudinal direction L. The second conductive resin layer 60B is disposed so as to cover the second base electrode layer 50B. In this embodiment, the second conductive resin layer 60B is disposed so as to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. Preferably, an end of the second conductive resin layer 60B is in contact with the laminate 10. The end of the second conductive resin layer 60B refers to a portion of the second conductive resin layer 60B that is closer to the first end surface LS1 than the second base electrode layer 50B in the longitudinal direction L.

[0062] The thickness in the longitudinal direction L of the first conductive resin layer 60A located on the first end face LS1 side is preferably, for example, approximately 10 μm or more and 200 μm or less at the center of the stacking direction T and width direction W of the first conductive resin layer 60A.

[0063] The thickness in the longitudinal direction L of the second conductive resin layer 60B located on the second end face LS2 side is preferably, for example, approximately 10 μm or more and 200 μm or less at the center of the stacking direction T and width direction W of the second conductive resin layer 60B.

[0064] When the first conductive resin layer 60A is provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness in the stacking direction T of the first conductive resin layer 60A provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and width direction W of the first conductive resin layer 60A provided on this portion.

[0065] When the first conductive resin layer 60A is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the thickness in the width direction W of the first conductive resin layer 60A provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the first conductive resin layer 60A provided on this portion.

[0066] When the second conductive resin layer 60B is provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness in the stacking direction T of the second conductive resin layer 60B provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and width direction W of the second conductive resin layer 60B provided on this portion.

[0067] When the second conductive resin layer 60B is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the thickness in the width direction W of the second conductive resin layer 60B provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the second conductive resin layer 60B provided on this portion.

[0068] As shown in Fig. 5, the conductive resin layer 60 is disposed on the base electrode layer 50. A plating layer 70 is disposed so as to cover the conductive resin layer 60. The plating layer 70 includes a Ni plating layer 71 and a Sn plating layer 72. Fig. 5 is an enlarged view of a cross section of the external electrode at portion V of the multilayer ceramic capacitor 1 shown in Fig. 2. In Fig. 5, the stacking direction T is oriented left-to-right on the paper, and the length direction L is oriented up-to-down on the paper.

[0069] As shown in FIG. 5, the conductive resin layer 60 has a resin portion R and conductive fillers F as metal fillers dispersed in the resin portion R.

[0070] The resin portion R of the conductive resin layer 60 may contain at least one selected from various known thermosetting resins, such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is one of the most suitable resins, due to its excellent heat resistance, moisture resistance, and adhesion. Furthermore, the resin portion R of the conductive resin layer 60 preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0071] Because the conductive resin layer 60 includes the resin portion R, it is more flexible than the base electrode layer 50, which is made of, for example, a plating film or a fired product of a metal component and a glass component. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer 60 functions as a buffer layer. Therefore, the conductive resin layer 60 suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0072] The conductive filler F is dispersed in a substantially uniform distribution within the resin portion R. The conductive filler F is mainly responsible for the electrical conductivity of the conductive resin layer 60. Specifically, when multiple conductive fillers F come into contact with each other, an electrical path is formed within the conductive resin layer 60, and electrical conductivity is established between the base electrode layer 50 and the plating layer 70.

[0073] The metal constituting the conductive filler F may be Ag alone, an alloy containing Ag, or a metal powder with Ag coated on its surface. Ag has the lowest resistivity of all metals, making it suitable as an electrode material. Furthermore, because Ag is a noble metal, it is resistant to oxidation and highly weather-resistant. Therefore, Ag metal powder is suitable as a conductive filler. Furthermore, when using a metal powder with Ag coated on its surface, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder containing any of these metal powders.

[0074] Furthermore, the conductive filler F may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive filler F may be a metal powder in which the surface of the metal powder is coated with Sn, Ni, or Cu. When using a metal powder in which the surface of the metal powder is coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0075] The metal constituting the conductive filler F in this embodiment is preferably Cu, Ag, Sn, or a mixture thereof. In particular, it is preferable that Sn is included as the metal constituting the conductive filler F. This makes it easier to form an intermetallic compound of Sn and Ni, which will be described later, between the conductive filler F and the Ni plating layer 71.

[0076] The conductive filler F may be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder. Here, the spherical particles of the conductive filler F may include those that are not perfectly spherical, and may include, for example, those having a length ratio of the major axis to the minor axis (major axis / minor axis) of 1.45 or less. The flat particles of the conductive filler F refer to particles having a flat and elongated shape, and are not particularly limited, but may, for example, have a length ratio of the major axis to the minor axis (major axis / minor axis) of 1.95 or more.

[0077] The average particle size of the conductive filler F may be, for example, 0.3 μm or more and 10 μm or less, more preferably 1 μm or more and 8 μm or less. When the conductive filler F is flat, the average major axis diameter of the planar portion of the conductive filler F may be, for example, 2 μm or more and 10 μm or less, more preferably 5 μm or more and 8 μm or less. When the conductive filler F is flat, the average minor axis diameter of the planar portion of the conductive filler F may be, for example, 0.3 μm or more and 3 μm or less, more preferably 0.5 μm or more and 1 μm or less.

[0078] The conductive filler F of this embodiment includes spherical fillers SF and deutzia-shaped fillers CF. The deutzia-shaped fillers CF are fillers having a substantially flat cut surface CP formed by cutting a portion of a sphere. The deutzia-shaped fillers CF may be, for example, hemispherical fillers whose cut surface CP passes through the approximate center of the sphere. However, this is not limiting, and the cut surface CP of the deutzia-shaped fillers CF does not have to pass through the center of the sphere.

[0079] 5 , the deformed filler CF is disposed near the boundary B between the conductive resin layer 60 and the plating layer 70. The deformed filler CF is disposed so that the cut surface CP faces the boundary B between the conductive resin layer 60 and the plating layer 70. Here, the boundary B is the region between the conductive resin layer 60 and the plating layer 70. The surface of the conductive resin layer 60 on the boundary B side includes the surface of the resin portion R and the surface of the conductive filler F.

[0080] The cut surface CP of the spherically-defective filler CF has a shape that conforms to the boundary B, as shown in FIG. 5 . The cut surface CP of the spherically-defective filler CF is in contact with the plating layer 70. This makes it possible to increase the contact area between the conductive filler F and the plating layer 70 at the boundary B. Furthermore, compared to when spherical fillers SF are disposed near the boundary B, the surface of the conductive resin layer 60 on the boundary B side can be made smoother. The surface of the conductive resin layer 60 on the boundary B side may be smoother than the surface of the conductive resin layer 60 on the laminate 10 side.

[0081] This structure improves the electrical bonding between the conductive filler F and the plating layer 70. Furthermore, when an external mechanical force is applied, the surface of the conductive resin layer 60 on the boundary portion B side is smooth, so that the conductive resin layer 60 and the plating layer 70 can be peeled off and quickly cause interfacial failure between the conductive resin layer 60 and the plating layer 70. This makes it possible to suppress the occurrence of cracks in the laminate 10, and improve the mechanical strength of the multilayer ceramic capacitor 1.

[0082] As shown in Fig. 5, the conductive resin layer 60 of this embodiment includes a plurality of spherical defect-shaped fillers CF as the conductive filler F. For example, the conductive resin layer 60 includes a first spherical defect-shaped filler CF1 and a second spherical defect-shaped filler CF2 arranged adjacent to the first spherical defect-shaped filler CF1. In the LT cross section shown in Fig. 5, the distance L1 between the contact portion between the first spherical defect-shaped filler CF1 and the plating layer 70 and the contact portion between the second spherical defect-shaped filler CF2 and the plating layer 70 may be shorter than the thickness L2 of the dielectric layer 20. This can further improve the electrical connection between the conductive filler F and the plating layer 70.

[0083] 5 , in one or more, preferably a plurality of, spherical detent-shaped fillers CF, the distance L3 of the contact portion between the spherical detent-shaped filler CF and the plating layer 70 may be longer than the distance L4 of the contact portion between the end of the internal electrode layer 30 and the base electrode layer 50. This can further improve the electrical connection between the conductive filler F and the plating layer 70.

[0084] 5 , the total distance L3 between the contact portions of the plurality of spherically-defect-shaped fillers CF and the plating layer 70 may be longer than the total distance L4 between the contact portions of the ends of the plurality of internal electrode layers 30 and the base electrode layer 50 constituting the external electrode 40. This can further improve the electrical connection between the conductive fillers F and the plating layer 70. Note that, in the LT cross section shown in FIG. 5 , the total distance between the contact portions of the plurality of conductive fillers F, including the spherically-defect-shaped fillers CF, and the plating layer 70 may be longer than the total distance between the contact portions of the plurality of conductive fillers F and the base electrode layer 50 constituting the external electrode 40.

[0085] In the LT cross section shown in FIG. 5 , the spherically-defected fillers CF may be unevenly distributed in the conductive resin layer 60, with a distribution different from that of the spherical fillers SF. The abundance ratio of the spherically-defected fillers CF to the resin portion R in the conductive resin layer 60 may be higher on the plating layer 70 side of the conductive resin layer 60 than on the laminate 10 side of the conductive resin layer 60. Furthermore, the abundance ratio of the spherically-defected fillers CF to the spherical fillers SF in the conductive resin layer 60 may be higher on the plating layer 70 side of the conductive resin layer 60 than on the laminate 10 side of the conductive resin layer 60. This can further improve the electrical connection between the conductive filler F and the plating layer 70. In the LT cross section shown in FIG. 5 , the number of the spherically-defected fillers CF arranged with their cut surface CP facing the plating layer 70 side in the conductive resin layer 60 may be greater than the number of the spherically-defected fillers CF arranged with their cut surface CP facing the laminate 10 side.

[0086] The boundary portion B between the conductive resin layer 60 and the plating layer 70 will be further described. The multilayer ceramic capacitor 1 of this embodiment may have an intermetallic compound or a solid solution between the conductive filler F and the plating layer 70 at the boundary portion B. The multilayer ceramic capacitor 1 of this embodiment has an intermediate metal portion IC as an intermetallic compound or a solid solution between the cut surface CP of the spherically deformed filler CF present at the boundary portion B and the plating layer 70. The intermediate metal portion IC may be formed in a layer shape at the boundary portion B.

[0087] When the intermediate metal portion IC is an intermetallic compound, the intermediate metal portion IC may be an intermetallic compound composed of a metal constituting the spherical detent-shaped fillers CF as the conductive filler F and a metal constituting the plating layer 70. For example, when the plating layer 70 includes a Ni plating layer 71, the intermediate metal portion IC may be an intermetallic compound composed of a metal constituting the spherical detent-shaped fillers CF as the conductive filler F and Ni. For example, when the spherical detent-shaped fillers CF as the conductive filler F include Ag and the plating layer 70 includes a Ni plating layer 71, the intermediate metal portion IC may be an intermetallic compound of Ag and Ni. For example, when the spherical detent-shaped fillers CF as the conductive filler F include Cu and the plating layer 70 includes a Ni plating layer 71, the intermediate metal portion IC may be an intermetallic compound of Cu and Ni. For example, when the spherical detent-shaped fillers CF as the conductive filler F include Sn and the plating layer 70 includes a Ni plating layer 71, the intermediate metal portion IC may be an intermetallic compound of Sn and Ni.

[0088] When the intermediate metal portion IC is a solid solution, the intermediate metal portion IC may be a solid solution in which the metal constituting the spherically deformed filler CF as the conductive filler F and the metal constituting the plating layer 70 are mixed together to form a uniform solid phase. For example, when the plating layer 70 includes a Ni plating layer 71, the intermediate metal portion IC may be a solid solution composed of the metal constituting the spherically deformed filler CF as the conductive filler F and Ni. For example, when the spherically deformed filler CF as the conductive filler F includes Ag and the plating layer 70 includes a Ni plating layer 71, the intermediate metal portion IC may be a solid solution of Ag and Ni. For example, when the spherically deformed filler CF as the conductive filler F includes Cu and the plating layer 70 includes a Ni plating layer 71, the intermediate metal portion IC may be a solid solution of Cu and Ni. For example, when the spherically deformed filler CF as the conductive filler F contains Sn and the plating layer 70 contains a Ni plating layer 71, the intermediate metal portion IC may be a solid solution of Sn and Ni.

[0089] This can further improve the bonding between the conductive filler F and the plating layer 70, thereby reducing the ESR of the multilayer ceramic capacitor 1.

[0090] The plating layer 70 includes a first plating layer 70A and a second plating layer 70B.

[0091] The first plating layer 70A is disposed so as to cover the first conductive resin layer 60A. In this embodiment, the first plating layer 70A is disposed so as to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0092] The second plating layer 70B is disposed so as to cover the second conductive resin layer 60B. In this embodiment, the second plating layer 70B is disposed so as to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0093] The plating layer 70 preferably has a two-layer structure of a Ni plating layer 71 and a Sn plating layer 72. A first Sn plating layer 72A is preferably disposed on the first Ni plating layer 71A, and a second Sn plating layer 72B is preferably disposed on the second Ni plating layer 71B. The Ni plating layer 71 prevents the base electrode layer 50 and the conductive resin layer 60 from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer 72 improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating the mounting of the multilayer ceramic capacitor 1.

[0094] The thickness of each of the first Ni plating layer 71A and the first Sn plating layer 72A is preferably 1 μm or more and 15 μm or less.

[0095] The thickness of each of the second Ni plating layer 71B and the second Sn plating layer 72B is preferably 1 μm or more and 15 μm or less.

[0096] If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 in the stacking direction is defined as T, then the T dimension is preferably 0.1 mm or more and 10 mm or less. The widthwise dimension of the multilayer ceramic capacitor 1 is defined as W. The W dimension is preferably 0.1 mm or more and 10 mm or less.

[0097] <Measurement Methods> Next, various measurement methods, including a method for checking the shape and arrangement of the conductive filler F, will be described.

[0098] First, the multilayer ceramic capacitor 1 is embedded in resin and polished from the first side surface WS1 or the second side surface WS2 down to a position halfway along the width direction W. This exposes the LT cross section at the center of the multilayer ceramic capacitor 1 in the width direction W. Next, the portion of the LT cross section exposed by polishing, including the external electrodes 40, is observed with a metallurgical microscope with a 10x eyepiece and a 100x objective lens to confirm the shape and arrangement of the conductive filler F. Similarly, by observing with a metallurgical microscope, the distribution of the conductive filler F and the presence or absence of intermetallic compounds and solid solutions can be confirmed. The presence or absence of intermetallic compounds and solid solutions can also be confirmed based on SEM-EDX elemental mapping images based on SEM images or quantitative analysis of characteristic X-ray spectra.

[0099] Similarly, by observing the portion of the LT cross section exposed by polishing, including the external electrode 40, with a metallurgical microscope or SEM, various distances, the average particle diameter of the conductive filler F, and the surface smoothness of the conductive resin layer can be measured. Image analysis software (e.g., WinROOF manufactured by Mitani Shoji Co., Ltd.) can be used to measure various distances, average particle diameter, etc. Furthermore, the surface roughness Ra, which represents the surface smoothness of the conductive resin layer 60, can be calculated by extracting the surface contour using image analysis software. The location where these measurements are performed can be the main surface side portion of the external electrode 40 that contacts the inner layer portion 11 of the laminate 10, as shown in FIG. 5 .

[0100] <Manufacturing Method> Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The multilayer ceramic capacitor 1 of this embodiment may be manufactured by any method as long as it satisfies the above-described requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0101] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0102] On the dielectric sheets, the conductive paste for the internal electrode layers 30 is printed in a predetermined pattern by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0103] A predetermined number of dielectric sheets on which no pattern of internal electrode layers is printed are stacked to form a portion that will become the first main surface side outer layer portion 12A on the first main surface TS1 side. A dielectric sheet on which the pattern of the first internal electrode layer 31 and a dielectric sheet on which the pattern of the second internal electrode layer 32 are printed are stacked in order on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the pattern of the internal electrode layers is not printed are stacked on top of this portion that will become the internal layer portion 11 to form a portion that will become the second main surface side outer layer portion 12B on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0104] The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0105] The laminated block is cut to a predetermined size to cut out laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0106] The laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.

[0107] A conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer 50. The temperature of the baking process at this time is preferably 700°C or higher and 950°C or lower.

[0108] In this embodiment, dipping is performed so that the portion that will become the first base electrode layer 50A extends from the first end surface LS1 of the laminate 10 to portions of the first main surface TS1 and the second main surface TS2. Dipping is also performed so that the portion that will become the second base electrode layer 50B extends from the second end surface LS2 to portions of the first main surface TS1 and the second main surface TS2. At the same time, dipping is preferably performed so that the portion that will become the first base electrode layer 50A extends to portions of the first side surface WS1 and the second side surface WS2 of the laminate 10. Dipping is also preferably performed so that the portion that will become the second base electrode layer 50B extends to portions of the first side surface WS1 and the second side surface WS2 of the laminate 10.

[0109] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, it is preferable to form the baked layer by adding a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are baked simultaneously to form the laminate 10 with the baked layer formed.

[0110] Next, the conductive resin layer 60 is formed. In this embodiment, the conductive resin layer 60 is formed on the surface of the base electrode layer 50.

[0111] First, a conductive resin paste is prepared by dispersing conductive fillers in a thermosetting resin as a base resin for the resin portion. This conductive resin paste is produced by stirring and mixing the thermosetting resin and the conductive fillers. Therefore, the conductive fillers are uniformly dispersed within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, Ag metal powder.

[0112] Thereafter, a conductive resin paste is applied onto the base electrode layer 50 by a dipping method, and a heat treatment is performed at a temperature of 200° C. to 550° C. This causes the resin portion to be thermally hardened, forming the conductive resin layer 60. The atmosphere during this heat treatment is N ２ In order to prevent the resin from scattering and the various metal components from being oxidized, the oxygen concentration is preferably kept at 100 ppm or less.

[0113] In this embodiment, dipping is performed so that the portion that will become the first conductive resin layer 60A extends from the first end surface LS1 of the laminate 10 to portions of the first main surface TS1 and the second main surface TS2. Dipping is also performed so that the portion that will become the second conductive resin layer 60B extends from the second end surface LS2 of the laminate 10 to portions of the first main surface TS1 and the second main surface TS2. At the same time, dipping is preferably performed so that the portion that will become the first conductive resin layer 60A extends to portions of the first side surface WS1 and the second side surface WS2 of the laminate 10. Dipping is also preferably performed so that the portion that will become the second conductive resin layer 60B extends to portions of the first side surface WS1 and the second side surface WS2. To smooth the surface of the conductive resin layer 60, an additional paste containing a metal component and a resin component may be applied and cured to form the conductive resin layer 60.

[0114] Next, the surface of the conductive resin layer 60 is polished to make it smooth. Examples of polishing methods include barrel polishing and sandblasting. Either dry or wet polishing may be used, but dry barrel polishing is preferably used. At this time, by adjusting the polishing conditions, including the hardness and particle shape of the abrasive used in the barrel polishing, it is possible to form a cut surface CP of the spherically deformed filler at the boundary between the conductive resin layer and the plating layer.

[0115] Thereafter, a plating layer 70 is formed on the surface of the conductive resin layer 60. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed sequentially using an electrolytic plating method. As the plating method, for example, barrel plating is preferably used.

[0116] By the above manufacturing method, the multilayer ceramic capacitor 1 is manufactured.

[0117] The multilayer ceramic capacitor 1 of this embodiment has the following advantages.

[0118] In recent years, ceramic electronic components, such as multilayer ceramic capacitors, have come to be used in harsher environments than before. For example, electronic components used in mobile devices such as mobile phones and portable music players are required to be able to withstand shocks when dropped. Specifically, it is necessary to ensure that the electronic components do not fall off the mounting board or crack even when subjected to a drop shock.

[0119] Furthermore, electronic components used in in-vehicle devices such as ECUs (Electronic Control Units) are required to withstand the impact of thermal cycles. Specifically, they must be able to withstand the bending stresses that occur when a mounting board expands and contracts due to thermal cycles, preventing cracks from occurring in the electronic components.

[0120] In response to this, the use of thermosetting conductive resin paste for the external electrodes of ceramic electronic components has been proposed as a measure to prevent cracks from occurring in the main body of the ceramic electronic component even in harsh environments. For example, an epoxy-based thermosetting resin layer is formed between a conventional electrode layer and a Ni-plated layer.

[0121] In such a configuration, when stress is generated due to an impact when dropped or deflection stress is generated due to the thermal expansion and contraction of the mounting substrate caused by a thermal cycle, the stress transmitted to the mounting substrate due to distortion of the mounting substrate is released by the epoxy-based thermosetting resin layer, thereby preventing cracks from occurring in the ceramic electronic component body.

[0122] However, reducing the ESR of multilayer ceramic capacitors with such conductive resin layers is a challenge. The resistance and impedance of components constituting an electronic circuit are very important factors in the operation of the circuit. Multilayer ceramic electronic components are particularly susceptible to high resistance and impedance due to the large influence of contact resistance at the interfaces between the constituent materials.

[0123] In particular, in designs that use a conductive resin layer for the external electrodes, it is necessary to ensure contact between the metal filler particles dispersed in the resin and the plating layer. External electrode configurations that use a conductive resin layer tend to be more difficult to establish electrical continuity and have higher resistance than external electrode configurations that do not use a conductive resin layer. Furthermore, if the metal filler particles and the plating layer are firmly bonded, interfacial breakdown is suppressed, which reduces the mechanical strength that is the objective of the conductive resin layer. In other words, in the design of a conductive resin layer, suppressing resistance and ensuring mechanical strength are in a trade-off relationship.

[0124] In the present disclosure, the metal filler F of the conductive resin layer 60 includes spherical detent fillers CF, and the spherical detent fillers CF are arranged so that their cut surfaces CP face the boundary B between the conductive resin layer 60 and the plating layer 70. This structure improves the electrical bonding between the conductive fillers F and the plating layer 70. Furthermore, when an external mechanical force is applied, the surface of the conductive resin layer 60 on the boundary B side is smooth, so that the conductive resin layer 60 and the plating layer 70 can peel off and quickly cause interfacial breakdown between the conductive resin layer 60 and the plating layer 70. This makes it possible to reduce the ESR while suppressing the occurrence of cracks in the laminate 10.

[0125] Furthermore, in the present disclosure, an intermetallic compound or solid solution is present between the metal filler present on the surface of the conductive resin layer 60 and the plating layer 70 covering the conductive resin layer 60. This can further improve the bonding between the conductive filler F and the plating layer 70, thereby reducing the ESR of the multilayer ceramic capacitor 1.

[0126] (1) The multilayer ceramic electronic component 1 (multilayer ceramic capacitor 1) according to this embodiment includes a laminate 10 including a plurality of laminated ceramic layers (dielectric layers 20) and a plurality of internal conductor layers (internal electrode layers 30), and having a first main surface TS1 and a second main surface TS2 facing each other in a height direction T (stacking direction T), a first side surface WS1 and a second side surface WS2 facing each other in a width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 facing each other in a length direction L perpendicular to the height direction T and the width direction W; The multilayer ceramic electronic component includes a first external electrode 40A arranged on the end face LS1 of the multilayer ceramic electronic component, and a second external electrode 40B arranged on the second end face LS2 of the multilayer ceramic electronic component, and the first external electrode 40A and the second external electrode 40B each have a conductive resin layer 60 and a plating layer 70 arranged on the conductive resin layer 60, and the conductive resin layer 60 includes a metal filler F and a resin portion R, and the metal filler F includes spherical detent-shaped fillers CF, and the cut surfaces CP of the spherical detent-shaped fillers CF are arranged at the boundary B between the conductive resin layer 60 and the plating layer 70. This makes it possible to provide a multilayer ceramic electronic component that can reduce ESR while suppressing the occurrence of cracks in the laminate.

[0127] (2) The multilayer ceramic capacitor 1 of this embodiment has an intermetallic compound or solid solution between the metal filler F present in the boundary portion B and the plating layer 70. This allows the ESR of the multilayer ceramic capacitor 1 to be further reduced.

[0128] (3) The conductive resin layer 60 of the multilayer ceramic capacitor 1 of this embodiment has, as the conductive filler F, first spherically deformed filler CF1 and second spherically deformed filler CF2 arranged in proximity to the first spherically deformed filler CF1, and in the LT cross-sectional view, the distance L1 between the contact portion between the first spherically deformed filler CF1 and the plating layer 70 and the contact portion between the second spherically deformed filler CF2 and the plating layer 70 is shorter than the thickness L2 of the dielectric layer 20. This further improves the electrical connection between the conductive filler F and the plating layer 70.

[0129] (4) The first external electrode 40A and the second external electrode 40B of the multilayer ceramic capacitor 1 of this embodiment include a base electrode layer 50 disposed between the laminate 10 and the conductive resin layer 60, and in the LT cross-sectional view, the distance L3 of the contact portion between one or more spherically-defect-shaped fillers CF and the plating layer 70 is longer than the distance L4 of the contact portion between the end of the internal electrode layer 30 and the base electrode layer 50. This further improves the electrical connection between the conductive fillers F and the plating layer 70.

[0130] (5) The first external electrode 40A and the second external electrode 40B of the multilayer ceramic capacitor 1 of this embodiment include a base electrode layer 50 disposed between the laminate 10 and the conductive resin layer 60, and the conductive resin layer 60 has a plurality of spherically deformed fillers CF as conductive fillers F, and in the LT cross-sectional view, the total distance L3 between the plurality of spherically deformed fillers CF and the plating layer 70 at their contact points is longer than the total distance L4 between the ends of the plurality of internal electrode layers 30 and the base electrode layer 50. This further improves the electrical connection between the conductive fillers F and the plating layer 70.

[0131] (6) The first external electrode 40A and the second external electrode 40B of the multilayer ceramic capacitor 1 of this embodiment include a base electrode layer 50 disposed between the laminate 10 and the conductive resin layer 60, and in the LT cross-sectional view, the total distance between the contact points of the plurality of conductive fillers F, including the spherically deformed fillers CF, and the plating layer 70 is longer than the total distance between the contact points of the plurality of conductive fillers F and the base electrode layer 50. This further improves the electrical connection between the conductive fillers F and the plating layer 70.

[0132] (7) In the multilayer ceramic capacitor of this embodiment, the abundance ratio of the spherically deformed fillers CF to the resin portion R in the conductive resin layer 60 is higher on the plating layer 70 side of the conductive resin layer 60 than on the laminate 10 side of the conductive resin layer 60. This further improves the electrical connection between the conductive fillers F and the plating layer 70.

[0133] (8) The conductive resin layer 60 of the multilayer ceramic capacitor 1 of this embodiment has a plurality of spherical fillers SF and a plurality of devoid fillers CF as the conductive filler F, and the abundance ratio of the devoid fillers CF to the spherical fillers SF in the conductive resin layer 60 is higher on the plating layer 70 side of the conductive resin layer 60 than on the laminate 10 side of the conductive resin layer 60. This further improves the electrical bonding between the conductive filler F and the plating layer 70.

[0134] (9) In the multilayer ceramic capacitor 1 of this embodiment, in the LT cross-sectional view, the number of spherically deformed fillers CF arranged with their cut surfaces CP facing the plating layer 70 in the conductive resin layer 60 is greater than the number of spherically deformed fillers CF arranged with their cut surfaces CP facing the laminate 10. This further improves the electrical connection between the conductive fillers F and the plating layer 70.

[0135] The configuration of the multilayer ceramic capacitor 1 is not limited to the configuration shown in Figures 1 to 4. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a double structure, a triple structure, or a quadruple structure as shown in Figures 6, 7, and 8.

[0136] The multilayer ceramic capacitor 1 shown in FIG. 6 is a double-structure multilayer ceramic capacitor 1, and includes, as the internal electrode layers 30, a first internal electrode layer 33, a second internal electrode layer 34, and a floating internal electrode layer 35 that is not extended to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in FIG. 7 is a triple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in FIG. 8 is a quadruple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as the floating internal electrode layers 35. By providing the floating internal electrode layers 35 as the internal electrode layers 30 in this way, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, thereby achieving a high withstand voltage for the multilayer ceramic capacitor 1. It goes without saying that the multilayer ceramic capacitor 1 of this embodiment may have a multi-row structure of four or more rows.

[0137] The multilayer ceramic capacitor 1 may be a two-terminal type having two external electrodes, or may be a multi-terminal type having a large number of external electrodes.

[0138] In the above-described embodiment, a multilayer ceramic capacitor in which the dielectric layers 20 made of a dielectric ceramic are used as ceramic layers has been described as an example of the multilayer ceramic electronic component. However, the multilayer ceramic electronic component of the present disclosure is not limited to this. For example, the ceramic electronic component of the present disclosure can also be applied to various multilayer ceramic electronic components, such as piezoelectric components using piezoelectric ceramics as ceramic layers, thermistors using semiconductor ceramics as ceramic layers, and inductors using magnetic ceramics as ceramic layers. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ceramics such as ferrite.

[0139] The present invention is not limited to the configurations of the above-described embodiments, and can be applied by making appropriate modifications within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0140] <1> A multilayer ceramic electronic component comprising: a laminate including a plurality of stacked ceramic layers and a plurality of internal conductor layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height and width directions; and first external electrodes arranged on the first end surfaces and second external electrodes arranged on the second end surfaces, wherein the first external electrodes and the second external electrodes have conductive resin layers and plating layers arranged on the conductive resin layers, the conductive resin layers including a metal filler and a resin portion, the metal filler including a spheroid-shaped filler, and a cross-section surface of the spheroid-shaped filler being arranged at a boundary between the conductive resin layer and the plating layer. <2> The multilayer ceramic electronic component according to claim 1, further comprising an intermetallic compound or a solid solution between the metal filler present at the boundary and the plating layer. <3> The multilayer ceramic electronic component according to <1> or <2>, wherein the conductive resin layer includes, as the metal filler, first deformed fillers and second deformed fillers arranged in proximity to the first deformed fillers, and in a cross section taken along a plane parallel to the length and height directions, a distance between a contact portion of the first deformed filler and the plating layer and a contact portion of the second deformed filler and the plating layer is shorter than a thickness of the ceramic layer. <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein the first external electrode and the second external electrode (40B) further include a base electrode layer arranged between the laminate and the conductive resin layer, and in a cross section taken along a plane parallel to the length and height directions, a distance between a contact portion of the one or more deformed fillers and the plating layer is longer than a distance between a contact portion of an end of the internal conductor layer and the base electrode layer.<5> The multilayer ceramic electronic component according to any one of <1> to <4>, wherein the first external electrode and the second external electrode include a base electrode layer disposed between the laminate and the conductive resin layer, the conductive resin layer having a plurality of the deuterium-shaped fillers as the metal filler, and in a cross section taken along a plane parallel to the length direction and the height direction, a total distance between contact portions of the plurality of the deuterium-shaped fillers and the plating layer is longer than a total distance between contact portions of ends of the plurality of the internal conductor layers and the base electrode layer. <6> The multilayer ceramic electronic component according to any one of <1> to <5>, wherein the first external electrode and the second external electrode include a base electrode layer disposed between the laminate and the conductive resin layer, and in a cross section taken along a plane parallel to the length direction and the height direction, a total distance between contact portions of the plurality of the metal fillers, including the deuterium-shaped fillers, and the plating layer is longer than a total distance between contact portions of the plurality of the metal fillers and the base electrode layer. <7> The multilayer ceramic electronic component according to any one of <1> to <6>, wherein the proportion of the depleted fillers relative to the resin portion in the conductive resin layer is higher on the plating layer side of the conductive resin layer than on the laminate side of the conductive resin layer. <8> The multilayer ceramic electronic component according to any one of <1> to <7>, wherein the conductive resin layer includes a plurality of spherical fillers and a plurality of the depleted fillers as the metal filler, and the proportion of the depleted fillers relative to the spherical fillers in the conductive resin layer is higher on the plating layer side of the conductive resin layer than on the laminate side of the conductive resin layer. <9> The multilayer ceramic electronic component according to any one of <1> to <8>, wherein, in a cross section taken along a plane parallel to the length direction and the height direction, the number of depleted fillers in the conductive resin layer whose cut surface faces the plating layer side is greater than the number of depleted fillers whose cut surface faces the laminate side.

[0141] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 10 Laminate 20 Dielectric layer (ceramic layer) 31 First internal electrode layer (first internal conductor layer) 32 Second internal electrode layer (second internal conductor layer) 40 External electrode 40A First external electrode 40B Second external electrode 50 Base electrode layer 60 Conductive resin layer 70 Plating layer B Boundary portion CF Spherical recessed filler CP Cut surface F Conductive filler (metal filler) R Resin portion T Stacking direction (height direction) TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface L Length direction LS1 First end face LS2 Second end face

Claims

1. A multilayer ceramic electronic component comprising: a laminate including a plurality of laminated ceramic layers and a plurality of internal conductor layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; a first external electrode arranged on the first end surface; and a second external electrode arranged on the second end surface, wherein the first external electrode and the second external electrode have a conductive resin layer and a plating layer arranged on the conductive resin layer, the conductive resin layer including a metal filler and a resin portion, the metal filler including a spherical depletion filler, and a cut surface of the spherical depletion filler being arranged at the boundary between the conductive resin layer and the plating layer.

2. The multilayer ceramic electronic component according to claim 1, wherein an intermetallic compound or solid solution exists between the metal filler present at the boundary and the plating layer.

3. A multilayer ceramic electronic component according to claim 1 or 2, wherein the conductive resin layer has, as the metal filler, a first deformed filler and a second deformed filler arranged in close proximity to the first deformed filler, and in a cross section parallel to the length and height directions, the distance between the contact portion of the first deformed filler with the plating layer and the contact portion of the second deformed filler with the plating layer is shorter than the thickness of the ceramic layer.

4. A multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the first external electrode and the second external electrode (40B) further include a base electrode layer disposed between the laminate and the conductive resin layer, and in a cross section on a plane parallel to the length and height directions, the distance between the contact point of one or more of the spherical notch-shaped fillers and the plating layer is longer than the distance between the contact point of the end of the internal conductor layer and the base electrode layer.

5. A multilayer ceramic electronic component according to any one of claims 1 to 4, wherein the first external electrode and the second external electrode include a base electrode layer disposed between the laminate and the conductive resin layer, the conductive resin layer having a plurality of the deformed fillers as the metal filler, and in a cross section taken along a plane parallel to the length and height directions, the total distance between the contact points of the plurality of the deformed fillers and the plating layer is longer than the total distance between the contact points of the ends of the plurality of internal conductor layers and the base electrode layer.

6. A multilayer ceramic electronic component according to any one of claims 1 to 5, wherein the first external electrode and the second external electrode include a base electrode layer disposed between the laminate and the conductive resin layer, and in a cross section parallel to the length and height directions, the total distance between the contact points of the plurality of metal fillers, including the spherically deformed fillers, and the plating layer is longer than the total distance between the contact points of the plurality of metal fillers and the base electrode layer.

7. A multilayer ceramic electronic component according to any one of claims 1 to 6, wherein the abundance ratio of the spherically deformed filler to the resin portion in the conductive resin layer is higher on the plating layer side of the conductive resin layer than on the laminate side of the conductive resin layer.

8. A multilayer ceramic electronic component according to any one of claims 1 to 7, wherein the conductive resin layer has a plurality of spherical fillers and a plurality of the devoid fillers as the metal filler, and the ratio of the devoid fillers to the spherical fillers in the conductive resin layer is higher on the plating layer side of the conductive resin layer than on the laminate side of the conductive resin layer.

9. A multilayer ceramic electronic component according to any one of claims 1 to 8, wherein, in a cross section taken along a plane parallel to the length and height directions, the number of spherical detent fillers in the conductive resin layer whose cut surfaces are arranged facing the plating layer is greater than the number of spherical detent fillers whose cut surfaces are arranged facing the laminate.

Images