Semiconductor device, power conversion device, and method for manufacturing semiconductor device

Abstract

The technology disclosed in the description of the present application is for enhancing bonding reliability via solder in a semiconductor device. A semiconductor device pertaining to the technology disclosed in the description of the present application is provided with: a semiconductor substrate; an electrode provided on a first surface, which is at least one main surface of the semiconductor substrate; and a plating layer provided on at least a part of a second surface, which is the surface of the electrode on the side opposite to the surface in contact with the first surface. An uneven part is formed on a side surface of the plating layer with respect to a third surface, which is a surface that is in contact with the second surface.

Description

Semiconductor device, power conversion device, and method of manufacturing the semiconductor device

[0001] The technology disclosed in the present specification relates to a semiconductor device.

[0002] Electroless plating is used as an electrode formation technology for semiconductor elements from the viewpoints of productivity and manufacturing costs. When mounting a front-to-back conductive semiconductor element on a module, the backside electrode of the semiconductor element is joined to the substrate by soldering, and the frontside electrode of the semiconductor element is mounted by wire bonding.

[0003] However, from the viewpoint of improving productivity and reducing manufacturing costs, a mounting method in which not only the backside electrodes of a semiconductor element but also the frontside electrodes are soldered has been used in recent years. The backside electrodes and the frontside electrodes of a semiconductor element are generally made of aluminum or an aluminum alloy, and in order to join these electrodes by soldering, it is necessary to plate a nickel film, a gold film, or the like on the top surface of the aluminum.

[0004] The reason for using plating technology is that it can form thick nickel films with high productivity. When joining by soldering, the nickel in the nickel film is reduced by an alloy reaction with the tin contained in the solder. Therefore, it is necessary to form a nickel film several micrometers thick in advance. However, when using vacuum film formation methods such as evaporation or sputtering, nickel films can only be obtained with a maximum thickness of about 1 micrometer, and attempting to obtain nickel films with thicknesses greater than this increases manufacturing costs.

[0005] One plating technique that reduces manufacturing costs is electroless plating using the zincate method. This method allows for selective formation of a plating layer only on the surface of aluminum or aluminum alloy (hereinafter also referred to as "aluminum electrode"), which is the electrode of a semiconductor element. Commonly used electroless plating methods include the palladium catalyst method and the zincate method.

[0006] In the palladium catalyst method, palladium is deposited on the surface of an aluminum electrode as a catalyst nucleus to form an electroless plating layer. The palladium catalyst method results in a small amount of etching of the aluminum electrode and good surface smoothness of the electroless plating layer. However, the palladium catalyst method increases manufacturing costs because palladium is a precious metal.

[0007] In the zincate method, zinc is substituted for aluminum on the surface of an aluminum electrode, causing it to precipitate as catalytic nuclei and form an electroless plating layer. The zincate solution used in this method is inexpensive, so it is widely used.

[0008] When mounting a front-back conductive semiconductor element on a module, it is mounted using the reflow method. In the reflow method, solder is placed on the top surface of the board at room temperature, and then the semiconductor element is placed on top of that and heated in a reflow furnace. This solders the backside electrodes of the semiconductor element to the board. The solder diffuses into the nickel-plated and gold-plated layers of the semiconductor element's electrodes, forming an alloy layer and bonding them. Mounting the frontside electrodes is done by wire bonding, where wire is adhered to the top surface of the electroless plated layer. When bonding with solder, solder is placed on top of the electroless plated layer, and a copper plate for the wiring circuit is placed on top of that, and then heated in a reflow furnace. As with the backside electrodes, the solder diffuses into the plated layer, forming an alloy layer and bonding them.

[0009] Repeated application of current inside the bonded electrodes can cause thermal stress, which can lead to cracks. Cracks can impede electrical or thermal conduction inside the electrodes, which can cause malfunctions in semiconductor devices. Therefore, it is necessary to suppress cracks that occur inside the electrodes.

[0010] For example, in Patent Document 1, an element structure is formed in which aluminum electrodes are formed on the front and back sides of a semiconductor chip, and a nickel layer and a gold plating layer are formed on the surface of each aluminum electrode. In particular, a recess is formed on the aluminum electrode side that comes into contact with the nickel layer. By forming a recess on the surface of the aluminum electrode, the nickel layer or an alloy layer formed from nickel and solder fills the recess after soldering, and the electrode bonding reliability is improved by the anchor effect.

[0011] International Publication No. 2021 / 246241

[0012] In Patent Document 1, an anchor effect is created by forming a recess on the top surface of the aluminum electrode, but there is a problem in that if another plating layer or the like is formed on the top surface of the aluminum electrode, the reliability of the joint via solder is not sufficiently high.

[0013] The technology disclosed in the present specification has been made in consideration of the problems described above, and is a technology for improving the reliability of solder joints in semiconductor devices.

[0014] A semiconductor device that is a first aspect of the technology disclosed in the present specification comprises a semiconductor substrate, an electrode provided on a first surface that is at least one of the main surfaces of the semiconductor substrate, and a plating layer provided on at least a portion of a second surface that is the surface of the electrode opposite to the surface that contacts the first surface, and an uneven portion is formed on the side of the plating layer that faces a third surface that is the surface that contacts the second surface.

[0015] According to the technology disclosed in the present specification, solder diffuses into the uneven portions formed on the side surfaces of the plating layer to form an alloy layer, thereby creating an anchor effect, thereby improving the reliability of solder-mediated joints in semiconductor devices.

[0016] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below.

[0017] FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor element according to a first embodiment. FIG. 2 is a flowchart showing an example of a manufacturing method of a semiconductor device according to the first embodiment. FIG. 3 is a flowchart showing an example of a plating pretreatment in FIG. 2. FIG. 4 is a flowchart showing an example of a plating treatment in FIG. 2. FIG. 5 is a cross-sectional view showing an example of the configuration of a semiconductor element according to the first embodiment connected to a heat dissipation substrate and external terminals. FIG. 6 is a cross-sectional view showing an example of the configuration of a semiconductor element according to a second embodiment. FIG. 7 is a cross-sectional view showing an example of the configuration of a semiconductor element according to a third embodiment. FIG. 8 is a flowchart showing an example of a plating treatment in FIG. 2. FIG. 9 is a cross-sectional view showing an example of the configuration of a power module according to a fourth embodiment, which includes a semiconductor element according to the first or second embodiment. FIG. 10 is a conceptual diagram showing an example of the configuration of a power conversion system including a power conversion apparatus according to a fifth embodiment.

[0018] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0019] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0020] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0021] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0022] Furthermore, in the description of this specification, even if ordinal numbers such as "first" or "second" are used, these terms are used for convenience to make it easier to understand the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0023] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0024] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude the interposition of another component "C" between A and B.

[0025] First Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to a first embodiment will be described below.

[0026] FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment. As shown in the example in FIG. 1 , the semiconductor device 1 includes a front-back conduction type substrate 2 as a semiconductor substrate, a front-side electrode 3a formed on at least a portion of one surface (top surface) of the front-back conduction type substrate 2, a back-side electrode 3b formed on the other surface (bottom surface or back surface) of the front-back conduction type substrate 2, and a plating layer 4 formed on the top surface of the front-side electrode 3a and the bottom surface of the back-side electrode 3b. A protective film 8 is formed on the top surface of the front-side electrode 3a, where the plating layer 4 is not formed. While FIG. 1 shows a case where both the front-side electrode 3a and the back-side electrode 3b are provided, only the front-side electrode 3a or only the back-side electrode 3b may be provided.

[0027] The plating layer 4 includes a nickel plating layer 5 formed by stacking multiple layers (laminated plating layer 50, laminated plating layer 52) having different nickel concentrations on the upper surface of the front electrode 3a and the lower surface of the back electrode 3b. Concave and convex portions 7 are formed on the side surfaces of the nickel plating layer 5. The plating layer 4 also includes a gold plating layer 6 on the upper surface of the uppermost nickel plating layer 5 on the front electrode 3a side (or on the lower surface of the lowermost nickel plating layer 5 on the back electrode 3b side). The nickel plating layer 5 need only include multiple layers having different nickel concentrations; layers with relatively high nickel concentrations and layers with relatively low nickel concentrations do not necessarily have to be stacked alternately.

[0028] The front-back conduction type substrate 2 may be a Si substrate, a SiC substrate, a GaAs substrate, a GaN substrate, or the like, and any known semiconductor substrate may be used without any particular limitations on the material. The thickness of the front-back conduction type substrate 2 is, for example, in the range of 50 μm or more and 300 μm or less. If the thickness of the front-back conduction type substrate 2 is too thin, the influence of chip warpage during electrode formation becomes greater. On the other hand, if the thickness of the front-back conduction type substrate 2 is too thick, the influence of electrode formation becomes less noticeable, but the electrical resistance increases. Therefore, it is preferable that the thickness of the front-back conduction type substrate 2 is as thin as possible.

[0029] The front-back conductive substrate 2 has components necessary for the operation of the semiconductor element 1, such as a pn junction layer including a P-type semiconductor and an N-type semiconductor, a gate electrode, and a gate insulating film.

[0030] The front electrode 3a is made of a material such as aluminum or an aluminum alloy. The aluminum alloy preferably contains an element more noble than aluminum. For example, iron, nickel, tin, lead, silicon, copper, silver, gold, tungsten, cobalt, platinum, palladium, iridium, rhodium, etc. The content of the element more noble than aluminum in the aluminum alloy is preferably 1% by mass or more and 3% by mass or less.

[0031] The thickness of the front-side electrode 3a is generally 1 μm or more and 10 μm or less, and is not particularly limited. The front-side electrode 3a is formed on the upper surface of the front-back conduction type substrate 2 by a sputtering method. The back-side electrode 3b is formed by a sputtering method in the process of forming the back-side electrode. Like the thickness of the front-side electrode 3a, the thickness of the back-side electrode 3b is not particularly limited, but is generally desirably 0.2 μm or more and 10 μm or less.

[0032] The nickel plating layer 5 is formed by electroless plating on the upper surface of the front electrode 3a or the lower surface of the back electrode 3b. The thickness of the nickel plating layer 5 is not particularly limited, but is, for example, 1 μm or more and 10 μm or less. If the nickel plating layer 5 is thin, there is a risk of electrode cracking when joining a wire in a wire bonding process. Therefore, the thickness of the nickel plating layer 5 is preferably 2 μm or more. If the nickel plating layer 5 is thick, it may be affected by chip warpage. Therefore, the thickness of the nickel plating layer 5 is preferably 8 μm or less.

[0033] The nickel plating layer 5 is formed by alternately stacking layers with a high nickel concentration (laminated plating layer 52) and layers with a low nickel concentration (laminated plating layer 50). The nickel concentrations of the multiple layers constituting the nickel plating layer 5 include, for example, a range of 90 mass% or more and 99 mass% or less. The concentration difference between the multiple layers constituting the nickel plating layer 5 (the difference between the nickel concentration of the laminated plating layer 50 and the nickel concentration of the laminated plating layer 52) is, for example, 1 mass% or more and 5 mass% or less. The thickness of each layer constituting the nickel plating layer 5 (laminated plating layer 50, laminate plating layer 52) is, for example, 0.1 μm or more and 0.5 μm or less. Elements other than nickel contained in the nickel plating layer 5 include, for example, phosphorus or boron.

[0034] The gold plating layer 6 formed on the upper surface of the nickel plating layer 5 on the upper surface of the front electrode 3a (or on the lower surface of the nickel plating layer 5 on the lower surface of the back electrode 3b) is formed by displacement plating. Displacement plating uses a displacement reaction that utilizes a difference in oxidation-reduction potential to dissolve the nickel in the nickel plating layer 5 and deposit gold on the outermost surface. Although not particularly limited, the thickness of the gold plating layer 6 is, for example, 0.01 μm or more and 0.1 μm or less.

[0035] When the gold plating layer 6 is formed by displacement plating, dissolution of the layer (laminated plating layer 52) having a relatively high nickel concentration among the multiple layers constituting the nickel plating layer 5 is promoted by a displacement reaction of the gold plating, resulting in the unevenness 7 being formed over the entire side surface of the nickel plating layer 5, in which the side surface of the layer (laminated plating layer 52) having a relatively low nickel concentration among the multiple layers constituting the nickel plating layer 5 is concave. The height difference of the unevenness 7 (in other words, the depth of the concave portion) is, for example, 0.1 μm or more and 2 μm or less.

[0036] The protective film 8 is not particularly limited, and any film known in the art can be used. Examples of the protective film 8 include glass-based films containing polyimide or silicon, which have excellent heat resistance. The surface (side surface) of the protective film 8 facing the plating layer 4 has a tapered shape that widens downward. The angle of the taper is preferably, for example, 10° or more and 85° or less.

[0037] Next, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to a flowchart shown in FIG.

[0038] First, in the process of fabricating the front-back conductive substrate 2, a semiconductor substrate known in the art, such as a Si substrate, SiC substrate, GaAs substrate, or GaN substrate, is prepared (step ST01 in FIG. 2 ). An epitaxial growth layer is formed on the surface of the semiconductor substrate. In mass production, multiple semiconductor elements 1 are fabricated on the semiconductor substrate with the epitaxial growth layer formed thereon, and finally, each semiconductor element 1 is cut out by dicing.

[0039] When the semiconductor substrate is a Si substrate, the epitaxially grown layer is typically obtained by growing Si on the semiconductor substrate in a temperature-controlled growth chamber using a source gas such as silane. The step of growing the epitaxially grown layer is carried out while adding impurities as necessary. For example, a chemical vapor deposition (CVD) method is used as the film formation method.

[0040] Next, after forming an epitaxial growth layer, a configuration (circuit configuration) that realizes the operation of the semiconductor device 1, such as a pn diffusion layer (not shown here) and a gate electrode (not shown here), is formed (step ST02 in FIG. 2). The pn diffusion layer is formed, for example, by ion implantation and activation. Boron or aluminum is used as an acceptor impurity when forming the pn diffusion layer. Phosphorus, arsenic, nitrogen, or the like is used as a donor impurity when forming the pn diffusion layer.

[0041] Next, a front-side electrode 3a is formed on the top surface of the front-back conduction type substrate 2 (step ST03 in FIG. 2 ). For example, an aluminum alloy containing aluminum and silicon is deposited on the top surface of the front-back conduction type substrate 2 as the front-side electrode 3a. For example, by performing a heat treatment at a temperature of 300° C. or higher and 400° C. or lower in a reducing atmosphere containing hydrogen or the like, the grain boundary density of the aluminum is reduced, ensuring ohmic contact between the front-side electrode 3a and the front-back conduction type substrate 2. Furthermore, the heat treatment recrystallizes the front-side electrode 3a, changing the grain size of the electrode material on the surface. If the grain size (diameter) is 10 μm or higher and 50 μm or lower, adhesion to the plating layer 4 is improved.

[0042] Next, the protective film 8 is formed. Specifically, a film made of silicon nitride, polyimide, or the like is formed on a part of the upper surface of the front electrode 3 a. The protective film 8 can be formed by, for example, a CVD method, a coating method using spin coating, or inkjet printing.

[0043] After the front electrode 3a is formed on the top surface of the front-back conduction type substrate 2 on which the pn junction layer, gate electrode, etc. are formed, the bottom surface of the front-back conduction type substrate 2 is ground using a grindstone made of alumina abrasive grains or diamond abrasive grains (step ST04 in FIG. 2). By this grinding, the front-back conduction type substrate 2 (semiconductor wafer) is thinned to a thickness of, for example, 50 μm or more and 300 μm or less.

[0044] Next, a back-side electrode 3b is formed on the underside of the front-back conduction type substrate 2 (step ST05 in FIG. 2 ). As in the case of the front-side electrode 3a, for example, an aluminum alloy containing aluminum and silicon is deposited as the back-side electrode 3b on the underside of the front-back conduction type substrate 2. For example, by performing a heat treatment at a temperature of 300° C. or higher and 400° C. or lower in a reducing atmosphere containing hydrogen or the like, the density of the aluminum grain boundaries is reduced, and ohmic contact between the back-side electrode 3b and the front-back conduction type substrate 2 is ensured.

[0045] Next, a nickel plating layer 5 and a gold plating layer 6 are sequentially formed on both the front electrode 3 a and the back electrode 3 b at the same time. This process is generally performed by a pre-plating process (step ST06 in FIG. 2 ) in which a plasma cleaning process, a degreasing process, an etching process, an acid immersion process, a first zincate treatment process, a zincate stripping process, and a second zincate treatment process are performed in this order, and a plating process (step ST07 in FIG. 2 ) in which a nickel plating process and a displacement gold plating process are performed in this order. A washing process is performed between each process in the pre-plating process and the plating process to prevent the treatment solution from the previous process from being carried over to the next process.

[0046] Fig. 3 is a flow chart showing an example of the plating pretreatment in Fig. 2. Fig. 4 is a flow chart showing an example of the plating treatment in Fig. 2.

[0047] The plasma cleaning process (step ST61 in FIG. 3 ) is performed on the surface of the front electrode 3a on the upper surface of the front-back conduction type substrate 2 and the surface of the back electrode 3b on the lower surface of the front-back conduction type substrate 2. In the plasma cleaning process, foreign matter and residues such as organic matter, oxides, or nitrides adhering to the surfaces of the front electrode 3a and the back electrode 3b are removed by oxidative decomposition using plasma. This process ensures the reactivity between the pretreatment solution and the front electrode 3a and the back electrode 3b in the plating pretreatment, and between the plating solution and the front electrode 3a and the back electrode 3b in the plating process.

[0048] Although not particularly limited, the plasma cleaning treatment on the front electrode 3a side is performed more intensively than the plasma cleaning treatment on the back electrode 3b side because the protective film 8 is formed on the front electrode 3a side. It is preferable to first perform the plasma cleaning treatment on the surface of the back electrode 3b, and then perform the plasma cleaning treatment on the surface of the front electrode 3a.

[0049] The degreasing step (step ST62 in FIG. 3) is performed on the surfaces of the front electrode 3a and the back electrode 3b of the front-back conductive substrate 2. The chemical solution used in the degreasing step is generally weakly alkaline and removes organic matter, oil and grease, or oxide films adhering to the surfaces of the front electrode 3a and the back electrode 3b.

[0050] The etching process (step ST63 in FIG. 3 ) is performed on the surfaces of the front electrode 3a and the back electrode 3b of the front-back conduction type substrate 2. Removal of oxide films from the surfaces of the front electrode 3a and the back electrode 3b after degreasing and roughening the surfaces improve adhesion to the plating layer 4 formed in a later process. If the etching process is alkaline etching, the degreasing process may be omitted because alkaline etching also has a degreasing effect. Because the etching rate varies depending on the alloy composition of the front electrode 3a and the back electrode 3b, the concentration of the etchant, bath temperature, and treatment time must be taken into consideration.

[0051] The acid immersion step (step ST64 in FIG. 3 ) is performed on the surfaces of the top electrode 3 a and the back electrode 3 b. The alloying elements (copper, magnesium, silicon, etc.) remaining on the surfaces of the top electrode 3 a and the back electrode 3 b after the etching step remain as smut, which reduces adhesion to the plating layer 4 formed in a subsequent step. In the acid immersion step, the smut is removed by immersion in nitric acid, sulfuric acid, hydrofluoric acid, acidic ammonium fluoride, or a mixed acid thereof.

[0052] In the first zincate treatment step (step ST65 in FIG. 3 ), the top electrode 3 a and the back electrode 3 b are subjected to a zincate treatment. The zincate solution used in the zincate treatment is primarily composed of sodium hydroxide and zinc oxide. This strong alkaline solution etches the surfaces of the top electrode 3 a and the back electrode 3 b, dissolving the oxide film. The newly exposed aluminum then dissolves, resulting in zinc displacement deposition. Finally, zinc coats the surfaces of the top electrode 3 a and the back electrode 3 b. Because the standard oxidation-reduction potential of the aluminum or aluminum alloy constituting the top electrode 3 a and the back electrode 3 b is lower than that of zinc, aluminum dissolves as ions. During this process, electrons generated by the dissolution of aluminum in the zincate solution bond with zinc ions in the zincate solution, resulting in zinc deposition as metal atoms.

[0053] When performing the first zincate treatment, if there is a large difference in the time it takes for the object to be plated to be completely immersed, unevenness in the treatment time will occur within the wafer surface. Therefore, it is desirable that the immersion speed into the first zincate solution be, for example, 10 mm / sec or more and 200 mm / sec or less.

[0054] The temperature of the first zincate liquid may be set appropriately depending on the type of the first zincate liquid, but is generally set in the range of, for example, 10° C. or higher and 30° C. or lower.

[0055] The plating time is set appropriately depending on the concentration and temperature of the first zincate solution, but is generally set in the range of, for example, 5 seconds or more and 300 seconds or less. Although not particularly limited, it is desirable that the plating time be 10 seconds or more and 120 seconds or less.

[0056] The zincate stripping step (step ST66 in FIG. 3) is performed on the zinc-coated front electrode 3a and the zinc-coated back electrode 3b. The zinc-coated front electrode 3a and the zinc-coated back electrode 3b are immersed in nitric acid to dissolve the zinc coating formed on each electrode surface.

[0057] In the second zincate treatment step (step ST67 in FIG. 3 ), the top electrode 3 a and the back electrode 3 b, from which the zinc coating has been dissolved in the zincate stripping step, are immersed again in the zincate treatment solution, thereby removing aluminum and its oxide film and forming zinc coatings on the surfaces of the top electrode 3 a and the back electrode 3 b.

[0058] The second zincate treatment is performed on the surfaces of the front electrode 3a and the back electrode 3b. As with the first zincate treatment, if the time difference until the object to be plated is completely immersed is large, uneven treatment time occurs within the wafer surface. Therefore, it is desirable that the immersion speed into the second zincate solution is, for example, 10 mm / sec or more and 200 mm / sec or less.

[0059] The temperature of the second zincate liquid may be set appropriately depending on the type of the second zincate liquid, but is generally set in the range of, for example, 10° C. or higher and 30° C. or lower.

[0060] The plating time is set appropriately depending on the concentration and temperature of the second zincate solution, but is generally set in the range of, for example, 5 seconds or more and 150 seconds or less. Although not particularly limited, it is desirable that it be 10 seconds or more and 60 seconds or less. If the treatment time is long, dissolution of aluminum will proceed, and the adhesion with the nickel plating layer 5 formed in a later step will decrease.

[0061] In the nickel plating process (step ST71 in FIG. 4 ), the front electrode 3 a and the back electrode 3 b that have been subjected to the second zincate treatment are immersed in a nickel plating solution to form a nickel plating layer 5. The nickel plating solution is not particularly limited, and any solution known in the art can be used.

[0062] The nickel concentration of the plating solution used for nickel is not particularly limited, but is generally, for example, 1.0 g / L or more and 10.0 g / L or less. The hydrogen ion concentration (pH) of the nickel plating solution is not particularly limited, but is generally, for example, 4.0 or more and 8.0 or less.

[0063] The immersion speed during nickel plating is desirably 10 mm / sec or more and 200 mm / sec or less. The object to be plated is swung up and down. The swung speed is 10 mm / sec or more and 500 mm / sec or less. The swung width is not particularly limited, but is carried out in the range of 50 mm or more and 500 mm or less. The swung method may be either a method in which the object to be plated is pulled up and allowed to fall freely by gravity, or a method in which the object is smoothly moved up and down (vertically). The hold time between switching between up and down movements is less than 1 second.

[0064] The temperature of the nickel plating solution may be set appropriately depending on the type of nickel plating solution, plating conditions, etc., but is generally 50°C or higher and 100°C or lower, and considering productivity, it is preferably 70°C or higher and 90°C or lower.

[0065] By changing the rocking speed of the workpiece, the stirring speed of the plating solution, or the nickel concentration in the nickel plating solution during plating immersion, it is possible to alternately stack layers with high nickel concentrations (laminated plating layer 52) and layers with low nickel concentrations (laminated plating layer 50). The thickness and number of layers can be set as desired by changing the time for changing various parameters.

[0066] The plating time is set appropriately depending on the plating conditions and the thickness of the nickel plating layer 5, but is generally 5 minutes or more and 60 minutes or less.

[0067] In the displacement gold plating process (step ST72 in FIG. 4 ), the top electrode 3 a on which the nickel plating layer 5 is formed and the back electrode 3 b on which the nickel plating layer 5 is formed are gold-plated to form a gold plating layer 6 on the surface of the nickel plating layer 5. The gold plating process is generally performed by a method known as displacement gold plating. In displacement gold plating, the deposition rate is affected by the difference in oxidation-reduction potential between metal ions with a noble oxidation-reduction potential present in the chemical solution and the base metal ion. By appropriately selecting a complexing agent contained in the gold plating solution, the nickel in the nickel plating layer 5 is substituted with gold.

[0068] The gold plating solution is not particularly limited, but any solution known in the art can be used. The gold concentration in the gold plating solution is not particularly limited, but is generally 1.0 g / L or more and 5 g / L or less.

[0069] The pH of the gold plating solution is not particularly limited, but is generally 6.0 or more and 8.0 or less. The temperature of the gold plating solution may be set appropriately depending on the type of gold plating solution, plating conditions, etc., but is generally 30° C. or more and 100° C. or less. When the nickel concentration in the nickel plating layer 5 is 95% by mass or more, the solution temperature is preferably 30° C. or more and 60° C. or less. On the other hand, when the nickel concentration in the nickel plating layer 5 is lower than 95% by mass, the solution temperature is preferably 40° C. or more and 100° C. or less.

[0070] The plating time may be set appropriately depending on the plating conditions, the thickness of the gold plating layer 6, etc., but is generally 5 minutes or more and 60 minutes or less.

[0071] FIG. 5 is a cross-sectional view showing an example of the configuration of the semiconductor element 1 in a state where it is connected to a heat dissipation substrate and external terminals.

[0072] 5, the plating layer 4 of the semiconductor element 1 is joined to an external terminal 10 via solder 9. In addition, a heat dissipation substrate 11 is further provided on the lower surface of the external terminal 10 below the back electrode 3b.

[0073] The solder 9 is not particularly limited, but may be a solder known in the art, such as a tin-silver-copper solder. The thickness of the solder is, for example, 0.1 μm or more and 500 μm or less.

[0074] The solder 9 joining the external terminals 10 and the plating layer 4 penetrates into the uneven portions 7 formed on the side surfaces of the plating layer 4 (side surfaces of the nickel plating layer 5) to join them, thereby increasing the bonding strength between the external terminals 10 and the plating layer 4.

[0075] Any known material in the art can be used for the heat dissipation substrate 11. The external terminals 10 are preferably made of an inexpensive metal with low electrical resistance, and are preferably made of copper or a copper alloy.

[0076] In this way, in the semiconductor element 1 having the above-described structure, the uneven portion 7 is formed on the side surface of the nickel plating layer 5, and during solder joining, the solder 9 diffuses into the uneven portion 7 to form an alloy layer, thereby providing an anchor effect and improving the joining reliability of the external terminal 10 (external electrode).

[0077] Embodiment 2. A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment 2 will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0078] 6 is a cross-sectional view showing an example of the configuration of a semiconductor element according to the second embodiment. As shown in the example of Fig. 6, a semiconductor element 1a includes a front-back conduction type substrate 2, a front-side electrode 3a on the top surface of the front-back conduction type substrate 2, a back-side electrode 3b on the bottom surface (or back surface) of the front-back conduction type substrate 2, and a plating layer 4a formed on the top surface of the front-side electrode 3a and the bottom surface of the back-side electrode 3b. In addition, a protective film 8 is formed on the top surface of the front-side electrode 3a on which the plating layer 4a is not formed.

[0079] The plating layer 4a includes a nickel plating layer 5a formed by stacking multiple layers (laminated plating layer 50a, laminate plating layer 52a) with different nickel concentrations on the upper surface of the top electrode 3a and the lower surface of the back electrode 3b. A concave-convex portion 7 is formed on the side surface of the nickel plating layer 5a. The nickel plating layer 5a also includes a groove 7a extending from the upper surface of the topmost nickel plating layer 5a on the top electrode 3a side (or the lower surface of the bottommost nickel plating layer 5a on the back electrode 3b side) into the nickel plating layer 5a. The plating layer 4a also includes a gold plating layer 6 on the upper surface of the topmost nickel plating layer 5a on the top electrode 3a side (or the lower surface of the bottommost nickel plating layer 5a on the back electrode 3b side). The nickel plating layer 5a need not necessarily be formed by alternately stacking layers with relatively high and relatively low nickel concentrations, as long as it includes multiple layers with different nickel concentrations.

[0080] Crystal grain boundaries exist within the nickel plating layer 5a, and grain boundaries (grain boundary portions) are formed in the depth direction of the nickel plating layer 5a. When the gold plating layer 6 is formed, the gold plating solution penetrates into the grain boundary portions from the surface of the nickel plating layer 5a, promoting a substitution reaction within the grain boundaries and forming the groove portions 7a. At this time, differences in the nickel concentration cause differences in the rate of the substitution reaction in the planar view direction, and the substitution reaction is promoted in layers with a relatively high nickel concentration, resulting in an uneven shape on the side surfaces of the groove portions 7a.

[0081] The electroless nickel plating bath used to form the nickel plating layer 5a is composed of metal salts, reducing agents, complexing agents, pH adjusters, buffers, additives, brighteners, stabilizers, etc. In particular, by adjusting the complexing agent that affects the crystal orientation of the nickel plating, it is possible to form the nickel plating layer 5a having grain boundaries. The grain boundaries of the nickel plating layer 5a are 1 per μm. ２ or more, and 100 pieces / μm ２ The depth of grooves 7a formed inside plating layer 4a is, for example, not less than 0.1 μm and not more than 1.0 μm.

[0082] According to the semiconductor element 1a of this embodiment, an anchor effect is exerted in the alloy layer formed by solder diffusing not only the uneven portion 7 on the side surface of the nickel plating layer 5a but also into the groove portion 7a formed inside the nickel plating layer 5a by solder bonding, thereby improving the bonding reliability of the external terminal 10 (external electrode).

[0083] Third Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to a third embodiment will be described.

[0084] In the following description, components similar to those described in the above embodiments will be illustrated with the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0085] FIG. 7 is a cross-sectional view showing an example of the configuration of a semiconductor element according to the third embodiment. The plating layer 4b includes a nickel plating layer 5 on the upper surface of the front electrode 3a and the lower surface of the back electrode 3b, each of which includes a laminated layer of multiple layers (laminated plating layer 50, laminate plating layer 52) with different nickel concentrations. The side surfaces of the nickel plating layer 5a have an uneven portion 7. The plating layer 4b also includes a gold plating layer 6 on the upper surface of the nickel plating layer 5 on the front electrode 3a side (or the lower surface of the nickel plating layer 5 on the lowermost side of the back electrode 3b), and a gold plating layer 6a on the side surfaces (or the side surfaces of the nickel plating layer 5 on the lowermost side of the back electrode 3b). The nickel plating layer 5 need only include multiple layers with different nickel concentrations; layers with relatively high nickel concentrations and layers with relatively low nickel concentrations do not necessarily need to be alternately laminated. The thickness of the gold plating layer 6a is 0.01 μm or more and 1.0 μm or less. If necessary, a palladium layer may be sandwiched between the nickel plating layer 5 and the gold plating layer 6 or 6a.

[0086] Fig. 8 is a flow chart showing an example of the plating process in Fig. 2. A cleaning process is carried out between each step in the plating process.

[0087] In the first displacement gold plating process (step ST73 in FIG. 8 ), the top electrode 3 a on which the nickel plating layer 5 is formed and the back electrode 3 b on which the nickel plating layer 5 is formed are gold-plated to form a gold plating layer 6 on the surface of the nickel plating layer 5. The gold plating process is generally performed by a method known as displacement gold plating. In displacement gold plating, the deposition rate is affected by the difference in oxidation-reduction potential between metal ions with a noble oxidation-reduction potential present in the chemical solution and the base metal ion. By appropriately selecting a complexing agent contained in the gold plating solution, the nickel in the nickel plating layer 5 is substituted for gold.

[0088] The gold plating solution is not particularly limited, but any solution known in the art can be used. The gold concentration in the gold plating solution is not particularly limited, but is generally 1.0 g / L or more and 5 g / L or less.

[0089] The pH of the gold plating solution is not particularly limited, but is generally 6.0 or more and 8.0 or less. The temperature of the gold plating solution may be set appropriately depending on the type of gold plating solution, plating conditions, etc., but is generally 30° C. or more and 100° C. or less. When the nickel concentration in the nickel plating layer 5 is 95% by mass or more, the solution temperature is preferably 30° C. or more and 60° C. or less. On the other hand, when the nickel concentration in the nickel plating layer 5 is lower than 95% by mass, the solution temperature is preferably 40° C. or more and 100° C. or less.

[0090] When the gold plating layer 6 is formed by displacement plating, dissolution of the gold plating is promoted by a displacement reaction in the layer (laminated plating layer 52) having a relatively high nickel concentration among the multiple layers constituting the nickel plating layer 5. As a result, the side surfaces of the layer (laminated plating layer 50) having a relatively low nickel concentration among the multiple layers constituting the nickel plating layer 5 are dissolved more than in the case of the layer (laminated plating layer 50) having a relatively low nickel concentration among the multiple layers constituting the nickel plating layer 5. As a result, uneven portions 7 are formed on the entire side surfaces of the nickel plating layer 5, where the side surfaces of the layer (laminated plating layer 52) having a relatively high nickel concentration among the multiple layers constituting the nickel plating layer 5 are concave.

[0091] The plating time may be set appropriately depending on the plating conditions, the thickness of the gold plating layer 6, etc., but is generally 5 minutes or more and 60 minutes or less.

[0092] A rinsing process is performed before the second immersion gold plating process (step ST74 in FIG. 8 ). The temperature of the rinsing water is preferably set to 10°C or higher and 40°C or lower. The formation of the uneven portion 7 in the first immersion gold plating process (step ST73 in FIG. 8 ) weakens the adhesion between the protective film 8 and the nickel plating layer 5, and when the protective film 8 and the nickel plating layer 5 are cooled by the rinsing water, they undergo thermal contraction and peel off. Therefore, in the second immersion gold plating process, gold ions can be supplied sufficiently to the side surfaces of the nickel plating layer 5, and a gold plating layer 6a can be formed on the side surfaces of the nickel plating layer 5 by a substitution reaction with nickel.

[0093] The semiconductor element 1b according to this embodiment can have a configuration similar to that of the semiconductor element connected to the heat dissipation substrate and external terminals shown in Fig. 5 of the first embodiment, but in the third embodiment, a gold plating layer is provided on the uneven portion 7 on the side surface of the nickel plating layer 5, which promotes the diffusion of solder into the uneven portion 7 and reduces the rate of void generation, thereby further improving the bonding reliability of the external terminals 10 (external electrodes).

[0094] Embodiment 4. A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0095] 9 is a cross-sectional view showing an example of the configuration of a power module including a semiconductor element according to any one of the first to third embodiments as a semiconductor element 101. As shown in the example in Fig. 9, the power module 100 (conversion circuit) includes a heat dissipation member 102, a housing 110 provided on the upper surface of the heat dissipation member 102, an insulating substrate 103 provided on the upper surface of the heat dissipation member 102 via solder 105, a semiconductor element 101 provided on the upper surface of the insulating substrate 103 via solder 105, an electrode plate 104 provided on the upper surface of the semiconductor element 101 via solder 105, a main terminal 106 extending from the upper surface and inner wall of the housing 110, a signal terminal 107 extending from the upper surface and inner wall of the housing 110, a wire 108 connecting the signal terminal 107 to (the electrode pattern of) the upper surface of the semiconductor element 101, and a sealing resin 112 filled inside the housing 110. The lower surface of the electrode plate 104 is connected to a main terminal 106 via solder 105 .

[0096] The heat dissipation member 102 is made of, for example, an aluminum alloy. A filler may be provided on the lower surface of the heat dissipation member 102. The entire surface of the heat dissipation member 102 is plated with nickel.

[0097] The insulating substrate 103 has a base material made of aluminum nitride and copper conductor layers provided on the front and back sides thereof, each conductor layer being formed by brazing.

[0098] The content of the solder 105 is not particularly limited, but may be, for example, 96.5% tin, 3% silver, and 0.5% copper, and the melting point of the solder 105 is 217°C.

[0099] Although the front and back electrodes of the semiconductor element 101 are not shown here, the back electrode is joined to the conductive layer of the insulating substrate 103, and the front electrode is joined to a copper electrode plate 104 using solder 105.

[0100] The wire 108 is made of aluminum or an aluminum alloy and connects an electrode (signal electrode) on the top surface of the semiconductor element 101 to the signal terminal 107 .

[0101] The interior surrounded by the housing 110 is filled with a liquid sealing resin 112, and the sealing resin 112 is hardened by heating in an oven at 150° C. for one hour, for example, to complete the sealing. This completes the power module 100.

[0102] Although not shown in FIG. 9, the power module 100 is connected to a power source, a control circuit, and a load, converts input DC power into AC power, and outputs the AC power.

[0103] The control circuit generates a control signal for controlling the driving of the switching element (semiconductor element 101) of the power module 100 and supplies the control signal to a signal terminal 107 of the power module 100. A DC power supply is assumed as the power source for the power module 100, and can be configured as a solar cell or a storage battery. Alternatively, a rectifier circuit or an AC / DC converter connected to an AC circuit can also be assumed as the power source for the power module 100.

[0104] The load is a three-phase electric motor driven by AC power supplied from the power module 100. The electric motor is not limited to a specific application, but is used in hybrid vehicles, electric vehicles, railway vehicles, elevators, air conditioners, and the like.

[0105] Next, the operation of the power module 100 will be described. Although not shown in Fig. 9, the power module 100 includes a switching element and a freewheeling diode. When the switching element performs a switching operation, the power module 100 converts DC power supplied from a power source into AC power and supplies it to a load.

[0106] A specific circuit configuration of the power module 100 is, for example, a three-phase full-bridge circuit, which includes six switching elements and six freewheeling diodes connected in anti-parallel to each of the switching elements.

[0107] At least one of the switching elements and free wheel diodes provided in the power module 100 is made of the semiconductor element 1 shown in the first embodiment or the semiconductor element 1a shown in the second embodiment, or a semiconductor element 101 which is a modified example thereof.

[0108] According to this embodiment, by using the semiconductor elements shown in the first or second embodiment for the switching elements and free wheel diodes that make up the power module 100, it is possible to suppress damage to the device due to stress that occurs when current is applied, and it is possible to increase the reliability of the power module 100.

[0109] Embodiment 5. A power conversion device and a method for manufacturing a power conversion device according to this embodiment 5 will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0110] In this embodiment, the semiconductor device according to the above-described embodiment is applied to a power conversion device. The power conversion device to which the semiconductor device is applied is not limited to a specific application, but the following description will be given of a case where the semiconductor device is applied to a three-phase inverter.

[0111] FIG. 10 is a diagram conceptually showing an example of the configuration of a power conversion system including a power conversion device according to the fifth embodiment.

[0112] As shown in the example of FIG. 10 , the power conversion system includes a power supply 2100, a power conversion device 2200, and a load 2300. The power supply 2100 is a DC power supply and supplies DC power to the power conversion device 2200. The power supply 2100 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery. The power supply 2100 can also be configured from a rectifier circuit connected to an AC system or an AC-DC converter. The power supply 2100 can also be configured from a DC-DC converter that converts DC power output from a DC system into a predetermined power.

[0113] The power conversion device 2200 is a three-phase inverter connected between the power supply 2100 and the load 2300. The power conversion device 2200 converts DC power supplied from the power supply 2100 into AC power, and further supplies the AC power to the load 2300.

[0114] Furthermore, as shown in an example in Figure 10, the power conversion device 2200 includes a conversion circuit 2201 that converts DC power into AC power and outputs it, and a control circuit 2203 that outputs a control signal to the conversion circuit 2201 to control the conversion circuit 2201.

[0115] The load 2300 is a three-phase electric motor driven by AC power supplied from the power conversion device 2200. The load 2300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, such as a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0116] The power conversion device 2200 will be described in detail below. The conversion circuit 2201 includes a switching element and a freewheeling diode (not shown). The switching element performs a switching operation to convert DC power supplied from the power supply 2100 into AC power, which is then supplied to the load 2300.

[0117] There are various specific circuit configurations for the conversion circuit 2201, but the conversion circuit 2201 according to the fourth embodiment is a two-level three-phase full-bridge circuit, and includes six switching elements and six freewheeling diodes connected in anti-parallel to each of the switching elements.

[0118] The semiconductor device according to any of the above-described embodiments is applied to at least one of the switching elements and freewheeling diodes in the conversion circuit 2201. Six switching elements are connected in series in groups of two to form upper and lower arms, each of which constitutes a phase (i.e., U phase, V phase, and W phase) of a full-bridge circuit. The output terminals of each of the upper and lower arms (i.e., the three output terminals of the conversion circuit 2201) are connected to the load 2300.

[0119] The conversion circuit 2201 also includes a drive circuit (not shown here) that drives each switching element, but the drive circuit may be built into the semiconductor device, which is a semiconductor module, or may be provided separately from the semiconductor module. The drive circuit generates drive signals for driving the switching elements of the conversion circuit 2201, and further supplies the drive signals to the control electrodes of the switching elements of the conversion circuit 2201. Specifically, based on control signals output from a control circuit 2203 (described later), the drive circuit outputs drive signals that turn the switching elements on and off to the control electrodes of the switching elements.

[0120] When the switching element is maintained in the on state, the drive signal is a voltage signal (i.e., an on signal) that is equal to or greater than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal is a voltage signal (i.e., an off signal) that is equal to or less than the threshold voltage of the switching element.

[0121] The control circuit 2203 controls the switching elements of the conversion circuit 2201 so that a desired power is supplied to the load 2300. Specifically, the control circuit 2203 calculates the time (i.e., on-time) that each switching element of the conversion circuit 2201 should be in the on-state based on the power to be supplied to the load 2300. For example, the conversion circuit 2201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output.

[0122] The control circuit 2203 then outputs a control command (i.e., a control signal) to the drive circuit so that an ON signal is output to a switching element that should be in an ON state at each point in time, and an OFF signal is output to a switching element that should be in an OFF state at each point in time. Based on the control signal, the drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.

[0123] In the power conversion device 2200 according to this fifth embodiment, a semiconductor device according to any of the embodiments described above is applied as the switching element of the conversion circuit 2201, and therefore the on-resistance can be stabilized after a current cycle.

[0124] In the fifth embodiment, an example has been described in which the semiconductor device in any of the above-described embodiments is applied to a two-level three-phase inverter, but the application example is not limited to this, and the semiconductor device in any of the above-described embodiments can be applied to various power conversion devices.

[0125] Although a two-level power conversion device has been described in the fifth embodiment, the semiconductor device according to any of the above-described embodiments may be applied to a three-level or multilevel power conversion device. When power is supplied to a single-phase load, the semiconductor device according to any of the above-described embodiments may be applied to a single-phase inverter.

[0126] Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to any of the above-described embodiments can be applied to a DC-DC converter or an AC-DC converter.

[0127] Furthermore, a power conversion device to which the semiconductor device according to any of the above-described embodiments is applied is not limited to a case in which the load is an electric motor, and can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, for example. Furthermore, a power conversion device to which the semiconductor device according to any of the above-described embodiments is applied can also be used as a power conditioner in a solar power generation system, a power storage system, or the like.

[0128] Next, a method for manufacturing the power converter according to this embodiment will be described.

[0129] First, a semiconductor device is manufactured by the manufacturing method described in the above-described embodiment. Then, a conversion circuit 2201 including the semiconductor device is provided as a component of a power conversion device. The conversion circuit 2201 is a circuit for converting input power and outputting it.

[0130] The power conversion device includes a control circuit 2203. The control circuit 2203 is a circuit for outputting a control signal for controlling the conversion circuit 2201 to the conversion circuit 2201.

[0131] The semiconductor switching elements used in the embodiments described above are not limited to switching elements made of silicon (Si) semiconductors, and for example, the semiconductor switching elements may be made of non-Si semiconductor materials having a wider band gap than Si semiconductors.

[0132] Examples of wide band gap semiconductors that are non-Si semiconductor materials include silicon carbide, gallium nitride-based materials, and diamond.

[0133] Switching elements made of wide bandgap semiconductors can be used in high voltage regions where unipolar operation is difficult with Si semiconductors, and can significantly reduce the switching loss that occurs during switching operation, thereby enabling a significant reduction in power loss.

[0134] Furthermore, switching elements made of wide bandgap semiconductors have low power loss and high heat resistance, which means that when configuring a power module with a cooling unit, it is possible to reduce the size of the heat dissipation fins of the heat sink, thereby enabling further miniaturization of the semiconductor module.

[0135] Furthermore, switching elements made of wide bandgap semiconductors are suitable for high-frequency switching operations. Therefore, when applied to converter circuits that require higher frequencies, increasing the switching frequency also enables the size of reactors or capacitors connected to the converter circuit to be reduced.

[0136] Therefore, the same effect can be obtained even when the semiconductor switching elements in the above-described embodiments are made of a wide-gap semiconductor such as silicon carbide.

[0137] Next, examples of effects obtained by the above-described embodiments will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the above-described embodiments, but these may be replaced with other specific configurations exemplified in the present specification as long as the same effects are obtained. In other words, for convenience, only one of the associated specific configurations may be described as a representative in the following description, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0138] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0139] According to the embodiment described above, the semiconductor device includes a semiconductor substrate, an electrode, and a plating layer 4 (or a plating layer 4a). The semiconductor substrate corresponds to, for example, a front-back conduction substrate 2. The electrode corresponds to, for example, a front-side electrode 3a or a back-side electrode 3b. The electrode is provided on a first surface (e.g., the top surface of the front-back conduction substrate 2), which is at least one of the main surfaces of the front-back conduction substrate 2. The plating layer 4 is provided on at least a portion of a second surface (e.g., the top surface of the electrode), which is the surface of the electrode opposite to the surface that contacts the first surface (e.g., the top surface of the front-back conduction substrate 2). The uneven portion 7 is formed on a side surface of the plating layer 4 opposite to a third surface (e.g., the bottom surface of the plating layer 4), which is the surface that contacts the second surface (e.g., the top surface of the electrode).

[0140] With this configuration, solder 9 diffuses into the uneven portion 7 formed on the side surface of the plating layer 4 to form an alloy layer, thereby creating an anchor effect, thereby improving the reliability of the connection between the plating layer 4 and the external terminal 10 (external electrode) via the solder 9.

[0141] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0142] Furthermore, according to the embodiment described above, the plating layer 4 is formed by stacking multiple nickel plating layers 5 (or nickel plating layers 5a) having different nickel concentrations. The multiple nickel plating layers 5 include a first laminate plating layer and a second laminate plating layer having a higher nickel concentration than the laminate plating layer 50. Here, the first laminate plating layer corresponds to, for example, the laminate plating layer 50 or the laminate plating layer 50a. The second laminate plating layer corresponds to, for example, the laminate plating layer 52 or the laminate plating layer 52a. The uneven portion 7 has a concave shape on the side surface corresponding to the laminate plating layer 52. With this configuration, the solder 9 diffuses into the uneven portion 7 formed on the side surface of the plating layer 4 to form an alloy layer, which provides an anchor effect, thereby improving the reliability of the joint between the plating layer 4 and the external terminal 10 (external electrode) via the solder 9. Furthermore, since the nickel plating layer 5 is formed by alternately stacking the laminate plating layer 50 and the laminate plating layer 52, an uneven portion 7 can be formed in which the locations corresponding to the laminate plating layer 52 become recesses due to a substitution reaction of the gold plating.Therefore, by adjusting the thicknesses of the laminate plating layer 50 and the laminate plating layer 52, it is easy to form a uniform uneven shape.

[0143] Furthermore, according to the embodiment described above, the nickel concentration of the nickel plating layer 5 is 90% by mass or more and 99% by mass or less. The difference in nickel concentration between the laminate plating layer 50 and the laminate plating layer 52 is 1% by mass or more and 5% by mass or less. The thicknesses of the laminate plating layer 50 and the laminate plating layer 52 are 0.1 μm or more and 0.5 μm or less. With this configuration, the solder 9 diffuses into the irregularities 7 formed on the side surfaces of the plating layer 4 to form an alloy layer, which provides an anchor effect and improves the reliability of the connection between the plating layer 4 and the external terminal 10 (external electrode) via the solder 9.

[0144] Furthermore, according to the embodiment described above, the grooves 7 a are formed on the side of the nickel plating layer 5 a opposite to the third surface (e.g., the lower surface) thereof. With this configuration, the grooves 7 a also provide an anchor effect in addition to the unevenness 7, improving the reliability of the joint between the plating layer 4 and the external terminal 10 (external electrode) via the solder 9.

[0145] Furthermore, according to the embodiment described above, the side surfaces of the grooves 7 a are uneven. With this configuration, the grooves 7 a also provide an anchoring effect in addition to the unevenness 7, improving the reliability of the joint between the plating layer 4 and the external terminals 10 (external electrodes) via the solder 9.

[0146] Furthermore, according to the embodiment described above, the grain boundaries formed in the nickel plating layer 5a are 1 line / μm ２ or more, and 100 pieces / μm ２ The grooves 7a are present at a density of 0.1 μm or more and 1.0 μm or less. In addition, the depth of the grooves 7a is 0.1 μm or more and 1.0 μm or less. With this configuration, an anchor effect is provided by the grooves 7a in addition to the unevenness 7, improving the reliability of the joint between the plating layer 4 and the external terminals 10 (external electrodes) via the solder 9.

[0147] Furthermore, according to the embodiment described above, in the semiconductor device, the plating layer 4 includes the gold plating layer 6 provided on the side opposite to the third surface. With this configuration, the solder 9 diffuses into the irregularities 7 formed on the side surfaces of the plating layer 4 to form an alloy layer, which produces an anchor effect, thereby improving the reliability of the connection between the plating layer 4 and the external terminals 10 (external electrodes) via the solder 9.

[0148] Furthermore, according to the embodiment described above, electrodes are provided on both main surfaces of the front-back conduction type substrate 2. Then, the plating layer 4 is provided on the second surfaces of both electrodes. With this configuration, in a semiconductor device having the front-back conduction type substrate 2, the solder 9 diffuses into the uneven portions 7 formed on the side surfaces of the plating layer 4 to form an alloy layer, which produces an anchor effect, thereby improving the reliability of the connection between the plating layer 4 and the external terminals 10 (external electrodes) via the solder 9.

[0149] Furthermore, according to the embodiment described above, the height difference of the uneven portion 7 is 0.1 μm or more and 2 μm or less. With such a configuration, the solder 9 diffuses into the uneven portion 7 formed on the side surface of the plating layer 4 to form an alloy layer, which brings about an anchor effect, thereby improving the reliability of the joint between the plating layer 4 and the external terminal 10 (external electrode) via the solder 9.

[0150] Furthermore, according to the embodiment described above, the plating layer 4 is provided on a portion of the second surface. The semiconductor device further includes a protective film 8 provided on the second surface where the plating layer 4 is not provided. The surface of the protective film 8 facing the plating layer 4 has a tapered shape of 10° or more and 85° or less. With this configuration, molten solder 9 penetrates the gap formed between the plating layer 4 and the protective film 8, and the solder 9 diffuses into the uneven portions 7 formed on the side surfaces of the plating layer 4 to form an alloy layer, thereby providing an anchor effect. This improves the reliability of the connection between the plating layer 4 and the external terminal 10 (external electrode) via the solder 9.

[0151] Furthermore, according to the embodiment described above, the conversion circuit 2201 of the power conversion device includes a semiconductor device having the semiconductor element 101, a housing 110 that houses the semiconductor device, external electrodes (main terminals 106, signal terminals 107, etc.) connected to the semiconductor device, and a sealing resin 112 that fills the housing 110. With such a configuration, the bonding reliability of the semiconductor device is improved, and therefore the reliability of the power conversion device is also improved.

[0152] According to the embodiment described above, in the method for manufacturing a semiconductor device, an electrode is provided on at least one of the first surfaces (e.g., the top surface of the back-side conduction substrate 2), which is a main surface of the front-back conduction substrate 2. A plating layer 4 is then provided on at least a portion of the second surface (e.g., the top surface of the electrode), which is the surface of the electrode opposite to the surface that contacts the first surface (e.g., the top surface of the front-back conduction substrate 2). A concave-convex portion 7 is then formed on the side of the plating layer 4 opposite to the third surface (e.g., the bottom surface of the plating layer 4), which is the surface that contacts the second surface (e.g., the top surface of the electrode). The plating layer 4 is formed by stacking multiple nickel plating layers 5 having different nickel concentrations, and a gold plating layer 6 is provided on the side opposite to the third surface. The multiple nickel plating layers 5 include a laminate plating layer 50 and a laminate plating layer 52 having a higher nickel concentration than the laminate plating layer 50. The concave shape of the uneven portion 7 is formed when the gold plating layer 6 is formed by displacement plating, and the laminate plating layer 52 dissolves more than the laminate plating layer 50 in a displacement reaction of the gold plating.

[0153] With this configuration, solder 9 diffuses into the uneven portion 7 formed on the side surface of the plating layer 4 to form an alloy layer, thereby creating an anchor effect, thereby improving the reliability of the connection between the plating layer 4 and the external terminal 10 (external electrode) via the solder 9.

[0154] Unless otherwise specified, the order in which the processes are performed can be changed.

[0155] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0156] Furthermore, according to the embodiment described above, when the gold plating layer 6 is formed by displacement plating, the gold plating solution is allowed to penetrate into the side of the nickel plating layer 5a opposite to the third surface to form the grooves 7a. With this configuration, an anchor effect is provided by the grooves 7a in addition to the unevenness 7, improving the reliability of the joint between the plating layer 4 and the external terminals 10 (external electrodes) via the solder 9.

[0157] Furthermore, according to the embodiment described above, when the gold plating layer 6 is formed by displacement plating, the displacement reaction of the gold plating dissolves more of the laminate plating layer 52 than the laminate plating layer 50, forming an uneven shape on the side surface of the groove 7 a. With this configuration, an anchor effect is provided by the groove 7 a in addition to the unevenness 7, improving the reliability of the joint between the plating layer 4 and the external terminal 10 (external electrode) via the solder 9.

[0158] In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0159] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component from at least one embodiment and combining it with a component from another embodiment.

[0160] Furthermore, in at least one embodiment described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0161] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, "one or more" of that component may be provided.

[0162] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to a part of a structure, and even cases where multiple components are provided in one structure.

[0163] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0164] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0165] Various aspects of the present disclosure are summarized below as appendices.

[0166] (Supplementary Note 1) A semiconductor device comprising: a semiconductor substrate; an electrode provided on a first surface which is at least one of the main surfaces of the semiconductor substrate; and a plating layer provided on at least a part of a second surface which is the surface of the electrode opposite to the surface in contact with the first surface, wherein an uneven portion is formed on a side surface of the plating layer opposite to the third surface which is the surface in contact with the second surface.

[0167] (Appendix 2) The semiconductor device according to Appendix 1, wherein the plating layer is configured by stacking a plurality of nickel plating layers having different nickel concentrations, the plurality of nickel plating layers include a first laminate plating layer and a second laminate plating layer having a higher nickel concentration than the first laminate plating layer, and the uneven portion has a concave shape on the side surface corresponding to the second laminate plating layer.

[0168] (Appendix 3) The semiconductor device according to Appendix 2, wherein the nickel concentration of the nickel plating layer is 90% by mass or more and 99% by mass or less, the difference in nickel concentration between the first laminate plating layer and the second laminate plating layer is 1% by mass or more and 5% by mass or less, and the thicknesses of the first laminate plating layer and the second laminate plating layer are 0.1 μm or more and 0.5 μm or less.

[0169] (Supplementary Note 4) The semiconductor device according to Supplementary Note 2 or 3, wherein a groove is formed on the nickel plating layer on a side opposite to the third surface.

[0170] (Supplementary Note 5) The semiconductor device according to Supplementary Note 4, wherein the side surface of the groove has an uneven shape.

[0171] (Supplementary Note 6) The semiconductor device according to Supplementary Note 4 or 5, wherein the grain boundaries formed in the nickel plating layer are 1 line / μm ２ or more, and 100 pieces / μm ２ and the depth of the groove is 0.1 μm or more and 1.0 μm or less.

[0172] (Supplementary Note 7) The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the plating layer further includes a gold plating layer provided on the side opposite to the third surface.

[0173] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the electrodes are provided on both main surfaces of the semiconductor substrate, and the plating layer is provided on the second surfaces of both of the electrodes.

[0174] (Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the uneven portion has a height difference of 0.1 μm or more and 2 μm or less.

[0175] (Appendix 10) A semiconductor device according to any one of appendices 1 to 9, wherein the plating layer is provided on a portion of the second surface, and the semiconductor device further comprises a protective film provided on the second surface on which the plating layer is not provided, and a surface of the protective film facing the plating layer has a tapered shape of 10° or more and 85° or less.

[0176] (Supplementary Note 11) A power conversion device including the semiconductor device according to any one of Supplementary Notes 1 to 10, and comprising: a conversion circuit that converts input power and outputs the converted power; and a control circuit that outputs a control signal to the conversion circuit for controlling the conversion circuit.

[0177] (Supplementary Note 12) The power conversion device according to Supplementary Note 11, wherein the conversion circuit includes: the semiconductor device; a housing that houses the semiconductor device; external electrodes connected to the semiconductor device; and a sealing resin that is filled in the housing.

[0178] (Supplementary Note 13) A method for manufacturing a semiconductor device, comprising: providing an electrode on a first surface which is at least one main surface of a semiconductor substrate; providing a plating layer on at least a part of a second surface of the electrode which is a surface opposite to a surface in contact with the first surface; forming a concave-convex portion on a side of the plating layer which faces a third surface which is a surface in contact with the second surface; the plating layer is configured by laminating a plurality of nickel plating layers having different nickel concentrations, and providing a gold plating layer on the side opposite to the third surface; the plurality of nickel plating layers include a first laminate plating layer and a second laminate plating layer having a higher nickel concentration than the first laminate plating layer; and forming the concave shape of the concave-convex portion by dissolving the second laminate plating layer more than the first laminate plating layer in a displacement reaction of gold plating when forming the gold plating layer by displacement plating.

[0179] (Appendix 14) The method for manufacturing a semiconductor device according to Appendix 13, wherein when forming the gold plating layer by displacement plating, a gold plating solution is allowed to penetrate to the side of the nickel plating layer opposite the third surface to form a groove.

[0180] (Appendix 15) The method for manufacturing a semiconductor device according to Appendix 14, wherein when the gold plating layer is formed by displacement plating, the second laminate plating layer is dissolved more than the first laminate plating layer in a displacement reaction of the gold plating, and the side surface of the groove portion is formed into an uneven shape.

[0181] 1 Semiconductor element, 1a Semiconductor element, 1b Semiconductor element, 2 Front and back conductive substrate, 3a Front electrode, 3b Back electrode, 4 Plating layer, 4a Plating layer, 4b Plating layer, 5 Nickel plating layer, 5a Nickel plating layer, 6 Gold plating layer, 6a Gold plating layer, 7 Concave and convex portion, 7a Groove portion, 8 Protective film, 9 Solder, 10 External terminal, 11 Heat dissipation substrate, 50 Laminated plating layer, 50a Laminated plating layer, 52 Laminated plating layer, 52a Laminated plating layer, 100 Power module, 101 Semiconductor element, 102 Heat dissipation member, 103 Insulating substrate, 104 Electrode plate, 105 Solder, 106 Main terminal, 107 Signal terminal, 108 Wire, 110 Housing, 112 Sealing resin, 2100 Power supply, 2200 Power conversion device, 2201 Conversion circuit, 2203 control circuit, 2300 load.

Claims

1. A semiconductor device comprising: a semiconductor substrate; an electrode provided on a first surface which is at least one of the main surfaces of the semiconductor substrate; and a plating layer provided on at least a portion of a second surface which is the surface of the electrode opposite to the surface in contact with the first surface, wherein an uneven portion is formed on the side of the plating layer which faces a third surface which is the surface in contact with the second surface.

2. A semiconductor device according to claim 1, wherein the plating layer is formed by laminating a plurality of nickel plating layers having different nickel concentrations, the plurality of nickel plating layers including a first laminate plating layer and a second laminate plating layer having a higher nickel concentration than the first laminate plating layer, and the uneven portion has a concave shape on the side surface corresponding to the second laminate plating layer.

3. A semiconductor device according to claim 2, wherein the nickel concentration of the nickel plating layer is 90% by mass or more and 99% by mass or less, the difference in nickel concentration between the first laminate plating layer and the second laminate plating layer is 1% by mass or more and 5% by mass or less, and the thickness of the first laminate plating layer and the second laminate plating layer is 0.1 μm or more and 0.5 μm or less.

4. A semiconductor device according to claim 2 or 3, wherein a groove is formed on the side of the nickel plating layer opposite to the third surface.

5. A semiconductor device according to claim 4, wherein the side surface of the groove has an uneven shape.

6. The semiconductor device according to claim 4, wherein the grain boundaries formed in the nickel plating layer are 1 line / μm. ２ or more, and 100 pieces / μm ２ and the depth of the groove is 0.1 μm or more and 1.0 μm or less.

7. A semiconductor device according to any one of claims 1 to 3, wherein the plating layer further comprises a gold plating layer provided on the side opposite to the third surface.

8. A semiconductor device according to any one of claims 1 to 3, wherein the electrodes are provided on both main surfaces of the semiconductor substrate, and the plating layer is provided on the second surfaces of both of the electrodes.

9. A semiconductor device according to any one of claims 1 to 3, wherein the height difference of the uneven portion is 0.1 μm or more and 2 μm or less.

10. A semiconductor device according to any one of claims 1 to 3, wherein the plating layer is provided on a portion of the second surface, and further comprising a protective film provided on the second surface where the plating layer is not provided.

11. A semiconductor device according to claim 10, wherein the surface of the protective film facing the plating layer has a tapered shape of 10° or more and 85° or less.

12. A semiconductor device according to claim 10, comprising: solder formed on said side surface; and an external terminal connected to said solder.

13. A semiconductor device according to any one of claims 1 to 3, comprising a gold plating layer containing gold as a main component on the uneven portion formed on the side surface of the plating layer, and the thickness of the gold plating layer is 0.01 μm or more and 1.0 μm or less.

14. A power conversion device comprising a semiconductor device according to any one of claims 1 to 3, a conversion circuit that converts input power and outputs it, and a control circuit that outputs a control signal to the conversion circuit for controlling the conversion circuit.

15. A power conversion device according to claim 14, wherein the conversion circuit comprises: the semiconductor device; a housing that houses the semiconductor device; external electrodes connected to the semiconductor device; and a sealing resin filled in the housing.

16. A method for manufacturing a semiconductor device, comprising: providing an electrode on a first surface which is at least one of the main surfaces of a semiconductor substrate; providing a plating layer on at least a part of a second surface of the electrode which is the surface opposite to the surface in contact with the first surface; forming a concave-convex portion on a side of the plating layer which faces a third surface which is the surface in contact with the second surface; the plating layer being configured by laminating a plurality of nickel plating layers having different nickel concentrations, and providing a gold plating layer on the side opposite to the third surface; the plurality of nickel plating layers including a first laminate plating layer and a second laminate plating layer having a higher nickel concentration than the first laminate plating layer; and forming the concave shape of the concave-convex portion by dissolving the second laminate plating layer more than the first laminate plating layer in a gold plating displacement reaction when the gold plating layer is formed by displacement plating.

17. A method for manufacturing a semiconductor device according to claim 16, wherein when forming the gold plating layer by displacement plating, a gold plating solution is allowed to penetrate to the side of the nickel plating layer opposite the third surface to form a groove.

18. A method for manufacturing a semiconductor device according to claim 17, wherein when the gold plating layer is formed by displacement plating, the second laminated plating layer dissolves more than the first laminated plating layer in a displacement reaction of the gold plating, forming an uneven shape on the side surface of the groove portion.

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