Array substrate and manufacturing method therefor, electronic paper and display apparatus

Abstract

An array substrate (1), which has a display area (AA) and a peripheral area (BB), wherein the peripheral area (BB) comprises a wiring area and a frame area. The frame area is provided with a drive module (111) located in a first side area (B1) and a clearance area (B4) located in a second side area (B2); and the wiring area is provided with a conductive portion (112) located in the second side area (B2) and located at an end portion. In the embodiments of the present disclosure, a conductive portion (112) located in the second side area (B2) is provided in the frame area, so as to improve the space utilization rate on the array substrate (1), and also reduce the region occupied by the wiring area in the second side area (B2), such that a larger region can be freed up to form the clearance area (B4), thereby reducing the influence of a communication module provided in the clearance area (B4) on a drive circuit, etc.

Description

Array substrate, manufacturing method thereof, electronic paper and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof, electronic paper and a display device. BACKGROUND

[0002] Electronic paper, also known as digital paper, is a product combining the display features of ordinary paper and display screens. Existing printed products are mainly realized by paper, and with the rapid increase in paper consumption, great damage has been caused to the environment. In this case, electronic paper has emerged as the times require. The thickness of electronic paper can be comparable to that of ordinary paper, and it can replicate the display features of paper and be reused, so electronic paper is expected to replace existing paper-based file display means in the near future.

[0003] With the continuous development of electronic paper, the design specifications for electronic paper are also required to be higher and higher. For example, electronic price tags are generally about 2-3 inches in size, and when displaying the price of goods, in order to facilitate the unified management of multiple electronic price tags, the electronic price tag includes a communication module arranged on the back of the electronic paper to receive the price of goods through the communication module and display it on the electronic paper.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0005] SUMMARY

[0006] The purpose of the present disclosure is to provide an array substrate, a manufacturing method thereof, electronic paper and a display device.

[0007] According to one aspect of the present disclosure, an array substrate is provided, which has a display area and a peripheral area, the peripheral area including a wiring area and a frame area, the wiring area being located between the display area and the frame area;

[0008] The display area has an array of driving circuits;

[0009] The wiring area has a driving wire, which extends to the display area and is connected to the driving circuit;

[0010] The frame area has a detection line, and the detection line is asymmetrically arranged along the center line parallel to the column direction on the array substrate;

[0011] The peripheral area includes a first side edge area and a second side edge area, the frame area is provided with a driving module located in the first side edge area, and a clearance area is formed in the second side edge area, the driving module is connected with the driving wire, the clearance area accounts for greater than or equal to 55% in the area of the second side edge area, the clearance area is used for setting a communication module, and there is no overlapping area with the detection line, the wire area is provided with one conductive part located in the second side edge area, the conductive part is located at the end of the second side edge area, and the conductive part is connected with the driving module.

[0012] According to any of the array substrates of the present disclosure, the first side edge area and the second side edge area are oppositely distributed along the column direction of the array substrate, and the clearance area accounts for greater than or equal to 65% in the area of the second side edge area.

[0013] The detection line includes a first detection line and a second detection line, the first detection line is located in the overlapping area of the frame area and the first side edge area, and the second detection line is located in the overlapping area of the frame area and the second side edge area.

[0014] The first detection line is connected with the driving module and has a first column break, the second detection line has a second column break, the first column break and the second column break respectively extend to the adjacent side edges on the array substrate along the column direction, and the line connecting the first column break and the second column break is parallel to the column direction, the second detection line has a first row break and a second row break which respectively extend to the two side edges of the array substrate along the row direction of the array substrate, and the line connecting the first row break and the second row break is parallel to the row direction.

[0015] According to any of the array substrates of the present disclosure, the second detection line is asymmetrically arranged along the center line parallel to the column direction on the array substrate.

[0016] According to any of the array substrates of the present disclosure, the second side edge area has a first pair of positioning marks and a second pair of positioning marks which are respectively located on the two sides of the conductive part in the row direction.

[0017] The second detection line has the first row break and the second row break, the end of the second detection line close to the first row break passes through the gap formed by the first pair of positioning marks, and the end of the second detection line close to the second row break is located in the periphery of the second pair of positioning marks.

[0018] According to any of the array substrates of the present disclosure, the first detection line includes a first segment of wire in a U shape, the first segment of wire has a detection end, and the two ends of the first segment of wire form two first column breaks, and the detection end is connected with the driving module.

[0019] The second detection line includes a first sub-detection line and a second sub-detection line, the first sub-detection line and the second sub-detection line are located on both sides of the conductive part in the row direction, the first sub-detection line has the first row break and one of the second column breaks, the second sub-detection line has the second row break and another of the second column breaks, the two second column breaks correspond to the two first column breaks one by one, and the line connecting the corresponding first column break and second column break is parallel to the column direction of the array substrate.

[0020] According to any of the array substrates of the present disclosure, the first segment of the wire includes a first detection wire and a first jumper, the first sub-detection line includes a second detection wire, and the second sub-detection line includes a third detection wire.

[0021] The array substrate includes a gate metal layer, a source-drain metal layer, and an array electrode layer, the gate metal layer and / or the source-drain metal layer has the first detection wire, the second detection wire, and the third detection wire, and the array electrode layer has the first jumper.

[0022] Two ends of the first detection wire respectively form the two first column breaks, one end of the first jumper is connected to the first detection wire through a via hole, and the other end of the first jumper forms the detection end, two ends of the second detection wire respectively form the first row break and one of the second column breaks, and two ends of the third detection wire respectively form the second row break and another of the second column breaks.

[0023] According to any of the array substrates of the present disclosure, the detection line further includes a third detection line, and the third detection line is located in the overlapping area of the frame area and the first side area.

[0024] The first detection line further includes a second segment of the wire, and the second segment of the wire is located on both sides of the third detection line in the row direction of the first segment of the wire.

[0025] The first segment of the wire has a first detection end, the second segment of the wire is connected to the first segment of the wire and has a third row break, the third row break extends to the adjacent side edge of the array substrate in the row direction, the third detection line has a fourth row break and a second detection end, the fourth row break extends to the adjacent side edge of the array substrate in the row direction, the first detection end and the second detection end are both connected to the driving module, and the line connecting the third row break and the fourth row break is parallel to the row direction.

[0026] According to any of the array substrates of the present disclosure, the second segment of the wire includes a fourth detection wire, the third detection line includes a fifth detection wire and a second jumper.

[0027] The array substrate comprises a gate metal layer, a source-drain metal layer and an array electrode layer, the gate metal layer and / or the source-drain metal layer has the fourth detection trace and the fifth detection trace, and the array electrode layer has the second jumper;

[0028] One end of the fourth detection trace is connected with the first segment trace, and the other end constitutes the third row breakage; one end of the fifth detection trace constitutes the fourth row breakage; one end of the second jumper is connected with the fifth detection trace through a via, and the other end of the second jumper constitutes the second detection end.

[0029] The array substrate according to any one of the present disclosure, the first detection line further comprises a third jumper;

[0030] The third jumper is located in the array electrode layer, and both ends of the third jumper are connected with the first detection trace and the fourth detection trace through vias respectively.

[0031] The array substrate according to any one of the present disclosure, one end of the first detection line is connected with the driving module, and the other end constitutes the first column breakage; the second detection line comprises a main trace and a branch trace;

[0032] Both ends of the main trace extend to both side edges of the array substrate along the row direction respectively, and both ends of the main trace form the first row breakage and the second row breakage respectively; one end of the branch trace is connected with the main trace, and the other end of the branch trace extends to a corresponding edge side of the array substrate along the column direction and forms the second column breakage.

[0033] The array substrate according to any one of the present disclosure, the second detection line comprises two groups of branch traces, and the frame area has two groups of first detection lines located in the first side area;

[0034] The two groups of first detection lines are located on both sides of the driving module along the row direction respectively; the first column breakage and the second column breakage corresponding to each first detection line and each branch trace are in one-to-one correspondence respectively, and the connecting line of the corresponding first column breakage and second column breakage is parallel to the column direction.

[0035] The array substrate according to any one of the present disclosure, the main trace comprises a sixth detection trace, the branch trace comprises a fourth jumper, and the first detection line comprises a fifth jumper;

[0036] The array substrate comprises a gate metal layer, a source-drain metal layer and an array electrode layer, the gate metal layer and / or the source-drain metal layer has the sixth detection trace, and the array electrode layer has the fourth jumper wire and the fifth jumper wire;

[0037] Two ends of the sixth detection trace respectively constitute the first row break and the second row break, one end of the fourth jumper wire is connected with the sixth detection trace through a via hole, the other end of the fourth jumper wire constitutes the second column break, one end of the fifth jumper wire constitutes the first column break, and the other end of the fifth jumper wire is connected with the driving module.

[0038] According to the array substrate of any one of the present disclosure, the detection line further comprises a fourth detection line, and the fourth detection line is located in an overlapping area of the frame area and the first side area;

[0039] The second detection line comprises a U-shaped structure and has two second column breaks, the first detection line and the fourth detection line are respectively located on two sides of the driving module along the row direction, the first detection line and the fourth detection line each have one first column break and respectively have the first row break and the second row break.

[0040] According to the array substrate of any one of the present disclosure, the second detection line comprises a trace segment extending along the row direction;

[0041] The trace segment and the driving module have an overlapping area in the column direction, the trace segment is located on one side of the clearance area close to the display area, and the trace segment and the clearance area are located on the same side of the conductive part.

[0042] According to the array substrate of any one of the present disclosure, the second detection line comprises a trace segment extending along the row direction;

[0043] The trace segment and the driving module have an overlapping area in the column direction, the trace segment is located on one side of the clearance area away from the display area, and the trace segment and the conductive part have an overlapping area in the column direction.

[0044] According to the array substrate of any one of the present disclosure, the first side area is adjacent to the second side area, the frame area comprises a third side area, the first side area and the third side area are oppositely distributed along the column direction of the array substrate, and a proportion of the area of the clearance area in the second side area is greater than or equal to 56%;

[0045] The conductive part is located on one side of the second side edge region close to the third side edge region, the detection line includes a fifth detection line, a sixth detection line and a seventh detection line, the fifth detection line and the sixth detection line are located in the overlapping area of the frame region and the first side edge region, and the seventh detection line is located in the overlapping area of the frame region and the third side edge region.

[0046] The driving module includes a first sub-module and a second sub-module, the first sub-module, the second sub-module, the fifth detection line and the sixth detection line are spaced apart along the row direction of the array substrate, the first sub-module is located between the fifth detection line and the sixth detection line, the second sub-module is located on the side of the first sub-module away from the fifth detection line, the fifth detection line is connected with the first sub-module, and the sixth detection line is connected with the second sub-module.

[0047] The fifth detection line and the sixth detection line each have a pair of row breaks extending to the adjacent side edges of the array substrate along the row direction and parallel to the connection line, and / or the seventh detection line has a row break extending to both side edges of the array substrate along the row direction and parallel to the connection line.

[0048] According to any of the array substrates of the present disclosure, the seventh detection line is asymmetrically arranged along the center line of the array substrate parallel to the column direction.

[0049] According to any of the array substrates of the present disclosure, one of the fifth detection line and the sixth detection line, and the seventh detection line each have at least one pair of column breaks extending to the adjacent side edges of the array substrate along the column direction and parallel to the connection line.

[0050] The fifth detection line and the sixth detection line each have a pair of row breaks extending to the adjacent side edges of the array substrate along the row direction and parallel to the connection line, and the seventh detection line has a pair of row breaks extending to both side edges of the array substrate along the row direction and parallel to the connection line.

[0051] According to any of the array substrates of the present disclosure, the fifth detection line includes a third segment of wire and a fourth segment of wire in a U shape, the fourth segment of wire is located between the third segment of wire and the first sub-module, and the sixth detection line is located on the side of the second sub-module away from the first sub-module.

[0052] Two ends of the fourth segment of the wire form two third column breaks extending to the adjacent side edge of the array substrate along the column direction, the third segment of the wire is connected with the fourth segment of the wire and has a fifth row break extending to the adjacent side edge of the array substrate along the row direction, the sixth detection line has a sixth row break extending to the adjacent side edge of the array substrate along the row direction, the seventh detection line has two fourth column breaks extending to the adjacent side edge of the array substrate along the column direction and a seventh row break and an eighth row break extending to the two side edges of the array substrate along the row direction;

[0053] The two third column breaks correspond to the two fourth column breaks, and the line connecting the corresponding third column break and fourth column break is parallel to the column direction, the line connecting the fifth row break and the sixth row break, and the line connecting the seventh row break and the eighth row break are all parallel to the row direction.

[0054] According to any of the array substrates of the present disclosure, the third segment of the wire includes an eighth detection wire and a seventh jumper, the fourth segment of the wire includes a seventh detection wire and a sixth jumper, the sixth detection line includes a ninth detection wire and an eighth jumper, and the seventh detection line includes a tenth detection wire.

[0055] The array substrate includes a gate metal layer, a source-drain metal layer and an array electrode layer, the gate metal layer and / or the source-drain metal layer has the seventh detection wire, the eighth detection wire, the ninth detection wire and the tenth detection wire, and the array electrode layer has the sixth jumper, the seventh jumper and the eighth jumper.

[0056] Two ends of the seventh detection wire form the two third column breaks, two ends of the sixth jumper are connected with the seventh detection wire and the first sub-driving module through vias respectively, one end of the eighth detection wire forms the fifth row break, and two ends of the seventh jumper are connected with the seventh detection wire and the eighth detection wire through vias respectively.

[0057] The eighth detection wire and the ninth detection wire are in the same layer, one end of the ninth detection wire forms the sixth row break, and two ends of the eighth jumper are connected with the ninth detection wire and the second sub-module through vias respectively.

[0058] Two ends of the tenth detection wire form the seventh row break and the eighth row break respectively, the tenth detection wire has a notch, and two ends of the notch form the two fourth column breaks respectively.

[0059] The fifth detection line and the sixth detection line each have a side edge extending to the array substrate along the row direction, and a line connecting the side edges is parallel to the row direction;

[0060] The fifth detection line and the seventh detection line, and the sixth detection line and the seventh detection line each have a side edge extending to the array substrate along the column direction, and at least one pair of column breaks connecting the side edges are parallel to the column direction.

[0061] The fifth detection line includes a fifth segment and a sixth segment, and the sixth detection line includes a seventh segment and an eighth segment, the sixth segment is located between the fifth segment and the first sub-module, the seventh segment is located between the first sub-module and the second sub-module, and the eighth segment is located on a side of the second sub-module away from the seventh segment;

[0062] The fifth segment and the eighth segment each have a fifth row break and a sixth row break extending to a side edge of the array substrate along the row direction, and a line connecting the fifth row break and the sixth row break is parallel to the row direction;

[0063] The fifth segment and the sixth segment each have a third column break extending to a side edge of the array substrate along the column direction, the seventh segment and the eighth segment each have a fifth column break extending to a side edge of the array substrate along the column direction, and the seventh detection line has a plurality of fourth column breaks and a plurality of sixth column breaks extending to side edges of the array substrate along the column direction, a line connecting each third column break and a corresponding fourth column break, and a line connecting each fifth column break and a corresponding sixth column break are parallel to the column direction.

[0064] The sixth detection line is located on a side of the second sub-module away from the first sub-module, and the fifth detection line and the sixth detection line each have an L-shaped structure;

[0065] One end of the fifth detection line forms a third column break extending to a side edge of the array substrate along the column direction, the other end of the fifth detection line forms a fifth row break extending to a side edge of the array substrate along the row direction, one end of the sixth detection line forms a fifth column break extending to a side edge of the array substrate along the column direction, and the other end of the sixth detection line forms a sixth row break extending to a side edge of the array substrate along the row direction;

[0066] The seventh detection line has a U-shaped structure, and two ends of the seventh detection line form a fourth column break and a sixth column break which extend to the adjacent side edges of the array substrate along the column direction respectively;

[0067] The line connecting the third column break and the fourth column break, and the line connecting the fifth column break and the sixth column break are parallel to the column direction, and the line connecting the fifth row break and the sixth row break is parallel to the row direction.

[0068] According to any one of the array substrates of the present disclosure, the seventh detection line has a pair of row breaks which extend to the adjacent side edges of the array substrate along the row direction and are parallel to the row direction;

[0069] The fifth detection line and the seventh detection line, and the sixth detection line and the seventh detection line each have at least one pair of column breaks which extend to the adjacent side edges of the array substrate along the column direction and are parallel to the column direction.

[0070] According to any one of the array substrates of the present disclosure, the sixth detection line is located between the first sub-module and the second sub-module, and the fifth detection line and the sixth detection line each have a U-shaped structure;

[0071] Two ends of the fifth detection line form two third column breaks which extend to the adjacent side edges of the array substrate along the column direction, two ends of the sixth detection line form two fifth column breaks which extend to the adjacent side edges of the array substrate along the column direction, and the seventh detection line has two fourth column breaks and two sixth column breaks which extend to the adjacent side edges of the array substrate along the column direction, and a seventh row break and an eighth row break which extend to the two side edges of the array substrate along the row direction;

[0072] The two third column breaks correspond to the two fourth column breaks, the two fifth column breaks correspond to the two sixth column breaks, the line connecting the corresponding third column break and fourth column break, and the line connecting the corresponding fifth column break and sixth column break are parallel to the column direction, and the line connecting the seventh row break and the eighth row break is parallel to the row direction.

[0073] According to one aspect of the present disclosure, an electronic paper is provided, comprising the array substrate of any one of the above aspects.

[0074] According to one aspect of the present disclosure, a display device is provided, comprising the electronic paper of any one of the above aspects.

[0075] According to one aspect of the present disclosure, a manufacturing method of an array substrate is provided, the method comprising:

[0076] A substrate is provided, the substrate has a plurality of array units, each of the array units comprises a display area and a peripheral area, the peripheral area comprises a trace area and a frame area, the trace area is located between the display area and the frame area;

[0077] A gate metal layer, a semiconductor layer, a source-drain metal layer and a pixel electrode layer are formed on one side of the substrate, and a driving circuit located in the display area, a driving trace located in the trace area and a detection line located in the frame area are formed in each of the array units, the driving trace is connected with the driving circuit, and the detection line is asymmetrically arranged along a center line of the array unit in parallel with a column direction;

[0078] A driving module located in the frame area and a conductive part located in the trace area are arranged on the side of the substrate close to the gate metal layer, the driving module is located in a first side edge area of the peripheral area and connected with the driving trace, the conductive part is located in a second side edge area of the peripheral area and connected with the driving module, the conductive part is located at an end of the second side edge area to form a clearance area in the second side edge area of the frame area, the clearance area has an area ratio of greater than or equal to 55% in the second side edge area and has no overlapping area with the detection line;

[0079] Each of the array units is cut along an edge to obtain a plurality of array substrates.

[0080] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0081] The drawings herein are incorporated into the specification and form part of the specification, show embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0082] Figure 1 is a schematic diagram of the cross-sectional structure of an electronic paper according to an embodiment of the present disclosure.

[0083] Figure 2 is a schematic diagram of the top view structure of an array substrate according to an embodiment of the present disclosure.

[0084] Figure 3 is a schematic diagram of the top view structure of an array mother board according to an embodiment of the present disclosure.

[0085] Figure 4 is a schematic diagram of the top view structure of another array substrate according to an embodiment of the present disclosure.

[0086] Fig. 5 is a schematic plan view of another array substrate according to an embodiment of the present disclosure.

[0087] Fig. 6 is a schematic plan view of a splice corner of the array substrate shown in Fig. 2.

[0088] Fig. 7 is a schematic plan view of a region O of the splice corner shown in Fig. 6.

[0089] Fig. 8 is a schematic plan view of another array substrate according to an embodiment of the present disclosure.

[0090] Fig. 9 is a schematic plan view of a splice corner of the array substrate shown in Fig. 8.

[0091] Fig. 10 is a schematic plan view of a region O of the splice corner shown in Fig. 9.

[0092] Fig. 11 is a schematic sectional view of a bridging region of the array substrate shown in Fig. 8.

[0093] Fig. 12 is a schematic sectional view of a jumper region of the array substrate shown in Fig. 8.

[0094] Fig. 13 is a schematic plan view of a splice corner of the array substrate shown in Fig. 5.

[0095] Fig. 14 is a schematic plan view of a partial region of the splice corner shown in Fig. 13.

[0096] Fig. 15 is a schematic plan view of another array substrate according to an embodiment of the present disclosure.

[0097] Fig. 16 is a schematic plan view of another array substrate according to an embodiment of the present disclosure.

[0098] Fig. 17 is a schematic plan view of an array motherboard corresponding to the array substrate shown in Fig. 4.

[0099] Fig. 18 is a schematic plan view of a region O of the array motherboard shown in Fig. 17.

[0100] Fig. 19 is a schematic sectional view of a bridging region of the array substrate shown in Fig. 4.

[0101] Fig. 20 is a schematic sectional view of a jumper region of the array substrate shown in Fig. 4.

[0102] Fig. 21 is a schematic plan view of an array motherboard corresponding to the array substrate shown in Fig. 16.

[0103] Fig. 22 is a schematic plan view of a region O of the array motherboard shown in Fig. 21.

[0104] Fig. 23 is a schematic plan view of a region O2 of the array motherboard shown in Fig. 22.

[0105] Fig. 24 is an enlarged structural schematic view of region O1 of the array mother substrate shown in Fig. 22.

[0106] Fig. 25 is a top structural schematic view of yet another array substrate provided by an embodiment of the present disclosure.

[0107] Fig. 26 is a top structural schematic view of still another array substrate provided by an embodiment of the present disclosure.

[0108] Reference signs: 10, array mother substrate; 20, detection line; 30, electronic paper; X, row direction; Y, column direction; 1, array substrate; 2, electronic paper film; 3, common electrode layer; 4, protective film; AA, display area; BB, peripheral area; B1, first side edge area; B2, second side edge area; B3, third side edge area; B4, clearance area; 11, substrate substrate; 12, gate metal layer; 13, gate insulating layer; 14, semiconductor layer; 15, source-drain metal layer; 16, planarization layer; 17, pixel electrode layer; 111, drive module; 112, conductive part; 113, first sub-module; 114, second sub-module; 115, flexible circuit board; D1, first positioning mark; D2, second positioning mark; L1, first detection line; L2, second detection line; L3, third detection line; L4, fourth detection line; L5, fifth detection line; L6, sixth detection line; L7, seventh detection line; Y1, first column break; Y2, second column break; Y3, third column break; Y4, fourth column break; Y5, fifth column break; Y6, sixth column break; X1, first row break; X2, second row break; X3, third row break; X4, fourth row break; X5, fifth row break; X6, sixth row break; X7, seventh row break; X8, eighth row break; L11, first segment of wire; L12, second segment of wire; L13, third jumper wire; L14, fifth jumper wire; L111, first detection wire; L112, first jumper wire; L121, fourth detection wire; L21, first sub-detection line; L22, second sub-detection line; L23, main line; L24, branch line; L25, wire segment; L211, second detection wire; L221, third detection wire; L231, sixth detection wire; L241, fourth jumper wire; L31, fifth detection wire; L32, second jumper wire; L51, third segment of wire; L52, fourth segment of wire; L53, fifth segment of wire; L54, sixth segment of wire; L511, eighth detection wire; L512, seventh jumper wire; L521, seventh detection wire; L522, sixth jumper wire; L61, ninth detection wire; L62, eighth jumper wire; L63, seventh segment of wire; L64, eighth segment of wire; L71, tenth detection wire. DETAILED DESCRIPTION

[0109] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any numerous ways, and example implementations should not be construed as limited to having been set forth in the description herein; rather, descriptions herein provide example implementations such that one skilled in the art could make and use example implementations. Identical reference numerals can have been used in different drawings to denote like or similar structures; thus, their detailed description can be omitted. Further, the drawings are merely schematic and viewed from different angles as a matter of illustration.

[0110] Although relative terms such as "upper," "lower," are used herein to describe one component's relationship to another component of a graphic icon, such terms are used herein for convenience only and are not intended to be limiting. It is to be understood that if the device of the graphic icon is turned upside down, the component described as being "upper" would then become the component that is "lower." When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure, or that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure via another structure.

[0111] The terms "one," "a," "an," "the," and "at least one" are used to mean that "one or more" of something is present; the term "or" is used to mean "and / or" both; the term "including" is used to mean "including without limitation"; and the term "have" is used to mean "having at least" and so on. The term "first," "second," and "third," and so on, are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0112] The display device according to the embodiments of the present disclosure mainly includes electronic paper to realize display of a picture through the electronic paper.

[0113] Taking the display device as an electronic price tag for example, the display device includes electronic paper, a communication module, and a single-chip microcomputer. The electronic paper is electrically connected with the communication module and the single-chip microcomputer respectively. When the communication module receives a radio frequency signal (commodity price) sent by a data system, the radio frequency signal is stored in the single-chip microcomputer and is displayed through the electronic paper after being processed by the single-chip microcomputer.

[0114] As shown in FIG. 1, the electronic paper 30 includes an array substrate 1, an electronic paper film 2, a common electrode layer 3, and a protective film 4. The electronic paper film 2 is located between the array substrate 1 and the common electrode layer 3, and the protective film 4 covers the common electrode layer 3.

[0115] The electronic paper film 2 includes a plurality of microstructures, such as micro-cups or micro-capsules, and each microstructure includes a transparent liquid and a plurality of charged particles suspended in the transparent liquid, such as white charged particles and black charged particles, wherein the white charged particles can be negatively charged, and the black charged particles can be positively charged, or the black charged particles can be negatively charged, and the white charged particles can be positively charged.

[0116] The array substrate 1 is provided with a driving module 111, a conductive part 112 (silver glue point, etc.), and a driving circuit. The input end of the driving module 111 is connected to a single-chip microcomputer (such as through a flexible circuit board 115), the output end of the driving module 111 is connected to the conductive part 112 and the driving circuit (such as through a driving trace), and the conductive part 112 is connected to the common electrode layer 3 (such as direct bonding). In this way, the driving module 111 can output a driving signal to the conductive part 112 and the driving circuit under the control of the single-chip microcomputer to form an electric field on both sides of the electronic paper film 2, and then the charged particles in the microstructure are driven to move under the action of the electric field, so that the microstructure presents a corresponding color, and the display of the picture on the electronic paper 30 is realized.

[0117] It should be noted that the communication module included in the display device in the related art is usually arranged on the back of the electronic paper 30 (i.e., the side of the array substrate 1 away from the electronic paper film 2), which undoubtedly increases the thickness of the display device. In the embodiment of the present disclosure, an array substrate 1 is provided, which can reserve a clearance area B4 on the array substrate 1 to provide a mounting space for the communication module, so as to avoid the influence of the communication module on the normal display of the display device while realizing the thinness of the display device.

[0118] FIG. 2 shows a top view structural schematic diagram of an array substrate 1. As shown in FIG. 2, the array substrate 1 has a display area AA and a peripheral area BB, the peripheral area BB includes a trace area (not shown in the figure) and a frame area (not shown in the figure), and the trace area is located between the display area AA and the frame area. The display area AA has an array of driving circuits (not shown in the figure), the trace area has a driving trace (not shown in the figure), the driving trace extends to the display area AA and is connected to the driving circuit. The peripheral area BB includes a first side edge area B1 and a second side edge area B2, the frame area is provided with a driving module 111 located in the first side edge area B1, and a clearance area B4 is formed in the second side edge area B2, the driving module 111 is connected to the driving trace, the clearance area B4 occupies an area ratio of greater than or equal to 55% in the second side edge area B2, and the clearance area B4 is used to arrange a communication module. The trace area is provided with one conductive part 112 located in the second side edge area B2, the conductive part 112 is located at the end of the second side edge area B2, and the conductive part 112 is connected to the driving module 111.

[0119] In the embodiments of the present disclosure, only one conductive part 112 is arranged in the frame area of the array substrate 1 and located at the end of the second side area B2, so as to improve the space utilization of the array substrate 1 and reduce the area of the wiring area in the second side area B2. Thus, a larger area is left in the second side area B2 to form a clearance area B4, so as to reduce the influence of the communication module arranged in the clearance area B4 on the driving circuit and the like.

[0120] The peripheral area BB includes the first side area B1 and the second side area B2, which are respectively the areas between the display area AA on the array substrate 1 and the corresponding side edges of the array substrate 1, and the first side area B1 and the second side area B2 can be two side areas on any two sides of the display area AA on the array substrate 1. The wiring area is the area between the edge of the display area AA on the array substrate 1 and the outermost driving wiring away from the display area AA, and the wiring area can include a plurality of wiring sub-areas, each of which is arranged along the circumference of the display area AA, and the plurality of wiring sub-areas are spaced apart along the circumference of the display area AA. The frame area is the area outside the outermost driving wiring away from the display area AA, and when the wiring area includes a plurality of wiring sub-areas, the frame area includes the area between the adjacent two wiring sub-areas and adjacent to the display area AA. The clearance area B4 is located in the area where the frame area and the second side area B2 of the array substrate 1 overlap, so as to ensure that there is no driving wiring in the clearance area B4, thereby avoiding the interference of the display signal transmitted by the driving wiring with the communication module in the clearance area B4. The area ratio of the clearance area B4 in the second side area B2 can be 55%, 57%, 59%, 62%, 65%, 68%, 70%, 72%, and the like.

[0121] The driving wiring of the wiring area includes a first voltage signal line, a second voltage signal line, a gate line and a data line. One end of the first voltage signal line, the gate line and the data line is extended from the wiring area to the frame area and connected with the driving module 111, and the other end of the first voltage signal line, the gate line and the data line is extended from the wiring area to the display area AA and connected with the driving circuit. One end of the second voltage signal line is connected with the conductive part 112, and the other end of the second voltage signal line is extended from the wiring area to the frame area and connected with the driving module 111.

[0122] The driving circuit includes a switching device (such as a thin film transistor) and a capacitor. The control electrode of the switching device is connected with the gate line for loading a scanning signal, the first electrode of the switching device is connected with the data line for loading a driving signal, and the second plate of the capacitor is connected with the first voltage signal line for loading a first voltage signal. In this way, the gate line can control the switching device to be turned on when the driving circuit loads the scanning signal, and the data line can load the driving signal to the switching device when the driving circuit loads the driving signal, so as to load the voltage on the side of the electronic paper film 2 close to the array substrate 1.

[0123] In some embodiments, as shown in FIG. 1, the array substrate 1 comprises a substrate 11, and sequentially stacked on the substrate 11 are a gate metal layer 12, a gate insulating layer 13, a semiconductor layer 14, a source-drain metal layer 15, a planarization layer 16, and a pixel electrode layer 17.

[0124] The substrate 11 can be a glass substrate, a quartz substrate, a plastic substrate, or other hard or flexible substrate, which can be a single-layer or multi-layer structure. Taking the multi-layer structure as an example, the substrate 11 comprises a first polyimide layer, a first protective layer, a second polyimide layer, and a second protective layer, which are sequentially stacked from bottom to top. The two protective layers are used to protect the polyimide layers from damage caused by subsequent processes. The second protective layer further covers a buffer layer, which can block water and oxygen and block alkali ions.

[0125] The driving wires described above can be a plurality of first voltage signal lines and a plurality of gate lines provided on the gate metal layer 12, and a plurality of data lines and a second voltage signal line provided on the source-drain metal layer 15. The switching devices and the capacitor included in the driving circuit described above can be that the gate metal layer 12 comprises a first conductive part and a second conductive part, the first conductive part forms a control electrode of the switching device, the second conductive part forms a second electrode plate of the capacitor, and the first conductive part is connected with the gate line, and the second conductive part is connected with the first voltage signal line; the semiconductor layer 14 comprises an active part, the active part comprises a channel region coinciding with the first conductive part, and connection parts on both sides of the channel region; the source-drain metal layer 15 comprises a third conductive part, a fourth conductive part, and a fifth conductive part, the third conductive part and the fourth conductive part form a first electrode and a second electrode of the switching device respectively, and the fifth conductive part forms a first electrode plate of the capacitor, the third conductive part and the fourth conductive part directly cover the connection parts on both sides of the channel region of the active part respectively, and the third conductive part is connected with the data line, and the fourth conductive part is connected with the fifth conductive part and the pixel electrode layer 17 respectively.

[0126] In the embodiments of the present disclosure, as shown in FIG. 2, the array substrate 1 is provided with a first positioning mark D1 and a second positioning mark D2 located in the peripheral area BB. One of the first positioning mark D1 and the second positioning mark D2 can be a cross mark, and the cross point of the cross mark is used for positioning, and the other can be an L-shaped mark, and the inner side of the L-shaped mark is used for positioning.

[0127] The first positioning mark D1 can be located in the second side edge area B2 to position the electronic paper film 2 when the electronic paper film 2 is fixed on the array substrate 1; and the second positioning mark D2 can be located in the second side edge area B2 to position the protective film 4 when the protective film 4 is fixed on the side of the common electrode layer 3 away from the array substrate 1. The positions of the first positioning mark D1 and the second positioning mark D2 can be set according to the corner positions of the wiring area in the second side edge area B2, and the first positioning mark D1 is located in the wiring area of the second side edge area B2, and the second positioning mark D2 is located in the frame area of the second side edge area B2, so that after the electronic paper film 2 is fixed on the array substrate 1 and the protective film 4 is fixed on the side of the common electrode layer 3 away from the array substrate 1, the protective film 4 can cover the entire electronic paper film 2, thereby effectively protecting the electronic paper film 2.

[0128] In addition, for the first positioning mark D1 and the second positioning mark D2 on the array substrate 1, one end of the second side edge area B2 can have a first pair of positioning marks including the first positioning mark D1 and the second positioning mark D2, or as shown in FIG. 2, both ends of the second side edge area B2 (the positions of the second side edge area B2 close to the left and right edges in the row direction X of the array substrate 1) can have a first pair of positioning marks including the first positioning mark D1 and the second positioning mark D2, and a second pair of positioning marks. For the case that both ends of the second side edge area B2 have the first positioning mark D1 and the second positioning mark D2, the accuracy of the alignment of the electronic paper film 2 and the protective film 4 can be better guaranteed, and the production yield of the electronic paper 30 can be improved.

[0129] In the embodiment of the present disclosure, as shown in FIG. 3, the array substrate 1 can be obtained by cutting the array mother board 10, and before the array mother board 10 is cut, as shown in FIG. 3, the array mother board 10 has a detection line 20 extending in the row direction X, and the detection line 20 extends to each array substrate 1 and is connected with the driving module 111 included in each array substrate 1.

[0130] In this way, each array substrate 1 can be detected by the multiple rows of detection lines 20 on the array mother board 10, so as to improve the detection efficiency of the array substrate 1 while guaranteeing the production yield of the array substrate 1.

[0131] After the array mother board 10 is cut, the detection line 20 can be located in the frame area of the array substrate 1, that is, the frame area of the array substrate 1 has the detection line 20, and the detection line 20 is asymmetrically arranged along the center line of the array substrate 1 parallel to the column direction Y. In addition, the clearance area B4 and the detection line 20 do not have an overlapping region, that is, the clearance area B4 does not have the detection line 20, so as to avoid the influence of the signal transmitted by the detection line 20 on the communication module arranged in the clearance area B4.

[0132] The detection lines 20 are connected to the driving module 111, so that the detection signals transmitted by the detection lines 20 can be driven by the driving circuit in the display area AA of the array substrate 1 through the driving module 111. Each row of detection lines 20 corresponding to a row of array substrates 1 includes at least four detection lines 20 to realize the transmission of multiple detection signals (first voltage signal, switching signal, scanning signal and data signal). For example, each row of detection lines 20 corresponding to a row of array substrates 1 includes six detection lines 20, two of which transmit the switching signal and the first voltage signal, respectively, and the remaining four detection lines 20 transmit the scanning signals of odd rows and even rows, respectively, and the other two detection lines 20 transmit the data signals of odd columns and even columns, respectively.

[0133] Next, the detection lines 20 on the array motherboard 10 will be explained in combination with a single array substrate 1.

[0134] In order to facilitate the connection of the detection lines 20 and the driving traces in the trace area, the detection lines 20 can extend in the row direction X, so that after the array motherboard 10 is cut, the two side edge areas of the array substrate 1 in the column direction Y can have detection lines 20.

[0135] At this time, in combination with the first side edge area B1 of the array substrate 1 provided with the driving module 111 and the second side edge area B2 provided with the conductive part 112 and the clearance area B4, it can be as shown in FIG. 2 that the first side edge area B1 and the second side edge area B2 are two side edge areas of the array substrate 1 distributed in the column direction Y, or as shown in FIG. 4 that the first side edge area B1 and the second side edge area B2 are two adjacent side edge areas of the array substrate 1 (i.e. the first side edge area B1 is one side edge area of the array substrate 1 in the column direction Y, and the second side edge area B2 is one side edge area of the array substrate 1 in the row direction X).

[0136] For the case where the first side edge area B1 and the second side edge area B2 are distributed in the column direction Y, the area ratio of the clearance area B4 in the second side edge area B2 is greater than or equal to 65%, for example, the area ratio of the clearance area B4 in the second side edge area B2 is 65%, 66%, 67%, 68%, 69%, 70%, 71%, 72%, etc.

[0137] For example, the first side edge region B1 is a lower side edge region, and the second side edge region B2 is an upper side edge region. In this case, the first side edge region B1 refers to a region between the display region AA on the array substrate 1 and a lower side edge of the array substrate 1, and the second side edge region B2 refers to a region between the display region AA on the array substrate 1 and an upper side edge of the array substrate 1. Alternatively, the first side edge region B1 is an upper side edge region, and the second side edge region B2 is a lower side edge region. In this case, the first side edge region B1 refers to a region between the display region AA on the array substrate 1 and an upper side edge of the array substrate 1, and the second side edge region B2 refers to a region between the display region AA on the array substrate 1 and a lower side edge of the array substrate 1.

[0138] In addition, as shown in FIG. 2 or FIG. 5, the detection line 20 includes a first detection line L1 and a second detection line L2. The first detection line L1 is located in a region where the frame region overlaps the first side edge region B1, and the second detection line L2 is located in a region where the frame region overlaps the second side edge region B2. The second detection line L2 and the first detection line L1 are connected to the driving module 111.

[0139] In some embodiments, as shown in FIG. 2 or FIG. 5, the second detection line L2 is asymmetrically arranged along a center line parallel to the column direction Y on the array substrate 1. In this way, by the asymmetrically arranged second detection line L2, the second side edge region B2 is avoided, and a larger clearance region B4 in the second side edge region B2 is ensured.

[0140] Of course, in addition to the asymmetrically arranged second detection line L2, the first detection line L1 can be located on one side of a center line parallel to the column direction Y on the array substrate 1 to achieve asymmetric arrangement of the detection line 20 in the frame region, which is not limited in the embodiments of the present disclosure.

[0141] In some embodiments, as shown in FIG. 2 or FIG. 5, the second detection line L2 includes a wire segment L25 extending along the row direction X, and the wire segment L25 overlaps the driving module 111 in the column direction Y on the array substrate 1. In this way, interference between the detection line 20 and the driving module 111 on the array substrate 10 can be avoided.

[0142] Optionally, as shown in FIG. 5, the wire segment L25 is located on a side of the clearance region B4 away from the display region AA, and the wire segment L25 overlaps the conductive part 112 in the column direction Y. In this case, the clearance region B4 can be formed between the wire segment L25 and the wire region, and a longer wire segment L25 facilitates the formation of a larger clearance region B4, which in turn facilitates the arrangement of the communication module in the clearance region B4.

[0143] Optionally, as shown in FIG. 2, the wire segment L25 is located at the side of the display area AA in the clearance area B4, and the wire segment L25 and the clearance area B4 are located at the same side of the conductive part 112. At this time, the clearance area B4 can be formed at the side of the wire segment L25 away from the display area AA, and the isolation of the wire area and the clearance area B4 can be achieved through the wire segment L25, so as to effectively avoid the influence of the communication module arranged in the clearance area B4.

[0144] In some embodiments, as shown in FIG. 2 or FIG. 5, the first detection line L1 has a first column break Y1, the second detection line L2 has a second column break Y2, the first column break Y1 and the second column break Y2 respectively extend to the adjacent side edges of the array substrate 1 along the column direction Y, i.e. the first column break Y1 and the second column break Y2 are respectively located at the upper edge and the lower edge of the array substrate 1, and the line connecting the first column break Y1 and the second column break Y2 is parallel to the column direction Y; the second detection line L2 has a first row break X1 and a second row break X2 extending to the side edges (left and right edges) of the array substrate 1 along the row direction X of the array substrate 1, and the line connecting the first row break X1 and the second row break X2 is parallel to the row direction X.

[0145] That is, the first detection line L1 has a first column break Y1 extending to the lower edge, and the second detection line L2 has a second column break Y2 extending to the upper edge. Thus, for the array-distributed array substrate 1, the connection between the first column break Y1 and the second column break Y2 on the adjacent two array substrates 1 can realize the bending design of the detection line 20, so as to avoid the case that the straight segment on the detection line 20 is too long. The second detection line L2 has a first row break X1 extending to the left edge and a second row break X2 extending to the right edge. Thus, for the array-distributed array substrate 1, the connection between the first row break X1 and the second row break X2 on the adjacent two array substrates 1 can realize the series connection between the multiple array substrates 1.

[0146] In combination with the above-mentioned case that the second side edge area B2 has the first pair of positioning marks and the second pair of positioning marks, the end of the second detection line L2 close to the first row break X1 can pass through the gap formed by the first pair of positioning marks, i.e. as shown in FIG. 2 or FIG. 5, the end of the second detection line L2 close to the first row break X1 passes through the gap between the first positioning mark D1 and the second positioning mark D2, and includes a right-angle bending structure, and the end of the second detection line L2 close to the second row break X2 is located at the periphery of the second pair of positioning marks. In this way, the interference between the second detection line L2 and the first pair of positioning marks and the second pair of positioning marks can be avoided, and the space utilization of the second detection line L2 can be improved, i.e. the space occupied by the second detection line L2 is reduced, so as to facilitate the increase of the area occupied by the clearance area B4.

[0147] In addition, in combination with the second detection line L2 described above, the trace segment L25 extending along the row direction X is located at the side of the display area AA in the clearance area B4, and the end of the second detection line L2 close to the second row break X2 can pass through the gap between the first positioning mark D1 and the second positioning mark D2 included in the second pair of positioning marks, so as to reduce the distance between the end of the second detection line L2 close to the second row break X2 and the trace area, thereby forming a larger clearance area B4 in the second side edge area B2.

[0148] It should be noted that in combination with the array of one row of detection lines 20 on the array mother board 10 corresponding to each row of array substrates 1, the frame area is provided with a plurality of first detection lines L1 located at the first side edge area B1, and a plurality of second detection lines L2 located at the second side edge area B2, and the number of first detection lines L1 is the same as the number of second detection lines L2, so as to facilitate the connection of the first column break Y1 of the first detection line L1 and the second column break Y2 of the second detection line L2 of the adjacent two array substrates 1.

[0149] In some embodiments, as shown in FIG. 2, the first detection line L1 includes a first segment of trace L11 in the shape of U, the first segment of trace L11 has a detection end, and the two ends of the first segment of trace L11 form two first column breaks Y1, and the detection end is connected with the driving module 111; the second detection line L2 has a first row break X1, a second row break X2 and two second column breaks Y2, the two second column breaks Y2 correspond to the two first column breaks Y1 one by one, and the connection line of the corresponding first column break Y1 and second column break Y2 is parallel to the column direction Y of the array substrate 1.

[0150] In this way, for the two array substrates 1 adjacent along the column direction Y, the connection of the first detection line L1 and the second detection line L2 can be realized through the two first column breaks Y1 of the first detection line L1 and the two second column breaks Y2 of the second detection line L2, and the U-shaped bending design on the detection line 20 is realized.

[0151] Among them, the detection end of the first segment of trace L11 is used to transmit one of the switch signal, the first voltage signal, the scanning signal and the data signal. For example, as shown in FIGS. 6 and 7, the frame area is provided with six first segments of trace L11 located at the first side edge area B1, so as to form six detection ends through the six first segments of trace L11, at this time, two detection ends in the six detection ends are used to respectively transmit the switch signal and the first voltage signal, two detection ends in the remaining four detection ends are used to respectively transmit the scanning signal of the odd row and the even row, and the other two detection ends are used to respectively transmit the data signal of the odd column and the even column.

[0152] Optionally, as shown in FIG. 2, the second detection line L2 includes a first sub-detection line L21 and a second sub-detection line L22, the first sub-detection line L21 and the second sub-detection line L22 are located on both sides of the conductive part 112 in the row direction X; the first sub-detection line L21 has a first row break X1 and one second column break Y2, and the second sub-detection line L22 has a second row break X2 and another second column break Y2. At this time, two array substrates 1 adjacent in the column direction Y can be connected with the two first column breaks Y1 of the first segment of the wire L11 respectively through the second column break Y2 of the first sub-detection line L21 and the second column break Y2 of the second sub-detection line L22, realizing the design of the U-shaped bend on the detection line 20.

[0153] Wherein, the second detection line L2 forms a gap through the first sub-detection line L21 and the second sub-detection line L22, and two second column breaks Y2 are formed through the two ends of the gap (i.e. one end of the first sub-detection line L21 and one end of the second sub-detection line L22). In combination with the above-mentioned case that the second side edge area B2 has a first pair of positioning marks and a second pair of positioning marks, the positional relationship between the first sub-detection line L21 and the first pair of positioning marks, and the positional relationship between the second sub-detection line L22 and the second pair of positioning marks can refer to the positional relationship between the two ends of the second detection line L2 and the first pair of positioning marks and the second pair of positioning marks respectively as described above. For example, the first sub-detection line L21 passes through the gap formed by the first pair of positioning marks, and includes at least one right-angled bend structure, and the end of the second sub-detection line L22 close to the second row break X2 is located on the periphery of the second pair of positioning marks.

[0154] As shown in FIGS. 6 and 7, the first segment of the wire L11 includes a first detection wire L111 and a first jumper L112, the first sub-detection line L21 includes a second detection wire L211, and the second sub-detection line L22 includes a third detection wire L221; in combination with the above-mentioned film layer structure of the array substrate 1, the gate metal layer 12 and / or the source-drain metal layer 15 has the first detection wire L111, the second detection wire L211 and the third detection wire L221, and the array electrode layer has the first jumper L112. The two ends of the first detection wire L111 respectively constitute two first column breaks Y1, one end of the first jumper L112 is connected with the first detection wire L111 through a via, and the other end of the first jumper L112 constitutes a detection end; the two ends of the second detection wire L211 respectively constitute a first row break X1 and one second column break Y2, and the two ends of the third detection wire L221 respectively constitute a second row break X2 and another second column break Y2.

[0155] The first detection wire L111, the second detection wire L211 and the third detection wire L221 can be single-layer wires or double-layer wires, and at least one of the first detection wire L111, the second detection wire L211 and the third detection wire L221 is a wire in the same layer, so as to facilitate the series connection of the detection lines 20 on the two adjacent array substrates 1. When the first detection wire L111, the second detection wire L211 and the third detection wire L221 are single-layer wires, the first detection wire L111, the second detection wire L211 and the third detection wire L221 can be single-layer wires of the gate metal layer 12. In this way, based on the arrangement of the gate insulating layer 13 and the planarization layer 16, the distance between the communication module and the detection line 20 in the thickness direction of the array substrate 1 can be increased, and the electrical coupling between the detection line 20 and the communication module can be effectively avoided.

[0156] In some embodiments, as shown in FIG. 8, the detection line 20 further includes a third detection line L3 located in the overlapping area of the frame region and the first side region B1; the first detection line L1 further includes a second segment wire L12 located on both sides of the first segment wire L11 along the row direction X with the third detection line L3; the first segment wire L11 has a first detection end, the second segment wire L12 is connected with the first segment wire L11 and has a third row break X3 extending to the adjacent side edge (left edge) of the array substrate 1 along the row direction X, the third detection line L3 has a fourth row break X4 extending to the adjacent side edge (right edge) of the array substrate 1 along the row direction X and a second detection end, the first detection end and the second detection end are connected with the driving module 111, and the connection line of the third row break X3 and the fourth row break X4 is parallel to the row direction X.

[0157] In this way, the first detection end can be arranged on the first segment wire L11, and the second detection end can be arranged on the third detection line L3, so as to realize the dispersed arrangement of multiple detection ends and avoid the mutual influence of multiple detection ends due to the concentration. For example, as shown in FIG. 8, the frame region is provided with six first detection lines L1 and six third detection lines L3 in the first side region B1, so as to form three first detection ends through three first segment wires L11 in the six first segment wires L11 and form three second detection ends through three third detection lines L3 in the six third detection lines L3. At this time, the three first detection ends are used to transmit the switch signal, the even row scan signal and the even column data signal respectively, and the three second detection ends are used to transmit the first voltage signal, the odd row scan signal and the odd column data signal respectively.

[0158] In combination with the above-mentioned case that the detection lines 20 are asymmetrically arranged along the middle line parallel to the column direction Y on the array substrate 1, when the detection lines further include a third detection line L3, in addition to the second detection line L2 being asymmetrically arranged, the first detection line L1 and the third detection line L3 can also be asymmetrically arranged about the middle line parallel to the column direction Y on the array substrate 1, so as to achieve the asymmetric arrangement of the detection lines 20 in the frame area, and the present disclosure does not limit this.

[0159] As shown in FIGS. 9 and 10, the second segment of the wiring L12 includes a fourth detection wiring L121, and the third detection line L3 includes a fifth detection wiring L31 and a second jumper L32; in combination with the above-mentioned film layer structure of the array substrate 1, the gate metal layer 12 and / or the source-drain metal layer 15 have the fourth detection wiring L121 and the fifth detection wiring L31, and the array electrode layer has the second jumper L32; one end of the fourth detection wiring L121 is connected to the first segment of the wiring L11 (the first detection wiring L111), and the other end constitutes a third row of breaks X3; one end of the fifth detection wiring L31 constitutes a fourth row of breaks X4; one end of the second jumper L32 is connected to the fifth detection wiring L31 through a via, and the other end of the second jumper L32 constitutes a second detection end.

[0160] The fourth detection wiring L121 and the fifth detection wiring L31 can be single-layer wiring or double-layer wiring, and at least one of the fourth detection wiring L121 and the fifth detection wiring L31 includes a same-layer wiring, so as to facilitate the series connection of the detection lines 20 on two adjacent array substrates 1. When the fourth detection wiring and the fifth detection wiring L31 are single-layer wiring, the fourth detection wiring L121 and the fifth detection wiring L31 can be single-layer wiring of the gate metal layer 12. In this way, based on the arrangement of the gate insulating layer 13 and the planarization layer 16, the distance between the communication module and the detection line 20 in the thickness direction of the array substrate 1 can be increased, and the electrical coupling between the detection line 20 and the communication module can be effectively avoided.

[0161] The fourth detection wiring L121 and the first detection wiring L111 included in the first segment of the wiring L11 can be arranged in the same layer and directly connected, or as shown in FIGS. 10 and 12, the first detection line L1 further includes a third jumper L13, the third jumper L13 is located in the array electrode layer, and the two ends of the third jumper L13 are connected to the first detection wiring L111 and the fourth detection wiring L121 through vias. In this way, by arranging the third jumper L13, the resistance during signal transmission can be increased, the influence of static electricity introduced on the third row of breaks X3 of the first detection wiring L111 can be reduced, the accuracy of detection of the array substrate 1 can be ensured, and the arrangement of the breaks on the first detection line L1 can be reduced.

[0162] In some other embodiments, as shown in FIG. 5, one end of the first detection line L1 is connected with the driving module 111, and the other end constitutes the first column break Y1, and the second detection line L2 includes a main line L23 and a branch line L24; the two ends of the main line L23 extend to the two side edges (left and right edges) of the array substrate 1 along the row direction X, and the two ends of the main line L23 form the first row break X1 and the second row break X2, respectively, and one end of the branch line L24 is connected with the main line L23, and the other end of the branch line L24 extends to the corresponding edge side of the array substrate 1 along the column direction Y, and forms the second column break Y2.

[0163] In this way, the two ends of the main line L23 constitute the first row break X1 and the second row break X2, respectively, so as to further reduce the number of breaks of the detection line 20, and to reduce the introduction of static electricity at the breaks of the detection line 20.

[0164] In some other embodiments, as shown in FIG. 13 and FIG. 14, the main line L23 includes a sixth detection line L231, the branch line L24 includes a fourth jumper L241, and the first detection line L1 includes a fifth jumper L14; in combination with the film layer structure of the array substrate 1, the gate metal layer 12 and / or the source-drain metal layer 15 has the sixth detection line L231, and the array electrode layer has the fourth jumper L241 and the fifth jumper L14; the two ends of the sixth detection line L231 constitute the first row break X1 and the second row break X2, respectively, one end of the fourth jumper L241 is connected with the sixth detection line L231 through a via, the other end of the fourth jumper L241 constitutes the second column break Y2, one end of the fifth jumper L14 constitutes the first column break Y1, and the other end of the fifth jumper L14 is connected with the driving module 111.

[0165] In some other embodiments, as shown in FIG. 13 and FIG. 14, the main line L23 includes a sixth detection line L231, the branch line L24 includes a fourth jumper L241, and the first detection line L1 includes a fifth jumper L14; in combination with the film layer structure of the array substrate 1, the gate metal layer 12 and / or the source-drain metal layer 15 has the sixth detection line L231, and the array electrode layer has the fourth jumper L241 and the fifth jumper L14; the two ends of the sixth detection line L231 constitute the first row break X1 and the second row break X2, respectively, one end of the fourth jumper L241 is connected with the sixth detection line L231 through a via, the other end of the fourth jumper L241 constitutes the second column break Y2, one end of the fifth jumper L14 constitutes the first column break Y1, and the other end of the fifth jumper L14 is connected with the driving module 111.

[0166] In some other embodiments, as shown in FIG. 14, the second detection line L2 includes two groups of branch lines L24, and the frame area has two groups of first detection lines L1 located in the first side edge area B1; the two groups of first detection lines L1 are located on the two sides of the driving module 111 along the row direction X, respectively, and the first column break Y1 of each group of first detection lines L1 corresponds to the second column break Y2 of each group of branch lines L24, and the connecting line of the corresponding first column break Y1 and second column break Y2 is parallel to the column direction Y. In this way, the connection of the two groups of first detection lines L1 and the driving module 111 is facilitated, and the wiring arrangement of the first detection line L1 is simplified.

[0167] In the embodiments of the present disclosure, in addition to the second detection line L2 having the first row of breaks X1 and the second row of breaks X2 to realize the series connection of the plurality of array substrates 1 in the row direction X, the series connection of the plurality of array substrates 1 in the row direction X can also be realized by other manners.

[0168] In some embodiments, as shown in FIG. 15, the detection line 20 further includes a fourth detection line L4 located in the overlapping area of the frame area and the first side area B1; the second detection line L2 has a U-shaped structure and has two second column breaks Y2; the first detection line L1 and the fourth detection line L4 are respectively located on the two sides of the driving module 111 in the row direction X, and the first detection line L1 and the fourth detection line L4 each have one first column break Y1 and respectively have the first row of breaks X1 and the second row of breaks X2.

[0169] In the embodiments of the present disclosure, in addition to the second detection line L2 having the first row of breaks X1 and the second row of breaks X2 to realize the series connection of the plurality of array substrates 1 in the row direction X, the series connection of the plurality of array substrates 1 in the row direction X can also be realized by other manners.

[0170] In the embodiments of the present disclosure, in addition to the second detection line L2 having the first row of breaks X1 and the second row of breaks X2 to realize the series connection of the plurality of array substrates 1 in the row direction X, the series connection of the plurality of array substrates 1 in the row direction X can also be realized by other manners.

[0171] In the embodiments of the present disclosure, in addition to the second detection line L2 having the first row of breaks X1 and the second row of breaks X2 to realize the series connection of the plurality of array substrates 1 in the row direction X, the series connection of the plurality of array substrates 1 in the row direction X can also be realized by other manners.

[0172] For the case that the first side edge region B1 and the second side edge region B2 are adjacent, the area ratio of the clearance region B4 in the second side edge region B2 is greater than or equal to 65%, for example, the area ratio of the clearance region B4 in the second side edge region B2 is 65%, 66%, 67%, 68%, 69%, 70%, etc.

[0173] For example, the first side edge region B1 is the lower side edge region, and the second side edge region B2 is the right side edge region, at this time, the first side edge region B1 refers to the region between the display region AA on the array substrate 1 and the lower side edge of the array substrate 1, and the second side edge region B2 refers to the region between the display region AA on the array substrate 1 and the right side edge of the array substrate 1; or the first side edge region B1 is the upper side edge region, and the second side edge region B2 is the left side edge region, at this time, the first side edge region B1 refers to the region between the display region AA on the array substrate 1 and the upper side edge of the array substrate 1, and the second side edge region B2 refers to the region between the display region AA on the array substrate 1 and the left side edge of the array substrate 1.

[0174] In addition, as shown in FIG. 4 or FIG. 16, the frame region includes a third side edge region B3, the first side edge region B1 and the third side edge region B3 are relatively distributed along the column direction Y of the array substrate 1, and the conductive part 112 is located on one side of the second side edge region B2 close to the third side edge region B3; the detection line 20 includes a fifth detection line L5, a sixth detection line L6 and a seventh detection line L7, the fifth detection line L5 and the sixth detection line L6 are located in the overlapping region of the frame region and the first side edge region B1, and the seventh detection line L7 is located in the overlapping region of the frame region and the third side edge region B3; the driving module 111 includes a first sub-module 113 and a second sub-module 114, the first sub-module 113, the second sub-module 114, the fifth detection line L5 and the sixth detection line L6 are spaced apart along the row direction X of the array substrate 1, the first sub-module 113 is located between the fifth detection line L5 and the sixth detection line L6, the second sub-module 114 is located on one side of the first sub-module 113 away from the fifth detection line L5, the fifth detection line L5 is connected with the first sub-module 113, and the sixth detection line L6 is connected with the second sub-module 114.

[0175] When the first side edge region B is the lower side edge region, the third side edge region B3 is the upper side edge region, and the third side edge region B3 refers to the region between the display region AA on the array substrate 1 and the upper side edge of the array substrate 1; when the first side edge region B is the upper side edge region, the third side edge region B3 is the lower side edge region, and the third side edge region B3 refers to the region between the display region AA on the array substrate 1 and the lower side edge of the array substrate 1.

[0176] In this way, the detection lines 20 (fifth detection line L5, sixth detection line L6, seventh detection line L7) are arranged in the first side edge area B1 and the third side edge area B3 to save the space of the second side edge area B2, and further increase the area of the clearance area B4 on the basis of the second side edge area B2 having only one conductive part 112, so as to reduce the influence of the communication module arranged in the clearance area B4 on the driving circuit and the like.

[0177] The fifth detection line L5, the sixth detection line L6, and the seventh detection line L7 can all be multiple detection lines 20, and the number of detection lines 20 is completely the same. The multiple fifth detection lines L5, the multiple sixth detection lines L6, and the multiple seventh detection lines L7 all include switch detection lines 20, voltage detection lines 20, data detection lines 20, and scanning detection lines 20, and the switch detection lines 20 and the scanning detection lines 20 in the multiple fifth detection lines L5 are connected with the first sub-module 113 (such as a source sub-module). The switch detection lines 20, the voltage detection lines 20, and the data detection lines 20 in the multiple sixth detection lines L6 are connected with the second sub-module 114 (such as a gate sub-module). At this time, the switch detection lines 20 and the scanning detection lines 20 in the multiple fifth detection lines L5 are used to respectively transmit switch signals and scanning signals, and the switch detection lines 20, the voltage detection lines 20, and the data detection lines 20 in the multiple sixth detection lines L6 are used to respectively transmit switch signals, first voltage signals, and data signals.

[0178] For example, the multiple fifth detection lines L5 and the multiple sixth detection lines L6 all include six detection lines 20 (switch detection lines 20, voltage detection lines 20, two data detection lines 20, and two scanning detection lines 20), and three detection lines 20 (switch detection lines 20, two scanning detection lines 20) in the multiple fifth detection lines L5 are used to respectively transmit switch signals, scanning signals of odd-numbered rows, and scanning signals of even-numbered rows. Four detection lines 20 (switch detection lines 20, voltage detection lines 20, two data detection lines 20) in the multiple sixth detection lines L6 are used to respectively transmit switch signals, first voltage signals, data signals of odd-numbered rows, and data signals of even-numbered rows.

[0179] In addition, for the fifth detection line L5, the sixth detection line L6, and the seventh detection line L7 in the first side edge area B1 and the third side edge area B3, the seventh detection line L7 can have a pair of row breaks extending to both side edges of the array substrate 1 along the row direction X and parallel to the row direction X, and / or the fifth detection line L5 and the sixth detection line L6 can each have a row break extending to the adjacent side edge of the array substrate along the row direction and parallel to the row direction. In this way, the seventh detection line L7 can be used to realize the series connection between multiple array substrates 1 through the pair of row breaks, or the fifth detection line L5 and the sixth detection line L6 can be used to realize the series connection between multiple array substrates 1 through the row breaks.

[0180] In some embodiments, as shown in FIG. 4 or FIG. 16, the seventh detection line L7 is asymmetrically arranged along the center line parallel to the column direction Y on the array substrate 1.

[0181] Of course, in addition to the seventh detection line L7 being asymmetrically arranged, the fifth detection line L5 and the sixth detection line L6 can also be asymmetrically arranged along the center line parallel to the column direction Y on the array substrate 1, which is not limited in the embodiments of the present disclosure.

[0182] In some embodiments, as shown in FIG. 4, the fifth detection line L5 and the seventh detection line L7 each have a side edge (lower edge, upper edge) extending to the array substrate 1 along the column direction Y and connected with a column break (third column break Y3 and fourth column break Y4) parallel to the column direction Y, the fifth detection line L5 and the sixth detection line L6 each have a side edge (left edge, right edge) extending to the array substrate 1 along the row direction X and connected with a row break (seventh row break X7 and eighth row break X8) parallel to the row direction X, and the seventh detection line L7 has two side edges (left edge, right edge) extending to the array substrate 1 along the row direction X and connected with a row break (fifth row break X5 and sixth row break X6) parallel to the row direction X.

[0183] In this way, the connection between two adjacent array substrates 1 in the row direction X is realized by the two row breaks of the seventh detection line L7 at the left and right edges of the array substrate 1, and the row breaks of the fifth detection line L5 at the left edge and the row breaks of the sixth detection line L6 at the right edge of the array substrate 1; the connection between two adjacent array substrates 1 in the column direction Y is realized by the column breaks of the fifth detection line L5 and the seventh detection line L7, thereby realizing the connection between the fifth detection line L5, the sixth detection line L6 and the seventh detection line L7 of adjacent array substrates 1, so as to facilitate one-time detection of multiple array substrates 1 and improve the detection efficiency of the array substrate 1.

[0184] Among them, the second sub-module 114 is located between the first sub-module 113 and the sixth detection line L6 to ensure that the sixth detection line L6 has a row break extending to the right edge along the row direction X; the column breaks of the fifth detection line L5 and the seventh detection line L7 can be one or two, etc.

[0185] As an example, the fifth detection line L5 and the seventh detection line L7 each have two column breaks, as shown in FIG. 4, the fifth detection line L5 includes a third segment of the trace L51 and a U-shaped fourth segment of the trace L52, the fourth segment of the trace L52 is located between the third segment of the trace L51 and the first sub-module 113, and the sixth detection line L6 is located on a side of the second sub-module 114 away from the first sub-module 113; the two ends of the fourth segment of the trace L52 form two third column breaks Y3 extending to the adjacent side edge (lower edge) on the array substrate 1 in the column direction Y, the third segment of the trace L51 is connected with the fourth segment of the trace L52 and has a fifth row break X5 extending to the adjacent side edge (left edge) on the array substrate 1 in the row direction X, the sixth detection line L6 has a sixth row break X6 extending to the adjacent side edge (right edge) on the array substrate 1 in the row direction X, and the seventh detection line L7 has two fourth column breaks Y4 extending to the adjacent side edge (upper edge) on the array substrate 1 in the column direction Y, and a seventh row break X7 and an eighth row break X8 extending to the two side edges (left edge and right edge) on the array substrate 1 in the row direction X; the two third column breaks Y3 correspond to the two fourth column breaks Y4, and the connecting line of the corresponding third column break Y3 and the fourth column break Y4 is parallel to the column direction Y, the connecting line of the fifth row break X5 and the sixth row break X6, and the connecting line of the seventh row break X7 and the eighth row break X8 are all parallel to the row direction X.

[0186] In this way, by connecting the two third column breaks Y3 of the third segment of the trace L51 and the fourth segment of the trace L52 with the two fourth column breaks Y4 of the seventh detection line L7, the connection of the adjacent array substrates 1 in the column direction Y is realized, and at the same time, the bending design of the detection line 20 is realized, avoiding the case that the straight line segment on the detection line 20 is too long. In addition, by the fifth row break X5 of the third segment of the trace L51, the sixth row break X6 of the sixth detection line L6, and the seventh row break X7 and the eighth row break X8 of the seventh detection line L7, the connection of the adjacent array substrates 1 in the row direction X is realized, thereby facilitating the one-time detection of multiple array substrates 1.

[0187] Among them, the connection of the third segment of the trace L51 and the fourth segment of the trace L52 can refer to the connection of the first segment of the trace L11 and the second segment of the trace L12 described above, and as an example, the third segment of the trace L51 and the fourth segment of the trace L52 can be connected by a jumper; the two fourth column breaks Y4 of the seventh detection line L7 can refer to the two second column breaks Y2 formed by the second detection line L2 described above; the connection of part of the traces included in the plurality of fourth segments of the trace L52 in the plurality of fifth detection lines L5 and the first sub-module 113, and the connection of part of the detection lines 20 in the plurality of sixth detection lines L6 and the second sub-module 114 can refer to the connection of the first segment of the trace L11, the third detection line L3 and the driving module 111 described above, and the present disclosure will not be repeated here.

[0188] As shown in FIGS. 17 and 18, the third segment of the wiring L51 includes the eighth detection wiring L511 and the seventh jumper L512, the fourth segment of the wiring L52 includes the seventh detection wiring L521 and the sixth jumper L522, the sixth detection line L6 includes the ninth detection wiring L61 and the eighth jumper L62, and the seventh detection line L7 includes the tenth detection wiring L71. In combination with the film layer structure of the array substrate 1 described above, the gate metal layer 12 and / or the source-drain metal layer 15 has the seventh detection wiring L521, the eighth detection wiring L511, the ninth detection wiring L61 and the tenth detection wiring L71, and the array electrode layer has the sixth jumper L522, the seventh jumper L512 and the eighth jumper L62. The two ends of the seventh detection wiring L521 form two third column breaks Y3, the two ends of the sixth jumper L522 are connected to the seventh detection wiring L521 and the first sub-driving module 111 through vias, respectively, one end of the eighth detection wiring L511 forms a fifth row break X5, and the two ends of the seventh jumper L512 are connected to the seventh detection wiring L521 and the eighth detection wiring L511 through vias, respectively. The eighth detection wiring L511 is in the same layer as the ninth detection wiring L61, one end of the ninth detection wiring L61 forms a sixth row break X6, and the two ends of the eighth jumper L62 are connected to the ninth detection wiring L61 and the second sub-module 114 through vias, respectively. The two ends of the tenth detection wiring L71 form a seventh row break X7 and an eighth row break X8, respectively, the tenth detection wiring L71 has a notch, and the two ends of the notch form two fourth column breaks Y4, respectively.

[0189] Since the seventh detection wiring L521, the eighth detection wiring L511 and the ninth detection wiring L61 are all far away from the clearance B4, they can all be set as double-layer wirings to reduce the resistance of signal transmission without affecting the communication module. For example, as shown in FIGS. 19 and 20, the seventh detection wiring L521 and the eighth detection wiring L511 each include double-layer wirings in the gate metal layer 12 and the source-drain metal layer 15, and the connection between the seventh detection wiring L521 and the sixth jumper L522 is shown in FIG. 19, and the connection between the seventh detection wiring L521 and the eighth detection wiring L511 through the seventh jumper L512 is shown in FIG. 20.

[0190] In some other embodiments, the fifth detection line L5 and the sixth detection line L6 each have a row break whose connecting line is parallel to the row direction X, and the fifth detection line L5 and the seventh detection line L7, and the sixth detection line L6 and the seventh detection line L7 each have at least one pair of column breaks whose connecting line is parallel to the column direction Y.

[0191] The sixth detection line L6 is located between the first sub-module 113 and the second sub-module 114, or on the side of the second sub-module 114 away from the first sub-module 113.

[0192] Alternatively, as shown in FIG. 16, the fifth detection line L5 includes a fifth segment L53 and a sixth segment L54, and the sixth detection line L6 includes a seventh segment L63 and an eighth segment L64. The sixth segment L54 is located between the fifth segment L53 and the first sub-module 113, the seventh segment L63 is located between the first sub-module 113 and the second sub-module 114, and the eighth segment L64 is located on the side of the second sub-module 114 away from the seventh segment L63. The fifth segment L53 and the eighth segment L64 have a fifth row break X5 and a sixth row break X6 extending to the adjacent side edge (left edge or right edge) of the array substrate 1 along the row direction X, respectively. The fifth segment L53 and the sixth segment L54 have a third column break Y3 extending to the adjacent side edge (lower edge) of the array substrate 1 along the column direction Y, respectively. The seventh segment L63 and the eighth segment L64 have a fifth column break Y5 extending to the adjacent side edge (lower edge) of the array substrate 1 along the column direction Y, respectively. The seventh detection line L7 has a plurality of fourth column breaks Y4 and a plurality of sixth column breaks Y6 extending to the adjacent side edge (upper edge) of the array substrate 1 along the column direction Y. The line connecting each third column break Y3 and a corresponding fourth column break Y4, and the line connecting each fifth column break Y5 and a corresponding sixth column break Y6 are parallel to the column direction Y.

[0193] As shown in FIG. 16, the fifth segment L53 and the eighth segment L64 can be L-shaped, the sixth segment L54 and the seventh segment L63 can be U-shaped, the fifth segment L53 is spaced apart from the sixth segment L54, the seventh segment L63 is spaced apart from the eighth segment L64, and the seventh detection line L7 includes three U-shaped segments. At this time, the fifth detection line L5 has three third column breaks Y3, the sixth detection line L6 has three fifth column breaks Y5, and the seventh detection line L7 has three fourth column breaks Y4 and three sixth column breaks Y6.

[0194] Alternatively, the fifth segment L53, the sixth segment L54, the seventh segment L63, and the eighth segment L64 are all L-shaped, and the seventh detection line L7 includes a U-shaped main line L23 and two branch lines L24 located in the U-shaped structure. At this time, the fifth detection line L5 has two third column breaks Y3, the sixth detection line L6 has two fifth column breaks Y5, and the seventh detection line L7 has two fourth column breaks Y4 and two sixth column breaks Y6.

[0195] For example, the fifth segment of the fifth detection line L5 and the sixth segment of the fifth detection line L5 are L-shaped lines, and the fifth segment of the fifth detection line L5 and the sixth segment of the fifth detection line L5 can be spaced apart or integrally arranged, and the present disclosure does not limit the arrangement of the fifth segment of the fifth detection line L5 and the sixth segment of the fifth detection line L5.

[0196] In addition, for the positions of the fifth detection line L5 and the sixth detection line L6 on the film layers on the array substrate 1, for example, the fifth segment of the fifth detection line L5 and the sixth segment of the fifth detection line L5, the fifth segment of the fifth detection line L5 can refer to the eighth detection line L511 described above, and the sixth segment of the fifth detection line L5 can refer to the seventh detection line L521 and the sixth jumper L522 described above; for the positions of the seventh detection line L7 on the film layers on the array substrate 1, the film layer position of the tenth detection line L71 can be referred to, and the present disclosure does not limit the film layer position of the tenth detection line L71.

[0197] It should be noted that the sixth segment of the fifth detection line L5 and the seventh segment of the fifth detection line L5 can refer to the fourth segment of the fifth detection line L52 described above. For example, as shown in FIGS. 21, 22 and 23, the sixth segment of the fifth detection line L5 includes the seventh detection line L521 and the sixth jumper L522; as shown in FIGS. 21, 22 and 24, the seventh segment of the fifth detection line L5 includes the seventh detection line L521 and the sixth jumper L522.

[0198] Alternatively, as shown in FIG. 25, the sixth detection line L6 is located on the side of the second sub-module 114 away from the first sub-module 113, and the fifth detection line L5 and the sixth detection line L6 are both L-shaped structures; one end of the fifth detection line L5 constitutes a third column break Y3 extending to the adjacent side edge on the array substrate 1 in the column direction Y, the other end of the fifth detection line L5 constitutes a fifth row break X5 extending to the adjacent side edge on the array substrate 1 in the row direction X, one end of the sixth detection line L6 constitutes a fifth column break Y5 extending to the adjacent side edge on the array substrate 1 in the column direction Y, and the other end of the sixth detection line L6 constitutes a sixth row break X6 extending to the adjacent side edge on the array substrate 1 in the row direction X.

[0199] The seventh detection line L7 is a U-shaped structure, and the two ends of the seventh detection line L7 respectively constitute a fourth column break Y4 and a sixth column break Y6 extending to the adjacent side edge on the array substrate 1 in the column direction Y; the line connecting the third column break Y3 and the fourth column break Y4, and the line connecting the fifth column break Y5 and the sixth column break Y6 are parallel to the column direction Y, and the line connecting the fifth row break X5 and the sixth row break X6 is parallel to the row direction X.

[0200] The fifth detection line L5 and the sixth detection line L6 are located at positions of the film layers on the array substrate 1. The fifth detection line L5 can refer to the fifth segment L53 described above, and the sixth detection line L6 can refer to the eighth segment L64 described above. The seventh detection line L7 is located at a position of a film layer on the array substrate 1, which can refer to the tenth detection line L71 described above, and the disclosure will not be described again.

[0201] In some other embodiments, the seventh detection line L7 extends to both side edges (left edge and right edge) of the array substrate 1 along the row direction X and has a pair of row breaks parallel to the row direction X. The fifth detection line L5 and the seventh detection line L7, and the sixth detection line L6 and the seventh detection line L7 each have at least one pair of column breaks extending to the adjacent side edge (lower edge and upper edge) of the array substrate 1 along the column direction Y and parallel to the column direction Y.

[0202] The sixth detection line L6 is located between the first sub-module 113 and the second sub-module 114, or on the side of the second sub-module 114 away from the first sub-module 113. The fifth detection line L5 and the sixth detection line L6 can have one or two column breaks.

[0203] Optionally, as shown in FIG. 26, the sixth detection line L6 is located between the first sub-module 113 and the second sub-module 114, and the fifth detection line L5 and the sixth detection line L6 each have a U-shaped structure. The two ends of the fifth detection line L5 form two third column breaks Y3 extending to the adjacent side edge (lower edge) of the array substrate 1 along the column direction Y, the two ends of the sixth detection line L6 form two fifth column breaks Y5 extending to the adjacent side edge (lower edge) of the array substrate 1 along the column direction Y, and the seventh detection line L7 has two fourth column breaks Y4 and two sixth column breaks Y6 extending to the adjacent side edge (upper edge) of the array substrate 1 along the column direction Y, and a seventh row break X7 and an eighth row break X8 extending to both side edges (left edge and right edge) of the array substrate 1 along the row direction X. The two third column breaks Y3 correspond to the two fourth column breaks Y4, and the two fifth column breaks Y5 correspond to the two sixth column breaks Y6. The lines connecting the corresponding third column break Y3 and the fourth column break Y4, and the lines connecting the corresponding fifth column break Y5 and the sixth column break Y6 are parallel to the column direction Y, and the line connecting the seventh row break X7 and the eighth row break X8 is parallel to the row direction X.

[0204] Thus, the connection of the two third column breaks Y3 of the fifth detection line L5 and the two fourth column breaks Y4 of the seventh detection line L7, and the connection of the two fifth column breaks Y5 of the sixth detection line L6 and the two sixth column breaks Y6 of the seventh detection line L7, realize the connection of the adjacent array substrates 1 in the column direction Y, and at the same time realize the multiple bending design of the detection line 20, avoiding the case that the straight line segment on the detection line 20 is too long. In addition, the seventh row break X7 and the eighth row break X8 of the seventh detection line L7 realize the connection of the adjacent array substrates 1 in the row direction X, thereby facilitating the one-time detection of multiple array substrates 1.

[0205] The two fourth column breaks Y4 and the two sixth column breaks Y6 on the seventh detection line L7 can be formed by the second column breaks Y2 of the second detection line L2 described above, that is, the seventh detection line L7 has two notches to form the two fourth column breaks Y4 and the two sixth column breaks Y6 at the ends of the two notches. The connection of part of the detection lines 20 in the plurality of fifth detection lines L5 and the first sub-module 113, and the connection of part of the detection lines 20 in the plurality of sixth detection lines L6 and the second sub-module 114 can be referred to the connection of the first section of the wiring L11, the third detection line L3 and the driving module 111 described above, and the present disclosure will not be repeated here.

[0206] In addition, the positions of the fifth detection line L5 on the film layers of the array substrate 1 can be referred to the seventh detection line L521 and the sixth jumper L522 included in the fourth section of the wiring L52 described above; the positions of the sixth detection line L6 on the film layers of the array substrate 1 can be referred to the ninth detection line L61 and the eighth jumper L62 included in the sixth detection line L6 described above; and the positions of the seventh detection line L7 on the film layers of the array substrate 1 can be referred to the tenth detection line L71 included in the seventh detection line L7 described above, and the present disclosure will not be repeated here.

[0207] In the present disclosure, the array substrate 1 can be manufactured by first manufacturing an array mother board 10 including a plurality of array substrates 1, and then cutting the array mother board 10 to obtain a single array substrate 1. For example, as shown in FIG. 3, the array mother board 10 includes 6 array substrates 1 distributed in 2*3, and the array substrate 1 can be obtained by cutting the array mother board 10.

[0208] In some embodiments, the manufacturing method of the array substrate 1 includes steps S110-S140, and the method is used to manufacture the array substrate 1 described in the above embodiments.

[0209] In step S110, a substrate 11 is provided, the substrate 11 has a plurality of array units, each array unit includes a display area AA and a peripheral area BB, the peripheral area BB includes a trace area and a frame area, the trace area is located between the display area AA and the frame area.

[0210] In step S120, a gate metal layer 12, a semiconductor layer 14, a source-drain metal layer 15 and a pixel electrode layer 17 are formed on one side of the substrate 11, and a driving circuit located in the display area AA, a driving trace located in the trace area and a detection line 20 located in the frame area are formed in each array unit, the driving trace is connected with the driving circuit, and the detection line 20 is asymmetrically arranged along the center line of the array unit which is parallel to the column direction Y.

[0211] In step S130, a driving module 111 located in the frame area and a conductive part 112 located in the trace area are arranged on the side of the substrate 11 close to the gate metal layer 12, the driving module 111 is located in the first side edge area B1 of the peripheral area BB and connected with the driving trace, the conductive part 112 is located in the second side edge area B2 of the peripheral area BB and connected with the driving module 111, the conductive part 112 is located at the end of the second side edge area B2 to form a clearance area B4 in the second side edge area B2 of the frame area, the clearance area B4 occupies an area ratio of greater than or equal to 55% in the second side edge area B2, and does not overlap with the detection line 20.

[0212] In step S140, cutting is performed along the edge of each array unit to obtain a plurality of array substrates 1.

[0213] In this way, by the above steps S110-S140, the space utilization of the array substrate 1 can be improved, the area occupied by the trace area in the second side edge area B2 is reduced, and a larger area in the second side edge area B2 of the frame area is formed to form a larger clearance area B4 in the second side edge area B2 of the frame area, so as to reduce the influence of the communication module arranged in the clearance area B4 on the driving circuit and the like.

[0214] In some embodiments, in step S120, when the gate metal layer 12, the semiconductor layer 14 and the source-drain metal layer 15 are formed on one side of the substrate 11, the detection line 20 extending to the frame area of each array unit can also be formed.

[0215] For example, as shown in FIG. 3, the array mother board 10 has detection lines 20 extending along the row direction X, and the detection lines 20 extend to each array substrate 1. In this way, each array substrate 1 can be detected by the plurality of rows of detection lines 20 on the array mother board 10 before the array mother board 10 is cut, so as to improve the detection efficiency of the array substrate 1 while ensuring the yield of the array substrate 1.

[0216] For the detection lines 20 included in the array substrate 10, specific reference can be made to the detection lines 20 on the array substrate 1 described above, and the disclosure embodiments do not repeat the description here.

[0217] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the concepts disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. An array substrate, wherein, The array substrate has a display area and a peripheral area, the peripheral area includes a wiring area and a frame area, the wiring area is located between the display area and the frame area; The display area has arrayed driving circuits; The wiring area has driving wires, the driving wires extend to the display area and are connected with the driving circuits; The frame area has detection lines, and the detection lines are asymmetrically arranged along a center line parallel to the column direction on the array substrate; The peripheral area includes a first side area and a second side area, the frame area is provided with a driving module located in the first side area, and a clearance area is formed in the second side area, the driving module is connected with the driving wires, the area ratio of the clearance area in the second side area is greater than or equal to 55%, the clearance area is used for arranging a communication module and does not have an overlapping area with the detection lines, and the wiring area is provided with a conductive part located in the second side area, the conductive part is located at the end of the second side area, and the conductive part is connected with the driving module.

2. The array substrate of claim 1, wherein, The first side area and the second side area are oppositely arranged along the column direction of the array substrate, and the area ratio of the clearance area in the second side area is greater than or equal to 65%; The detection lines include first detection lines and second detection lines, the first detection lines are located in the overlapping area of the frame area and the first side area, and the second detection lines are located in the overlapping area of the frame area and the second side area; The first detection lines are connected with the driving module and have first column breaks, the second detection lines have second column breaks, the first column breaks and the second column breaks respectively extend to the adjacent side edges on the array substrate along the column direction, and the line connecting the first column breaks and the second column breaks is parallel to the column direction, the second detection lines have first row breaks and second row breaks which respectively extend to the two side edges of the array substrate along the row direction of the array substrate, and the line connecting the first row breaks and the second row breaks is parallel to the row direction.

3. The array substrate of claim 2, wherein, The second detection lines are asymmetrically arranged along the center line parallel to the column direction on the array substrate.

4. The array substrate of claim 3, wherein, The second side area has a first pair of positioning marks and a second pair of positioning marks which are respectively located on the two sides of the conductive part in the row direction; The second detection lines have the first row breaks and the second row breaks, the end of the second detection lines close to the first row breaks passes through the gap formed by the first pair of positioning marks, and the end of the second detection lines close to the second row breaks is located in the periphery of the second pair of positioning marks.

5. The array substrate of claim 3, wherein, The first detection lines include a first segment of wires in a U shape, the first segment of wires has a detection end, and the two ends of the first segment of wires form two first column breaks, and the detection end is connected with the driving module; The second detection line includes a first sub-detection line and a second sub-detection line, the first sub-detection line and the second sub-detection line are located on both sides of the conductive part in the row direction, the first sub-detection line has the first row break and one of the second column breaks, the second sub-detection line has the second row break and another second column break, the two second column breaks correspond to the two first column breaks one by one, and the line connecting the corresponding first column break and second column break is parallel to the column direction of the array substrate.

6. The array substrate of claim 5, wherein, The first segment of the wire includes a first detection wire and a first jumper, the first sub-detection line includes a second detection wire, and the second sub-detection line includes a third detection wire. The array substrate includes a gate metal layer, a source-drain metal layer, and an array electrode layer, the gate metal layer and / or the source-drain metal layer has the first detection wire, the second detection wire, and the third detection wire, and the array electrode layer has the first jumper. Two ends of the first detection wire respectively form the two first column breaks, one end of the first jumper is connected to the first detection wire through a via, and the other end of the first jumper forms the detection end, two ends of the second detection wire respectively form the first row break and one of the second column breaks, and two ends of the third detection wire respectively form the second row break and another second column break.

7. The array substrate of claim 5, wherein, The detection line further includes a third detection line, and the third detection line is located in the overlapping area of the frame area and the first side area. The first detection line further includes a second segment of wire, and the second segment of wire is located on both sides of the third detection line along the row direction of the first segment of wire. The first segment of wire has a first detection end, the second segment of wire is connected to the first segment of wire and has a third row break, the third row break extends to the adjacent side edge of the array substrate along the row direction, the third detection line has a fourth row break and a second detection end, the fourth row break extends to the adjacent side edge of the array substrate along the row direction, and the first detection end and the second detection end are connected to the driving module. The line connecting the third row break and the fourth row break is parallel to the row direction.

8. The array substrate of claim 7, wherein, The second segment of wire includes a fourth detection wire, and the third detection line includes a fifth detection wire and a second jumper. The array substrate includes a gate metal layer, a source-drain metal layer, and an array electrode layer, the gate metal layer and / or the source-drain metal layer has the fourth detection wire and the fifth detection wire, and the array electrode layer has the second jumper. One end of the fourth detection wire is connected to the first segment of wire, and the other end forms the third row break, one end of the fifth detection wire forms the fourth row break, one end of the second jumper is connected to the fifth detection wire through a via, and the other end of the second jumper forms the second detection end.

9. The array substrate of claim 8, wherein, The first detection line further includes a third jumper. The third jumper is located in the array electrode layer, and two ends of the third jumper are respectively connected to the first detection wire and the fourth detection wire through vias.

10. The array substrate of claim 3, wherein, One end of the first detection line is connected with the driving module, and the other end constitutes the first column breakage; the second detection line comprises a main line and a branch line; Two ends of the main line extend to two side edges of the array substrate along the row direction, and the two ends of the main line form the first row breakage and the second row breakage respectively; one end of the branch line is connected with the main line, and the other end of the branch line extends to a corresponding edge side of the array substrate along the column direction and forms the second column breakage.

11. The array substrate of claim 10, wherein, The second detection line comprises two groups of branch lines, and the frame region has two groups of first detection lines in the first side edge region; Two groups of the first detection lines are respectively located on two sides of the driving module along the row direction, a plurality of first column breakages of each group of the first detection lines correspond to a plurality of second column breakages of each group of the branch lines one by one, and the connecting lines of the corresponding first column breakage and second column breakage are parallel to the column direction.

12. The array substrate of claim 10, wherein, The main line comprises a sixth detection line, the branch line comprises a fourth jumper line, and the first detection line comprises a fifth jumper line; The array substrate comprises a gate metal layer, a source-drain metal layer and an array electrode layer, the gate metal layer and / or the source-drain metal layer has the sixth detection line, and the array electrode layer has the fourth jumper line and the fifth jumper line; Two ends of the sixth detection line form the first row breakage and the second row breakage respectively, one end of the fourth jumper line is connected with the sixth detection line through a via, the other end of the fourth jumper line constitutes the second column breakage, one end of the fifth jumper line constitutes the first column breakage, and the other end of the fifth jumper line is connected with the driving module.

13. The array substrate of claim 2, wherein, The detection line further comprises a fourth detection line, and the fourth detection line is located in the overlapping area of the frame region and the first side edge region; The second detection line comprises a U-shaped structure and has two second column breakages, the first detection line and the fourth detection line are respectively located on two sides of the driving module along the row direction, the first detection line and the fourth detection line each have one first column breakage and have the first row breakage and the second row breakage respectively.

14. The array substrate of any one of claims 2-13, wherein, The second detection line comprises a wire segment extending along the row direction; The wire segment and the driving module have an overlapping area in the column direction, the wire segment is located on one side of the clearance area close to the display area, and the wire segment and the conductive part are located on the same side of the clearance area.

15. The array substrate of any one of claims 2-13, wherein, The second detection line comprises a wire segment extending along the row direction; The wire segment and the driving module have an overlapping area in the column direction, the wire segment is located on one side of the clearance area away from the display area, and the wire segment and the conductive part have an overlapping area in the column direction.

16. The array substrate of claim 1, wherein, The first side edge region is adjacent to the second side edge region, the frame region comprises a third side edge region, the first side edge region and the third side edge region are oppositely distributed along the column direction of the array substrate, and the proportion of the area of the clearance area in the second side edge region is greater than or equal to 56%; The conductive part is located on one side of the second side edge region close to the third side edge region, the detection line includes a fifth detection line, a sixth detection line and a seventh detection line, the fifth detection line and the sixth detection line are located in the overlapping area of the frame region and the first side edge region, and the seventh detection line is located in the overlapping area of the frame region and the third side edge region. The driving module includes a first sub-module and a second sub-module, the first sub-module, the second sub-module, the fifth detection line and the sixth detection line are spaced along the row direction of the array substrate, The first sub-module is located between the fifth detection line and the sixth detection line, the second sub-module is located on the side of the first sub-module away from the fifth detection line, the fifth detection line is connected with the first sub-module, and the sixth detection line is connected with the second sub-module. The fifth detection line and the sixth detection line each have a pair of row breaks extending to the adjacent side edges of the array substrate along the row direction and parallel to the connection line of the row direction, and / or the seventh detection line has a row break extending to both side edges of the array substrate along the row direction and parallel to the connection line of the row direction.

17. The array substrate of claim 16, wherein, The seventh detection line is asymmetrically arranged along the middle line of the array substrate parallel to the column direction.

18. The array substrate of claim 17, wherein, One of the fifth detection line and the sixth detection line, and the seventh detection line each have at least one pair of column breaks extending to the adjacent side edges of the array substrate along the column direction and parallel to the connection line of the column direction. The fifth detection line and the sixth detection line each have a pair of row breaks extending to the adjacent side edges of the array substrate along the row direction and parallel to the connection line of the row direction, and the seventh detection line has a pair of row breaks extending to both side edges of the array substrate along the row direction and parallel to the connection line of the row direction.

19. The array substrate of claim 18, wherein, The fifth detection line includes a third segment of wire and a U-shaped fourth segment of wire, the fourth segment of wire is located between the third segment of wire and the first sub-module, and the sixth detection line is located on the side of the second sub-module away from the first sub-module. Two ends of the fourth segment of wire form two third column breaks extending to the adjacent side edges of the array substrate along the column direction, the third segment of wire is connected with the fourth segment of wire and has a fifth row break extending to the adjacent side edge of the array substrate along the row direction, the sixth detection line has a sixth row break extending to the adjacent side edge of the array substrate along the row direction, and the seventh detection line has two fourth column breaks extending to the adjacent side edges of the array substrate along the column direction, and a seventh row break and an eighth row break extending to both side edges of the array substrate along the row direction. The two third column breaks correspond to the two fourth column breaks, and the connection line of the corresponding third column break and fourth column break is parallel to the column direction, the connection line of the fifth row break and the sixth row break, and the connection line of the seventh row break and the eighth row break are all parallel to the row direction.

20. The array substrate of claim 19, wherein, The third segment of the wire includes an eighth detection wire and a seventh jumper wire, the fourth segment of the wire includes a seventh detection wire and a sixth jumper wire, the sixth detection wire includes a ninth detection wire and an eighth jumper wire, and the seventh detection wire includes a tenth detection wire; The array substrate includes a gate metal layer, a source-drain metal layer, and an array electrode layer, the gate metal layer and / or the source-drain metal layer has the seventh detection wire, the eighth detection wire, the ninth detection wire, and the tenth detection wire, and the array electrode layer has the sixth jumper wire, the seventh jumper wire, and the eighth jumper wire; Two ends of the seventh detection wire constitute two third column breaks, two ends of the sixth jumper wire are connected to the seventh detection wire and the first sub-driving module through vias, one end of the eighth detection wire constitutes a fifth row break, and two ends of the seventh jumper wire are connected to the seventh detection wire and the eighth detection wire through vias; The eighth detection wire and the ninth detection wire are in the same layer, one end of the ninth detection wire constitutes a sixth row break, and two ends of the eighth jumper wire are connected to the ninth detection wire and the second sub-module through vias; Two ends of the tenth detection wire constitute a seventh row break and an eighth row break, respectively, the tenth detection wire has a notch, and two ends of the notch constitute two fourth column breaks, respectively.

21. The array substrate of claim 17, wherein, The fifth detection wire and the sixth detection wire each have a side edge adjacent to the array substrate extending in the row direction, and a row break parallel to the row direction; The fifth detection wire and the seventh detection wire, and the sixth detection wire and the seventh detection wire each have at least one pair of column breaks parallel to the column direction, the column breaks extending to side edges adjacent to the array substrate in the column direction.

22. The array substrate of claim 21, wherein, The fifth detection wire includes a fifth segment of wire and a sixth segment of wire, the sixth detection wire includes a seventh segment of wire and an eighth segment of wire, the sixth segment of wire is located between the fifth segment of wire and the first sub-module, the seventh segment of wire is located between the first sub-module and the second sub-module, and the eighth segment of wire is located on a side of the second sub-module away from the seventh segment of wire; The fifth segment of wire and the eighth segment of wire each have a fifth row break and a sixth row break extending to side edges adjacent to the array substrate in the row direction, respectively, and a line connecting the fifth row break and the sixth row break is parallel to the row direction; The fifth segment of wire and the sixth segment of wire each have a third column break extending to a side edge adjacent to the array substrate in the column direction, the seventh segment of wire and the eighth segment of wire each have a fifth column break extending to a side edge adjacent to the array substrate in the column direction, the seventh detection wire has a plurality of fourth column breaks and a plurality of sixth column breaks extending to side edges adjacent to the array substrate in the column direction, a line connecting each third column break and a corresponding fourth column break, and a line connecting each fifth column break and a corresponding sixth column break are parallel to the column direction.

23. The array substrate of claim 21, wherein, The sixth detection line is located on a side of the second sub-module away from the first sub-module, and the fifth detection line and the sixth detection line both have an L-shaped structure. One end of the fifth detection line constitutes a third column breakage extending to an adjacent side edge of the array substrate along the column direction, and the other end of the fifth detection line constitutes a fifth row breakage extending to an adjacent side edge of the array substrate along the row direction; one end of the sixth detection line constitutes a fifth column breakage extending to an adjacent side edge of the array substrate along the column direction, and the other end of the sixth detection line constitutes a sixth row breakage extending to an adjacent side edge of the array substrate along the row direction. The seventh detection line has a U-shaped structure, and both ends of the seventh detection line respectively constitute a fourth column breakage and a sixth column breakage extending to adjacent side edges of the array substrate along the column direction. The connecting line of the third column breakage and the fourth column breakage, the connecting line of the fifth column breakage and the sixth column breakage are parallel to the column direction, and the connecting line of the fifth row breakage and the sixth row breakage is parallel to the row direction.

24. The array substrate of claim 17, wherein, The seventh detection line has a pair of row breakages extending to adjacent side edges of the array substrate along the row direction, and the connecting line is parallel to the row direction. The fifth detection line and the seventh detection line, and the sixth detection line and the seventh detection line both have at least one pair of column breakages extending to adjacent side edges of the array substrate along the column direction, and the connecting line is parallel to the column direction.

25. The array substrate of claim 24, wherein, The sixth detection line is located between the first sub-module and the second sub-module, and the fifth detection line and the sixth detection line both have a U-shaped structure. Both ends of the fifth detection line constitute two third column breakages extending to adjacent side edges of the array substrate along the column direction, both ends of the sixth detection line constitute two fifth column breakages extending to adjacent side edges of the array substrate along the column direction, and the seventh detection line has two fourth column breakages and two sixth column breakages extending to adjacent side edges of the array substrate along the column direction, and a seventh row breakage and an eighth row breakage extending to both side edges of the array substrate along the row direction. The two third column breakages correspond to the two fourth column breakages, the two fifth column breakages correspond to the two sixth column breakages, and the connecting line of the corresponding third column breakage and fourth column breakage, and the connecting line of the corresponding fifth column breakage and sixth column breakage are both parallel to the column direction, and the connecting line of the seventh row breakage and the eighth row breakage is parallel to the row direction.

26. An electronic paper, wherein, The array substrate of any one of claims 1-25.

27. A display device comprising: The electronic paper of claim 26.

28. A method of manufacturing an array substrate, wherein, The method comprises: providing a substrate substrate, the substrate substrate has a plurality of array units, each array unit includes a display area and a peripheral peripheral area, the peripheral area includes a wiring area and a frame area, the wiring area is located between the display area and the frame area; A gate metal layer, a semiconductor layer, a source-drain metal layer and a pixel electrode layer are formed on one side of the substrate, and a driving circuit in the display area, a driving trace in the trace area and a detection line in the frame area are formed in each array unit, the driving trace is connected with the driving circuit, and the detection line is asymmetrically arranged along the center line of the array unit parallel to the column direction; A driving module in the frame area and a conductive part in the trace area are arranged on the side of the substrate close to the gate metal layer, the driving module is located in the first side edge area of the peripheral area and connected with the driving trace, the conductive part is located in the second side edge area of the peripheral area and connected with the driving module, the conductive part is located at the end of the second side edge area to form a clearance area in the second side edge area of the frame area, the clearance area accounts for greater than or equal to 55% in the area of the second side edge area, and there is no overlapping area with the detection line; Each array unit is cut along the edge to obtain a plurality of array substrates.

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