Semiconductor structure and manufacturing method therefor

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method therefor. The semiconductor structure at least comprises: a bottom conductive layer and a blocking part, wherein the plane where the blocking part is located is located above the plane where the bottom conductive layer is located, and the projections of the blocking part and the bottom conductive layer in a vertical direction have an overlapping region; a three-dimensional structure, wherein the three-dimensional structure comprises a first part and a second part, the top surface of the blocking part is higher than the bottom surface of the second part and lower than or flush with the bottom surface of the first part, and the first part is at least partially located directly above the overlapping region; contact holes and a first conductive layer, wherein the plane where the first conductive layer is located is higher than the top surface of the three-dimensional structure, the contact holes are directly connected to the first conductive layer, the bottom conductive layer is electrically connected to the first conductive layer by means of the contact holes, and the contact holes are located at the side of the first part away from the second part; and a first isolation layer, wherein the first isolation layer is used for filling the region between each contact hole and the three-dimensional structure, and filling the region between different contact holes.

Description

Semiconductor structure and method of manufacturing the same Cross-reference to related applications

[0001] This application claims priority to the Chinese patent application No. 202411133716.9, filed on August 16, 2024, entitled “Semiconductor structure and method of manufacturing the same”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the field of semiconductor, and in particular, to a semiconductor structure and a method of manufacturing the same. BACKGROUND

[0003] In the manufacturing process of a semiconductor structure, a film layer with a specific shape is formed by deposition and etching. However, the specific effect of material deposition and etching is related to the morphology of the target structure, for example, when material deposition is performed on a groove with a high aspect ratio to achieve filling, a hollow gap is easily formed. When the actual effect of material deposition or etching deviates from the expected effect, it may have an impact on the actual performance of the final structure. SUMMARY

[0004] Embodiments of the present application provide a semiconductor structure and a method of manufacturing the same, which at least solve the problem of signal crosstalk between contact holes.

[0005] According to some embodiments of the present application, in one aspect, a semiconductor structure is provided, comprising: a bottom conductive layer and a barrier portion, a plane where the barrier portion is located is above a plane where the bottom conductive layer is located, a projection of the barrier portion and the bottom conductive layer in a vertical direction has an overlapping region; a three-dimensional structure, the three-dimensional structure comprises a first portion and a second portion, a top surface of the barrier portion is higher than a bottom surface of the second portion and is lower than or flush with a bottom surface of the first portion, the first portion is at least partially located directly above the overlapping region; a contact hole and a first conductive layer, a plane where the first conductive layer is located is higher than a top surface of the three-dimensional structure, the contact hole is directly connected with the first conductive layer, the bottom conductive layer is electrically connected with the first conductive layer through the contact hole, the contact hole is located on a side of the first portion away from the second portion; a first isolation layer, the first isolation layer is used to fill a region between the contact hole and the three-dimensional structure and fill a region between different contact holes.

[0006] In some embodiments, the semiconductor structure further comprises: a second conductive layer, the barrier portion belongs to a part of the second conductive layer, the bottom conductive layer is electrically connected with the second conductive layer through a first conductive plug, the second conductive layer is electrically connected with the first conductive layer through the contact hole.

[0007] In some embodiments, the second conductive layer further comprises a signal transmission portion, the signal transmission portion is separated from the barrier portion, the barrier portion is located between the signal transmission portion and the second portion, and the bottom conductive layer is electrically connected to the contact hole through the signal transmission portion.

[0008] In some embodiments, the vertical direction is perpendicular to a first horizontal direction, the semiconductor structure further comprises a plurality of the contact holes arranged along the first horizontal direction and a barrier portion extending along the first horizontal direction, each of the contact holes is electrically connected to the bottom conductive layer through a corresponding second signal line in the signal transmission portion, and the barrier portion is located between the corresponding second signal line and the second portion of any of the contact holes.

[0009] In some embodiments, the vertical direction is perpendicular to a first horizontal direction and a second horizontal direction, the first horizontal direction is perpendicular to the second horizontal direction, the semiconductor structure further comprises a plurality of the contact holes arranged along the first horizontal direction, and the barrier portion comprises a plurality of the barrier blocks arranged along the first horizontal direction, in a projection plane perpendicular to the vertical direction, the plurality of the contact holes and the plurality of the barrier blocks are alternately arranged in the first horizontal direction and staggered in the second horizontal direction.

[0010] In some embodiments, the second conductive layer comprises a plurality of second signal lines, the bottom conductive layer transmits electrical signals to the contact hole through the second signal lines, the second signal lines extend to below the at least part of the first portion, and the barrier portion comprises a part of the second signal lines extending to below the first portion.

[0011] In some embodiments, the second conductive layer further comprises a redundant line, the contact hole is not arranged on the redundant line, and the barrier portion further comprises a part of the redundant line extending to below the first portion.

[0012] In some embodiments, the second conductive layer further comprises a second filling line, a width of the second filling line is smaller than a width of the second signal line, the second filling line is used to balance the density of conductive material in different regions of the second conductive layer, and the barrier portion further comprises a part of the second filling line extending to below the first portion.

[0013] In some embodiments, the barrier portion surrounds the three-dimensional structure.

[0014] In some embodiments, the three-dimensional structure is a capacitor electrode, the capacitor electrode comprises an upper electrode for storing a capacitor, or an upper electrode or a lower electrode for a non-storing capacitor.

[0015] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a method for manufacturing a semiconductor structure, comprising: sequentially forming a bottom conductive layer and a barrier portion, a plane where the barrier portion is located is above a plane where the bottom conductive layer is located, and the barrier portion and the bottom conductive layer have an overlapping region in a vertical direction; forming a three-dimensional structure, the three-dimensional structure comprises a first portion and a second portion, a top surface of the barrier portion is higher than a bottom surface of the second portion and is lower than or flush with a bottom surface of the first portion, and the first portion is at least partially located directly above the overlapping region; forming a first isolation layer, the first isolation layer is used to fill a region above the bottom conductive layer and the barrier portion, a top surface of the first isolation layer is higher than a top surface of the three-dimensional structure, and the first isolation layer is located on a side of the first portion away from the second portion and covers a sidewall of the first portion; and forming a contact hole and a first conductive layer, the contact hole penetrates through the first isolation layer, and the first conductive layer is electrically connected with the bottom conductive layer through the contact hole. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which illustrate some embodiments of the application, but are not limiting of the application, unless otherwise specifically stated herein. In the figures:

[0017] FIG. 1 is a front view of a semiconductor structure according to some embodiments of the present application;

[0018] FIG. 2 is a top view of the semiconductor structure shown in FIG. 1;

[0019] FIG. 3 is a front view of a semiconductor structure;

[0020] FIG. 4 is a top view of the semiconductor structure shown in FIG. 3;

[0021] FIG. 5 is a front view of a semiconductor structure according to some embodiments of the present application;

[0022] FIG. 6 is a front view of a semiconductor structure according to some embodiments of the present application;

[0023] FIG. 7 is a top view corresponding to the semiconductor structure shown in FIG. 6 according to some embodiments of the present application;

[0024] FIG. 8 is a top view corresponding to the semiconductor structure shown in FIG. 6 according to some other embodiments of the present application;

[0025] FIG. 9 is a front view of a semiconductor structure;

[0026] FIG. 10 is a front view of a semiconductor structure according to some embodiments of the present application;

[0027] FIG. 11 is a top view corresponding to the semiconductor structure shown in FIG. 10 according to some embodiments of the present application;

[0028] FIG. 12 is a top view of a semiconductor structure according to some embodiments of the present application;

[0029] FIG. 13 is a top view of a semiconductor structure according to some embodiments of the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application will be described in detail with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are presented in order to make the reader better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0031] FIG. 1 is a front view of a semiconductor structure according to some embodiments of the present application; and FIG. 2 is a top view of the semiconductor structure shown in FIG. 1. Referring to FIGS. 1 and 2, a semiconductor structure includes a bottom conductive layer 21 and a barrier layer 22, the barrier layer 22 is located above the plane of the bottom conductive layer 21, and the projection of the barrier layer 22 on the vertical direction Z has an overlapping region 212 with the bottom conductive layer 21; a three-dimensional structure 20, the three-dimensional structure 20 includes a first part 201 and a second part 202, the top surface of the barrier layer 22 is higher than the bottom surface of the second part 202 and is lower than or flush with the bottom surface of the first part 201, and the first part 201 is at least partially located directly above the overlapping region 212; a contact hole 23 and a first conductive layer 25, the plane of the first conductive layer 25 is higher than the top surface of the three-dimensional structure 20, the contact hole 23 is directly connected to the first conductive layer 25, the bottom conductive layer 21 is electrically connected to the first conductive layer 25 through the contact hole 23, and the contact hole 23 is located on the side of the first part 201 away from the second part 202; and a first isolation layer 265, the first isolation layer 265 is used to fill the area between the contact hole 23 and the three-dimensional structure 20 and to fill the area between different contact holes 23.

[0032] In the embodiments of the present application, by providing the barrier layer 22 and at least partially the three-dimensional structure 20 (i.e., at least partially the first part 201) on the barrier layer 22, the bottom surface position of at least partially the three-dimensional structure 20 is raised, thereby reducing the aspect ratio of this part of the three-dimensional structure 20, avoiding the formation of a recess toward the second part 202 on the sidewall of the first part 201 due to the excessively high aspect ratio, and further avoiding the generation of gaps due to the existence of the recess when the first isolation layer 265 is filled and covers the sidewall of the first part 201, and further avoiding the expansion and transfer of a single gap and the connection between different gaps, and avoiding signal crosstalk or even short circuit between different contact holes due to the existence of the gap.

[0033] Fig. 3 is a front view of a semiconductor structure; Fig. 4 is a top view of the semiconductor structure shown in Fig. 3. Referring to Fig. 3, without the barrier, the side wall of the contact hole 12 is formed with a recess 101 due to the high aspect ratio. The present inventors have found that the recess 101 usually appears in the region of the first portion 201 opposite the bottom portion. When the isolation material is deposited to form the first isolation layer 165, the recess 101 is difficult to fill completely due to the blocking of the upper structure of the recess 101 and the filling angle, etc., and the first void 102 is easily formed. Further, referring to Fig. 4, after the isolation layer 165 is formed, a via hole is usually formed by etching to expose the bottom conductive layer 11, and then the via hole is filled to form the contact hole 12. However, the present inventors have found that in the isolation layer 165, a void is also formed between different via holes, which is referred to as a second void 121. Since the first void 102 can be connected in a sheet in the first horizontal direction 12, and the first void 102 and the second void 121 both have the possibility of expansion, the possibility of the via hole being in communication with one or both of the first void 102 or the second void 121 can occur. When the conductive material is deposited to form the contact hole 12, the first void 102 and the second void 121 can also be filled with part of the conductive material, thereby causing different contact holes 12 to have crosstalk or even short circuit when transmitting electrical signals.

[0034] The embodiments of the present application will be described in more detail with reference to the drawings.

[0035] Referring to Fig. 1, in some embodiments, the bottom conductive layer 21 is connected to the source, drain or gate of a transistor (not shown) in the active region through the second conductive plug 24, and no other conductive layer is arranged below the plane where the bottom conductive layer 21 is located, and the position where the gate of different transistors is located does not meet the definition of "conductive layer" in the present application. The cross-sectional shape of the bottom conductive layer 21 is related to the cross-sectional position of the front view, and the cross-sectional shape can be different at different cross-sectional positions. Referring to Fig. 2, the bottom conductive layer 21 at least includes a plurality of bottom signal lines 211, each of which is connected to a corresponding contact hole 23 for transmitting electrical signals. Although the plurality of bottom signal lines 211 shown in Fig. 2 are a plurality of straight lines with the same length and parallel to each other, in fact, each bottom signal line 211 can have a different length from the adjacent bottom signal line 211, or be a bent line, and there is no parallel restriction between different bottom signal lines 211.

[0036] It should be noted that the "plane" mentioned in the present application, such as the plane of the baffle 22 and the plane of the bottom conductive layer 21, is defined by the bottom surface of the corresponding structure, that is, the plane of a structure refers to the plane in which the bottom surface of the structure is located. In some embodiments, the definition of "conductive layer" is that the conductive layer has a two-dimensional top surface and a bottom surface, that is, the top surfaces of different positions of the conductive layer are flush, and the bottom surfaces of different positions are flush. In addition, the top surface of the baffle 22 is not limited in the embodiments of the present application, and the top surface of the baffle 22 can be a plane or a three-dimensional surface.

[0037] In some embodiments, the projection of the baffle 22 in the vertical direction Z is completely located within the projection of the bottom conductive layer 21, wherein the side edge of the baffle 22 towards the second part 202 can fall within the projection of the bottom conductive layer 22, or can be flush with the side edge of the bottom conductive layer 21 close to the second part 202. In still other embodiments, in the vertical direction Z, the projection of the baffle 22 partially overlaps with the projection of the bottom conductive layer 21, that is, the projection of the side edge of the baffle 22 away from the second part 202 is located within the projection of the bottom conductive layer 21, and the projection of the side edge of the bottom conductive layer 21 close to the second part 202 is located within the projection of the baffle 22.

[0038] In some embodiments, the top surface of the first part 201 is lower than or flush with the top surface of the second part 202. The top surface of the first part 201 being lower than the top surface of the second part 202 can be an actual design, or can be originally designed to be flush, but due to subsequent process reasons, the top surface of the first part 201 is actually lower than or flush with the top surface of the second part 202, for example, the top surface of the first part 201 and the top surface of the second part 202 are continuous surfaces.

[0039] In some embodiments, the semiconductor structure is provided with a second isolation layer 261. The second isolation layer 261 is used to isolate the bottom conductive layer 21 and the transistors in the active region, and also used to support the bottom conductive layer 261. The bottom conductive layer 261 can be obtained by etching a recess with a pre-designed pattern in the second isolation layer 261, and then filling the recess. In other embodiments, the second isolation layer includes a first sub-layer located below the bottom conductive layer and a second sub-layer in the same layer as the bottom conductive layer, that is, the first sub-layer is formed first, then the material is deposited and etched to form the bottom conductive layer 261, and finally the second sub-layer is formed by filling the gap in the bottom conductive layer. All "isolation layers" mentioned in the present application can be composed of multiple sub-layers and can be made by different process methods, and the present application does not limit the actual number of layers and the manufacturing method of any film layer.

[0040] In some embodiments, the bottom conductive layer 21 further comprises bottom redundant lines, which have the same width and material as the bottom signal lines, except that the bottom redundant lines are not electrically connected to any contact hole. In yet some embodiments, the bottom conductive layer further comprises bottom filler lines, which have the same material as the bottom signal lines, but have a width less than or equal to the width of the bottom signal lines, and are not electrically connected to any contact hole. The bottom filler lines serve to balance the density of conductive material in different areas, so that the bottom conductive layer 21 has a relatively even stress distribution. The bottom filler lines and the bottom redundant lines can be formed in the same way as the bottom signal lines.

[0041] In some embodiments, the three-dimensional structure 20 is a conductive structure, and the second portion 202 overlaps the bottom conductive layer 21 in the vertical direction Z. The semiconductor structure further comprises a third isolation layer 262, which is used to isolate the bottom conductive layer 21 and the three-dimensional structure 20. In other embodiments, if the second portion 202 of the three-dimensional structure 20 does not overlap the bottom conductive layer 21 in the vertical direction Z, or if the bottom surface of the second portion 202 of the three-dimensional structure 20 is an insulating material, the third isolation layer 262 can also be omitted. In this application, the "projection" refers to the "orthographic projection".

[0042] It should be noted that the three-dimensional structure 20 in this application can comprise multiple complete film layers, or can comprise both complete film layers and partial structures of some film layers, or can only comprise partial structures of film layers. That is, this application does not limit the material, the number of film layers, or the integrity of the film layers of the three-dimensional structure 20.

[0043] In some embodiments, the semiconductor structure further comprises a fourth isolation layer 263, and the barrier portion 22 is disposed on the fourth isolation layer 263, that is, the top surface of the fourth isolation layer 263 is flush with the bottom surface of the barrier portion 22. The fourth isolation layer 263 serves to adjust the height of the barrier portion 22, and thus adjust the height of at least part of the first portion 201, which is beneficial to avoid the occurrence of a recess on the sidewall of the first portion 201 facing the contact hole 23, and is beneficial to ensure the complete filling of the first isolation layer 265. It should be noted that the fourth isolation layer 263 should not be too thick, otherwise it will affect the thickness of the three-dimensional structure in the second horizontal direction Y, which may cause stress concentration at the bottom of the three-dimensional structure 20 and weak isolation effect. Here, the isolation effect refers to the isolation of the conductive material on the opposite sides of the three-dimensional structure 20 in the second horizontal direction Y, to avoid charge leakage and signal interference.

[0044] In some embodiments, in the vertical direction Z, the thickness of the fourth isolation layer 263 is 1.5% to 5% of the maximum thickness of the three-dimensional structure 20, for example, 2%, 2.5%, 3%, 3.5%, or 4.5%.

[0045] In some embodiments, a fifth isolation layer 264 is further provided in the semiconductor structure, and the fifth isolation layer 264 is used to isolate the barrier 22 and the three-dimensional structure 20. In some embodiments, if the barrier 22 is made of insulating material or the surface of the three-dimensional structure 20 facing the barrier 22 is made of insulating material, the fifth isolation layer can not be provided. It can be understood that, since the fifth isolation layer 264 is provided between the barrier 22 and the second part 202 in the second horizontal direction Y to isolate them, the part of the fifth isolation layer 264 also functions as a barrier, and therefore, in the case where the fifth isolation layer 264 is provided, only part of the first part 201 is located directly above the barrier 22, but the first part 201 is located completely above the fifth isolation layer 264. In the present application, “above” refers to directly above unless otherwise specified.

[0046] FIG. 5 is a front view of a semiconductor structure according to some embodiments of the present application. Referring to FIG. 5, the semiconductor structure further comprises a second conductive layer 37 (the range of the second conductive layer 37 is marked by a dashed box), the barrier 32 is part of the second conductive layer 37, the bottom conductive layer 31 is electrically connected to the second conductive layer 37 through a first conductive plug 38, and the second conductive layer 37 is electrically connected to the first conductive layer 35 through a contact hole 33. In this embodiment, since the second conductive layer 37 is made of conductive material, if the surface of the three-dimensional structure 30 facing the barrier 32 is made of insulating material, the fifth isolation layer 364 can not be provided; otherwise, the fifth isolation layer 364 should be provided. In this embodiment, the fourth isolation layer 363 is provided to adjust the spacing between different conductive layers, which is beneficial to weaken the signal crosstalk between different conductive layers.

[0047] In the embodiment shown in FIG. 5, although the dashed box used to mark the range of the second conductive layer 37 exceeds the side of the barrier 32 facing the second part 302, this is only for the purpose of clearly expressing that the range of the second conductive layer 37 includes the part of the barrier 32. In different embodiments, the side of the second conductive layer 37 facing the second part 302 can be flush with the side of the barrier 32 facing the second part 302, or can be closer to the second part 302 relative to the side of the barrier 32 facing the second part 302. Further, in some embodiments, the side of the barrier 32 facing the second part 302 is the side of the second conductive layer 37 facing the second part 302.

[0048] Fig. 6 is a front view of a semiconductor structure according to some embodiments of the present application. Referring to Fig. 6, the three-dimensional structure 40 includes a first portion 401 and a second portion 402, the second conductive layer 47 further includes a signal transmission portion 472, the signal transmission portion 472 is electrically isolated from the blocking portion 471, the blocking portion 471 is located between the signal transmission portion 472 and the second portion 402, and the bottom conductive layer 41 is electrically connected to the contact hole 43 through the signal transmission portion 472. That is, although the signal transmission portion 472 and the blocking portion 471 belong to the same conductive layer, they are different parts electrically separated from each other, the blocking portion 471 is not electrically connected to the contact hole 43, and the electrical signal is only transmitted between different conductive layers through the signal transmission portion 472. By arranging the signal transmission portion 472 and the blocking portion 471 to be separated from each other, it is beneficial to avoid the three-dimensional structure 40 affecting the electrical signal transmitted in the signal transmission portion 472 through the blocking portion 471, which may be more obvious when the potential of the three-dimensional structure 40 changes.

[0049] Fig. 7 is a top view of a semiconductor structure corresponding to the semiconductor structure shown in Fig. 6 according to some embodiments of the present application. Referring to Fig. 7, the vertical direction Z is perpendicular to the first horizontal direction X, the semiconductor structure further includes a plurality of contact holes 43 arranged along the first horizontal direction X and a blocking portion 471 extending along the first horizontal direction X, each contact hole 43 is electrically connected to the bottom conductive layer (not shown) through the corresponding second signal line in the signal transmission portion 472, and the blocking portion 471 is located between the second signal line corresponding to any contact hole 43 and the second portion 402. By arranging the blocking portion 471 to extend along the first horizontal direction X, it is beneficial to avoid the first gap in the first horizontal direction X, and further avoid the second gap 431 that may exist between the first gap and the adjacent contact hole 43 from being connected, in this way, it is beneficial to avoid or weaken the signal crosstalk between different contact holes. It should be noted that the above-mentioned "different contact holes" include adjacent contact holes and non-adjacent contact holes in the first horizontal direction X.

[0050] FIG. 8 is a top view of the semiconductor structure of FIG. 6, according to some embodiments of the present application. Referring to FIG. 8, the vertical direction Z is perpendicular to the first horizontal direction X and the second horizontal direction Y, and the first horizontal direction X is perpendicular to the second horizontal direction Y. The semiconductor structure further includes a plurality of contact holes 43 arranged along the first horizontal direction X, and the barrier portion 471 includes a plurality of barrier blocks 47a arranged along the first horizontal direction X. In a projection plane perpendicular to the vertical direction Z, the plurality of contact holes 43 and the plurality of barrier blocks 47a are arranged alternately in the first horizontal direction X and staggered in the second horizontal direction Y. In this way, in the case where the barrier portion 471 is not a unitary structure but includes a plurality of barrier blocks separated from each other, the first voids 403 formed between adjacent barrier blocks 47a and the second voids 431 located between adjacent contact holes 43 are staggered in the first horizontal direction X. In this way, it is beneficial to avoid the first voids 403 and the second voids 431 from being connected during expansion, and to avoid different second voids 431 from being connected through the first voids 403, thereby reducing the signal crosstalk between different contact holes 43 caused by the filling of conductive medium in the voids. In addition, by staggering the possible formation regions of the first voids 403 and the second voids 431, it is beneficial to avoid the separation and movement of some first voids 403 during device preparation, so that voids appear in regions that originally have no second voids 431.

[0051] In some embodiments, in a projection plane perpendicular to the vertical direction, the plurality of contact holes and the plurality of barrier blocks are arranged in alignment in the first horizontal direction, i.e., each contact hole has a corresponding barrier block, and the contact hole and the corresponding barrier block are aligned in the first horizontal direction. In this way, it is beneficial to avoid the formation of first voids between the contact holes and the first or second portion, and to avoid the impact of the existence of the first voids on the stress and support strength of the contact holes.

[0052] FIG. 9 is a front view of a semiconductor structure. Referring to FIG. 9, in the case that the semiconductor structure includes the second conductive layer 53 but the second conductive layer 53 does not include the blocking portion, if the distance L1 between the second conductive layer 53 and the three-dimensional structure 50 is in the target range, after the filling of the isolation layer material, a third gap 503 can be formed between the second conductive layer 53 or the first conductive plug 52 and the three-dimensional structure 50, and the third gap 503 can be in communication with the first gap 502 in the recess 501 to form a larger gap, which can affect the support strength of the device. In addition, during the manufacturing of the semiconductor structure, even if the designed distance between the second conductive layer 53 and the three-dimensional structure 50 is not in the target range, due to the fact that, during the formation of the three-dimensional structure 50, part of the to-be-etched portion 504 between the second conductive layer 55 and the three-dimensional structure 50 is not effectively etched, the minimum distance between the three-dimensional structure 50 and the adjacent structure is actually the distance between the three-dimensional structure 50 and the to-be-etched portion 504, which can be smaller than the designed distance and fall within the target range, thereby resulting in the formation of the third gap 503.

[0053] FIG. 10 is a front view of a semiconductor structure provided by some embodiments of the present application. Referring to FIG. 10, the second conductive layer 67 includes a plurality of second signal lines (not shown), and the bottom conductive layer 61 transmits electrical signals through the second signal lines and the contact holes 63. The second signal lines extend to at least below the first portion 601, and the blocking portion 671 includes the part of the second signal lines extending below the first portion 601. The second conductive layer 67 no longer has the layout in which the signal transmission portion and the blocking portion 671 are separated, and thus, the formation process of the second conductive layer 67 is simplified, and the deformation resistance of the blocking portion 671 is enhanced.

[0054] FIG. 11 is a top view of the semiconductor structure of FIG. 10, according to some embodiments of the present application. Referring to FIG. 11, the second conductive layer 67 further includes a redundant line 67b, and the barrier portion 671 further includes a portion of the redundant line 67b extending below the first portion 601. The redundant line 67b is distinguished from the second signal line 67a in that the second signal line 67a is connected to the contact hole 63 and is used to transmit electrical signals, while the redundant line 67b does not have a corresponding contact hole 63 connected thereto and is not used to transmit electrical signals. However, both the second signal line 67a and the redundant line 67b can be connected to the underlying conductive layer through the first conductive plug, and both typically have the same width. The redundant line 67b can be used as an alternative to replace a damaged second signal line, or as a redundancy in layout design to allow the layout design to be applied to different projects. It should be noted that any second signal line that cannot perform the signal transmission function is considered to be a damaged second signal line, including but not limited to a second signal line whose signal transmission path to the underlying conductive layer is disconnected or whose resistance is too large to meet design requirements, a second signal line whose actual length and width are less than the designed length and width, and the like.

[0055] FIG. 12 is a top view of the semiconductor structure of FIG. 10, according to some embodiments of the present application. Referring to FIG. 12, the second conductive layer 67 further includes a filler line 67c, and the barrier portion 671 further includes a portion of the filler line 67c extending below the first portion 601. The filler line 67c has a width smaller than that of the second signal line 67a, and is used to balance the density of the conductive material in different regions of the second conductive layer 67. In some embodiments, only the filler line 67c is provided without the redundant line 67b, or only the redundant line 67b is provided without the filler line 67c.

[0056] In addition, the above-mentioned "conductive material" refers to the second signal line, or the second signal line and the redundant line, depending on whether the redundant line is provided in the embodiment. The filler line 67c can be used not only to balance the density of the conductive material in different regions of the second conductive layer 67c, but also to increase the density of the conductive material in a certain region, for example, in a region where no second signal line and redundant line are provided, the filler line can be extended to at least partially below the first portion to achieve the function of the barrier portion.

[0057] Figure 13 is a top view of a semiconductor structure according to some embodiments of the present application. Referring to Figure 13, the barrier 705 surrounds the three-dimensional structure 70. The barrier 705 surrounding the three-dimensional structure 70 means that the barrier 705 is located on at least two sides of the three-dimensional structure 705, which includes both adjacent sides and opposite sides. The barrier 705 located on any side of the three-dimensional structure 70 can be a continuous structure extending in the same direction as the corresponding part of the three-dimensional structure 70, or can be a separate structure including a plurality of barrier blocks or a part in which a plurality of second signal lines extend below the first part 701. In addition, if the barrier 705 surrounds at least two adjacent sides of the three-dimensional structure 70, the barriers 705 located on the two adjacent sides can be a continuous structure, which is advantageous for simplifying the manufacturing process of the barrier. Figure 13 takes the barrier 705 surrounding the three-dimensional structure 705 as an example, and the barrier 705 includes at least a part in which a plurality of second signal lines 703 extend below the first part 701.

[0058] In some embodiments, referring to Figure 13, the three-dimensional structure 70 is a ring structure. The three-dimensional structure 70 can surround the target structure 704, which is equivalent to the second part 702 surrounding the target structure 704. Further, the three-dimensional structure 704 can also cover the top of the target structure 704. The three-dimensional structure 704 can be a functional structure for shielding or supporting the target structure 704, or can be a partial structure for realizing a specific function together with the target structure 704. In some embodiments, the target structure can be a storage capacitor, and the three-dimensional structure 70 is an upper electrode connected to the upper plate of the storage capacitor.

[0059] In some embodiments, the three-dimensional structure 70 is a capacitor electrode, which includes an upper electrode of a storage capacitor, or an upper electrode or a lower electrode of a non-storage capacitor. The storage capacitor refers to a capacitor connected to a storage transistor in a storage unit, which is commonly used in dynamic random access memory. The gate of the storage transistor is connected to a word line, the source is connected to a bit line, and the drain is connected to the storage capacitor.

[0060] The application further provides a semiconductor structure manufacturing method. Referring to FIG. 1, the semiconductor structure manufacturing method comprises the following steps: sequentially forming a bottom conductive layer 24 and a barrier portion 22, the barrier portion 22 is located above the plane where the bottom conductive layer 24 is located, and the projection of the barrier portion 22 and the bottom conductive layer 24 in the vertical direction Z has an overlapping area 212; forming a three-dimensional structure 20, the three-dimensional structure 20 comprises a first portion 201 and a second portion 202, the top surface of the barrier portion 22 is higher than the bottom surface of the second portion 202 and is lower than or flush with the bottom surface of the first portion 201, and the first portion 201 is at least partially located directly above the overlapping area 212; forming a first isolation layer 265, the first isolation layer 265 is used to fill the area above the bottom conductive layer 24 and the barrier portion 22, the top surface of the first isolation layer 265 is higher than the top surface of the three-dimensional structure 20, the first isolation layer 265 is located on the side of the first portion 201 away from the second portion 202 and covers the sidewall of the first portion 201; forming a contact hole 23 and a first conductive layer 25, the contact hole 23 penetrates through the first isolation layer 265, and the first conductive layer 25 is electrically connected with the bottom conductive layer 24 through the contact hole 23.

[0061] It should be noted that the sequential formation of the bottom conductive layer 24 and the barrier portion 22 only limits that the bottom conductive layer 24 is formed first, and other process steps can be arranged between the step of forming the bottom conductive layer 24 and the step of forming the barrier portion 22, such as forming various isolation layers and the like, which are not limited in the application.

[0062] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the application, therefore the protection scope of the application should be limited by the scope defined in the claims.

Claims

1. A semiconductor structure, comprising: a bottom conductive layer and a barrier, the barrier being located above the plane of the bottom conductive layer, and the projection of the barrier and the bottom conductive layer in a vertical direction having an overlapping region; a three-dimensional structure, the three-dimensional structure comprising a first part and a second part, the top surface of the barrier being higher than the bottom surface of the second part and lower than or flush with the bottom surface of the first part, and the first part being at least partially located directly above the overlapping region; a contact hole and a first conductive layer, the first conductive layer being located above the top surface of the three-dimensional structure, the contact hole being directly connected to the first conductive layer, the bottom conductive layer being electrically connected to the first conductive layer through the contact hole, and the contact hole being located on the side of the first part away from the second part; a first isolation layer, the first isolation layer being used to fill the region between the contact hole and the three-dimensional structure and the region between different contact holes. a second conductive layer, the barrier belonging to a part of the second conductive layer, the bottom conductive layer being electrically connected to the second conductive layer through a first conductive plug, and the second conductive layer being electrically connected to the first conductive layer through the contact hole. The second conductive layer further comprises a signal transmission part, the signal transmission part and the barrier being separated from each other, the barrier being located between the signal transmission part and the second part, and the bottom conductive layer being electrically connected to the contact hole through the signal transmission part. The vertical direction is perpendicular to a first horizontal direction, and the semiconductor structure further comprises a plurality of contact holes arranged along the first horizontal direction and a plurality of barriers extending along the first horizontal direction, each contact hole being electrically connected to the bottom conductive layer through a corresponding second signal line in the signal transmission part, and the barrier being located between the corresponding second signal line of any contact hole and the second part. The vertical direction is perpendicular to a first horizontal direction and a second horizontal direction, the first horizontal direction being perpendicular to the second horizontal direction, and the semiconductor structure further comprises a plurality of contact holes arranged along the first horizontal direction, the barrier comprising a plurality of barrier blocks arranged along the first horizontal direction, in a projection plane perpendicular to the vertical direction, the plurality of contact holes and the plurality of barrier blocks being arranged alternately in the first horizontal direction and offset in the second horizontal direction.

2. The semiconductor structure of claim 1, further comprising: The second conductive layer comprises a plurality of second signal lines, the bottom conductive layer transmitting electrical signals to the contact hole through the second signal lines, the second signal lines extending below the at least part of the first part, and the barrier comprising the part of the second signal lines extending below the first part.

3. The semiconductor structure of claim 2, wherein, The second conductive layer further comprises a redundant line, the contact hole not being arranged on the redundant line, and the barrier further comprising the part of the redundant line extending below the first part.

4. The semiconductor structure of claim 3, wherein, ​ 5. The semiconductor structure of claim 3, wherein, ​ 6. The semiconductor structure of claim 3, wherein, ​ 7. The semiconductor structure of claim 6, wherein, ​ 8. The semiconductor structure of claim 6 or 7, wherein, The second conductive layer further comprises a second filling line, the width of the second filling line is smaller than the width of the second signal line, the second filling line is used for balancing the density of conductive material in different areas of the second conductive layer, and the barrier portion further comprises a portion in which the second filling line extends below the first portion.

9. The semiconductor structure of claim 1, wherein, The barrier portion surrounds the three-dimensional structure.

10. The semiconductor structure of claim 1, wherein, The three-dimensional structure is a capacitor electrode, and the capacitor electrode comprises an upper electrode for storing a capacitor or an upper electrode or a lower electrode for a non-storage capacitor.

11. A method for manufacturing a semiconductor structure, comprising: sequentially forming a bottom conductive layer and a barrier portion, the barrier portion is located above the plane of the bottom conductive layer, and the projection of the barrier portion on the vertical direction has an overlapping area with the bottom conductive layer; forming a three-dimensional structure, the three-dimensional structure comprises a first portion and a second portion, the top surface of the barrier portion is higher than the bottom surface of the second portion and is lower than or flush with the bottom surface of the first portion, and the first portion is at least partially located directly above the overlapping area; forming a first isolation layer, the first isolation layer is used for filling the area above the bottom conductive layer and the barrier portion, the top surface of the first isolation layer is higher than the top surface of the three-dimensional structure, the first isolation layer is located on the side of the first portion away from the second portion and covers the sidewall of the first portion; forming a contact hole and a first conductive layer, the contact hole penetrates through the first isolation layer, and the first conductive layer is electrically connected with the bottom conductive layer through the contact hole.

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