Delay-locked loop and memory

Abstract

The present disclosure provides a delay-locked loop and a memory. The delay-locked loop comprises: a first adjustable delay line configured to delay a first clock signal on the basis of a control code, and output a first delayed clock signal; a second adjustable delay line configured to delay a second clock signal on the basis of the control code, and output a second delayed clock signal; a first clock distribution network configured to transmit the first delayed clock signal to an output port area of a memory; a second clock distribution network configured to transmit the second delayed clock signal to the output port area of the memory; and a multi-phase clock generation circuit electrically connected to the first clock distribution network, and configured to generate a first phase clock signal and a second phase clock signal. When the operating frequency of the memory is greater than or equal to a preset frequency, the second adjustable delay line and the second clock distribution network are disabled; and when the operating frequency of the memory is less than the preset frequency, the multi-phase clock generation circuit is disabled. The present disclosure is at least conducive to reducing power consumption of delay-locked loops and reducing clock jitter.

Description

Delay-locked loop and memory

[0001] The present application claims priority to the Chinese patent application No. 202411133770.3, filed on August 16, 2024, and entitled "Delay-locked loop and memory", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, in particular to a delay-locked loop and a memory. BACKGROUND

[0003] In a storage system, data is usually transmitted in a certain timing. The normal operation of the memory depends on the internal commands and clocks having accurate timing. In a dynamic random access memory (DRAM), a delay-locked loop needs to synchronize and lock four-phase clock signals (i.e., 4 clock signals with a phase difference of 90 degrees) in order to generate a data strobe signal DQS for subsequent sampling processing of a data signal DQ. However, as the operating frequency of the memory increases, the power consumption of the circuit increases, and the internal clock signal may also have a large jitter, resulting in a decrease in signal quality. SUMMARY

[0004] Embodiments of the present disclosure provide a delay-locked loop and a memory, which at least reduce the power consumption of the circuit, reduce the jitter of the clock signal, and improve the quality of the clock signal.

[0005] In a first aspect, embodiments of the present disclosure provide a delay-locked loop applied to a memory, comprising:

[0006] A first adjustable delay line configured to receive a first clock signal and a control code, delay process the first clock signal based on the control code, and output a first delayed clock signal;

[0007] A second adjustable delay line configured to, when the operating frequency of the memory is less than a preset frequency, receive a second clock signal and the control code, delay process the second clock signal based on the control code, and output a second delayed clock signal; and when the operating frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line is disabled;

[0008] A first clock distribution network electrically connected to the first adjustable delay line and configured to receive the first delayed clock signal and transmit it to an output port region of the memory to output a first target clock signal;

[0009] A second clock distribution network is electrically connected with the second adjustable delay line and is configured to receive the second delayed clock signal and transmit the second delayed clock signal to an output port area of the memory to output a second target clock signal when the operating frequency of the memory is less than the preset frequency, the second target clock signal having a preset phase difference with the first target clock signal; the second clock distribution network is disabled when the operating frequency of the memory is greater than or equal to the preset frequency.

[0010] A multiphase clock generation circuit is electrically connected with the first clock distribution network and is configured to receive the first target clock signal and generate at least a first phase clock signal and a second phase clock signal based on the first target clock signal when the operating frequency of the memory is greater than or equal to the preset frequency, the first phase clock signal being in phase with the first target clock signal, and the second phase clock signal having a preset phase difference with the first target clock signal; the multiphase clock generation circuit is disabled when the operating frequency of the memory is less than the preset frequency.

[0011] In some embodiments, the delay-locked loop further includes,

[0012] A replica adjustable delay line is configured to simulate a delay of the first adjustable delay line, receive a replica clock signal, delay the replica clock signal based on the control code, and output a replica delayed clock signal when the operating frequency of the memory is less than the preset frequency; the replica adjustable delay line is disabled when the operating frequency of the memory is greater than or equal to the preset frequency.

[0013] A replica clock distribution network is electrically connected with the replica adjustable delay line and is configured to receive the replica delayed clock signal, simulate a delay of the first clock distribution network, and output a replica target clock signal when the operating frequency of the memory is less than the preset frequency; the replica clock distribution network is disabled when the operating frequency of the memory is greater than or equal to the preset frequency.

[0014] In some embodiments, the delay-locked loop further includes,

[0015] A selection circuit is electrically connected with the multiphase clock generation circuit and the replica clock distribution network and is configured to receive the replica target clock signal and the first phase clock signal, output the replica target clock signal when the operating frequency of the memory is less than the preset frequency, and output the first phase clock signal when the operating frequency of the memory is greater than or equal to the preset frequency.

[0016] In some embodiments, the delay-locked loop further includes,

[0017] a delay simulation circuit electrically connected to the output terminal of the selection circuit, configured to simulate the delay of a clock input path and a clock output path in the memory, and output a feedback clock signal; the clock input path comprises a clock receiver and a frequency divider, and the clock output path comprises an output driver circuit;

[0018] a phase detector electrically connected to the delay simulation circuit, configured to receive the feedback clock signal and a reference clock signal, and output an indication signal based on the phase sequence of the two;

[0019] a control code generation circuit electrically connected to the phase detector, configured to adjust and output the control code based on the indication signal.

[0020] In some embodiments, when the operating frequency of the memory is less than a preset frequency, the phase-locked loop has completed phase locking, and the memory is not performing a read operation, the first adjustable delay line, the second adjustable delay line, the first clock distribution network and the second clock distribution network are disabled, and only the replica adjustable delay line and the replica clock distribution network are enabled.

[0021] In some embodiments, the multiphase clock generation circuit is adjacent to an output port region of the memory.

[0022] In some embodiments, the circuit structures of the first adjustable delay line, the second adjustable delay line and the replica adjustable delay line are the same.

[0023] In some embodiments, the first adjustable delay line, the second adjustable delay line and the replica adjustable delay line each comprise a coarse adjustment delay line, a fine adjustment delay line and a driver.

[0024] In some embodiments, the first adjustable delay line, the second adjustable delay line and the replica adjustable delay line each further comprise a duty cycle correction circuit and a quadrant error correction circuit; when the operating frequency of the memory is greater than or equal to a preset frequency, the duty cycle correction circuit and the quadrant error correction circuit of the first adjustable delay line are disabled; when the operating frequency of the memory is less than the preset frequency, the duty cycle correction circuit and the quadrant error correction circuit of the first adjustable delay line are enabled.

[0025] In some embodiments, the circuit structures of the first clock distribution network, the second clock distribution network and the replica clock distribution network are the same.

[0026] In some embodiments, the first adjustable delay line and the second adjustable delay line are located in a first voltage domain, and the first clock distribution network and the second clock distribution network are located in a second voltage domain; the power supply voltage of the first voltage domain and the power supply voltage of the second voltage domain are the same.

[0027] In some embodiments, the delay-locked loop further comprises:

[0028] a third adjustable delay line configured to, when the operating frequency of the memory is less than the preset frequency, receive a third clock signal and the control code, delay the third clock signal based on the control code, and output a third delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the third adjustable delay line is disabled;

[0029] a fourth adjustable delay line configured to, when the operating frequency of the memory is less than the preset frequency, receive a fourth clock signal and the control code, delay the fourth clock signal based on the control code, and output a fourth delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the fourth adjustable delay line is disabled;

[0030] a third clock distribution network electrically connected to the third adjustable delay line and configured to, when the operating frequency of the memory is less than the preset frequency, receive the third delayed clock signal and transmit it to an output port area of the memory to output a third target clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the third clock distribution network is disabled;

[0031] a fourth clock distribution network electrically connected to the fourth adjustable delay line and configured to, when the operating frequency of the memory is less than the preset frequency, receive the fourth delayed clock signal and transmit it to the output port area of the memory to output a fourth target clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the fourth clock distribution network is disabled;

[0032] wherein the phase difference between the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is 90 degrees in sequence.

[0033] In some embodiments, the clock frequency of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is half of the clock frequency of an initial clock signal received by the memory, wherein the clock frequency of the initial clock signal is equal to the operating frequency of the memory.

[0034] In some embodiments, the delay-locked loop further comprises:

[0035] The mode control circuit is configured to, when the operating frequency of the memory is less than a preset frequency, send the first clock signal to the first adjustable delay line, send the second clock signal to the second adjustable delay line, send the third clock signal to the third adjustable delay line, and send the fourth clock signal to the fourth adjustable delay line; when the operating frequency of the memory is greater than or equal to the preset frequency, only send the first clock signal to the first adjustable delay line; and do not send the second clock signal, the third clock signal, and the fourth clock signal.

[0036] In some embodiments, when the operating frequency of the memory is greater than or equal to a preset frequency, the multi-phase clock generation circuit also generates a third phase clock signal and a fourth phase clock signal; the phases of the first phase clock signal, the second phase clock signal, the third phase clock signal and the fourth phase clock signal are sequentially 90 degrees apart.

[0037] In some embodiments, the output port region of the memory includes a high-order output port region and a low-order output port region; the multi-phase clock generation circuit includes a high-order multi-phase clock generation circuit and a low-order multi-phase clock generation circuit; the high-order multi-phase clock generation circuit is adjacent to the high-order output port region and is configured to provide at least the first phase clock signal and the second phase clock signal to the high-order output port; the low-order multi-phase clock generation circuit is adjacent to the low-order output port region and is configured to provide at least the first phase clock signal and the second phase clock signal to the low-order output port; when one of the high-order output port and the low-order output port is not enabled, the corresponding multi-phase clock generation circuit is disabled.

[0038] In a second aspect, embodiments of this disclosure provide a memory that includes at least the delay phase-locked loop described in the first aspect.

[0039] The technical solutions provided in this disclosure have at least the following advantages:

[0040] When the memory is operating at high speed, i.e., when the operating frequency is greater than or equal to the preset frequency, the second adjustable delay line and the second clock distribution network are turned off, and only the first adjustable delay line and the first clock distribution network are enabled. At least the first phase clock signal and the second phase clock signal are generated through the multi-phase clock generation circuit. This can reduce circuit power consumption, reduce power supply noise, thereby reducing clock jitter and improving the quality of the clock signal. Attached Figure Description

[0041] One or more embodiments are illustrated by way of example in the drawings and described herein in connection with the appended drawings, which are incorporated herein by reference, and in which, unless otherwise noted, like reference numerals refer to like elements throughout the several views and where appropriate the figures themselves have been used to describe the features illustrated. The figures are not necessarily drawn to scale and the dimensions of the various features can have been generalized in order to illustrate clearly the embodiments of the present disclosure. As used herein, the term "or" as used herein, without additional context, can be used to indicate alternative examples or non-limiting examples.

[0042] FIG. 1 is a schematic diagram of a structure of a delay-locked loop (DLL);

[0043] FIG. 2 is a schematic diagram of a structure of a delay-locked loop (DLL) according to an embodiment of the present disclosure;

[0044] FIG. 3 is a schematic diagram of a structure of a delay-locked loop (DLL) according to another embodiment of the present disclosure;

[0045] FIG. 4 is a schematic diagram of a structure of a delay-locked loop (DLL) according to another embodiment of the present disclosure;

[0046] FIG. 5 is a schematic diagram of a structure of a memory according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related application, but not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first", "second", "third" used in the embodiments of the present disclosure are only used to distinguish similar objects, and can be understood that "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0048] Dynamic Random Access Memory (DRAM)

[0049] Synchronous Dynamic Random Access Memory (SDRAM)

[0050] Double Data Rate SDRAM (DDR)

[0051] Low Power DDR (LPDDR)

[0052] DDRn Specification (DDRn), such as DDR3, DDR4, DDR5, DDR6

[0053] LPDDRn Specification (LPDDRn), such as LPDDR3, LPDDR4, LPDDR5, LPDDR6

[0054] Delay Locked Loop (DLL)

[0055] In a memory system, data is usually transmitted with certain timing. The normal operation of a memory relies on the internal commands and clocks to have accurate timing. For example, when a memory receives a read command, it needs to output data from the data port after a desired latency time. When a memory receives a write command, it also needs to receive data from the data port after a desired latency time.

[0056] The above-mentioned desired latency, also known as “latency”, is an important parameter defined in the DRAM design specification. This parameter is configured by the DRAM controller and stored in the register of the DRAM. This parameter specifies that after receiving a read or write command from the DRAM, the data (DQ) and data strobe signal (DQS) need to be transmitted or received after a fixed time interval that is an integer multiple of the clock period. For example, if the read latency (RL) is set to 28, it means that after the DRAM receives a read command, the data (DQ) and data strobe signal (DQS) need to be transmitted after 28 clock periods. The RL can have many settings configured by the DRAM controller. In this disclosure, one clock period, denoted as tck, is the clock period of the initial clock signal CK_t received by the DRAM. The purpose of setting the latency is to meet the timing constraints when the master and slave communicate and to give the DRAM time to prepare data. During the communication between the DRAM and the host, latency errors can cause communication failure or data loss, etc.

[0057] In order to establish timing constraints, the DRAM design specification requires that the latency must be an integer multiple of the clock period (N*tck, N is a positive integer), but in the actual circuit, due to the process, voltage, temperature changes, the actual circuit through the delay is full of uncertain factors, and will be affected by external noise. The designer must convert the actual circuit delay into an integer multiple of the clock period delay, and the operation is achieved by a delay-locked loop.

[0058] Referring to FIG. 1, a structure of a delay-locked loop (DLL) is shown. A clock input buffer (CLK IB) receives an initial clock signal CK_t, and then generates four-phase clock signals CLKI, CLKQ, CLKIB, and CLKQB through a divider. At present, the memory gradually develops towards high speed. For example, due to the speed improvement and process limitation of DDR5, the high-speed clock signal at the interface needs to be converted into a low-speed clock signal internally. Therefore, the phases of CLKI, CLKQ, CLKIB, and CLKQB are sequentially different by 90 degrees, and their frequencies are half of the frequency of the initial clock signal CK_t. Subsequently, the four-phase clock signals CLKI, CLKQ, CLKIB, and CLKQB enter four adjustable delay lines respectively, each of which includes a coarse delay line (CDL), a fine delay line (FDL), a duty cycle corrector (DCC), a quadrant error corrector (QEC), and a driver (DRV). Then, the four-phase clock signals are transmitted to the output port area through four read clock distribution networks (RD CLK CDN) respectively, for sampling processing of data signals DQ. In the figure, LDQ and UDQ represent the output port area of low-bit data and the output port area of high-bit data, respectively. The DLL further includes a replica adjustable delay line for simulating the delay of the above adjustable delay line. The replica adjustable delay line receives CLKI and also includes the same CDL, FDL, DCC+QEC, and DRV modules. The clock signal output from the replica adjustable delay line passes through a read clock distribution network replica (RD CLK CDN Replica) to simulate the delay of the read clock distribution network. The clock signal output from the read clock distribution network replica passes through an input / output replica (I / O Replica) to generate a feedback clock signal FBCLK. A phase detector (PD) compares the phases of a reference clock signal REFCLK and the feedback clock signal FBCLK, and then controls the delay of the CDL and FDL through a delay control module (CDL / FDL Control) so that the phase difference between the reference clock signal REFCLK and the feedback clock signal FBCLK is approximately 0, and the DLL reaches a locked state.Ideally, when the DLL is locked, the rising edges of the reference clock signal REFCLK and the feedback clock signal FBCLK are aligned, and the phase difference between the two is equal to 0. However, in actual situations, as long as the phase difference between REFCLK and FBCLK is approximately 0 within an error tolerance range, the DLL is considered to be in a locked state. CLK1 can be selected as the reference clock signal REFCLK.

[0059] As known from the above, the initial clock signal CK_t enters the delay-locked loop DLL in four paths, four adjustable delay lines, four read clock distribution networks, and the replicated adjustable delay line and the replicated read clock distribution network need to work simultaneously for phase synchronization and locking processing. However, the delay path of this architecture is long, and when the memory works at high speed, the clock signal will jitter. In addition, in this architecture, multiple adjustable delay lines and read clock distribution networks work simultaneously, the circuit power consumption is very large, and additional power supply noise is introduced, further exacerbating the jitter of the clock signal. When the memory works at high speed, the delay between the four paths may not match, causing the phase difference between the four-phase clock signals to deviate, which is not conducive to the subsequent generation of the data strobe signal DQS and the sampling processing of the data signal DQ.

[0060] Based on this, the embodiment of the present disclosure provides a delay-locked loop, which is applied to a memory and includes: a first adjustable delay line configured to receive a first clock signal and a control code, delay process the first clock signal based on the control code, and output a first delay clock signal; a second adjustable delay line configured to, when a working frequency of the memory is less than a preset frequency, receive a second clock signal and the control code, delay process the second clock signal based on the control code, and output a second delay clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line is disabled; a first clock distribution network electrically connected with the first adjustable delay line and configured to receive the first delay clock signal and transmit it to an output port area of the memory to output a first target clock signal; a second clock distribution network electrically connected with the second adjustable delay line and configured to, when the working frequency of the memory is less than the preset frequency, receive the second delay clock signal and transmit it to the output port area of the memory to output a second target clock signal, the phase difference between the second target clock signal and the first target clock signal being a preset value; when the working frequency of the memory is greater than or equal to the preset frequency, the second clock distribution network is disabled; and a multi-phase clock generation circuit electrically connected with the first clock distribution network and configured to, when the working frequency of the memory is greater than or equal to the preset frequency, receive the first target clock signal and generate at least a first phase clock signal and a second phase clock signal based on the first target clock signal, the first phase clock signal being in phase with the first target clock signal, and the phase difference between the second phase clock signal and the first target clock signal being the preset value; when the working frequency of the memory is less than the preset frequency, the multi-phase clock generation circuit is disabled. In this way, when the memory works at a high speed, i.e., the working frequency is greater than or equal to the preset frequency, the second adjustable delay line and the second clock distribution network are closed, only the first adjustable delay line and the first clock distribution network are enabled, and at least the first phase clock signal and the second phase clock signal are generated through the multi-phase clock generation circuit, which can reduce circuit power consumption, reduce power supply noise, thereby reducing clock jitter and improving the quality of the clock signal.

[0061] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0062] In an embodiment of the present disclosure, referring to FIG. 2, a structural schematic diagram of a delay-locked loop 10 provided by the embodiment of the present disclosure is shown. As shown in FIG. 2, the delay-locked loop 10 includes:

[0063] The first adjustable delay line 11 is configured to receive a first clock signal and a control code, delay process the first clock signal based on the control code, and output a first delay clock signal;

[0064] The second adjustable delay line 13 is configured to receive the second clock signal and the control code when the working frequency of the memory is less than the preset frequency, delay process the second clock signal based on the control code, and output a second delayed clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line 13 is disabled.

[0065] The first clock distribution network 12 is electrically connected with the first adjustable delay line 11 and is configured to receive the first delayed clock signal and transmit it to the output port area 31 of the memory to output a first target clock signal.

[0066] The second clock distribution network 14 is electrically connected with the second adjustable delay line 13 and is configured to receive the second delayed clock signal when the working frequency of the memory is less than the preset frequency, and transmit it to the output port area 31 of the memory to output a second target clock signal, the phase difference between the second target clock signal and the first target clock signal being a preset value; when the working frequency of the memory is greater than or equal to the preset frequency, the second clock distribution network 14 is disabled.

[0067] The multi-phase clock generation circuit 15 is electrically connected with the first clock distribution network 12 and is configured to receive the first target clock signal when the working frequency of the memory is greater than or equal to the preset frequency, and generate at least a first phase clock signal and a second phase clock signal based on the first target clock signal, the first phase clock signal being in phase with the first target clock signal, and the phase difference between the second phase clock signal and the first target clock signal being a preset value; when the working frequency of the memory is less than the preset frequency, the multi-phase clock generation circuit 15 is disabled.

[0068] It should be noted that the delay phase-locked loop 10 of the embodiments of the present disclosure can be applied to but is not limited to memories such as DRAM, SDRAM, etc. In addition, in other analog circuits / digital circuits such as controllers, processors, etc., a set of clock signals with different phases can also be generated by the delay phase-locked loop 10 provided by the embodiments of the present disclosure.

[0069] When the working frequency of the memory is less than the preset frequency, the first adjustable delay line 11, the second adjustable delay line 13, the first clock distribution network 12 and the second clock distribution network 14 all work, delay process the first clock signal and the second clock signal based on the control code, and then transmit the first target clock signal and the second target clock signal to the output port area 31 of the memory through the first clock distribution network 12 and the second clock distribution network 14 for subsequent generation of data strobe signal DQS and sampling process of data signal DQ. The output port area 31 refers to a circuit area for outputting data near the data pin (DQ Pad) in the memory, including data DQ sampling circuit and output driving circuit, etc.

[0070] When the operating frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line 13 and the second clock distribution network 14 are disabled, only the first adjustable delay line 11 and the first clock distribution network 12 are enabled, and at least the first phase clock signal and the second phase clock signal are generated based on the first target clock signal by the multi-phase clock generation circuit 15 for subsequent generation of the data strobe signal DQS and sampling processing of the data signal DQ. Because the adjustable delay line and the clock distribution network will consume a large amount of power when the memory operates at high speed, thus, by reducing the path of clock transmission, the circuit power consumption can be reduced, the power supply noise can be reduced, and thus the clock jitter can be reduced, and the quality of the clock signal can be improved.

[0071] It can be understood that the multi-phase clock generation circuit 15 generates at least the first phase clock signal and the second phase clock signal based on the first target clock signal when the operating frequency of the memory is greater than or equal to the preset frequency, the first phase clock signal is in phase with the first target clock signal, and the phase difference between the second phase clock signal and the first target clock signal is a preset value. In some examples, the preset value can be 90 degrees, 180 degrees, or 270 degrees. The multi-phase clock generation circuit can be a four-phase clock generation circuit, and further generates a third phase clock signal and a fourth phase clock signal, wherein the phase difference between the first phase clock signal, the second phase clock signal, the third phase clock signal, and the fourth phase clock signal is 90 degrees in sequence. When the operating frequency of the memory is less than the preset frequency, the multi-phase clock generation circuit 15 is disabled, further saving circuit power consumption.

[0072] In short, when the memory operates at low speed, a plurality of adjustable delay lines and clock distribution networks are enabled to generate a plurality of phase-locked phase clock signals for subsequent generation of the data strobe signal DQS and sampling processing of the data signal DQ. When the memory operates at high speed, only one adjustable delay line and clock distribution network are enabled, and a plurality of phase-locked phase clock signals are generated at the output port region by the multi-phase clock generation circuit, which can reduce circuit power consumption, reduce power supply noise, thereby reducing clock jitter, and improving the quality of the clock signal.

[0073] It should be understood that the definition of the phase difference in the present disclosure allows a certain error. That is, the phase difference between the first phase clock signal, the second phase clock signal, the third phase clock signal, and the fourth phase clock signal is 90 degrees in sequence within the error allowed range. The subsequent related definitions of the phase value, the signal edge alignment, or the signal waveform are within the error allowed range.

[0074] In some embodiments, the multi-phase clock generation circuit 15 is adjacent to the output port region 31 of the memory. When the operating frequency of the memory is greater than or equal to the preset frequency, only the first adjustable delay line 11 and the first clock distribution network 12 are enabled, and the first target clock signal is transmitted to the output port region 31 of the memory. The multi-phase clock generation circuit 15 is adjacent to the output port region 31 of the memory, so that the first target clock signal can be received at the output port region 31, and the first phase clock signal and the second phase clock signal generated can also be directly transmitted into the output port region 31, avoiding phase skew caused by long-distance signal transmission.

[0075] It can be understood that the operating frequency of the memory is equal to the clock frequency of the initial clock signal CK_t received by the memory. The above-mentioned preset frequency can be set to a required value according to an actual scene, for example, in DDR5, the preset frequency can be set to 5.6 Gbps. In some embodiments, the multi-phase clock generation circuit 15 can be an analog phase generator (APG), which can generate a first phase clock signal, a second phase clock signal, a third phase clock signal and a fourth phase clock signal, which are 90 degrees apart from each other in phase. However, the APG can only work in a specific frequency band and cannot cover a wide enough operating frequency band. For example, when the APG is designed to work at a higher frequency, it may not be able to generate correct four-phase clock signals at a lower frequency. Therefore, the setting of the preset frequency also needs to take into account the operating frequency band of the multi-phase clock generation circuit 15, to ensure that the multi-phase clock generation circuit 15 can work normally when the operating frequency of the memory is greater than or equal to the preset frequency.

[0076] In some embodiments, as shown in FIG. 3, the delay-locked loop 10 further comprises:

[0077] The copy adjustable delay line 16 is configured to, when the operating frequency of the memory is less than the preset frequency, simulate the delay of the first adjustable delay line 11, receive a copy clock signal, delay the copy clock signal based on the control code, and output a copy delay clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the copy adjustable delay line 16 is not enabled;

[0078] The copy clock distribution network 17 is electrically connected with the copy adjustable delay line 16 and is configured to, when the operating frequency of the memory is less than the preset frequency, receive the copy delay clock signal, simulate the delay of the first clock distribution network 12, and output a copy target clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the copy clock distribution network 17 is not enabled.

[0079] When the operating frequency of the memory is less than the preset frequency, the replica adjustable delay line 16 receives a replica clock signal to simulate the delay of the first adjustable delay line 11. The replica clock signal can be the first clock signal or a signal with the same phase waveform as the first clock signal. The delay of the replica adjustable delay line 16 is simulated to be as close as possible to the delay of the first adjustable delay line 11 to reduce the phase error when the DLL is locked. It is understood that the delay of the second adjustable delay line 13 is the same as the delay of the first adjustable delay line 11, so the delay of the replica adjustable delay line 16 is also the same as the delay of the second adjustable delay line 13. They can achieve the same delay by using the same circuit structure and the same control code. The replica clock distribution network 17 receives a replica delay clock signal to simulate the delay of the first clock distribution network 12, i.e., to make the delay of the replica clock distribution network 17 as close as possible to the delay of the first clock distribution network 12 to reduce the phase error when the DLL is locked. It is understood that the delay of the second clock distribution network 14 is the same as the delay of the first clock distribution network 12, so the delay of the replica clock distribution network 17 is also the same as the delay of the second clock distribution network 14. It is noted that the delays mentioned here are the same within the error tolerance range.

[0080] When the operating frequency of the memory is greater than or equal to the preset frequency, the replica adjustable delay line 16 and the replica clock distribution network 17 are disabled, which can further save the circuit power consumption of the memory when operating at high speed.

[0081] In some embodiments, when the operating frequency of the memory is less than the preset frequency, the phase-locked state of the delay-locked loop 10 is achieved, and the memory does not perform a read operation, the first adjustable delay line 11, the second adjustable delay line 13, the first clock distribution network 12, and the second clock distribution network 14 are disabled, and only the replica adjustable delay line 16 and the replica clock distribution network 17 are enabled. At this time, because the read operation is not performed, the clock signal does not need to be transmitted to the output port region 31 to generate the data strobe signal DQS, and the first adjustable delay line 11, the second adjustable delay line 13, the first clock distribution network 12, and the second clock distribution network 14 can all be turned off to achieve the purpose of power saving. Because the delay-locked loop 10 has already achieved the phase-locked state, only the replica adjustable delay line 16 and the replica clock distribution network 17 need to be enabled to maintain the locked state of the delay-locked loop 10. In some cases, when the delay-locked loop 10 is in the locked state, the replica adjustable delay line 16 and the replica clock distribution network 17 can also operate at a reduced frequency, i.e., receive a replica clock signal at a reduced frequency, which can further save the circuit power consumption of the delay-locked loop.

[0082] In some embodiments, as shown in FIG. 3, the delay-locked loop 10 further includes:

[0083] The selection circuit 18 is electrically connected with the multi-phase clock generation circuit 15 and the replica clock distribution network 17, and is configured to receive the replica target clock signal and the first phase clock signal, output the replica target clock signal when the working frequency of the memory is less than the preset frequency, and output the first phase clock signal when the working frequency of the memory is greater than or equal to the preset frequency.

[0084] In some embodiments, as shown in FIG. 3, the delay-locked loop 10 further includes:

[0085] The delay simulation circuit 19 is electrically connected with the output terminal of the selection circuit 18, and is configured to simulate the delay of the clock input path and the clock output path in the memory, and output the feedback clock signal; the clock input path includes a clock receiver and a frequency divider, and the clock output path includes an output driving circuit.

[0086] The phase detector 20 is electrically connected with the delay simulation circuit 19, and is configured to receive the feedback clock signal and the reference clock signal, and output the indication signal based on the phase sequence of the two.

[0087] The control code generation circuit 21 is electrically connected with the phase detector 20, and is configured to adjust and output the control code based on the indication signal.

[0088] When the working frequency of the memory is less than the preset frequency, the selection circuit 18 selects the replica target clock signal output by the replica clock distribution network 17 to enter the DLL feedback loop, and then generates the feedback clock signal. When the working frequency of the memory is greater than or equal to the preset frequency, the selection circuit 18 selects the first phase clock signal to enter the DLL feedback loop, and then generates the feedback clock signal. In this way, when the memory works at high speed, the replica adjustable delay line 16 and the replica clock distribution network 17 can be turned off to save power consumption, thereby reducing power supply noise and clock jitter.

[0089] It should be noted that the delay simulation circuit 19 simulates the delay of the clock input path and the clock output path in the memory, that is, the delay of the delay simulation circuit 19 is as same as the delay of the clock input path and the clock output path as much as possible, so as to reduce the phase error during DLL locking. The clock input path includes a clock receiver CLK IB and a frequency divider Divider that receive an initial clock signal CK_t, and the clock output path includes an output driving circuit that outputs a data signal DQ and a data selection signal DQS.

[0090] The phase detector 20 receives the feedback clock signal and a reference clock signal, which can be the first clock signal or a signal having the same phase waveform as the first clock signal. The phase detector 20 compares the phases of the reference clock signal and the feedback clock signal, and then controls the time delay of the first adjustable delay line, the second adjustable delay line, and / or the replica adjustable delay line through the control code generation circuit 21, so that the phase difference between the final reference clock signal and the feedback clock signal is approximately 0 under the closed-loop feedback mechanism, and the DLL reaches a locked state. Ideally, when the DLL is locked, the rising edges of the reference clock signal and the feedback clock signal are aligned, and the phase difference between the two is equal to 0. However, in actual situations, as long as the phase difference between the reference clock signal and the feedback clock signal is approximately 0 within the error tolerance range, it can be considered that the DLL reaches a locked state.

[0091] It can be understood that when the operating frequency of the memory is less than the preset frequency, the DLL feedback loop is composed of the replica adjustable delay line 16, the replica clock distribution network 17, the selection circuit 18, the delay simulation circuit 19, the phase detector 20, and the control code generation circuit 21. When the operating frequency of the memory is greater than or equal to the preset frequency, the DLL feedback loop is composed of the first adjustable delay line 11, the first clock distribution network 12, the multi-phase clock generation circuit 15, the selection circuit 18, the delay simulation circuit 19, the phase detector 20, and the control code generation circuit 21. In this way, when the memory operates at a high speed, the adjustable delay line 16 and the replica clock distribution network 17 can be turned off, greatly saving power consumption, thereby reducing power supply noise and clock jitter.

[0092] In some embodiments, the circuit structures of the first adjustable delay line 11, the second adjustable delay line 13, and the replica adjustable delay line 16 are the same. In some embodiments, the circuit structures of the first clock distribution network 12, the second clock distribution network 14, and the replica clock distribution network 17 are the same. In this way, the time delays of different paths can be ensured to be the same, so that the phase difference between the first target clock signal and the second target clock signal is a preset value, the deviation (skew) of the phase difference is reduced, and the phase error when the DLL is locked can be reduced.

[0093] In some embodiments, as shown in FIG. 4, the first adjustable delay line 11, the second adjustable delay line 13, and the replica adjustable delay line 16 each include a coarse delay line CDL, a fine delay line FDL, and a driver DRV.

[0094] The coarse delay line CDL and the fine delay line FDL receive the control code outputted by the control code generating circuit, and adjust the delay time in response to the control code. The step size of the adjustment of the coarse delay line CDL is larger than that of the fine delay line FDL. The first adjustable delay line 11, the second adjustable delay line 13, and the replica adjustable delay line 16 mainly rely on the coarse delay line CDL and the fine delay line FDL to adjust the delay time of themselves. The driver DRV is generally located at the end of the first adjustable delay line 11, the second adjustable delay line 13, and the replica adjustable delay line 16, and is used to enhance the driving capability of the output signal, so as to improve the quality of the clock signal transmitted to the subsequent circuit. The driver DRV can be composed of an even number of inverters, and the size of the inverters can be set according to the length of the subsequent transmission path and the size of the load.

[0095] In some embodiments, as shown in FIG. 4, the first adjustable delay line 11, the second adjustable delay line 13, and the replica adjustable delay line 16 further each include a duty cycle correction circuit DCC and a quadrant error correction circuit QEC; when the working frequency of the memory is greater than or equal to the preset frequency, the duty cycle correction circuit DCC and the quadrant error correction circuit QEC of the first adjustable delay line 11 are disabled; and when the working frequency of the memory is less than the preset frequency, the duty cycle correction circuit DCC and the quadrant error correction circuit QEC of the first adjustable delay line 11 are enabled.

[0096] Because the clock signal is transmitted over a long distance, the rising edge and the falling edge can be offset, causing duty cycle distortion and phase offset. The duty cycle correction circuit DCC is used to adjust the duty cycle of the clock signal, so that the duty cycle is as close to 50% as possible, which is beneficial to the accurate sampling of the subsequent data signal DQ. The quadrant error correction circuit QEC is used to adjust the phase difference between the clock signals in different paths, so that the phase difference is as close to the preset value as possible, reducing the deviation (skew) of the phase difference between the clock signals in different paths, which is also beneficial to the accurate sampling of the subsequent data signal DQ.

[0097] When the working frequency of the memory is greater than or equal to the preset frequency, because the multiphase clock generating circuit 15 is enabled, and the first phase clock signal and the second phase clock signal generated by the multiphase clock generating circuit 15 can be directly transmitted into the output port region 31 adjacent to the output port region of the memory, the duty cycle distortion and the phase offset caused by long-distance signal transmission are avoided, so the duty cycle correction circuit DCC and the quadrant error correction circuit QEC can be disabled. In this way, the path of the first adjustable delay line 11 can be shortened, and the number of logic gates working on the first adjustable delay line 11 can be reduced, which is beneficial to reducing the jitter of the clock signal. At the same time, the circuit power consumption can be reduced, the power supply noise can be reduced, and the jitter of the clock signal can be further reduced.

[0098] In some embodiments, the first adjustable delay line 11 and the second adjustable delay line 13 are located in a first voltage domain, and the first clock distribution network 12 and the second clock distribution network 14 are located in a second voltage domain; the power supply voltage of the first voltage domain and the power supply voltage of the second voltage domain are the same. For example, the first voltage domain can be a voltage domain VDLL specially provided for the delay-locked loop DLL inside the memory, and the second voltage domain can be a voltage domain VDD commonly used with other circuits, such as a read-write path, an output driving circuit, etc. The power supply of the first voltage domain is purer and has less noise than the power supply of the second voltage domain, so that the delay adjustment is more accurate, and it is also beneficial to reduce the jitter of the clock signal.

[0099] In some embodiments, as shown in FIG. 4, the delay-locked loop 10 further comprises:

[0100] The third adjustable delay line 23 is configured to, when the working frequency of the memory is less than the preset frequency, receive the third clock signal CLKIB and the control code, delay the third clock signal CLKIB based on the control code, and output a third delayed clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the third adjustable delay line 23 is disabled;

[0101] The fourth adjustable delay line 25 is configured to, when the working frequency of the memory is less than the preset frequency, receive the fourth clock signal CLKQB and the control code, delay the fourth clock signal CLKQB based on the control code, and output a fourth delayed clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the fourth adjustable delay line 25 is disabled;

[0102] The third clock distribution network 24 is electrically connected with the third adjustable delay line 23 and is configured to, when the working frequency of the memory is less than the preset frequency, receive the third delayed clock signal and transmit it to the output port area of the memory to output a third target clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the third clock distribution network 24 is disabled;

[0103] The fourth clock distribution network 26 is electrically connected with the fourth adjustable delay line 25 and is configured to, when the working frequency of the memory is less than the preset frequency, receive the fourth delayed clock signal and transmit it to the output port area of the memory to output a fourth target clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the fourth clock distribution network 26 is disabled;

[0104] Among them, the phase difference between the first clock signal CLKI, the second clock signal CLKQ, the third clock signal CLKIB and the fourth clock signal CLKQB is 90 degrees in turn.

[0105] Referring to FIG. 4, the first adjustable delay line 11, the second adjustable delay line 13, the third adjustable delay line 23, the fourth adjustable delay line 25 and the replica adjustable delay line 16 all have the same circuit structure, including a coarse delay line CDL, a fine delay line FDL, a duty cycle correction circuit DCC, a quadrant error correction circuit QEC and a driver DRV. Among them, the second adjustable delay line 13, the third adjustable delay line 23, the fourth adjustable delay line 25 and the replica adjustable delay line 16 are represented by a dashed box, which is to illustrate that the second adjustable delay line 13, the third adjustable delay line 23, the fourth adjustable delay line 25 and the replica adjustable delay line 16 are not enabled when the working frequency of the memory is greater than or equal to the preset frequency, and are only enabled when the working frequency of the memory is less than the preset frequency. The first adjustable delay line 11 is represented by a solid line box, which illustrates that it is enabled at any working frequency. The duty cycle correction circuit DCC and the quadrant error correction circuit QEC in the first adjustable delay line 11 are represented by a dashed box, which is to illustrate that they are not enabled when the working frequency of the memory is greater than or equal to the preset frequency. In this way, the circuit power consumption of the memory working at high frequency can be reduced, the power supply noise can be reduced, and the jitter of the clock signal can be reduced.

[0106] Continuing to refer to FIG. 4, the first clock distribution network 12, the second clock distribution network 14, the third clock distribution network 24, the fourth clock distribution network 26 and the replica clock distribution network 17 all have the same circuit structure to reduce the delay deviation between different paths. Among them, the second clock distribution network 14, the third clock distribution network 24, the fourth clock distribution network 26 and the replica clock distribution network 17 are represented by a dashed box, which is to illustrate that the second clock distribution network 14, the third clock distribution network 24, the fourth clock distribution network 26 and the replica clock distribution network 17 are not enabled when the working frequency of the memory is greater than or equal to the preset frequency, and are only enabled when the working frequency of the memory is less than the preset frequency. The first clock distribution network 12 is represented by a solid line box, which illustrates that it is enabled at any working frequency. In this way, the circuit power consumption of the memory working at high frequency can be reduced, the power supply noise can be reduced, and the jitter of the clock signal can be reduced.

[0107] In some embodiments, the clock frequencies of the first clock signal CLKI, the second clock signal CLKQ, the third clock signal CLKIB and the fourth clock signal CLKQB are half of the clock frequency of an initial clock signal CK_t received by the memory, wherein the clock frequency of the initial clock signal CK_t is equal to the working frequency of the memory.

[0108] As shown in FIG. 4, a clock input buffer (CLK IB) 27 receives an initial clock signal CK_t, and then a divider 28 generates a first clock signal CLKI, a second clock signal CLKQ, a third clock signal CLKIB, and a fourth clock signal CLKQB, which are transmitted to four adjustable delay lines, respectively.

[0109] In some embodiments, referring to FIG. 4, when the working frequency of the memory is greater than or equal to a preset frequency, the multi-phase clock generation circuit can be a four-phase clock generation circuit (4-Phase Generator, 4-Phase Gen), which further generates a third phase clock signal and a fourth phase clock signal; the phases between the first phase clock signal, the second phase clock signal, the third phase clock signal, and the fourth phase clock signal are sequentially different by 90 degrees. In this way, when the memory works at high speed, only the first adjustable delay line 11 and the first clock distribution network 12 need to be enabled, and the first clock signal CLKI is transmitted to the four-phase clock generation circuit, and then the required four-phase clock signals are generated, which are further used for sampling of the data signal DQ. In this way, the circuit power consumption can be greatly saved, the power supply noise can be reduced, and the clock jitter can be reduced.

[0110] In some embodiments, as shown in FIG. 4, the delay-locked loop 10 further includes:

[0111] A mode control circuit 29 is configured to, when the working frequency of the memory is less than the preset frequency, send the first clock signal CLKI to the first adjustable delay line 11, send the second clock signal CLKQ to the second adjustable delay line 13, send the third clock signal CLKIB to the third adjustable delay line 23, and send the fourth clock signal CLKQB to the fourth adjustable delay line 25; when the working frequency of the memory is greater than or equal to the preset frequency, only send the first clock signal CLKI to the first adjustable delay line 11; do not send the second clock signal CLKQ, the third clock signal CLKIB, and the fourth clock signal CLKQB. Because when the working frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line 13, the third adjustable delay line 23, and the fourth adjustable delay line 25 are not enabled, at this time, if the second clock signal CLKQ, the third clock signal CLKIB, and the fourth clock signal CLKQB are still received, the circuit devices at the head end, such as inverters, will still generate current. The mode control circuit 29 makes the second adjustable delay line 13, the third adjustable delay line 23, and the fourth adjustable delay line 25 not receive any clock signal when the working frequency of the memory is greater than or equal to the preset frequency, which can further reduce the circuit power consumption.

[0112] In some embodiments, as shown in FIG. 4, the output port region 31 of the memory includes a high-bit output port region 312 and a low-bit output port region 311; the multi-phase clock generation circuit 15 includes a high-bit multi-phase clock generation circuit 152 and a low-bit multi-phase clock generation circuit 151; the high-bit multi-phase clock generation circuit 152 is adjacent to the high-bit output port region 312 and is configured to provide at least the first phase clock signal and the second phase clock signal for the high-bit output port UDQ; the low-bit multi-phase clock generation circuit 151 is adjacent to the low-bit output port region 311 and is configured to provide at least the first phase clock signal and the second phase clock signal for the low-bit output port LDQ; when one of the high-bit output port UDQ and the low-bit output port LDQ is not enabled, the multi-phase clock generation circuit corresponding thereto is disabled.

[0113] It can be understood that there are various configurations in the memory, such as DDR5, such as X4, X8, X16, etc. The enabled output ports are different under different configurations. A set of multi-phase clock generation circuits is provided for the high-bit and low-bit output ports respectively, so that they can be enabled respectively according to the actual use to achieve the effect of power saving. More groups of output ports can also be formed according to the actual situation, and a set of multi-phase clock generation circuits is provided for each group to achieve the effect of more accurate control.

[0114] Continuing to refer to FIG. 4, the delay-locked loop 10 further includes a selection circuit (Mux) 18, an input / output replica circuit (I / O Replica) 19, a phase detector (PD) 20, and a delay control module (CDL / FDL Control) 21. When the working frequency of the memory is less than a preset frequency, the Mux selects to send the replica target clock signal output by the replica clock distribution network 17 into the DLL feedback loop, and then generates a feedback clock signal. When the working frequency of the memory is greater than or equal to the preset frequency, the Mux selects to send the first phase clock signal into the DLL feedback loop, and then generates a feedback clock signal. The DLL feedback loop includes the I / O Replica, the PD, and the CDL / FDL Control. In this way, when the memory works at high speed, the replica adjustable delay line 16 and the replica clock distribution network 17 can be turned off to achieve the purpose of saving power consumption, thereby reducing power supply noise and clock jitter.

[0115] In summary, the delay-locked loop provided by the embodiments of the present disclosure can reduce circuit power consumption, reduce power supply noise, thereby reducing clock jitter, and improving the quality of the clock signal by closing the second adjustable delay line and the second clock distribution network, enabling only the first adjustable delay line and the first clock distribution network, and generating at least the first phase clock signal and the second phase clock signal through the multi-phase clock generation circuit when the memory is working at high speed.

[0116] In yet another embodiment of the present disclosure, referring to FIG. 5, a schematic diagram of a composition structure of a memory 40 provided by the embodiments of the present disclosure is shown. As shown in FIG. 5, the memory 40 at least includes the aforementioned delay-locked loop 10.

[0117] In some embodiments, the memory at least meets one of the following specifications: DDR3, DDR4, DDR5, DDR6, LPDDR3, LPDDR4, LPDDR5, and LPDDR6.

[0118] The delay-locked loop included in the memory can reduce circuit power consumption, reduce power supply noise, thereby reducing clock jitter, and improving the quality of the clock signal by closing the second adjustable delay line and the second clock distribution network, enabling only the first adjustable delay line and the first clock distribution network, and generating at least the first phase clock signal and the second phase clock signal through the multi-phase clock generation circuit when the memory is working at high speed. Thus, the data strobe signal DQS can be accurately generated, and the sampling processing of the data signal DQ can be more accurately performed, thereby improving the signal quality of the DQS and DQ output by the memory.

[0119] The above merely describes preferred embodiments of the present disclosure, but is not intended to limit the protection scope of the present disclosure. It should be explained that, in the present disclosure, the terms “comprising”, “containing” or any other variants thereof are intended to cover non-exclusive containing, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement “including a…” does not exclude the presence of other identical elements in the process, method, article or device including the element. The above sequence number of the embodiments of the present disclosure is only for description, and does not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method or device embodiments. The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A delay-locked loop, comprising: The application is applied to a memory, comprising: a first adjustable delay line (11) configured to receive a first clock signal and a control code, delay the first clock signal based on the control code, and output a first delayed clock signal; a second adjustable delay line (13) configured to, when the working frequency of the memory is less than a preset frequency, receive a second clock signal and the control code, delay the second clock signal based on the control code, and output a second delayed clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line is disabled; a first clock distribution network (12) electrically connected with the first adjustable delay line and configured to receive the first delayed clock signal and transmit it to an output port area of the memory to output a first target clock signal; a second clock distribution network (14) electrically connected with the second adjustable delay line and configured to, when the working frequency of the memory is less than the preset frequency, receive the second delayed clock signal and transmit it to the output port area of the memory to output a second target clock signal, the phase difference between the second target clock signal and the first target clock signal being a preset value; when the working frequency of the memory is greater than or equal to the preset frequency, the second clock distribution network is disabled; a multi-phase clock generation circuit (15) electrically connected with the first clock distribution network and configured to, when the working frequency of the memory is greater than or equal to the preset frequency, receive the first target clock signal and generate at least a first phase clock signal and a second phase clock signal based on the first target clock signal, the first phase clock signal being in phase with the first target clock signal, and the phase difference between the second phase clock signal and the first target clock signal being the preset value; when the working frequency of the memory is less than the preset frequency, the multi-phase clock generation circuit is disabled.

2. The delay-locked loop of claim 1, wherein, Further comprising: a replica adjustable delay line (16) configured to, when the working frequency of the memory is less than the preset frequency, simulate the delay of the first adjustable delay line, receive a replica clock signal, delay the replica clock signal based on the control code, and output a replica delayed clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the replica adjustable delay line is disabled; a replica clock distribution network (17) electrically connected with the replica adjustable delay line and configured to, when the working frequency of the memory is less than the preset frequency, receive the replica delayed clock signal, simulate the delay of the first clock distribution network, and output a replica target clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the replica clock distribution network is disabled.

3. The delay-locked loop of claim 2, wherein, Further comprising: The selection circuit (18) is electrically connected with the multi-phase clock generation circuit and the replica clock distribution network, configured to receive the replica target clock signal and the first phase clock signal, output the replica target clock signal when the working frequency of the memory is less than a preset frequency, and output the first phase clock signal when the working frequency of the memory is greater than or equal to the preset frequency.

4. The delay-locked loop of claim 3, wherein, Further comprising, The delay simulation circuit (19) is electrically connected with the output end of the selection circuit, used for simulating the delay of a clock input path and a clock output path in the memory, and outputting a feedback clock signal; the clock input path comprises a clock receiver and a frequency divider, and the clock output path comprises an output driver circuit; The phase detector (20) is electrically connected with the delay simulation circuit, configured to receive the feedback clock signal and a reference clock signal, and output an indication signal based on the phase sequence of the two; The control code generation circuit (21) is electrically connected with the phase detector, configured to adjust and output the control code based on the indication signal.

5. The delay-locked loop of claim 2, wherein, When the working frequency of the memory is less than the preset frequency, the delay-locked loop has completed phase locking, and the memory does not perform a read operation, the first adjustable delay line, the second adjustable delay line, the first clock distribution network and the second clock distribution network are not enabled, and only the replica adjustable delay line and the replica clock distribution network are enabled.

6. The delay-locked loop of claim 1, wherein, The multi-phase clock generation circuit is adjacent to an output port region of the memory.

7. The delay-locked loop of claim 2, wherein, The circuit structures of the first adjustable delay line, the second adjustable delay line and the replica adjustable delay line are the same.

8. The delay-locked loop of claim 7, wherein, The first adjustable delay line, the second adjustable delay line and the replica adjustable delay line each comprise a coarse adjustment delay line, a fine adjustment delay line and a driver.

9. The delay-locked loop of claim 7, wherein, The first adjustable delay line, the second adjustable delay line and the replica adjustable delay line each further comprise a duty cycle correction circuit and a quadrant error correction circuit; when the working frequency of the memory is greater than or equal to the preset frequency, the duty cycle correction circuit and the quadrant error correction circuit of the first adjustable delay line are not enabled; when the working frequency of the memory is less than the preset frequency, the duty cycle correction circuit and the quadrant error correction circuit of the first adjustable delay line are enabled.

10. The delay-locked loop of claim 2, wherein, The circuit structures of the first clock distribution network, the second clock distribution network and the replica clock distribution network are the same.

11. The delay-locked loop of claim 1, wherein, The first adjustable delay line and the second adjustable delay line are located in a first voltage domain, and the first clock distribution network and the second clock distribution network are located in a second voltage domain; the power supply voltage of the first voltage domain and the power supply voltage of the second voltage domain are the same.

12. The delay-locked loop of claim 1, wherein, Further comprising: The third adjustable delay line is configured to receive a third clock signal and the control code when the working frequency of the memory is less than the preset frequency, delay process the third clock signal based on the control code, and output a third delay clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the third adjustable delay line is not enabled. A fourth adjustable delay line is configured to, when the working frequency of the memory is less than the preset frequency, receive a fourth clock signal and the control code, perform delay processing on the fourth clock signal based on the control code, and output a fourth delayed clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the fourth adjustable delay line is disabled; A third clock distribution network is electrically connected with the third adjustable delay line and is configured to, when the working frequency of the memory is less than the preset frequency, receive the third delayed clock signal and transmit it to an output port area of the memory to output a third target clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the third clock distribution network is disabled; A fourth clock distribution network is electrically connected with the fourth adjustable delay line and is configured to, when the working frequency of the memory is less than the preset frequency, receive the fourth delayed clock signal and transmit it to the output port area of the memory to output a fourth target clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the fourth clock distribution network is disabled. The phase difference between the first clock signal, the second clock signal, the third clock signal and the fourth clock signal is 90 degrees.

13. The delay-locked loop of claim 12, wherein, The clock frequency of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal is half of the clock frequency of an initial clock signal received by the memory, wherein the clock frequency of the initial clock signal is equal to the working frequency of the memory.

14. The delay-locked loop of claim 12, wherein, Further comprising: A mode control circuit is configured to, when the working frequency of the memory is less than the preset frequency, send the first clock signal to the first adjustable delay line, send the second clock signal to the second adjustable delay line, send the third clock signal to the third adjustable delay line, and send the fourth clock signal to the fourth adjustable delay line; when the working frequency of the memory is greater than or equal to the preset frequency, only send the first clock signal to the first adjustable delay line; and not send the second clock signal, the third clock signal and the fourth clock signal.

15. The delay-locked loop of claim 1, wherein, When the working frequency of the memory is greater than or equal to the preset frequency, the multiphase clock generation circuit further generates a third phase clock signal and a fourth phase clock signal; the phase difference between the first phase clock signal, the second phase clock signal, the third phase clock signal and the fourth phase clock signal is 90 degrees.

16. The delay-locked loop of claim 6, wherein, The output port region of the memory comprises a high-bit output port region and a low-bit output port region; the multi-phase clock generation circuit comprises a high-bit multi-phase clock generation circuit and a low-bit multi-phase clock generation circuit; the high-bit multi-phase clock generation circuit is adjacent to the high-bit output port region and is configured to provide at least the first phase clock signal and the second phase clock signal for the high-bit output port; the low-bit multi-phase clock generation circuit is adjacent to the low-bit output port region and is configured to provide at least the first phase clock signal and the second phase clock signal for the low-bit output port; when one of the high-bit output port and the low-bit output port is not enabled, the multi-phase clock generation circuit corresponding to the one is not enabled.

17. A memory (40) characterized by A delay-locked loop (10) comprising any one of the claims 1-16.

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