ADC synchronous acquisition and conversion circuit

Abstract

The present application provides an ADC synchronous acquisition and conversion circuit. The circuit comprises at least two channel branches, each channel branch comprising a first capacitor and first to third switches. The circuit further comprises an operational amplifier, a second capacitor, a fourth switch, and an ADC module. A lower plate of the first capacitor of each channel branch is connected to a corresponding channel input signal via the first switch, and is connected to the second switch. An upper plate of the first capacitor is connected to a negative terminal of the operational amplifier via the third switch. The negative terminal of the operational amplifier is connected to an upper plate of the second capacitor, and a positive terminal of the operational amplifier is connected to a fixed potential. An output terminal of the operational amplifier is connected to the ADC module, is connected to the negative terminal of the operational amplifier via the fourth switch, and is connected to a lower plate of the second capacitor via a fifth switch. The lower plate of the second capacitor is connected to ground via a sixth switch.

Description

ADC synchronous acquisition conversion circuit Cross-reference to Related Applications

[0001] This patent application claims priority to the Chinese patent application with the application number 202411124939.9, the title of which is "ADC synchronous acquisition conversion circuit", filed on August 16, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of electronic circuits, in particular to an ADC synchronous acquisition conversion circuit. BACKGROUND

[0003] Analog to Digital Converter (ADC) front-end sampling circuit needs to complete the sampling and holding function of the analog input signal. When AD conversion of multiple channel analog signals is required, multiple channel analog signals need to be collected. From the time angle of sampling, it can be divided into two categories: synchronous acquisition and sequential acquisition. Synchronous acquisition refers to sampling and converting multiple channel analog signals at the same time, usually containing multiple sampling and holding circuits and analog to digital converters inside to realize synchronous acquisition and conversion. Sequential sampling refers to multiple channels sharing a sampling and holding circuit, sampling, quantizing and outputting the results of different channel signals at different times. When there is no phase relationship between the analog signals of each channel, such as environmental temperature, environmental humidity, pressure, etc., there is no need to use synchronous acquisition and conversion to maintain phase information. At this time, sequential acquisition and quantization are usually used to realize the function of multi-channel analog to digital conversion. When the phase relationship between the channels contains important information, synchronous acquisition and conversion method must be used. For example, in the field of power measurement, it is usually necessary to collect voltage and current data at the same time, and the phase relationship between the two provides information such as instantaneous power and power factor. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide an ADC synchronous acquisition conversion circuit.

[0005] One aspect of the present application provides an ADC synchronous acquisition conversion circuit. The ADC synchronous acquisition conversion circuit comprises at least two channel branches, each of the at least two channel branches is configured to receive a corresponding at least one channel input signal, each of the channel branches comprises a first capacitor, a first switch, a second switch and a third switch, the ADC synchronous acquisition conversion circuit further comprises an operational amplifier, a second capacitor, a fourth switch and an ADC module. Wherein, the lower plate of the first capacitor in each of the channel branches is connected to the corresponding channel input signal through the first switch and connected to the second switch, the upper plate of the first capacitor is connected to the negative input terminal of the operational amplifier through the third switch; the negative input terminal of the operational amplifier is connected to the upper plate of the second capacitor, the positive input terminal of the operational amplifier is connected to a fixed potential, the output terminal of the operational amplifier is connected to the negative input terminal of the operational amplifier through the fourth switch and connected to the lower plate of the second capacitor through a fifth switch; the lower plate of the second capacitor is connected to a ground potential through a sixth switch; the output terminal of the operational amplifier is connected to the ADC module.

[0006] Further, the lower plate of the first capacitor in each of the channel branches is connected to the fixed potential through the second switch.

[0007] Further, in the case of being in a synchronous acquisition phase for synchronously acquiring all channel input signals, the first switch and the third switch in all channel branches are closed, the second switch is open, and the fourth switch is closed.

[0008] Further, in the case of being in a quantization phase for quantizing a certain channel input signal, the second switch and the third switch in the corresponding channel branch connected to the channel input signal are closed, the first switch is open, the first switch, the second switch and the third switch in the channel branches other than the corresponding channel branch are all open, and the fourth switch is open.

[0009] Further, the ADC synchronous acquisition conversion circuit has a synchronous acquisition phase, a quantization phase and a holding phase, the synchronous acquisition phase is configured to synchronously acquire all channel input signals, the quantization phase is configured to quantize each channel input signal, and the holding phase is between the synchronous acquisition phase and the quantization phase for quantizing a first channel input signal, wherein, in the case of being in the holding phase, the first switch, the second switch and the third switch in all channel branches, and the fourth switch are all open.

[0010] Further, the ADC synchronous acquisition conversion circuit has a quantization stage and an interval reset stage, the quantization stage is used for quantizing each channel input signal, the interval reset stage is located between each two quantization stages, wherein, in the case of being in the interval reset stage, the first switch, the second switch and the third switch in all channel branches are all disconnected, and the fourth switch is connected.

[0011] Further, the first switch to the fourth switch are formed by transmission gates composed of NMOS tubes and PMOS tubes.

[0012] Further, the second switch in each channel branch is formed by an NMOS tube.

[0013] Further, the ADC synchronous acquisition conversion circuit further comprises a fifth switch and a sixth switch, the lower plate of the first capacitor in each channel branch is connected to the ground potential through the second switch, and the output end of the operational amplifier is connected to the lower plate of the second capacitor through the fifth switch; the lower plate of the second capacitor is connected to the ground potential through the sixth switch.

[0014] Further, in the case of being in the synchronous acquisition stage of synchronously acquiring all channel input signals, the first switch and the third switch in all channel branches are connected, the second switch is disconnected, and the fourth switch and the sixth switch are connected, and the fifth switch is disconnected.

[0015] Further, in the case of being in the quantization stage of quantizing a certain channel input signal, the second switch and the third switch in the corresponding channel branch connected with the channel input signal are connected, the first switch is disconnected, the first switch, the second switch and the third switch in the channel branches other than the corresponding channel branch are all disconnected, and the fourth switch and the sixth switch are disconnected, and the fifth switch is connected.

[0016] Further, the ADC synchronous acquisition conversion circuit has a synchronous acquisition stage, a quantization stage and a holding stage, the synchronous acquisition stage is used for synchronously acquiring all channel input signals, the quantization stage is used for quantizing each channel input signal, and the holding stage is located between the synchronous acquisition stage and the quantization stage of quantizing the first channel input signal, wherein, in the case of being in the holding stage, the first switch, the second switch and the third switch, and the fourth switch, the fifth switch and the sixth switch in all channel branches are all disconnected.

[0017] Further, the ADC synchronous acquisition conversion circuit has a quantization stage and an interval reset stage, the quantization stage is used for quantizing each channel input signal, and the interval reset stage is located between every two quantization stages, wherein, in the case of being in the interval reset stage, the first switch, the second switch and the third switch in all channel branches are all disconnected, and the fourth switch and the sixth switch are connected, and the fifth switch is disconnected.

[0018] Further, the first switch to the sixth switch are formed by transmission gates composed of NMOS tubes and PMOS tubes.

[0019] Further, the second switch and the sixth switch in each channel branch are formed by one NMOS tube.

[0020] A control method of the ADC synchronous acquisition conversion circuit, comprising: controlling the ADC synchronous acquisition conversion circuit to enter a synchronous acquisition stage; after the synchronous acquisition stage, controlling the ADC synchronous acquisition conversion circuit to enter a holding stage; after the holding stage, controlling the ADC synchronous acquisition conversion circuit to enter a quantization stage of one channel input signal; after the quantization stage, controlling the ADC synchronous acquisition conversion circuit to enter an interval reset stage; after the interval reset stage, controlling the ADC synchronous acquisition conversion circuit to enter a quantization stage of a next channel input signal; repeating the entering interval reset stage and the quantization stage of the next channel input signal until the quantization of all channel input signals is completed.

[0021] The ADC synchronous acquisition conversion circuit of one or more embodiments of the present application can realize the synchronous acquisition function by using a simple operational amplifier, the input range requirement is very low, and the input voltage of the operational amplifier does not need to meet the requirement of the entire power supply voltage range, either NMOS or PMOS can be used as the input pair tube, only one of the two is needed, which greatly reduces the chip design requirement and energy consumption, thereby reducing the chip area, saving the cost and improving the energy efficiency.

[0022] The ADC synchronous acquisition conversion circuit of one or more embodiments of the present application can eliminate the influence of the offset voltage of the operational amplifier, and greatly improve the overall analog-to-digital conversion precision and performance consistency of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0023] FIG. 1 is a structural schematic diagram of an ADC synchronous acquisition conversion circuit in the related art.

[0024] FIG. 2 is a structural schematic diagram of another ADC synchronous acquisition conversion circuit in the related art.

[0025] Fig. 3 is a state diagram of switches of the ADC synchronous acquisition conversion circuit in the first embodiment of the present application in the synchronous acquisition stage.

[0026] Fig. 4 is a state diagram of switches of the ADC synchronous acquisition conversion circuit in the first embodiment of the present application in the holding stage.

[0027] Fig. 5 is a state diagram of switches of the ADC synchronous acquisition conversion circuit in the first embodiment of the present application in the quantization stage of the first channel input signal.

[0028] Fig. 6 is a state diagram of switches of the ADC synchronous acquisition conversion circuit in the first embodiment of the present application in the interval reset stage.

[0029] Fig. 7 is a state diagram of switches of the ADC synchronous acquisition conversion circuit in the first embodiment of the present application in the quantization stage of the second channel input signal.

[0030] Fig. 8 is a timing diagram of switches of the ADC synchronous acquisition conversion circuit in the first embodiment of the present application.

[0031] Fig. 9 is a state diagram of switches of the ADC synchronous acquisition conversion circuit in the second embodiment of the present application in the synchronous acquisition stage.

[0032] Fig. 10 is a state diagram of switches of the ADC synchronous acquisition conversion circuit in the second embodiment of the present application in the holding stage.

[0033] Fig. 11 is a state diagram of switches of the ADC synchronous acquisition conversion circuit in the second embodiment of the present application in the quantization stage of the first channel input signal.

[0034] Fig. 12 is a state diagram of switches of the ADC synchronous acquisition conversion circuit in the second embodiment of the present application in the interval reset stage.

[0035] Fig. 13 is a state diagram of switches of the ADC synchronous acquisition conversion circuit in the second embodiment of the present application in the quantization stage of the second channel input signal.

[0036] Fig. 14 is a flow chart of a control method of the ADC synchronous acquisition conversion circuit in one embodiment of the present application. DETAILED DESCRIPTION

[0037] The exemplary embodiments will be described in detail herein below with reference to the drawings. The following description is related to the drawings, in which like numbers refer to like or similar elements, unless otherwise described. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with some aspects of the present application as detailed in the appended claims.

[0038] FIG. 1 discloses a structural diagram of an ADC synchronous acquisition conversion circuit 100 in the related art. As shown in FIG. 1, taking two-channel synchronous acquisition and conversion as an example, VIN1 represents a first-channel input signal, and VIN2 represents a second-channel input signal. The ADC synchronous acquisition conversion circuit 100 needs two sample-and-hold circuits and two ADCs in total. Among them, the sample-and-hold circuit 1 is used for sampling and holding the first-channel input signal VIN1, and then quantizing the sampled signal through the ADC 1; the sample-and-hold circuit 2 is used for sampling and holding the second-channel input signal VIN2, and then quantizing the sampled signal through the ADC 2. To realize synchronous acquisition and conversion, the two sample-and-hold circuits sample the first-channel input signal VIN1 and the second-channel input signal VIN2 at the same time, and the ADC 1 and the ADC 2 quantize the sampled signals synchronously.

[0039] The ADC synchronous acquisition conversion circuit 100 shown in FIG. 1 needs multiple sets of sample-and-hold circuits and ADCs, although it can realize multi-channel synchronous sampling and synchronous conversion, it sacrifices a lot of chip area, has high cost and low efficiency, and there will be differences between the ADCs of different channels, thereby causing different conversion errors between different channels.

[0040] FIG. 2 discloses a structural diagram of another ADC synchronous acquisition conversion circuit 200 in the related art and a switching timing diagram thereof. As shown in FIG. 2, taking two channels as an example, the ADC synchronous acquisition conversion circuit 200 is to acquire in a synchronous manner, that is, to acquire two-channel input signals at the same time, and then to store them, and then to convert them into digital signals in time. Although the analog-to-digital conversion values of the channels are output sequentially, the requirement of synchronous acquisition is still guaranteed, so that the phase relationship between the channels can be preserved, and synchronous acquisition and conversion can be realized. In the ADC synchronous acquisition conversion circuit 200 of FIG. 2, the first-channel input signal VIN1 and the second-channel input signal VIN2 are synchronously acquired through the switch SAMPLE, and the acquired voltages of the first-channel input signal VIN1 and the second-channel input signal VIN2 are stored on the capacitors CIN1 and CIN2, respectively. Then, by opening the switches CON1 and CON2 in time, the voltages stored on the capacitors CIN1 and CIN2 are quantized by the ADC module in time, and the analog-to-digital conversion of the two channels is sequentially completed.

[0041] The ADC synchronous acquisition conversion circuit 200 shown in FIG. 2 can realize that multiple channels share the same ADC through synchronous acquisition and sequential conversion, and the cost is reduced compared with the ADC synchronous acquisition conversion circuit 100 in FIG. 1, but still has the following two shortcomings: 1) Since the input signal range usually covers the entire power supply voltage range, assuming that the power supply voltage is 5V, the signal range of each input channel is 0V to 5V, which will cause the input range of the operational amplifier AMP1 in FIG. 2 to be 0V to 5V, and the output range must also be 0V to 5V. Therefore, the ADC synchronous acquisition conversion circuit 200 has high requirements for the operational amplifier AMP1, which needs to meet the input and output being rail-to-rail, thereby causing design complexity, high cost, and large energy consumption; 2) The operational amplifier AMP1 will have a offset voltage VOS1 in actual process production, and the offset voltage in the ADC synchronous acquisition conversion circuit 200 will be directly superimposed on the input signal. Therefore, the actual conversion voltage of the ADC is VIN1+VOS1 and VIN2+VOS1, and VOS1 is inconsistent between different chips and has a temperature coefficient, thereby causing the conversion error between different chips to be inconsistent and varying with temperature, thereby affecting the overall analog-to-digital conversion accuracy and performance consistency of the chip.

[0042] Therefore, the present application provides an improved ADC synchronous acquisition conversion circuit, which can solve at least one of the problems existing in the related art.

[0043] The ADC synchronous acquisition conversion circuit provided by the present application comprises at least two channel branches, and the at least two channel branches can be used to receive at least two corresponding channel input signals respectively. Each channel branch comprises a first capacitor, a first switch, a second switch, and a third switch. The ADC synchronous acquisition conversion circuit further comprises an operational amplifier, a second capacitor, a fourth switch, and an ADC module.

[0044] The lower plate of the first capacitor in each channel branch is connected to the corresponding channel input signal through the first switch and connected to the second switch, and the upper plate of the first capacitor is connected to the negative input terminal of the operational amplifier through the third switch. The negative input terminal of the operational amplifier is connected to the upper plate of the second capacitor, the positive input terminal of the operational amplifier is connected to a fixed potential, the output terminal of the operational amplifier is connected to the negative input terminal of the operational amplifier through the fourth switch and connected to the lower plate of the second capacitor through the fifth switch; the lower plate of the second capacitor is connected to a ground potential through the sixth switch; and the output terminal of the operational amplifier is connected to the ADC module.

[0045] The application provides two specific embodiments of an ADC synchronous acquisition conversion circuit, which will be described in detail below with reference to the accompanying drawings and taking two channels as an example. The features in the following embodiments and implementation manners can be combined with each other without conflict.

[0046] First embodiment

[0047] FIGS. 3-7 disclose a structural schematic diagram of an ADC synchronous acquisition conversion circuit 300 of the first embodiment of the application. The ADC synchronous acquisition conversion circuit 300 of the first embodiment can solve the problem of the input voltage range of the operational amplifier and the problem of the offset voltage of the operational amplifier.

[0048] As shown in FIGS. 3-7, in some embodiments, the ADC synchronous acquisition conversion circuit 300 of the application can include two channel branches, i.e., a first channel branch 301 and a second channel branch 302, which can be used to correspondingly receive a first channel input signal VIN1 and a second channel input signal VIN2, respectively.

[0049] The first channel branch 301 includes a first capacitor C11, a first switch S11, a second switch S21 and a third switch S31; and the second channel branch 302 includes a first capacitor C12, a first switch S12, a second switch S22 and a third switch S32.

[0050] The ADC synchronous acquisition conversion circuit 300 of the application further includes an operational amplifier AMP2, a second capacitor C2, a fourth switch S4, a fifth switch S5, a sixth switch S6 and an ADC module 305.

[0051] The lower plate of the first capacitor C11 in the first channel branch 301 is connected to the first channel input signal VIN1 through the first switch S11 and connected to the ground potential through the second switch S21, and the upper plate of the first capacitor C11 is connected to the negative input terminal of the operational amplifier AMP2 through the third switch S31; the lower plate of the first capacitor C12 in the second channel branch 302 is connected to the second channel input signal VIN2 through the first switch S12 and connected to the ground potential through the second switch S22, and the upper plate of the first capacitor C12 is connected to the negative input terminal of the operational amplifier AMP2 through the third switch S32.

[0052] The negative input terminal of the operational amplifier AMP2 is connected to the upper plate of the second capacitor C2, the positive input terminal of the operational amplifier AMP2 is connected to a fixed potential, the output terminal of the operational amplifier AMP2 is connected to the negative input terminal of the operational amplifier AMP2 through the fourth switch S4 and connected to the lower plate of the second capacitor C2 through the fifth switch S5; the lower plate of the second capacitor C2 is connected to a ground potential through the sixth switch S6; and the output terminal of the operational amplifier AMP2 is connected to the ADC module 305.

[0053] The ADC synchronous acquisition conversion circuit 300 of the present application comprises five stages. FIG. 8 discloses a switch timing diagram of the ADC synchronous acquisition conversion circuit 300 of the first embodiment of the present application. Each stage of the ADC synchronous acquisition conversion circuit 300 of the present application will be described in detail below in combination with FIG. 8.

[0054] The ADC synchronous acquisition conversion circuit 300 of the present application comprises a first stage, i.e. a synchronous acquisition stage, for synchronously acquiring all channel input signals. FIG. 3 discloses a state diagram of each switch of the ADC synchronous acquisition conversion circuit 300 in the synchronous acquisition stage. As shown in FIG. 3 and in combination with FIG. 8, in the synchronous acquisition stage, the first switch and the third switch in all channel branches are closed, the second switch is opened, for example, the first switch S11 and the third switch S31 in the first channel branch 301 and the first switch S12 and the third switch S32 in the second channel branch 302 are closed, the second switch S21 in the first channel branch 301 and the second switch S22 in the second channel branch 302 are opened, and the fourth switch S4 and the sixth switch S6 are closed, and the fifth switch S5 is opened.

[0055] At this time, the first channel input signal VIN1 and the second channel input signal VIN2 are transmitted to the lower plates of the first capacitors C11 and C12 through the first switches S11 and S12 respectively, the upper plates of the first capacitors C11 and C12 are transmitted to the negative input terminal (point A shown in the figure) of the operational amplifier AMP2 through the third switches S31 and S32 respectively, the positive input terminal of the operational amplifier AMP2 is connected to a fixed voltage VCM, and the output terminal VOUT of the operational amplifier AMP2 is transmitted to the negative input terminal of the operational amplifier AMP2 through the fourth switch S4, so that the operational amplifier AMP2 is connected in the form of a unit buffer at this time.

[0056] Therefore, the total charge at point A at this time can be listed as: Q A = (VA-VIN1) *C11 + (VA-VIN2) *C12 + (VA-0) / C2 VA=VCM+VOS (1) wherein VOS is the offset voltage value of the operational amplifier AMP2.

[0057] The charge stored on the top plate of the first capacitor C11 is: C11 = (VA-VIN1) *C11 = (VCM+VOS-VIN1) *C11

[0058] The charge stored on the top plate of the first capacitor C12 is: C12 = (VA-VIN2) *C12 = (VCM+VOS-VIN2) *C12

[0059] The charge stored on the top plate of the second capacitor C2 is: C2 = (VA-0) *C2 = (VCM+VOS-0) *C2

[0060] The ADC synchronous acquisition conversion circuit 300 of the present application further comprises a second stage, i.e. a holding stage. Fig. 4 discloses a state diagram of each switch of the ADC synchronous acquisition conversion circuit 300 in the holding stage. As shown in Fig. 4 and in combination with Fig. 8, in the holding stage, the first switch, the second switch and the third switch in all channel branches are all turned off, for example, the first switch S11, the second switch S21 and the third switch S31 in the first channel branch 301, and the first switch S12, the second switch S22 and the third switch S32 in the second channel branch 302 are all turned off, and the fourth switch S4, the fifth switch S5 and the sixth switch S6 are all turned off.

[0061] In order to minimize the nonlinearity introduced by the charge injection effect at the moment when the switches are turned off, optionally, when entering the holding stage, the first switch in each channel branch can be controlled to be turned off with a delay of a predetermined time compared with the third switch, for example, the first switch S11, S12 can be controlled to be turned off with a delay compared with the third switch S31 and S32 respectively, and the fourth switch S4 can be controlled to be turned off with a delay of a predetermined time compared with the sixth switch S6.

[0062] After all the switches are turned off, the charge stored on the top plate of the first capacitor C11 is: C11 = (VA-VIN1') *C11 = (VCM+VOS-VIN1 ′ ) *C11 (2)

[0063] The charge stored on the top plate of the first capacitor C12 is: C12 = (VA-VIN2') *C12 = (VCM+VOS-VIN2 ′ ) *C12 (3)

[0064] The charge stored on the top plate of the second capacitor C2 is: C2= (VA - 0) * C2 = (VCM + VOS - 0) * C2 (4) Wherein, VIN1', VIN2' are voltage values of the first channel input signal VIN1 and the second channel input signal VIN2 at the moment when the third switch S31, S32 changes from the "1" state (i.e. the closed state) to the "0" state (i.e. the open state), thereby completing the sample-and-hold operation on the first channel input signal VIN1 and the second channel input signal VIN2.

[0065] The ADC synchronous acquisition conversion circuit 300 of the present application further comprises a third stage, i.e. a quantization stage of the first channel input signal VIN1. Fig. 5 discloses the state diagram of each switch of the ADC synchronous acquisition conversion circuit 300 in the quantization stage of the first channel input signal VIN1. As shown in Fig. 5 and in combination with Fig. 8, in the quantization stage of the first channel input signal VIN1, the second switch S21 and the third switch S31 in the first channel branch 301 are closed, the first switch S11 is open, the first switch S11, the second switch S21 and the third switch S31 in the second channel branch 302 are all open, and the fourth switch S4 and the sixth switch S6 are open, and the fifth switch S5 is closed.

[0066] At this time, the output end VOUT of the operational amplifier AMP2 is connected to the lower plate of the second capacitor C2 through the fifth switch S5, so as to work in the closed loop condition of the negative feedback, and thus the voltage VA at the negative end of the operational amplifier AMP2 is the same as the above formula (1).

[0067] According to the charge conservation principle at point A, we can obtain: (VA - VIN1') * C11 + (VA - 0) * C2 = (VA - 0) * C11 + (VA - VOUT) * C2 (5)

[0068] Through further simplification of formula (5), we can obtain: When C11 = C2, we can obtain: VOUT = VIN1'.

[0069] Therefore, at this time, the output signal VOUT of the operational amplifier AMP2 is input to the ADC module 305, the signal SOC rising edge triggers a quantization operation once, and after the quantization is completed, the signal EOC changes from the "0" state (i.e. the low level state) to the "1" state (i.e. the high level state), and finally the n-bit digital code D1 [n-1:0] is obtained, which is the analog-to-digital conversion value of VIN1'. As can be seen from the above derivation, although there is an offset voltage VOS in the operational amplifier AMP2, which causes the voltage VA = VCM + VOS, the voltage VA in the final formula (6) will be eliminated, so that the voltage finally subjected to the analog-to-digital conversion is the voltage VIN1' of the first channel input signal VIN1. That is, the voltage VOUT of the analog-to-digital conversion is irrelevant to the voltage VA, and thus it can be seen that the ADC synchronous acquisition conversion circuit 300 of the present application can realize the function of eliminating the offset voltage of the operational amplifier AMP2.

[0070] In addition, it can be seen from the formula (6) that, in the ADC synchronous acquisition conversion circuit 300 of the present application, if it is required to amplify the input signal of the first channel branch 301, the capacitance of the first capacitor C11 can be designed to be greater than that of the second capacitor C2, and thus it can be seen that the ADC synchronous acquisition conversion circuit 300 of the present application can also realize the function of amplifying the input signal of the first channel branch 301.

[0071] The ADC synchronous acquisition conversion circuit 300 of the present application further comprises a fourth stage, i.e., an interval reset stage. Fig. 6 discloses the state diagram of each switch of the ADC synchronous acquisition conversion circuit 300 in the interval reset stage. As shown in Fig. 6 and in combination with Fig. 8, in the interval reset stage, the first switch, the second switch and the third switch in all channel branches are all disconnected, for example, the first switch S11, the second switch S21 and the third switch S31 in the first channel branch 301, and the first switch S12, the second switch S22 and the third switch S32 in the second channel branch 302 are all disconnected, and the fourth switch S4 and the sixth switch S6 are closed and the fifth switch S5 is disconnected.

[0072] At this time, the output end VOUT of the operational amplifier AMP2 is connected to the negative input end of the operational amplifier AMP2 through the fourth switch S4, and the operational amplifier AMP2 is connected in the form of a unit buffer, and thus the voltage VA at the negative end of the operational amplifier AMP2 is the same as that in the formula (1). Therefore, the charge stored on the second capacitor C2 is again reset to the value in the formula (4).

[0073] All switches (i.e., the first switch to the third switch in all channel branches, and the fourth switch C4 and the sixth switch C6) in the ADC synchronous acquisition conversion circuit 300 of the present application can be formed by using the transmission gate composed of an NMOS transistor and a PMOS transistor.

[0074] The second switch in each channel branch and the sixth switch C6 can also be formed by using a simpler NMOS transistor, so as to further simplify the circuit structure.

[0075] The ADC synchronous acquisition conversion circuit 300 of the present application further comprises a fifth stage, i.e. a quantization stage of the second channel input signal VIN2. Fig. 7 discloses the state diagram of each switch of the ADC synchronous acquisition conversion circuit 300 in the quantization stage of the second channel input signal VIN2. As shown in Fig. 7 and in combination with Fig. 8, in the quantization stage of the second channel input signal VIN2, the second switch S22 and the third switch S32 in the second channel branch 302 are closed, the first switch S12 is disconnected, the first switch S11, the second switch S21 and the third switch S31 in the first channel branch 301 are all disconnected, and the fourth switch S4 and the sixth switch S6 are disconnected, and the fifth switch S5 is closed.

[0076] At this time, the output end VOUT of the operational amplifier AMP2 is connected to the lower plate of the second capacitor C2 through the fifth switch S5, so as to work in a closed loop under negative feedback, and thus the voltage VA at the negative end of the operational amplifier AMP2 is the same as formula (1).

[0077] According to the charge conservation principle at point A, the following equation can be obtained: (VA-VIN2')*C12+(VA-0)*C2=(VA-0)*C12+(VA-VOUT)*C2 (7)

[0078] Through further simplification of formula (7), the following equation can be obtained: When C12=C2, the following equation can be obtained: VOUT=VIN2'.

[0079] Therefore, at this time, the output signal VOUT of the operational amplifier AMP2 is input to the ADC module 305, the rising edge of the signal SOC triggers a quantization operation, and after the quantization is completed, the signal EOC changes from the "0" state to the "1" state, and finally the n-bit digital code D2[n-1:0] is obtained, which is the analog-to-digital conversion value of VIN2'. Similarly, it can be seen from the above derivation that although the operational amplifier AMP2 has an offset voltage VOS, resulting in the voltage VA=VCM+VOS, the VA in the final formula (8) will be cancelled out, so that the voltage VOUT for analog-to-digital conversion is independent of the voltage VA. That is, the analog-to-digital conversion voltage VOUT is independent of the voltage VA, and thus it can be seen that the ADC synchronous acquisition conversion circuit 300 of the present application can realize the function of eliminating the offset voltage of the operational amplifier AMP2.

[0080] Similarly, it can be seen from formula (8) that if it is necessary to amplify the input signal of the second channel branch 302, the capacitance value of the first capacitor C12 can be designed to be greater than that of the second capacitor C2, and thus it can be seen that the ADC synchronous acquisition conversion circuit 300 of the present application can also realize the function of amplifying the input signal of the second channel branch 302.

[0081] After the above five stages, if the next sampling and quantization of the input signals VIN1 and VIN2 is still needed, the above five stages can be repeated after a sampling and quantization gap, as shown in FIG. 8. According to the application, the sampling and quantization gap can be set to be very small or even removed.

[0082] As can be seen from the above derivation, the positive input terminal of the operational amplifier AMP2 of the present application is always connected to the fixed potential VCM. In actual circuits, the voltage of the fixed potential VCM is usually designed to be half of the supply voltage. For example, if the supply voltage is 5V, the fixed potential VCM is designed to be 2.5V. The input range requirement of the operational amplifier AMP2 only needs to cover 2.5V, so the operational amplifier AMP2 of the present application can use either NMOS as the input pair or PMOS as the input pair, and only one of the two is required, without the requirement that the input satisfies 0V to 5V. This greatly reduces the design requirements and energy consumption of the operational amplifier AMP2, thereby reducing the chip area, saving costs, and improving energy efficiency.

[0083] The above is an example of two channels. Correspondingly, the ADC synchronous acquisition and conversion circuit 300 of the present application includes two channel branches. The ADC synchronous acquisition and conversion circuit 300 of the present application can be divided into the above five stages, which are the synchronous acquisition stage, the holding stage, the quantization stage of the first channel input signal VIN1, the interval reset stage, and the quantization stage of the second channel input signal VIN2. It can be understood that the ADC synchronous acquisition and conversion circuit 300 of the present application is not limited to two channels. The ADC synchronous acquisition and conversion circuit 300 of the present application can be easily extended to other more channels according to actual conditions. Correspondingly, in other embodiments, the ADC synchronous acquisition and conversion circuit 300 of the present application can include three, four or more channel branches for receiving a corresponding number of channel input signals.

[0084] In the case where the ADC synchronous acquisition and conversion circuit 300 of the present application includes a plurality of channel branches for receiving a plurality of channel input signals, the ADC synchronous acquisition and conversion circuit 300 of the present application can include a quantization stage for quantizing each channel input signal. In the quantization stage for quantizing a certain channel input signal, only the second switch and the third switch in the corresponding channel branch connected to the channel input signal are closed, the first switch is opened, the first switch, the second switch and the third switch in the other channel branches are all opened, and the fourth switch S4 and the sixth switch S6 are opened and the fifth switch S5 is closed.

[0085] In the case that the ADC synchronous acquisition conversion circuit 300 of the present application comprises a plurality of channel branches for corresponding receiving a plurality of channel input signals, the holding stage is located between the synchronous acquisition stage and the quantization stage for quantizing the first channel input signal, and the interval reset stage is located between each two quantization stages.

[0086] Compared with the ADC synchronous acquisition conversion circuit 100 shown in FIG. 1 and the ADC synchronous acquisition conversion circuit 200 shown in FIG. 2, the ADC synchronous acquisition conversion circuit 300 of the present application has at least the following two beneficial technical effects: first, the ADC synchronous acquisition conversion circuit 300 of the present application can realize the synchronous acquisition function by using a simple operational amplifier, the input range requirement is very low, and the input of the operational amplifier does not need to meet the requirement of the entire power supply voltage range, either NMOS or PMOS can be used as the input pair tube, only one of the two is needed, which greatly reduces the chip design requirement and energy consumption, thereby reducing the chip area, saving cost and improving energy efficiency; second, the ADC synchronous acquisition conversion circuit 300 of the present application can eliminate the influence of the offset voltage of the operational amplifier, greatly improving the overall analog-to-digital conversion accuracy and performance consistency of the chip.

[0087] Second embodiment

[0088] Without considering the offset voltage of the operational amplifier, the present application also provides an ADC synchronous acquisition conversion circuit of a second embodiment. FIGS. 9-13 disclose a structural schematic diagram of the ADC synchronous acquisition conversion circuit 400 of the second embodiment of the present application. The ADC synchronous acquisition conversion circuit 400 of the second embodiment can solve the problem of the input voltage range of the operational amplifier.

[0089] As shown in FIGS. 9-13, the ADC synchronous acquisition conversion circuit 400 of the second embodiment is different from the ADC synchronous acquisition conversion circuit 300 of the first embodiment in that the ADC synchronous acquisition conversion circuit 400 of the second embodiment can omit the fifth switch S5 and the sixth switch S6, and in the ADC synchronous acquisition conversion circuit 400 of the second embodiment, the lower plate of the first capacitor in each channel branch is connected to the fixed potential VCM through the second switch.

[0090] Similar to the ADC synchronous acquisition conversion circuit 300 of the first embodiment, the ADC synchronous acquisition conversion circuit 400 of the second embodiment also has five stages.

[0091] As shown in FIG. 9, in the synchronous acquisition stage, the first switch S11 and the third switch S31 in the first channel branch 401 and the first switch S12 and the third switch S32 in the second channel branch 402 are closed, the second switch S21 in the first channel branch 401 and the second switch S22 in the second channel branch 402 are open, and the fourth switch S4 is closed.

[0092] As shown in FIG. 10, in the holding stage, the first switch S11, the second switch S21 and the third switch S31 in the first channel branch 401, and the first switch S12, the second switch S22 and the third switch S32 in the second channel branch 402 are all disconnected, and the fourth switch S4 is disconnected.

[0093] As shown in FIG. 11, in the quantization stage of the first channel input signal VIN1, the second switch S21 and the third switch S31 in the first channel branch 401 are closed, the first switch S11 is disconnected, the first switch S11, the second switch S21 and the third switch S31 in the second channel branch 402 are all disconnected, and the fourth switch S4 is disconnected.

[0094] The charge conservation of point A becomes: (VA-VIN1') *C11=(VA-VCM) *C11+(VA-VOUT) *C2

[0095] Since VA=VCM+VOS, it is simplified as: (VA-VIN1') *C11=VOS*C11+(VA-VOUT) *C2 When C11=C2, VOUT=VIN1 ′ +VOS

[0096] It can be seen that at this time, the offset voltage VOS will also be directly superimposed on the output, and the ADC synchronous acquisition conversion circuit 400 of the second embodiment does not have the offset voltage elimination function.

[0097] As shown in FIG. 12, in the interval reset stage, the first switch, the second switch and the third switch in all channel branches are all disconnected, for example, the first switch S11, the second switch S21 and the third switch S31 in the first channel branch 401, and the first switch S12, the second switch S22 and the third switch S32 in the second channel branch 402 are all disconnected, and the fourth switch S4 is closed.

[0098] As shown in FIG. 13, in the quantization stage of the second channel input signal VIN2, the second switch S22 and the third switch S32 in the second channel branch 402 are closed, the first switch S12 is disconnected, the first switch S11, the second switch S21 and the third switch S31 in the first channel branch 401 are all disconnected, and the fourth switch S4 is disconnected.

[0099] The charge conservation of point A becomes: (VA-VIN2') *C12=(VA-VCM) *C12+(VA-VOUT) *C2

[0100] Since VA = VCM + VOS, it is simplified as: (VA-VIN2') * C12 = VOS * C12 + (VA-VOUT) * C2 When C12 = C2, VOUT = VIN2 ′ + VOS

[0101] At this time, the offset voltage VOS will also be directly superimposed on the output, and the ADC synchronous acquisition conversion circuit 400 of the second embodiment does not have the offset voltage elimination function.

[0102] Of course, it can be understood that the ADC synchronous acquisition conversion circuit 400 of the second embodiment is not limited to two channels, and can be easily expanded to other more channels according to actual conditions.

[0103] In the entire process of completing the synchronous acquisition and conversion of the signal, the operation state of each switch in the ADC synchronous acquisition conversion circuit 400 of the second embodiment is basically the same as that of the ADC synchronous acquisition conversion circuit 300 of the first embodiment, and will not be described in detail.

[0104] The application also provides an ADC synchronous acquisition conversion circuit control method. FIG. 14 discloses a flowchart of an ADC synchronous acquisition conversion circuit control method according to an embodiment of the application. As shown in FIG. 14, the ADC synchronous acquisition conversion circuit control method according to the application can include steps S11 to S16.

[0105] In step S11, the ADC synchronous acquisition conversion circuit is controlled to enter a synchronous acquisition stage.

[0106] For the ADC synchronous acquisition conversion circuit 300 of the first embodiment, the first switch and the third switch in all channel branches are controlled to be closed, the second switch is controlled to be open, the fourth switch S4 and the sixth switch S6 are controlled to be closed, and the fifth switch S5 is controlled to be open, so as to perform synchronous acquisition on all channel input signals.

[0107] For the ADC synchronous acquisition conversion circuit 400 of the second embodiment, the first switch and the third switch in all channel branches are controlled to be closed, the second switch is controlled to be open, and the fourth switch S4 is controlled to be closed, so as to perform synchronous acquisition on all channel input signals.

[0108] In step S12, after the synchronous acquisition stage, the ADC synchronous acquisition conversion circuit is controlled to enter a holding stage.

[0109] For the first embodiment of the ADC synchronous sampling and conversion circuit 300, the first switch and the third switch in all channel branches, and the fourth switch S4 and the sixth switch S6 are controlled to switch from closed to open, and the second switch and the fifth switch S5 remain open.

[0110] For the first embodiment of the ADC synchronous sampling and conversion circuit 400, the first switch and the third switch in all channel branches, and the fourth switch S4 are controlled to switch from closed to open, and the second switch remains open.

[0111] In step S13, after the holding phase, the ADC synchronous sampling and conversion circuit is controlled to enter a quantization phase for one of the channel input signals.

[0112] For the first embodiment of the ADC synchronous sampling and conversion circuit 300, the second switch and the third switch in the corresponding channel branch connected to the channel input signal are controlled to close, the first switch in the corresponding channel branch, the first switch, the second switch and the third switch in the other channel branches except the corresponding channel branch, and the fourth switch S4 and the sixth switch S6 are all open, and the channel input signal is quantized.

[0113] For the second embodiment of the ADC synchronous sampling and conversion circuit 400, the second switch and the third switch in the corresponding channel branch connected to the channel input signal are controlled to close, the first switch in the corresponding channel branch, the first switch, the second switch and the third switch in the other channel branches except the corresponding channel branch, and the fourth switch S4 are all open, and the channel input signal is quantized.

[0114] In step S14, after the quantization phase, the ADC synchronous sampling and conversion circuit is controlled to enter an interval reset phase.

[0115] For the first embodiment of the ADC synchronous sampling and conversion circuit 300, the fourth switch S4 and the sixth switch S6 are controlled to close, and the first switch, the second switch and the third switch in all channel branches, and the fifth switch S5 are all open.

[0116] For the second embodiment of the ADC synchronous sampling and conversion circuit 400, the fourth switch S4 is controlled to close, and the first switch, the second switch and the third switch in all channel branches are all open.

[0117] In step S15, after the interval reset stage, the control unit controls the ADC synchronous acquisition conversion circuit to enter the quantization stage of the next channel input signal.

[0118] For the ADC synchronous acquisition conversion circuit 300 of the first embodiment, the control unit controls the second switch and the third switch in the next channel branch, and the fifth switch S5 to be closed, and controls the first switch in the next channel branch, the first switch, the second switch and the third switch in the other channel branches except the next channel branch, and the fourth switch S4 and the sixth switch S6 to be opened, so as to quantize the next channel input signal.

[0119] For the ADC synchronous acquisition conversion circuit 400 of the second embodiment, the control unit controls the second switch and the third switch in the next channel branch to be closed, and controls the first switch in the next channel branch, the first switch, the second switch and the third switch in the other channel branches except the next channel branch, and the fourth switch S4 to be opened, so as to quantize the next channel input signal.

[0120] In step S16, it is judged whether the quantization of all the channel input signals is completed. If the result of the judgment is "yes", the process is ended. If the result of the judgment is "no", the process returns to step S14, i.e. the above-mentioned steps of entering the interval reset stage and entering the quantization stage of the next channel input signal are repeated until the quantization of all the channel input signals is completed.

[0121] That is to say, for the ADC synchronous acquisition conversion circuit with two channels, the whole ADC synchronous acquisition conversion process for the two channels is completed after the steps S11 to S15. For the ADC synchronous acquisition conversion circuit with three or more channels, after the steps S11 to S15, the process of steps S14 and S15 is continued to be repeated until the ADC synchronous acquisition conversion of all the channels is completed, and then the whole ADC synchronous acquisition conversion process for all the channels is completed.

[0122] The control method of the ADC synchronous acquisition conversion circuit of the present application can have the similar beneficial technical effects as the ADC synchronous acquisition conversion circuits 300, 400 described above, and thus will not be described here again.

[0123] The above has carried out the detailed introduction to the ADC synchronous acquisition conversion circuit and the control method thereof provided by the embodiment of the application. The ADC synchronous acquisition conversion circuit and the control method thereof of the embodiment of the application are described by applying specific examples in the paper, and the above embodiment is only used to help understand the core idea of the application and does not limit the application. It should be pointed out that, for ordinary skilled persons in the technical field, some improvements and modifications can be made to the application without departing from the spirit and principles of the application, and these improvements and modifications should also fall within the protection scope of the appended claims of the application.

Claims

1. An ADC synchronous sampling and conversion circuit, characterized by, The ADC synchronous acquisition conversion circuit comprises at least two channel branches, at least two of which are used for receiving corresponding at least two channel input signals respectively, each of the channel branches comprises a first capacitor, a first switch, a second switch and a third switch, and the ADC synchronous acquisition conversion circuit further comprises an operational amplifier, a second capacitor, a fourth switch and an ADC module, wherein the lower plate of the first capacitor in each of the channel branches is connected to the corresponding channel input signal through the first switch and connected to the second switch, and the upper plate of the first capacitor is connected to the negative input end of the operational amplifier through the third switch; the negative input end of the operational amplifier is connected to the upper plate of the second capacitor, the positive input end of the operational amplifier is connected to a fixed potential, the output end of the operational amplifier is connected to the negative input end of the operational amplifier and the lower plate of the second capacitor through the fourth switch, and the output end of the operational amplifier is connected to the ADC module.

2. The ADC synchronous sampling and conversion circuit of claim 1, wherein, the lower plate of the first capacitor in each of the channel branches is connected to the corresponding channel input signal through the first switch and connected to the second switch, and the upper plate of the first capacitor is connected to the negative input end of the operational amplifier through the third switch; 3. The ADC synchronous sampling and conversion circuit of claim 2, wherein, in the case of being in the synchronous acquisition phase for synchronously acquiring all channel input signals, the first switch and the third switch in all channel branches are closed, the second switch is opened, and the fourth switch is closed.

4. The ADC synchronous acquisition conversion circuit of claim 2, wherein in the case of being in the quantization phase for quantizing a certain channel input signal, the second switch and the third switch in the corresponding channel branch connected to the channel input signal are closed, the first switch is opened, the first switch, the second switch and the third switch in the channel branches other than the corresponding channel branch are all opened, and the fourth switch is opened.

5. The ADC synchronous sampling and conversion circuit of claim 2, wherein, The ADC synchronous acquisition conversion circuit has a synchronous acquisition phase, a quantization phase and a holding phase, the synchronous acquisition phase is used for synchronously acquiring all channel input signals, the quantization phase is used for quantizing each channel input signal, and the holding phase is located between the synchronous acquisition phase and the quantization phase for quantizing a first channel input signal, wherein in the case of being in the holding phase, the first switch, the second switch and the third switch in all channel branches and the fourth switch are all opened.

6. The ADC synchronous sampling and conversion circuit of claim 2, wherein, The ADC synchronous acquisition conversion circuit has a quantization phase and an interval reset phase, the quantization phase is used for quantizing each channel input signal, and the interval reset phase is located between every two quantization phases, wherein in the case of being in the interval reset phase, the first switch, the second switch and the third switch in all channel branches are all opened, and the fourth switch is closed.

7. The ADC synchronous acquisition conversion circuit of any one of claims 1 to 6, wherein, The first switch to the fourth switch are formed by transmission gates composed of NMOS tubes and PMOS tubes.

8. The ADC synchronous acquisition conversion circuit of any one of claims 1 to 6, wherein, The second switch in each of the channel branches is formed by an NMOS tube. The second switch in each of the channel branches is formed by an NMOS tube.

9. The ADC synchronous sampling and conversion circuit of claim 1, wherein, The fifth switch and the sixth switch are further included, the lower plate of the first capacitor in each channel branch is connected to the ground potential through the second switch, and the output end of the operational amplifier is connected to the lower plate of the second capacitor through the fifth switch; and the lower plate of the second capacitor is connected to the ground potential through the sixth switch. 10.The ADC synchronous acquisition conversion circuit of claim 9, wherein, In the case of being in the synchronous acquisition phase for synchronously acquiring all channel input signals, the first switch and the third switch in all channel branches are closed, the second switch is open, and the fourth switch and the sixth switch are closed, and the fifth switch is open. 11.The ADC synchronous acquisition conversion circuit of claim 9, wherein, In the case of being in the quantization phase for quantizing a channel input signal, the second switch and the third switch in the corresponding channel branch connected with the channel input signal are closed, the first switch is open, the first switch, the second switch and the third switch in the channel branches other than the corresponding channel branch are all open, and the fourth switch and the sixth switch are open, and the fifth switch is closed.

12. The ADC synchronous sampling and conversion circuit of claim 9, wherein, The ADC synchronous acquisition conversion circuit has a synchronous acquisition phase, a quantization phase and a holding phase, the synchronous acquisition phase is used for synchronously acquiring all channel input signals, the quantization phase is used for quantizing each channel input signal, and the holding phase is between the synchronous acquisition phase and the quantization phase for quantizing a first channel input signal, wherein, In the case of being in the holding phase, the first switch, the second switch and the third switch, and the fourth switch, the fifth switch and the sixth switch in all channel branches are all open.

13. The ADC synchronous sampling and conversion circuit of claim 9, wherein, The ADC synchronous acquisition conversion circuit has a quantization phase and an interval reset phase, the quantization phase is used for quantizing each channel input signal, and the interval reset phase is between every two quantization phases, wherein, In the case of being in the interval reset phase, the first switch, the second switch and the third switch in all channel branches are all open, and the fourth switch and the sixth switch are closed, and the fifth switch is open.

14. The ADC synchronous acquisition conversion circuit of any of claims 9 to 13, wherein, The first switch to the sixth switch are formed by transmission gates composed of NMOS tubes and PMOS tubes.

15. The ADC synchronous acquisition conversion circuit of any of claims 9 to 13, wherein, The second switch and the sixth switch in each channel branch are both formed by an NMOS tube.

16. A method of controlling an ADC synchronous sampling and conversion circuit according to any one of claims 1 to 15, characterized in that, The method comprises: controlling the ADC synchronous acquisition conversion circuit to enter the synchronous acquisition phase; after the synchronous acquisition phase, controlling the ADC synchronous acquisition conversion circuit to enter the holding phase; after the holding phase, controlling the ADC synchronous acquisition conversion circuit to enter the quantization phase for one of the channel input signals; after the quantization phase, controlling the ADC synchronous acquisition conversion circuit to enter the interval reset phase; after the interval reset phase, controlling the ADC synchronous acquisition conversion circuit to enter the quantization phase for the next channel input signal; and after the quantization phase, controlling the ADC synchronous acquisition conversion circuit to enter the interval reset phase. The above-mentioned entry interval resetting stage and the quantization stage for the next channel input signal are repeated until the quantization of all channel input signals is completed.

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