Method for manufacturing semiconductor apparatus

Abstract

Provided is a method for manufacturing a semiconductor apparatus, the method comprising: preparing a first substrate by forming a separation layer on the surface of the first substrate by epitaxial growth, forming an epitaxial film on the separation layer by epitaxial growth, and forming a first device layer on the epitaxial film; preparing a second substrate; forming a combined substrate by bonding the first substrate and the second substrate together; and transferring the first device layer onto the second substrate by separating the first substrate from the second substrate through irradiation of the separation layer in the first substrate included in the combined substrate with laser light. The separation layer includes a laser-absorbing layer including at least one epitaxial film doped with a dopant. The first device layer includes a circuit element constituting at least a part of a memory cell array of a DRAM or a region where the circuit element is to be formed. The circuit element includes a transistor.

Description

Semiconductor device manufacturing method

[0001] The present disclosure relates to a method for manufacturing a semiconductor device.

[0002] Patent Document 1 discloses that pillars are formed by epitaxially growing silicon on the top of a substrate, and vertical channel transistors are formed by processing the pillars. A capacitor connected to the vertical channel transistors is formed, thereby forming a DRAM.

[0003] Japanese Patent Application Laid-Open No. 2003-122222 discloses a semiconductor device having a memory cell array structure in which a plurality of vertical channel transistors and capacitor structures are formed in an active pattern on a substrate.

[0004] Japanese Patent Publication No. 2013-98532 Japanese Patent Publication No. 2024-41033

[0005] The technology disclosed herein appropriately removes the first substrate from a laminated substrate in which the first and second substrates are bonded together when transferring at least a portion of a layer formed on the first substrate to the second substrate.

[0006] One aspect of the present disclosure is a method for manufacturing a semiconductor device, comprising: preparing a first substrate by forming a separation layer on a surface of a first substrate by epitaxial growth; forming an epitaxial film on the separation layer by epitaxial growth; and forming a first device layer on the epitaxial film; preparing a second substrate; bonding the first substrate and the second substrate to form an overlapped substrate; and separating the first substrate from the second substrate by irradiating the separation layer in the first substrate included in the overlapped substrate with laser light, thereby transferring the first device layer to the second substrate; wherein the separation layer includes a laser absorption layer including at least one epitaxial film doped with a dopant; and the first device layer includes a circuit element constituting at least a portion of a memory cell array of a DRAM, or a region in which the circuit element is to be formed, and the circuit element includes a transistor.

[0007] According to the present disclosure, when transferring at least a portion of a layer formed on a first substrate to a second substrate, the first substrate can be appropriately removed from a laminated substrate in which the first substrate and the second substrate are bonded together.

[0008] FIG. 1 is a flow diagram showing main steps of wafer processing; FIG. 2 is an explanatory diagram showing a state in which a first wafer and a second wafer are bonded to form an overlapped wafer; FIG. 3 is an explanatory diagram showing details of an example configuration of a separation layer; FIG. 4 is an explanatory diagram showing a state in which a laser absorbing film is irradiated with laser light; FIG. 5 is an explanatory diagram showing a state in which a laser absorbing film is irradiated with laser light; FIG. 6 is an explanatory diagram showing a state in which a first wafer and a second wafer are separated; FIG. 7 is a flow diagram showing main steps of a manufacturing method according to a first embodiment; FIG. 8 is an explanatory diagram showing main steps of a manufacturing method according to a second embodiment; FIG. 9 is an explanatory diagram showing main steps of a manufacturing method according to a third embodiment; FIG. 10 is an explanatory diagram showing main steps of a manufacturing method according to a fourth embodiment; FIG. 11 is an explanatory diagram showing main steps of a manufacturing method according to the fourth embodiment; FIG. 12 is an explanatory diagram showing steps in a modified example of the fourth embodiment; FIG. 13 is a flow diagram showing main steps of a manufacturing method according to a fifth embodiment; FIG. 14 is an explanatory diagram showing main steps of a manufacturing method according to the fifth embodiment; FIG. 15 is an explanatory diagram showing main steps of a manufacturing method according to the sixth embodiment; FIG. 16 is an explanatory diagram showing main steps of a manufacturing method according to the sixth embodiment. Fig. 10 is a flow chart showing main steps of a manufacturing method according to a seventh embodiment; Fig. 11 is an explanatory diagram showing main steps of a manufacturing method according to a seventh embodiment; Fig. 12 is a flow chart showing main steps of a manufacturing method according to an eighth embodiment; Fig. 13 is an explanatory diagram showing main steps of a manufacturing method according to an eighth embodiment.

[0009] Hereinafter, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to the drawings. In this specification and the drawings, elements having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0010] A common configuration among the semiconductor device manufacturing methods of various embodiments described below will be described. In the manufacturing methods of various embodiments, first, a first wafer W is prepared as a first substrate (St1 in FIG. 1), and a second wafer S is prepared as a second substrate (St2 in FIG. 1). The preparation of the first wafer W and the preparation of the second wafer S may be performed in parallel. Hereinafter, as shown in FIG. 2, the surface of the first wafer W that is bonded to the second wafer S will be referred to as the front surface Wa, and the surface opposite the front surface Wa will be referred to as the back surface Wb. Similarly, the surface of the second wafer S that is bonded to the first wafer W will be referred to as the front surface Sa, and the surface opposite the front surface Sa will be referred to as the back surface Sb.

[0011] The first wafer W prepared in St1 is a semiconductor wafer such as a silicon substrate. In one embodiment, the first wafer W has a substantially circular disk shape. As shown in FIG. 2( a), a laminated film formed by stacking multiple films is formed on the front surface Wa of the first wafer W. The laminated film includes, in order from the front surface Wa side, a separation layer Mw, a first device layer Dw, and a surface film Fw. The separation layer Mw includes, in order from the front surface Wa side, a sacrificial layer P, a laser absorption layer Q, and an etching stop layer R.

[0012] The first device layer Dw includes one or more of a plurality of devices described later. Note that there may be cases where no device is formed in the first device layer Dw at the time of preparation in St1, but a device is formed in the first device layer Dw in a subsequent process. In other words, the first device layer Dw may be a region where a device is to be formed in the first device layer Dw in a process after St1. The surface film Fw may be, for example, an oxide film (THOX film, SiO ２ film, TEOS film), SiC film, SiCN film, adhesive, etc. In one embodiment, the surface film Fw includes a copper pad Cu that constitutes a part of a wiring layer Wr (described later) as a signal network or a power supply network.

[0013] 3 , the sacrificial layer P as the separation layer Mw, the laser absorption layer Q, and the etching stop layer R each include a Si film, a SiGe film, a Ge film, or a combination of two or more thereof formed by epitaxial growth. In this specification, a crystalline Si film, a SiGe film, or a Ge film formed by epitaxial growth, or a film composed of a combination of two or more thereof, is simply referred to as an “epitaxial film.” The epitaxial film can be formed by a known process, including, for example, CVD (Chemical Vapor Deposition) in a film formation apparatus (not shown).

[0014] The sacrificial layer P has the effect of protecting the first wafer W from damage due to heat generated when the laser absorption layer Q absorbs the laser light L during laser separation, which will be described later. When the first wafer W is reused after laser separation of the first wafer W, the sacrificial layer P is removed, for example, by etching. As an example, by forming a SiGe film as the sacrificial layer P on the front surface Wa side of the first wafer W, it is possible to ensure an etching selectivity between the SiGe film and the front surface Wa of the first wafer W. This makes it possible to perform suitable etching when the first wafer W is reused, and to improve the total thickness variation (TTV) of the reused first wafer W.

[0015] The laser absorbing layer Q absorbs the laser light L during laser separation, which will be described later, and undergoes ablation or thermal expansion. This allows the laser absorbing layer Q to function as a starting point for separation due to laser irradiation. At least a portion of the epitaxial film of the laser absorbing layer Q is doped with a desired dopant.

[0016] As an example, a dopant may be supplied together with the film components during the formation of the epitaxial film in a film formation apparatus (not shown) to dope the epitaxial film, such as, but not limited to, phosphorus (P), boron (B), arsenic (As), or carbon (C).

[0017] As another example, dopants can be implanted into the epitaxial film after deposition, such as, but not limited to, oxygen (O), hydrogen (H), or various metal elements.

[0018] In this specification, an epitaxial film doped with a dopant is referred to as a “doped epitaxial film.” Note that Si (Doped) and SiGe (Doped) in FIG. 3 indicate that these are doped epitaxial films.

[0019] In this embodiment, the laser absorption layer Q includes a first layer Q1 that mainly absorbs laser light L with higher efficiency and converts it to heat, and a second layer Q2 that mainly experiences greater thermal expansion. In this case, the first layer Q1 includes a doped epitaxial film doped with a desired dopant that improves laser absorption efficiency. The second layer Q2 includes a doped epitaxial film doped with a desired dopant that improves thermal expansion coefficient. Therefore, the dopants in the doped epitaxial films of the first layer Q1 and the second layer Q2 may be different from each other. With this configuration, the first layer Q1 absorbs laser light L and converts it to heat more efficiently per laser output than the second layer Q2. Part of the heat causes thermal expansion of the first layer Q1 itself, and the other part of the heat is conducted to the second layer Q2. The second layer Q2 experiences greater thermal expansion per laser output than the first layer Q1 due to heat conducted from the first layer Q1 in addition to heat from the laser light L absorbed by the second layer Q2. The laser absorption efficiency and the thermal expansion coefficient can be adjusted by appropriately adjusting the output and wavelength of the laser light L, the type and concentration of the dopant, or the film thicknesses of the first layer Q1 and the second layer Q2.

[0020] The laser absorption layer Q also includes a third layer Q3 as a cleavage layer. The third layer Q3 is an epitaxial film that is not doped with a dopant. In this embodiment, the third layer Q3 is a SiGe film. As shown in FIG. 3 , the laser absorption layer Q is formed such that the first layer Q1 or the second layer Q2, which are doped epitaxial films, sandwich the third layer Q3 from above and below. In this embodiment, the third layer Q3 itself does not absorb laser light L, but is cleaved due to stress caused by thermal expansion of the doped epitaxial films provided above and below it, or due to thermal expansion of the third layer Q3 itself caused by heat conduction from the doped epitaxial films.

[0021] 3, the first layer Q1 is a SiGe film, the second layer Q2 is a Si film, and the third layer is a SiGe film, but this is not limiting. Each of the first to third layers Q1 to Q3 may include a Si film, a SiGe film, or a Ge film, or a combination of two or more of these.

[0022] In the laser absorption layer Q according to the present embodiment, both the Si film and the SiGe film are provided as doped epitaxial films, and thus a film thickness sufficient to improve the efficiency of laser absorption can be ensured, compared to the case where, for example, only the SiGe film is provided.

[0023] Furthermore, the laser absorption layer Q includes the first layer Q1 and the second layer Q2, which improves the efficiency of laser absorption and thermal expansion.

[0024] Furthermore, the provision of the third layer Q3 in the laser absorption layer Q can promote separation by cleavage in the third layer Q3, which allows the separation surface in laser separation to be concentrated mainly on the third layer Q3, improving the uniformity of the separation surface and increasing the possibility of reusing the first wafer W.

[0025] From the viewpoint of absorbing laser light L during laser separation and serving as the starting point for separation, it is sufficient for the laser absorption layer Q to have at least one doped epitaxial film, and the third layer Q3 and any of the first layer Q1 and second layer Q2 may be omitted as appropriate.

[0026] The etching stop layer R is provided for performing selective wet etching on the separation surface of the second wafer S, from which the first wafer W is separated, after separation of the first wafer W, as described below. Specifically, since the laser absorbing layer Q is the main separation surface during separation of the first wafer W, a portion of the laser absorbing layer Q and the etching stop layer R remain on the second wafer S side (first device layer Dw side) after separation. In this state, selective etching of the laser absorbing layer Q and the etching stop layer R first removes only the laser absorbing layer Q. Subsequently, selective etching of the etching stop layer R and the surface of the second wafer S, for example, the first device layer Dw, removes only the etching stop layer R. This can improve the total thickness variation (TTV) of the first device layer Dw after wet etching.

[0027] Conventionally, a method for manufacturing a semiconductor device has been proposed in which two substrates are bonded together to form a laminated substrate. In this manufacturing method, one of the laminated substrates is removed by grinding with a grinder or chemical mechanical polishing (CMP). During this process, a portion of the device layer, including circuit elements such as transistors, formed on the first substrate remains on the other substrate after the first substrate is removed. When grinding is used to remove the substrate, chipping may occur. Furthermore, grinding may require the consumption of a large amount of grinding water. Furthermore, trimming may be required, which may limit the area on the substrate where devices can be formed. Furthermore, the removed substrate cannot be reused in the grinding and CMP processes. Therefore, there is room for improvement in terms of improving yield and reducing costs.

[0028] To solve the above problem, it is conceivable to use a laser separation technique in which one of the laminated substrates is separated by laser irradiation. In the conventional laser separation technique, an oxide film (SiO ２In general, oxide films (oxide films, TEOS films, etc.) are used. However, because such oxide films lack crystallinity, it is not possible to form an epitaxial film on them. Therefore, conventional laser separation techniques using oxide films have limited applicability, such as when a device layer can be formed on the oxide film or when bonding to a support wafer on which no device layer is formed. For example, a transistor cannot be formed in a continuous film formation process on an oxide film. For these reasons, grinding or CMP is exclusively used in methods for bonding substrates having device layers including transistors to form a laminated substrate, which results in the above-mentioned problems.

[0029] Here, as a substrate having a laser absorption layer and a device layer, it is conceivable to use an SOI (Silicon on Insulator) wafer, which is a substrate having a crystalline silicon layer and an oxide film formed as a laser absorption layer. In this case, a device layer including a transistor can be formed in the crystalline silicon layer on the oxide film. However, SOI wafers are expensive, and there is room for improvement in terms of cost reduction.

[0030] To address the above-described problem, in the separation layer Mw according to this embodiment, the sacrificial layer P, the laser absorption layer Q, and the etching stop layer R are all made of epitaxial films, so that an epitaxial film can also be formed on the separation layer Mw. This allows the first device layer Dw including circuit elements such as transistors to be formed on the epitaxial film on the separation layer Mw.

[0031] The crystalline Si film and SiGe film themselves formed by epitaxial growth are irradiated with the laser light L (e.g., CO ２ However, it is difficult to use the film as the laser absorption layer Q as it is because the film is transparent to laser light (laser light, YAG laser light, etc.).

[0032] In contrast, the doped epitaxial film is configured to absorb laser light L of a desired wavelength. In the laser absorption layer Q according to this embodiment, the doped epitaxial film absorbs the laser light L, causing ablation or thermal expansion in the laser absorbing portion. This makes it possible to separate the laser absorption layer Q by irradiating it with a laser.

[0033] As described above, the separation layer Mw according to this embodiment includes the sacrificial layer P, the laser absorption layer Q, and the etching stop layer R, but the technology of the present disclosure is not limited to this. For example, depending on the purpose of the process, one or both of the sacrificial layer P and the etching stop layer R may be omitted from the separation layer Mw.

[0034] The second wafer S prepared in St2 is a semiconductor wafer such as a silicon substrate. In one embodiment, the second wafer S has a substantially circular disk shape.

[0035] In one embodiment, the second wafer S is a device wafer. In this case, as shown in FIG. 2B, a second device layer Ds and a surface film Fs are formed on the surface Sa of the second wafer S. The device layer Ds includes a plurality of devices, which will be described later. There may be cases where devices are not formed in the second device layer Ds when it is prepared in St2, but devices will be formed in a subsequent process. In other words, the second device layer Ds may be a region where devices are to be formed in a process after St2.

[0036] In another embodiment, the second wafer S is a support wafer. In this case, the second device layer Ds is not formed on the surface Sa. In this case, as an example, a separation layer Ms is formed on the surface Sa instead of the second device layer Ds. The separation layer Ms includes a laser absorption layer that absorbs the laser light L. The laser absorption layer is, for example, an oxide film (SiO ２ However, there is no particular limitation as long as it absorbs the laser light L. In one embodiment, the separation layer Ms includes a laser absorption layer Q made of an epitaxial film, similar to the separation layer Mw. A surface film Fs can be formed above the separation layer Ms.

[0037] After preparing the first wafer W and the second wafer S as described above, the first wafer W and the second wafer S are bonded together as shown in Fig. 2(c) to form an overlapped wafer T (St3 in Fig. 1). For convenience of explanation, the description relating to Figs. 2 to 6 will be given assuming that the second wafer S is a device wafer including the second device layer Ds, but the same applies to the case where the second wafer S is a support wafer that does not include the second device layer Ds.

[0038] In St3, the first wafer W and the second wafer S are bonded. The bonding method for the first wafer W and the second wafer S is determined appropriately depending on the types of the device layers Dw and Ds. As an example, in a surface modification device (not shown), the surface films Fw and Fs formed on the device layers Dw and Ds of the first wafer W and the second wafer S are modified by plasma treatment. Furthermore, in a surface hydrophilization device (not shown), pure water is supplied to the surface films to make them hydrophilic, and then the surface films are bonded together in a bonding device (not shown) by van der Waals forces and hydrogen bonds (intermolecular forces).

[0039] Next, as shown in Fig. 4, the laser absorbing layer Q is irradiated with laser light L (St4 in Fig. 1). In St4, a laser irradiation device (not shown) irradiates the laser absorbing layer Q or the interface between the laser absorbing layer Q and the sacrificial layer P with pulsed laser light. The laser light is a CO ２Laser light of a desired wavelength, such as a YAG laser or a GaN laser, can be used according to the laser absorption characteristics of the doped epitaxial film. In this case, the laser light L may be irradiated spirally over the entire surface of the laser absorbing layer Q in a planar view. Alternatively, the laser light L may be irradiated concentrically over the entire surface of the laser absorbing layer Q in an annular pattern. Alternatively, the laser light L may be irradiated in pulses onto the laser absorbing layer Q while a lens (not shown) included in the laser irradiation device is moved linearly. In this case, for example, a linear movement mechanism (transporter) may be provided for the lens to move the lens horizontally, or the laser light from the lens may be scanned by a galvanometer scanner (not shown). The laser light L passes through the first wafer W, the sacrificial layer P, and the etching stop layer R from the back surface Wb side of the first wafer W and is absorbed in the laser absorbing layer Q. This laser light L then causes separation starting from the laser absorbing layer Q.

[0040] 5, the focal region LF of the laser light L is sufficiently wide relative to the width of the stacked epitaxial films in the laser absorbing layer Q. Therefore, even when the laser absorbing layer Q includes first to third layers Q1 to Q3, the laser light L can be absorbed by the entire layer. In one embodiment, the laser light L is irradiated so that the center of the focal region LF of the laser light L is located at the center of the laser absorbing layer Q in the stacking direction, i.e., the third layer Q3. This allows the laser light L to be irradiated onto the entire laser absorbing layer Q.

[0041] Next, as shown in FIG. 6 , the first wafer W and the second wafer S are separated (St5 in FIG. 1 ). In St5, in a separation device (not shown), the first wafer W and the second wafer S are separated from each other using the laser absorption layer Q, the bonding strength of which has been reduced in St4, as a base point. In this specification, the second wafer S after at least a portion of the layers formed on the first wafer W have been transferred and the first wafer W has been separated is referred to as the “second wafer S to which the layers have been transferred” or simply as the “second wafer S.” In the example of FIG. 6 , the first device layer Dw, the surface films Fw and Fs, the second device layer Ds, and the second wafer S are referred to as the “second wafer S to which the first device layer Dw has been transferred” or simply as the “second wafer S.” In the embodiments described below, the same applies to the third wafer U or the fourth wafer V to which at least a portion of the layers of one substrate are transferred.

[0042] After St5, one of the portions Q′ of the laser absorbing layer Q remains on the first wafer W side and the other remains on the second wafer S side. In one embodiment, the laser absorbing layer Q remains on the first wafer W side. In another embodiment, the laser absorbing layer Q remains on the second wafer S side.

[0043] The first wafer W may be separated by any method. As an example, as shown in FIG. 6( a), a suction chuck 10 suction-holds the back surface Sb of the second wafer S, and a suction pad 11 suction-holds the front surface Wa of the first wafer W. Then, as shown in FIG. 6( b), while the suction pad 11 suction-holds the first wafer W, the suction pad 11 is raised to separate the first wafer W and the second wafer S. At this time, because the bonding strength of the laser absorption layer Q has been reduced by the irradiation of the laser light L as described above, the first wafer W and the second wafer S can be separated without applying a large load.

[0044] Next, in the second wafer S onto which the first device layer Fw has been transferred, the separation surface, ie, the surface including the portion Q' of the laser absorption layer Q and the etching stop layer R, is treated (St6 in FIG. 1).

[0045] In St6, first, only the laser absorption layer Q is removed by selective etching of the laser absorption layer Q and the etching stop layer R. Then, only the etching stop layer R is removed by selective etching of the etching stop layer R and the first device layer Dw. This makes it possible to improve the total thickness variation (TTV) of the first device layer Dw after wet etching.

[0046] If the separation layer Mw does not include the etching stop layer R, in St6, the separation surface may be cleaned in, for example, a cleaning device (not shown) to remove the portion Q′ of the laser absorption layer Q. Alternatively, the separation surface may be polished in, for example, a polishing device (not shown) or an etching device (not shown) to flatten or remove the portion Q′ of the laser absorption layer Q.

[0047] In this manner, a semiconductor device in which the first device layer Dw and the second device layer Ds are stacked on the second wafer S is manufactured.

[0048] On the other hand, the separated first wafer W is reused (St8 in FIG. 1). The reuse process for the first wafer W is performed, for example, as follows.

[0049] First, in an etching apparatus (not shown), a portion Q' of the laser absorption layer Q is etched and removed. The etching of the laser absorption layer Q may be dry etching or wet etching. Next, in an etching apparatus (not shown), the sacrificial layer P is etched and removed. The etching of the sacrificial layer P may be dry etching or wet etching.

[0050] The first wafer W from which the laser absorbing layer Q and the sacrificial layer P have been removed is then subjected to the same process as in St1, and a separation layer Mw, a first device layer Dw, and a surface film Fw are formed on the surface Wa. In this way, the first wafer W is reused for the next second wafer S. Note that the first wafer W from which the laser absorbing layer Q and the sacrificial layer P have been removed is a bare wafer with no film formed on the surface Wa, and therefore may be reused as the next second wafer S.

[0051] Although the above description deals with bonding and separation of a first wafer W as a first substrate and a second wafer S as a second substrate, the present disclosure is not limited thereto. For example, the technology disclosed herein can also be suitably used when the second wafer S, onto which a layer on the first wafer W has been transferred, is used as the first or second substrate and bonded to and separated from another substrate. For example, in the embodiment described below, after bonding the first wafer W and the second wafer S, the second wafer S onto which the layer on the first wafer W has been transferred serves as the first substrate, and is bonded to a third wafer U as the second substrate to obtain an overlapped substrate. Furthermore, in another embodiment, after bonding the first wafer W and the second wafer S, the second wafer S onto which the layer on the first wafer W has been transferred serves as the first substrate, and after bonding the third wafer U and a fourth wafer V, the fourth wafer V onto which the layer on the third wafer U has been transferred serves as the second substrate, and these are bonded to obtain an overlapped substrate.

[0052] First Embodiment A method for manufacturing a semiconductor device according to a first embodiment will be described below. As an example, the semiconductor device manufactured by the manufacturing method according to this embodiment is a DRAM (Dynamic Random Access Memory), and more specifically, a 4F ２ (4F square) DRAM. Each step included in the manufacturing method according to this embodiment will be described below.

[0053] First, a first wafer W is prepared (St100 in FIGS. 7 and 8). St100 constitutes a part of the above-mentioned St1. Next, a separation layer Mw is formed on the front surface Wa of the first wafer W, and an epitaxial layer Ep is formed on the separation layer Mw (St101 in FIGS. 7 and 8). St101 constitutes a part of the above-mentioned St1.

[0054] Next, a first circuit region D1 is formed in the epitaxial layer Ep (St102 in FIGS. 7 and 8). St102 constitutes a part of the above-mentioned St1. The first circuit region D1 is an example of a first device layer Dw. Similarly, in the following embodiments, a circuit region formed in the epitaxial layer Ep on one substrate and transferred from one substrate to another substrate is an example of the first device layer Dw. The first circuit region D1, together with a second circuit region D2 and a third circuit region D3 described later, constitutes a memory cell array according to this embodiment. Specifically, as shown in FIG. 8, the first circuit region D1 includes a transistor Tr and a word line WL that constitutes the gate of the transistor Tr.

[0055] The transistor Tr formed in this embodiment, as an example, is a vertical channel transistor (VCT). The VCT has a channel (not shown) formed to extend in a direction perpendicular to the surface of the first wafer W. The channel is made of a crystalline Si film formed on an epitaxial layer Ep. The channel also has doped crystalline Si films as a source or drain at both ends of the channel connected to a bit line BL or a capacitor Cp. The VCT also has a back gate electrode (not shown), and two transistors Tr share this back gate electrode.

[0056] An interlayer insulating film Ox is laminated on the first circuit region D1 except for the transistors Tr and the word lines WL. The interlayer insulating film Ox is made of, for example, a silicon oxide film.

[0057] Next, a bit line BL is formed in the first circuit region D1, which is electrically connected to one end of the channel of the transistor Tr, and a surface film Fw for junction is further formed (Step 103 in FIGS. 7 and 8). Step 103 constitutes a part of Step 1 described above.

[0058] Next, a second wafer S is prepared (St104 in FIGS. 7 and 8 ). St104 is the same as St2 described above. In the second device layer Ds of the second wafer S according to this embodiment, a peripheral circuit for controlling the memory cell array is formed. The peripheral circuit in the second device layer Ds according to this embodiment includes a CMOS (Complementary Metal-Oxide-Semiconductor) and a wiring layer Wr. A surface film Fs for bonding is formed on the second device layer Ds.

[0059] Next, the first wafer W and the second wafer S are bonded together to obtain an overlapped wafer T (Step 105 in FIGS. 7 and 8 ). Step 105 is the same as Step 3 described above. In this embodiment, the bonding between the first wafer W and the second wafer S is performed by fusion bonding of a surface film Fw of the first wafer W and a surface film Fs of the second wafer S, both of which are made of insulating films. The dashed line in the overlapped wafer T in FIG. 8 indicates the bonding surfaces of the surface films Fw and Fs.

[0060] Next, a laser is irradiated onto the laser absorption layer Q of the separation layer Mw in the first wafer W, thereby separating the first wafer W (St106 in FIGS. 7 and 8 ). St106 is the same as St4 and St5 described above. As a result, the first circuit region D1 is transferred to the second wafer S. Thereafter, wet etching is performed on the separation surface Ps of the second wafer S from which the first wafer W has been separated. In one embodiment, the wet etching exposes the first circuit region D1 at the separation surface Ps of the second wafer S. In one embodiment, a portion of the transistor Tr included in the first circuit region D1 is exposed.

[0061] Next, a second circuit region D2 is formed on the separation surface Ps of the second wafer S (Step 107 in FIGS. 7 and 8). The second circuit region D2 includes a capacitor Cp electrically connected to one end of the channel of the transistor Tr. The capacitor Cp can be formed using a known method such as RIE or CVD. An interlayer insulating film Ox is laminated on the portion of the second circuit region D2 excluding the capacitor Cp.

[0062] Next, a third circuit region D3 is formed (Step St108 in FIGS. 7 and 8 ). The third circuit region D3 includes a wiring layer Wr formed by a known wiring process (BEOL: Back End of Line). The wiring layer Wr formed in Step St108 includes, for example, a through-silicon via TSV (Through-Silicon Via) electrically connected to the wiring layer Wr included in the second device layer Ds. In one embodiment, the wiring layer Wr formed in Step St108 is formed as a back side power delivery network (BSPDN).

[0063] By using a method including the above steps, a DRAM structure in which a memory cell array and a CMOS are bonded can be obtained on the second wafer S. Furthermore, the first wafer W separated in St106 can be reused.

[0064] In this embodiment, 4F ２ Although an example of a DRAM structure has been described, the manufacturing method of the present disclosure is not limited to this and can also be applied to bonding and laser separation of substrates having different types of DRAM structures or other device structures. That is, the technology of the present disclosure can be suitably used when bonding and laser separation of a device structure including any circuit element having a crystalline Si film (crystalline SiGe film) formed based on the epitaxial layer Ep of the first wafer W.

[0065] Second Embodiment A method for manufacturing a semiconductor device according to the first embodiment will be described below. As an example, a semiconductor device manufactured by the manufacturing method according to this embodiment is a 4F ２ The manufacturing method according to this embodiment will be described below.

[0066] First, a first wafer W is prepared (Step 200 in FIGS. 9 and 10 ). Step 200 constitutes a part of Step 1 described above. Next, a separation layer Mw is formed on the front surface Wa of the first wafer W, and an epitaxial layer Ep is formed on the separation layer Mw (Step 201 in FIGS. 9 and 10 ). Step 201 constitutes a part of Step 1 described above.

[0067] Next, a first circuit region D1 is formed in the epitaxial layer Ep (Step St202 in FIGS. 9 and 10). Step St202 constitutes a part of Step St1. The first circuit region D1, together with a second circuit region D2 (described later), constitutes a memory cell array according to this embodiment.

[0068] The first circuit region D1 includes a transistor Tr, a word line WL, and a capacitor Cp. The details of the formation of the transistor Tr, the word line WL, and the capacitor Cp are the same as those in the first embodiment. A surface film Fw for bonding is formed on the first circuit region D1.

[0069] Next, a second wafer S is prepared (Step 203 in FIGS. 9 and 10 ). Step 203 is the same as Step 2 described above. The second wafer S according to this embodiment is a support wafer including a separation layer Ms. A bonding surface film Fs is formed on the separation layer Ms.

[0070] Next, the first wafer W and the second wafer S are bonded together to obtain a first overlapped wafer T1 (Step 204 in FIGS. 9 and 10 . Step 204 is the same as Step 3 described above, and the obtained first overlapped wafer T1 corresponds to the overlapped wafer T obtained in Step 3. In this embodiment, the bonding of the first wafer W and the second wafer S is performed by fusion bonding of the surface film Fw of the first wafer W and the surface film Fs of the second wafer S, both of which are made of insulating films.

[0071] Next, the laser absorption layer Q of the separation layer Mw in the first wafer W is irradiated with a laser to separate the first wafer W (St205 in FIGS. 9 and 10 ). St205 is the same as St4 and St5 described above. As a result, the first circuit region D1 is transferred to the second wafer S. Thereafter, wet etching is performed on the separation surface Ps of the second wafer S from which the first wafer W has been separated. In one embodiment, the wet etching exposes the first circuit region D1 at the separation surface Ps of the second wafer S. In one embodiment, a portion of the transistor Tr included in the first circuit region D1 is exposed.

[0072] Next, a second circuit region D2 is formed on the separation surface Ps of the second wafer S (Step 206 in FIGS. 9 and 10). The second circuit region D2 includes the bit lines BL and a portion of the wiring layer Wr for power supply. A bonding surface film Ft is also formed on the second circuit region D2. The surface film Ft includes copper pads Cu that are electrically connected to the bit lines BL and the wiring layer Wr for power supply. While the copper pads Cu in this embodiment are made of copper, this is not a limitation and desired pads made of other metals, such as aluminum, may also be used. This also applies to other wiring layers Wr and copper pads Cu or wiring layers Wr in other embodiments.

[0073] Next, a third wafer U is prepared (St207 in FIGS. 9 and 10 ). St207 is the same as St2 described above, and the third wafer U has the same configuration as the second wafer S as a device wafer. In this embodiment, the third wafer U includes a third device layer Du, which includes a CMOS as a peripheral circuit for controlling the memory cell array. A bonding surface film Fu is formed on the third device layer Du. The surface film Fu includes a copper pad Cu electrically connected to the CMOS via a wiring layer Wr.

[0074] Next, the second wafer S and the third wafer U are bonded together to obtain a second overlapping wafer T2 (St208). The bonding between the second wafer S and the third wafer U according to this embodiment is similar to the bonding between the first wafer W and the second wafer S in St3 described above, and the obtained second overlapping wafer T2 corresponds to the overlapping wafer T obtained in St3. The bonding between the second wafer S and the third wafer U is a hybrid bonding that includes fusion bonding between the surface films Ft and Fu and bonding between the copper pads Cu formed on the surface films Ft and Fu, respectively.

[0075] Next, the separation layer Ms of the second wafer S included in the second overlapped wafer T2 is irradiated with a laser to separate the second wafer S (St209 in FIGS. 9 and 10 ). As a result, the first circuit region D1 and the second circuit region D2 are transferred to the third wafer U. St209 is the same as St4 and St5 described above. Thereafter, wet etching is performed on the separation surface Pu of the third wafer U from which the second wafer S has been separated.

[0076] Next, a third circuit region D3 is formed on the separation surface Pu of the third wafer U (Step 210 in FIGS. 9 and 10). The third circuit region D3 includes a wiring layer Wr formed by a known wiring process (BEOL).

[0077] By a method including the above steps, a DRAM structure in which a memory cell array and a CMOS are bonded can be obtained on the third wafer U. The first wafer W separated in St205 can be reused. The second wafer S separated in St209 can be reused. Third Embodiment A method for manufacturing a semiconductor device according to the first embodiment will be described below. As an example, a semiconductor device manufactured by the manufacturing method according to this embodiment is a 3D DRAM. Each step included in the manufacturing method according to this embodiment will be described below.

[0078] First, a first wafer W is prepared (St300 in FIGS. 11 and 12). St300 constitutes a part of the above-mentioned St1. Next, a separation layer Mw is formed on the front surface Wa of the first wafer W, and an epitaxial layer Ep is formed on the separation layer Mw (St301 in FIGS. 11 and 12). St301 constitutes a part of the above-mentioned St1. The epitaxial layer Ep formed on the separation layer Mw in St301 has a structure in which multiple Si films and SiGe films are alternately stacked.

[0079] Next, a first circuit region D1 is formed in the epitaxial layer Ep (Step St302 in FIGS. 11 and 12). Step St302 constitutes a part of Step St1. The first circuit region D1, together with a second circuit region D2 (described later), constitutes a memory cell array according to this embodiment.

[0080] The first circuit region D1 includes a plurality of transistors Tr stacked in a direction perpendicular to the surface of the first wafer W, as well as word lines WL and capacitors Cp electrically connected to the transistors Tr. The first circuit region D1 also includes vertical bit lines BL extending perpendicular to the surface of the first wafer W. In one embodiment, electrodes (not shown) that form part of the through-silicon electrodes formed in a wiring process described below are formed in the first circuit region D1. The manufacturing method of the present disclosure is not limited to the case where vertical bit lines are provided, and is also applicable to the case where the first circuit region D1 includes vertical word lines WL extending perpendicular to the surface of the first wafer W.

[0081] Next, in the first circuit region D1, a wiring layer Wr is formed, and further, a bonding surface film Fw is formed (St303 in FIGS. 11 and 12 ). St303 constitutes a part of the above-mentioned St1. The surface film Fw includes a copper pad Cu electrically connected to the wiring layer Wr. In one embodiment, when an electrode (not shown) is formed in the first circuit region D1, the wiring layer Wr can be formed in St303 so as to be electrically connected to the electrode.

[0082] Next, a second wafer S is prepared (St304 in FIGS. 11 and 12). St304 is the same as St2 described above. In the second device layer Ds of the second wafer S according to this embodiment, a peripheral circuit for controlling the memory cell array is formed. The peripheral circuit in the second device layer Ds according to this embodiment includes a CMOS. A surface film Fs for bonding is formed on the second device layer Ds. The surface film Fs includes a copper pad Cu electrically connected to the CMOS via the wiring layer Wr.

[0083] Next, the first wafer W and the second wafer S are bonded together to obtain a laminated wafer T (Step 305 in FIGS. 11 and 12 ). Step 305 is the same as Step 3 described above. The bonding of the first wafer W and the second wafer S according to this embodiment is a hybrid bonding method that includes fusion bonding between the surface films Fw and Fs and bonding between the copper pads Cu formed on the surface films Ft and Fu, respectively.

[0084] Next, a laser is irradiated onto the laser absorption layer Q of the separation layer Mw in the first wafer W, thereby separating the first wafer W (St306 in FIGS. 11 and 12 ). St306 is the same as St4 and St5 described above. As a result, the first circuit region D1 is transferred to the second wafer S. Thereafter, wet etching is performed on the separation surface Sp of the second wafer S from which the first wafer W has been separated. In one embodiment, the first circuit region D1 is exposed on the separation surface Sp of the second wafer S by wet etching. In one embodiment, when an electrode (not shown) is formed in the first circuit region D1, a portion of the electrode is exposed.

[0085] Next, a second circuit region D2 is formed on the separation surface Sp of the second wafer S (Step 307 in FIGS. 11 and 12 ). The second circuit region D2 includes a wiring layer Wr formed by a known wiring process (BEOL). In one embodiment, if an electrode (not shown) is formed in the first circuit region D1, the wiring layer Wr can be formed in Step 307 so as to be electrically connected to the electrode.

[0086] By using a method including the above steps, a 3D DRAM structure in which a memory cell array and a CMOS are bonded together can be obtained on the second wafer S. In addition, the first wafer W separated in St306 can be reused.

[0087] Fourth Embodiment A method for manufacturing a semiconductor device according to a fourth embodiment will be described below. As an example, a semiconductor device manufactured by the manufacturing method according to this embodiment is a 4F ２ In another embodiment, the semiconductor device is a 3D DRAM. Each step included in the manufacturing method according to this embodiment will be described below.

[0088] First, a first wafer W is prepared (Step 400 in FIGS. 13 and 14 ). Step 400 constitutes a part of Step 1 described above. Next, a separation layer Mw is formed on the front surface Wa of the first wafer W, and an epitaxial layer Ep is formed on the separation layer Mw (Step 401 in FIGS. 13 and 14 ). Step 401 constitutes a part of Step 1 described above.

[0089] Next, a first circuit region D1 is formed in the epitaxial layer Ep (Step St402 in FIGS. 13 and 14). Step St402 constitutes a part of Step St1. The first circuit region D1 constitutes a peripheral circuit for controlling the memory cell array according to this embodiment. The peripheral circuit includes a CMOS and a wiring layer Wr electrically connected to the CMOS. A surface film Fw for bonding is formed on the first circuit region D1.

[0090] Next, a second wafer S is prepared (Step 403 in FIGS. 13 and 14 ). Step 403 is the same as Step 2 described above. The second wafer S according to this embodiment is a support wafer including a separation layer Ms. A surface film Fs for bonding is formed on the separation layer Ms.

[0091] Next, the first wafer W and the second wafer S are bonded together to obtain a first overlapping wafer T1 (Step 404 in FIGS. 13 and 14 . Step 404 is the same as Step 3 described above, and the obtained first overlapping wafer T1 corresponds to the overlapping wafer T obtained in Step 3. In this embodiment, the bonding of the first wafer W and the second wafer S is performed by fusion bonding of the surface film Fw of the first wafer W and the surface film Fs of the second wafer S, both of which are made of insulating films.

[0092] Next, the laser absorption layer Q of the separation layer Mw in the first wafer W is irradiated with a laser to separate the first wafer W (St405 in FIGS. 13 and 14 ). St405 is the same as St4 and St5 described above. As a result, the first circuit region D1 is transferred to the second wafer S. Thereafter, wet etching is performed on the separation surface Sp of the second wafer S from which the first wafer W has been separated. In one embodiment, the first circuit region D1 is exposed on the separation surface Sp of the second wafer S by wet etching.

[0093] Next, a surface film Ft for bonding is formed on the separation surface Ps of the second wafer S (Step 406 in FIGS. 13 and 14).

[0094] Next, a third wafer U is prepared (Step 407 in FIGS. 13 and 14). Step 407 is the same as Step 2 described above, and the third wafer U has the same configuration as the second wafer S as a device wafer. In this embodiment, the third wafer U includes a third device layer Du. The third device layer Du includes at least a part of a memory cell array. In this embodiment, the third device layer Du is 4F ２ The third device layer Du includes at least a part of a memory cell array in a DRAM, specifically, a transistor Tr, a word line WL, a bit line BL, a capacitor Cp, and a wiring layer Wr. A surface film Fu for bonding is formed on the third device layer Du.

[0095] Next, the second wafer S and the third wafer U are bonded together to obtain a second overlapping wafer T2 (Step 408 in FIGS. 13 and 14 ). Step 408 is similar to the bonding of the first wafer W and the second wafer S in Step 3 described above, and the obtained second overlapping wafer T2 corresponds to the overlapping wafer T obtained in Step 3. The bonding of the second wafer S and the third wafer U is performed by fusion bonding of the surface films Ft and Fu.

[0096] Next, the separation layer Ms of the second wafer S included in the second overlapped wafer T2 is irradiated with a laser to separate the second wafer S (Step 409 in FIGS. 13 and 14 ). As a result, the first circuit region D1 is transferred to the third wafer U. Thereafter, the separation surface Pu of the third wafer U from which the second wafer S has been separated is wet-etched.

[0097] Next, a second circuit region D2 is formed on the separation surface Pu of the third wafer U (Step 410 in FIGS. 13 and 14). The second circuit region D2 includes a wiring layer Wr formed by a known wiring process (BEOL).

[0098] By using a method including the above steps, a DRAM structure in which a memory cell array and a CMOS are bonded can be obtained on the third wafer U. The first wafer W separated in St405 can be reused. The second wafer S separated in St409 can be reused.

[0099] A modified example of the method for manufacturing a semiconductor device according to the fourth embodiment will now be described. In this modified example, CFETs (Complementary Field-Effect Transistors) are formed as peripheral circuits for controlling a memory cell array in the first circuit region D1 of the first wafer W. Specifically, as shown in FIG. 15 , the steps of St401 and St402 for preparing the first wafer W include the following steps:

[0100] In St401 according to this modification, the epitaxial layer Ep formed on the separation layer Mw has a structure in which a plurality of Si films and SiGe films, which are crystalline epitaxial films, are alternately stacked. More specifically, the epitaxial layer Ep includes stacked layers of Si films and SiGe films, which are regions (nMOS') where an nMOS is to be formed and regions (pMOS') where a pMOS is to be formed, and a SiGe film, which is a region (MDI') where an interlayer insulating layer (MDI: Middle Dielectric Isolation) is to be formed between the nMOS and pMOS. The MDI according to this modification is a replacement MDI formed by epitaxial growth continuously with the Si films and SiGe films in the regions where the nMOS and pMOS are to be formed.

[0101] In St402 according to this modification, a CFET is formed on the epitaxial layer Ep, including an nMOS and a pMOS stacked in a direction perpendicular to the surface of the first wafer W, and an interlayer insulating layer MDI provided therebetween. In St402 according to this modification, the CFET can be formed on the epitaxial layer Ep by a known monolithic-CFET process. Note that the stacking positions of the nMOS and pMOS may be reversed from the example in FIG. 15 .

[0102] By the method including steps St401 and St402 according to this modification, it is possible to obtain the second overlapped wafer T2 having a DRAM structure in which a memory cell array and a CFET are bonded together.

[0103] Fifth Embodiment A method for manufacturing a semiconductor device according to a fifth embodiment will be described below. As an example, the semiconductor device manufactured by the manufacturing method according to this embodiment is a 3D DRAM. Each step included in the manufacturing method according to this embodiment will be described below.

[0104] First, a first wafer W is prepared (St500 in FIGS. 16 and 17 ). St500 constitutes a part of the above-mentioned St1. Next, a separation layer Mw is formed on the front surface Wa of the first wafer W, and an epitaxial layer Ep is formed on the separation layer Mw (St501 in FIGS. 16 and 17 ). St501 constitutes a part of the above-mentioned St1.

[0105] Next, a first circuit region D1 is formed in the epitaxial layer Ep (St502 in FIGS. 16 and 17). St502 constitutes a part of St1 described above. The first circuit region D1 constitutes a peripheral circuit for controlling the memory cell array according to this embodiment. The peripheral circuit includes a CMOS and a wiring layer Wr electrically connected to the CMOS. A surface film Fw for bonding is formed on the first circuit region D1. The surface film Fw includes a copper pad Cu electrically connected to the wiring layer Wr. In one embodiment, the first circuit region D1 includes an electrode (not shown) connected to the wiring layer Wr of the second circuit region D2 described below.

[0106] Next, a second wafer S is prepared (St503 in FIGS. 16 and 17 ). St503 is the same as St2 described above. At least a portion of a memory cell array of a 3D DRAM is formed in the second device layer Ds of the second wafer S according to this embodiment. The formation of the memory cell array of the 3D DRAM in the second device layer Ds of the second wafer S is the same as in the third embodiment. In one embodiment, when an electrode (not shown) is formed in the first circuit region D1, the wiring layer Wr can be formed in St503 so as to be electrically connected to the electrode.

[0107] Specifically, the second device layer Ds includes a plurality of transistors Tr, word lines WL electrically connected to the transistors Tr, and capacitors Cp stacked in a direction perpendicular to the surface of the first wafer W. The second device layer Ds also includes vertical bit lines extending perpendicular to the surface of the first wafer W as bit lines BL. The manufacturing method of the present disclosure is not limited to the case where vertical bit lines are provided, and in one embodiment, is also applicable to the case where the first circuit region D1 includes vertical word lines extending perpendicular to the surface of the first wafer W as word lines WL. A bonding surface film Fs is formed on the second device layer Ds. The surface film Fs includes copper pads Cu electrically connected to the wiring layer Wr.

[0108] Next, the first wafer W and the second wafer S are bonded together to obtain a laminated wafer T (Step 504 in FIGS. 16 and 17 ). Step 504 is the same as Step 3 described above. In this embodiment, the bonding between the first wafer W and the second wafer S is performed by hybrid bonding between copper pads Cu formed on the surface films Fw and Fs, respectively.

[0109] Next, a laser is irradiated onto the laser absorption layer Q of the separation layer Mw in the first wafer W to separate the first wafer W (St505 in FIGS. 16 and 17 ). St505 is the same as St4 and St5 described above. Thereafter, wet etching is performed on the separation surface Ps of the second wafer S from which the first wafer W has been separated. In one embodiment, the wet etching exposes the first circuit region D1 at the separation surface Ps of the second wafer S. In one embodiment, when an electrode (not shown) is formed in the first circuit region D1, a portion of the electrode is exposed.

[0110] Next, a second circuit region D2 is formed on the separation surface Ps of the second wafer S (Step 506 in FIGS. 16 and 17 ). The second circuit region D2 includes a wiring layer Wr formed by a known wiring process (BEOL). In one embodiment, if an electrode (not shown) is formed in the first circuit region D1, the wiring layer Wr can be formed in Step 506 so as to be electrically connected to the electrode.

[0111] By using a method including the above steps, a 3D DRAM structure in which a memory cell array and a CMOS are bonded together can be obtained on the second wafer S. In addition, the first wafer W separated in St505 can be reused.

[0112] Sixth Embodiment A method for manufacturing a semiconductor device according to a sixth embodiment will be described below. The manufacturing method according to this embodiment is an example of a combination of the manufacturing methods according to the first to fourth embodiments. As an example, a semiconductor device manufactured by the manufacturing method according to this embodiment is 4F ２ The manufacturing method according to this embodiment will be described below.

[0113] First, a first wafer W is prepared (St600 in FIG. 18 ). St600 constitutes a part of the above-mentioned St1. Next, the first wafer W is prepared. Specifically, a separation layer Mw is formed on the front surface Wa of the first wafer W, and an epitaxial layer Ep is formed on the separation layer Mw (St601 in FIGS. 18 and 19 ). St601 constitutes a part of the above-mentioned St1.

[0114] Next, a first circuit region D1 is formed in the epitaxial layer Ep (Step St602 in FIGS. 18 and 19). Step St602 constitutes a part of Step St1. The first circuit region D1 constitutes a memory cell array according to this embodiment.

[0115] The first circuit region D1 includes a transistor Tr, a word line WL, and a capacitor Cp. The details of the formation of the transistor Tr, the word line WL, and the capacitor Cp are the same as those in the first embodiment. The first circuit region D1 also includes a part of the wiring layer Wr for power supply. A surface film Fw for bonding is formed on the first circuit region D1.

[0116] Next, a second wafer S is prepared (Step 603 in FIGS. 18 and 19 ). Step 603 is the same as Step 2 described above. The second wafer S according to this embodiment is a support wafer including a separation layer Ms. A surface film Fs for bonding is formed on the separation layer Ms.

[0117] Next, the first wafer W and the second wafer S are bonded together to obtain a first overlapping wafer T1 (Step 604 in FIGS. 18 and 19 . Step 604 is the same as Step 3 described above, and the obtained first overlapping wafer T1 corresponds to the overlapping wafer T obtained in Step 3. The bonding of the first wafer W and the second wafer S according to this embodiment is performed by fusion bonding of the surface film Fw of the first wafer W and the surface film Fs of the second wafer S, both of which are made of insulating films.

[0118] Next, a laser is irradiated onto the laser absorption layer Q of the separation layer Mw in the first wafer W, thereby separating the first wafer W (St605 in FIGS. 18 and 19 ). St605 is the same as St4 and St5 described above. As a result, the first circuit region D1 is transferred to the second wafer S. Thereafter, wet etching is performed on the separation surface Ps of the second wafer S from which the first wafer W has been separated. In one embodiment, the wet etching exposes the first circuit region D1 at the separation surface Ps of the second wafer S. In one embodiment, a portion of the transistor Tr included in the first circuit region D1 is exposed.

[0119] Next, a second circuit region D2 is formed on the separation surface Ps of the second wafer S (Step 606 in FIGS. 18 and 19). The second circuit region D2 includes a bit line BL electrically connected to the transistor Tr. A bonding surface film Ft1 is formed on the second circuit region D2.

[0120] Next, a third wafer U is prepared. Specifically, a separation layer Mu is formed on the surface of the third wafer U, and an epitaxial layer Ep is formed on the separation layer Mu (Step 607 in FIGS. 18 and 19 ). The third wafer U is similar to the first wafer W in Step 1 described above. The separation layer Mu is similar to the separation layer Mw in the first wafer W, and includes a laser absorption layer Q including a doped epitaxial film.

[0121] Next, a third circuit region D3 is formed in the epitaxial layer Ep (Step St608 in FIGS. 18 and 19). Step St608 constitutes a part of Step St1 described above. The third circuit region D3 constitutes a peripheral circuit for controlling the memory cell array according to this embodiment. The peripheral circuit includes a CMOS and a wiring layer Wr electrically connected to the CMOS. A surface film Fw for bonding is formed on the third circuit region D3.

[0122] Next, a fourth wafer V is prepared (Step 609 in FIGS. 18 and 19 ). Step 609 is the same as Step 2 described above, and the fourth wafer V is the same as the second wafer S according to this embodiment. The fourth wafer V according to this embodiment is a support wafer including a fourth separation layer Mv. A bonding surface film Fv is formed on the fourth separation layer Mv.

[0123] Next, the third wafer U and the fourth wafer V are bonded together to obtain a second overlapping wafer T2 (Step 610 in FIGS. 18 and 19 . Step 610 is the same as Step 3 described above, and the obtained second overlapping wafer T2 corresponds to the overlapping wafer T obtained in Step 3. In this embodiment, the bonding of the third wafer U and the fourth wafer V is performed by fusion bonding of the surface film Fu of the third wafer U and the surface film Fv of the fourth wafer V, both of which are made of insulating films.

[0124] Next, the laser absorption layer Q of the separation layer Mu in the third wafer U is irradiated with a laser to separate the first wafer W (Step 611 in FIGS. 18 and 19 ). Step 611 is the same as Steps 4 and 5 described above. This transfers the third circuit region D3 to the fourth wafer V. Thereafter, wet etching is performed on the separation surface Pv of the fourth wafer V from which the third wafer U has been separated. In one embodiment, the wet etching exposes the third circuit region D3 at the separation surface Pv of the fourth wafer V.

[0125] Next, a surface film Ft2 for bonding is formed on the separation surface Pv of the fourth wafer V (St612 in FIGS. 18 and 19).

[0126] Next, the second wafer S and the fourth wafer V are bonded together to obtain a third overlapping wafer T3 (Step 613 in FIGS. 18 and 19 ). The bonding between the second wafer S and the fourth wafer V according to this embodiment is similar to the bonding between the first wafer W and the second wafer S in Step 3 described above, and the obtained third overlapping wafer T3 corresponds to the overlapping wafer T obtained in Step 3. The bonding between the second wafer S and the fourth wafer V is performed by fusion bonding of the surface films Ft1 and Ft2.

[0127] Next, the fourth separation layer Mv of the fourth wafer V included in the third overlapped wafer T3 is irradiated with a laser to separate the fourth wafer V (St614 in FIGS. 18 and 19 ). As a result, the third circuit region D3 is transferred to the second wafer S. Thereafter, the separation surface Ps of the second wafer S from which the fourth wafer V has been separated is wet-etched.

[0128] Next, a fourth circuit region D4 is formed on the separation surface Ps of the second wafer S (Step 615 in FIGS. 18 and 19). The fourth circuit region D4 includes a wiring layer Wr formed by a known wiring process (BEOL).

[0129] By using a method including the above steps, a DRAM structure in which a memory cell array and a CMOS are bonded can be obtained on the second wafer S. In addition, the first wafer W separated in St605 and the third wafer U separated in St611 can be reused.

[0130] In this embodiment, the first overlapping wafer T1 has a memory cell array of 4F ２ In the above embodiment, a circuit region including a DRAM is formed, and a circuit region including a CMOS is formed as a peripheral circuit in the second overlapping wafer T2, but this is not limiting. The manufacturing method of the present disclosure is also applicable to cases where a 3D DRAM is included as a memory cell array, or where a CFET is included as a peripheral circuit. <Seventh Embodiment> A method for manufacturing a semiconductor device according to a seventh embodiment will be described below. As an example, a semiconductor device manufactured by the manufacturing method according to this embodiment includes a stacked CMOS. Each step included in the manufacturing method according to this embodiment will be described below.

[0131] First, a first wafer W is prepared (Step 700 in FIG. 20). Step 700 constitutes a part of the above-mentioned Step 1. Next, a separation layer Mw is formed on the front surface Wa of the first wafer W, and an epitaxial layer Ep is formed on the separation layer Mw (Step 701 in FIGS. 20 and 21). Step 701 constitutes a part of the above-mentioned Step 1.

[0132] Next, a first device layer Dw is formed on the epitaxial layer Ep (Step 702 in FIGS. 20 and 21). Step 702 constitutes a part of Step 1 described above. The first device layer Dw includes a CMOS and a wiring layer Wr electrically connected to the CMOS. A surface film Fw for bonding is formed on the first device layer Dw. The surface film Fw includes a copper pad Cu electrically connected to the wiring layer Wr.

[0133] Next, a second wafer S is prepared (Step 703 in FIGS. 20 and 21). Step 703 is the same as Step 2 described above. The second device layer Ds of the second wafer S according to this embodiment includes a wiring layer Wr electrically connected to the CMOS. A surface film Fs for bonding is formed on the second device layer Ds. The surface film Fs includes a copper pad Cu electrically connected to the wiring layer Wr.

[0134] Next, the first wafer W and the second wafer S are bonded together to obtain a laminated wafer T (Step 704 in FIGS. 20 and 21 ). Step 704 is the same as Step 3 described above. In this embodiment, the bonding between the first wafer W and the second wafer S is performed by hybrid bonding between copper pads Cu formed on the surface films Fw and Fs, respectively.

[0135] Next, the laser absorption layer Q of the separation layer Mw in the first wafer W is irradiated with a laser to separate the first wafer W (St705 in FIGS. 20 and 21 ). St705 is the same as St4 and St5 described above. As a result, the first device layer Dw is transferred to the second wafer S. Thereafter, wet etching is performed on the separation surface Ps of the second wafer S from which the first wafer W has been separated.

[0136] A method including the above steps can obtain a second wafer S having stacked CMOSs ​​stacked in a direction perpendicular to the surface of the second wafer S. The first wafer W separated at St705 can be reused. In one embodiment, the stacked CMOSs ​​of the second wafer S can be used as a peripheral circuit for controlling the memory cell array in the other embodiments described above.

[0137] Eighth Embodiment A method for manufacturing a semiconductor device according to an eighth embodiment will be described below. As an example, a semiconductor device manufactured by the manufacturing method according to this embodiment includes a CFET. Each step included in the manufacturing method according to this embodiment will be described below.

[0138] First, a first wafer W is prepared (St800 in FIG. 22). St800 constitutes a part of the above-described St1. Next, an isolation layer Mw is formed on the front surface Wa of the first wafer W, and an epitaxial layer Ep1 is formed on the isolation layer Mw (St801 in FIGS. 22 and 23). St801 constitutes a part of the above-described St1. The epitaxial layer Ep1 according to this embodiment formed on the isolation layer Mw has a structure in which multiple crystalline epitaxial films, Si films and SiGe films, are alternately stacked. More specifically, the epitaxial layer Ep1 includes a stack of Si films and SiGe films, which is a region (nMOS') where an nMOS is to be formed. Furthermore, a surface film Fw for bonding is formed on the region (nMOS') where an nMOS is to be formed. The surface film Fw constitutes a part of a region MDI' where an interlayer insulating layer MDI is to be formed.

[0139] Next, a second wafer S is prepared (Step St802 in FIG. 22). Step St802 constitutes a part of Step St1 described above. Next, a separation layer Ms is formed on the surface Sa of the second wafer S, and an epitaxial layer Ep2 is formed on the separation layer Ms (Step St803 in FIGS. 22 and 23). Note that the separation layer Ms is similar to the separation layer Mw in the first wafer W and includes a laser absorption layer Q including a doped epitaxial film. Step St803 constitutes a part of Step St2 described above. The epitaxial layer Ep2 according to this embodiment formed on the separation layer Ms has a structure in which multiple crystalline epitaxial films, Si films and SiGe films, are alternately stacked. More specifically, the epitaxial layer Ep2 includes a stack of Si films and SiGe films, which are the planned region for forming a pMOS (pMOS'). Furthermore, a surface film Fs for bonding is formed on the planned region for forming a pMOS (pMOS'). The surface film Fs constitutes a part of a region MDI' in which an interlayer insulating layer MDI is to be formed.

[0140] Next, the first wafer W and the second wafer S are bonded together to obtain a first overlapping wafer T1 (Step 804 in FIGS. 22 and 23 ). Step 804 is the same as Step 3 described above, and the obtained first overlapping wafer T1 corresponds to the overlapping wafer T obtained in Step 3. In this embodiment, the bonding between the first wafer W and the second wafer S is performed by fusion bonding of a surface film Fw of the first wafer W and a surface film Fs of the second wafer S, both of which are made of insulating films. The bonded portion between the surface film Fw and the surface film Fs constitutes an interlayer insulating layer MDI.

[0141] Next, the laser absorption layer Q of the separation layer Mw in the first wafer W is irradiated with a laser to separate the first wafer W (St805 in FIGS. 22 and 23 ). St805 is the same as St4 and St5 described above. As a result, the epitaxial layer Ep1 is transferred to the second wafer S. Thereafter, wet etching is performed on the separation surface Ps of the second wafer S from which the first wafer W has been separated.

[0142] Next, an nMOS and a pMOS are formed in the nMOS formation region (nMOS') of the epitaxial layer Ep1 and the pMOS formation region (pMOS') of the epitaxial layer Ep2, respectively (Step 806 in FIGS. 22 and 23). This results in a CFET including an nMOS and a pMOS stacked in a direction perpendicular to the surface of the second wafer S, and an interlayer insulating layer MDI provided between them. In Step 806, the CFET can be formed by a known monolithic CFET process for the epitaxial layers Ep1 and Ep2. The MDI according to this embodiment is a buried MDI (embedded-MDI) formed by bonding an insulating film on the nMOS and an insulating film on the pMOS. The stacking positions of the nMOS and pMOS may be reversed from those shown in the figures.

[0143] A second wafer S having a CFET can be obtained by a method including the above steps. The first wafer W separated in St805 can be reused. In one embodiment, the CFET included in the second wafer S can be used as a peripheral circuit for controlling the memory cell array in the other embodiments described above.

[0144] In one embodiment, after St806 is performed, a wiring layer (not shown) and a bonding surface film Ft are formed on the CFET. A third wafer U is also prepared (St807 in FIGS. 22 and 23). St807 is the same as St2 described above. The third wafer U in this embodiment is a support wafer including a separation layer Mu. A bonding surface film Fu is formed on the separation layer Mu.

[0145] Next, the second wafer S and the third wafer U are bonded together to obtain a second overlapping wafer T2 (Step 808 in FIGS. 22 and 23 . Step 808 is the same as Step 3 described above, and the obtained second overlapping wafer T2 corresponds to the overlapping wafer T obtained in Step 3. The bonding of the second wafer S and the third wafer U according to this embodiment is performed by fusion bonding of the surface film Ft of the second wafer S and the surface film Fu of the third wafer U, both of which are made of insulating films.

[0146] Next, a laser is irradiated onto the laser absorption layer Q of the separation layer Ms in the second wafer S included in the second overlapping wafer T2, thereby separating the second wafer S (Step 809 in FIGS. 22 and 23 ). Step 809 is the same as Steps 4 and 5 described above. As a result, the CFET and a wiring layer (not shown) are transferred to the third wafer U. Thereafter, wet etching is performed on the separation surface Pv of the third wafer U from which the second wafer S is separated. The separated second wafer S can be reused. In one embodiment, further, other circuit regions including a wiring layer (not shown) are formed on the surface of the third wafer U from which the second wafer S is separated by a known wiring process (BEOL).

[0147] A modified example of the method for manufacturing a semiconductor device according to the eighth embodiment will now be described. In the above St801 to St806, the CFET is formed by a monolithic CFET process, but in this modified example, the CFET is formed by a sequential-CFET process.

[0148] Specifically, in St803 of this modification, after the epitaxial layer Ep2 is formed on the second wafer S, a pMOS is formed in the region (pMOS') of the epitaxial layer Ep2 where the pMOS is to be formed, before bonding the first wafer W and the second wafer S in St804. Then, in St804 of this modification, the first wafer W and the second wafer S are bonded to obtain the first overlapped wafer T1. Further thereafter, in St806 of this modification, an nMOS is formed in the region of the epitaxial layer Ep1 where the nMOS is to be formed. In St803 to St806 of this modification, the CFET can be formed by a known sequential CFET process. Note that the stacking positions of the nMOS and pMOS may be reversed from those shown in the figure.

[0149] By the method including steps St803 to St806 according to this modified example, the second wafer S or the third wafer U having a CFET can be obtained.

[0150] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims. For example, the components of the above-described embodiments may be arbitrarily combined. Such an arbitrary combination naturally provides the functions and effects of each of the components involved in the combination, and also provides other functions and effects that are apparent to those skilled in the art from the description of this specification.

[0151] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that are apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0152] Mw Separation layer P Sacrificial layer Q Laser absorption layer R Etching stop layer S Second wafer T Overlap wafer W First wafer

Claims

1. A method for manufacturing a semiconductor device, comprising: preparing a first substrate by forming a separation layer on a surface of a first substrate by epitaxial growth; forming an epitaxial film on the separation layer by epitaxial growth; and forming a first device layer on the epitaxial film; preparing a second substrate; bonding the first substrate and the second substrate to form an overlapped substrate; and separating the first substrate from the second substrate by irradiating the separation layer in the first substrate included in the overlapped substrate with laser light, thereby transferring the first device layer to the second substrate; wherein the separation layer includes a laser absorption layer including at least one epitaxial film doped with a dopant; and the first device layer includes circuit elements that constitute at least a part of a memory cell array of a DRAM, or regions where the circuit elements are to be formed, and the circuit elements include transistors.

2. The method for manufacturing a semiconductor device according to claim 1, wherein in forming the separation layer, the dopant is supplied together with the film components of at least one of the epitaxial films included in the laser absorption layer during deposition of the epitaxial film, thereby doping the epitaxial film.

3. The method for manufacturing a semiconductor device according to claim 1, wherein in forming the separation layer, after the formation of at least one of the epitaxial films included in the laser absorption layer, the dopant is doped into the epitaxial film by ion implantation.

4. The first device layer is 4F ２ 2. The method for manufacturing a semiconductor device according to claim 1, wherein the method includes the circuit element constituting at least a part of a memory cell array of a DRAM, or a region where the circuit element is to be formed.

5. The method for manufacturing a semiconductor device according to claim 1, wherein in forming an epitaxial film on the separation layer, the epitaxial film includes a plurality of Si films and SiGe films alternately stacked, and the first device layer includes the circuit element constituting at least a part of a memory cell array of a 3D DRAM, or a region in which the circuit element is to be formed.

6. The method for manufacturing a semiconductor device according to claim 1, further comprising reusing the first substrate after separating the first substrate from the second substrate.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the separation layer includes a sacrificial layer, the sacrificial layer and the laser absorption layer are formed in this order from the surface of the first substrate, and reusing the first substrate includes removing the sacrificial layer by selectively etching the surface of the first substrate and the sacrificial layer.

8. The method for manufacturing a semiconductor device according to claim 1, further comprising, after separating the first substrate from the second substrate, etching the separation surface of the second substrate.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the separation layer includes an etching stop layer, the laser absorption layer and the etching stop layer are formed in this order from the surface of the first substrate, and etching the separation surface of the second substrate includes removing the etching stop layer by selectively etching the surface of the second substrate at the separation surface and the etching stop layer.

10. The method for manufacturing a semiconductor device according to claim 8, further comprising, after etching the separation surface of the second substrate, forming a wiring layer electrically connected to at least one of the circuit elements of the first device layer.

11. The method for manufacturing a semiconductor device according to claim 8, further comprising, after etching the separation surface of the second substrate, forming a capacitor connected to the transistor of the first device layer.

12. The method for manufacturing a semiconductor device according to claim 1, wherein the laser absorption layer includes: a first layer configured to primarily absorb the laser light with higher efficiency and convert it into heat; and a second layer configured primarily to produce greater thermal expansion.

13. The method for manufacturing a semiconductor device according to claim 1, wherein the laser absorption layer includes a cleavage layer that cleaves due to stress caused by thermal expansion of other layers included in the laser absorption layer and serves as a starting point for separation when the first substrate is separated from the second substrate.

14. The method for manufacturing a semiconductor device according to claim 1, wherein the second substrate includes a peripheral circuit for controlling the memory cell array.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the peripheral circuitry includes a CMOS.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the peripheral circuit includes a CFET.

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