Wafer backside defect reduction through layered pedestal undercoat

Abstract

Certain embodiments pertain to methods of in-situ deposition of a layered pedestal undercoat having one or more bilayers of material layers with different stiffness / toughness and semiconductor fabrication chambers with a pedestal having a layered undercoat with one or more bilayers.

Description

Attorney Docket No. LAM1P042WO-11884-1WOWAFER BACKSIDE DEFECT REDUCTIONTHROUGH LAYERED PEDESTAL UNDERCOATRELATED APPLICATION(S)

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.BACKGROUND

[0002] Semiconductor manufacturing typically involves one or more processes to deposit and pattern a structure on a wafer. As the semiconductor industry advances, the complexity and nonuniformity of structures and / or materials on wafers increases. Stress induced or applied to these wafers can results in wafer deformation such as bowing, twisting, etc. Wafer deformation can impact various aspects from structure formation to product yield. For example, in three- dimensional NOT-AND logic gate (3D-NAND) structure fabrication, multi-stacked films with thick, high stress carbon-based hard masks, metallization patterns, and substrate trenches can cause significant wafer warpage, leading to issues such as frontside lithographic overlay mismatches, wafer bow requiring high chucking loads (e.g., by an electrostatic chuck), etc.

[0003] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0004] Certain embodiments pertain to methods of in-situ deposition of a layered undercoat on an upper surface of a pedestal of each process station in a single or multi-station reaction chamber. The methods include (a) depositing a first material layer of a bilayer of the layered undercoat on the upper surface of the pedestal of each process station and (b) depositing a second material layer of the bilayer of the layered undercoat on the upper surface of the pedestal of each process station. The second material layer has a higher elastic modulus than the first materialAttorney Docket No. LAM1P042WO-11884-1WO layer. These methods repeat (a) and (b) until the layered undercoat reaches at least a minimum thickness of bilayers and / or at least a minimum number of bilayers. In one embodiment, the minimum thickness of the one or more bilayers is between 100 nm and 2000nm. In one embodiment, the minimum number of the one or more bilayers is at least two bilayers between 100 nm and 2000nm.

[0005] Certain embodiments pertain to methods of in-situ deposition of a layered undercoat on an upper surface of a pedestal of each process station in a single or multi-station reaction chamber. The methods include (a) depositing a silicon oxide layer of a bilayer of the layered undercoat on the upper surface of the pedestal of each process station and (b) depositing a silicon nitride layer or a silicon carbon layer of the bilayer of the layered undercoat on the upper surface of the pedestal of each process station. These methods repeat (a) and (b) until the layered undercoat reaches at least a minimum thickness of bilayers and / or reaches at least a minimum number of bilayers.

[0006] Certain embodiments pertain to semiconductor fabrication chambers including one or more process stations and a pedestal in each of the one or more processing stations. The pedestal includes a first upper surface and a layered undercoat disposed on the first upper surface. The layered undercoat is configured to support a semiconductor substrate during one or more electronic device fabrication operations. The layered undercoat includes a plurality of bilayers. Each of the bilayers includes a first material layer and a second material layer. The second material layer has a higher elastic modulus than the first material layer. The semiconductor fabrication chambers also include a chuck within, or connected to, the body of the pedestal. The chuck is configured to apply a clamping force to hold the semiconductor substrate in place during the one or more electronic device fabrication operations, semiconductor fabrication chambers also include a showerhead above the pedestal electrically connected to an electrical ground and a radio frequency (RF) power supply electrically connected to the showerhead of each process station.

[0007] These and other aspects are described in further detail below with reference to the drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1A is a schematic drawing of a cross-sectional view of a portion of a pedestal having a single-layer silicon oxide undercoat.

[0009] FIG. IB is a schematic drawing of a cross-sectional view of a portion of a pedestal having a single-layer silicon oxide undercoat.Attorney Docket No. LAM1P042WO-11884-1WO

[0010] FIG. 1C is a schematic drawing of a cross-sectional view of a portion of a pedestal having a single-layer silicon oxide undercoat.

[0011] FIG. 2 depicts two schematic drawings of a cross-sectional view of a portion of a wafer and a portion of a pedestal having a single-layer silicon oxide undercoat.

[0012] FIG. 3A depicts a schematic drawing of a cross-sectional view of a portion of a pedestal having a single-layer silicon oxide undercoat.

[0013] FIG. 3B depicts another schematic drawing of the cross-sectional view of the portion of the pedestal shown in FIG. 3A after a chucking force has caused a crack to form in the single- layer silicon oxide undercoat.

[0014] FIG. 4 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal having a layered undercoat formed on an upper surface of an MCA portion of the pedestal, according to an embodiment.

[0015] FIG. 5 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal having a layered undercoat with two bilayers and an adhesion material layer formed on an upper surface of an MCA portion of the pedestal, according to an embodiment.

[0016] FIG. 6 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal having a layered undercoat with a single bilayer, according to an embodiment.

[0017] FIG. 7 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal having a layered undercoat with two bilayers, according to an embodiment.

[0018] FIG. 8 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal having a layered undercoat with three bilayers, according to an embodiment.

[0019] FIG. 9 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal having a layered undercoat with N bilayers sequentially stacked one on top of another on an upper surface of an MCA portion of a pedestal, according to an embodiment.

[0020] FIG. 10 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal having a layered undercoat formed on an upper surface of a pedestal, according to various embodiments.

[0021] FIG. 11 is a schematic drawing of a cross-sectional view of a portion of a pedestal having a layered undercoat formed on an MCA portion of a pedestal, according to an embodiment.Attorney Docket No. LAM1P042WO-11884-1WO

[0022] FIG. 12 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal having a layered undercoat formed on an MCA portion of a pedestal, according to an embodiment.

[0023] FIG. 13 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal having a layered undercoat including an idle coat (ICT) layer, a silane-based oxide layer, precoat layers including three bilayers, and a ministack film formed on an MCA portion of the pedestal, according to an embodiment.

[0024] FIG. 14A depicts a bar chart of experimental data showing the number of backside defects detected in wafers processed on pedestals having various undercoats, according to embodiments.

[0025] FIG. 14B depicts a plot of experimental data of total number of backside defects in wafers processed on pedestals with various estimated total thicknesses, according to embodiments.

[0026] FIG. 15 depicts a graph of estimated layer thicknesses and trace deposition times (seconds) of a layered undercoat including an idle coat (ICT) layer, a silane-based oxide layer, two precoat layers including a silicon-based oxide layer and a silicon-based nitride layer, and a ministack film, according to an embodiment.

[0027] FIG. 16 depicts a graph of an example estimated layer thicknesses and trace deposition times (seconds) of a layered undercoat, according to an embodiment.

[0028] FIG. 17 depicts a graph of estimated layer thicknesses (pm) and trace deposition times (seconds) of a layered undercoat with only oxide precoat layers, according to an embodiment.

[0029] FIG. 18 depicts a graph of estimated layer thicknesses (pm) and trace deposition times (seconds) of a layered undercoat with only nitride precoat layers, according to an embodiment.

[0030] FIG. 19A depicts a bar chart of the estimated backside cracking probability (%) of wafers processed while secured to pedestals with four different undercoats formed thereon where the pedestals are polished with either a 3% CIP procedure or with a 25% CIP procedure, according to embodiments.

[0031] FIG. 19B depicts a bar chart of the total number of detected defects on the backside surface (backside defects) of the wafers processed on pedestals with four different layered undercoats and that have either been polished with a 3% CIP procedure or a 25% CIP procedure, according to embodiments.Attorney Docket No. LAM1P042WO-11884-1WO

[0032] FIG. 19C depicts a bar chart of the estimated total cracks in wafers processed on pedestals with four different layered undercoats and that have either been polished with a 3% CIP procedure or a 25% CIP procedure, according to embodiments.

[0033] FIG. 20 is a flowchart depicting a method of in-situ deposition of a layered undercoat on an upper surface of a pedestal of each process station in a reaction chamber, according to various embodiments.

[0034] FIG. 21 depicts a schematic drawing of an embodiment of a multi-station processing tool for depositing films on semiconductor substrates using any number of processes, according to embodiments.

[0035] FIG. 22 depicts a block diagram illustrating a side view of a process chamber, according to various embodiments.

[0036] The figures and components therein may not be drawn to scale.DETAILED DESCRIPTION

[0037] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.I. Some Terminology

[0038] As used herein, a “layered undercoat” refers to a stack of material layers formed on one or more internal surfaces of a reaction chamber after a chamber clean procedure. In various embodiments, a layered undercoat is formed in situ on at least an upper surface of a pedestal of each processing station of a single station or multi-station reaction chamber (e.g., process chamber 2200 in FIG. 22). The layered undercoat may include one or more bilayers, each bilayer having two material layers with different stiffness / toughness. In one embodiment, each bilayer includes a silicon nitride layer (e.g., SiNx layer) or a silicon carbon layer (e.g., silicon carbide (SiC) layer) and a silicon oxide layer (e.g., silane-based silicon dioxide layer or a TEOS- based silicon dioxide layer). In some examples, a layered undercoat also includes an idle coatAttorney Docket No. LAM1P042WO-11884-1WO(ICT) layer and / or an initial oxide layer between the internal surfaces and the bilayers and / or a ministack film.

[0039] As used herein, an “ICT layer” refers to a layer of a layered undercoat formed first on the one or more internal chamber surfaces. The ICT layer serves to protect the surfaces during idle mode before device deposition so that the reaction chamber will not be idling with unprotected internal surfaces. The ICT layer may be a silane-based oxide layer such as a SiH4 base layer, and a Atox based layer. The ICT layer may have a thickness in the range of 0.5pm to 1 pm.

[0040] As used herein, an “initial oxide layer” or “UCT” layer refers to a layer of a layered undercoat typically formed between the ICT layer and the one or more bilayers. The initial oxide layer can function to paste down layers deposited on the interior chamber surfaces to prevent material from flaking off and potentially causing defects in wafers being processed. The initial oxide layer has density and adhesion properties to provide suitable adherence of layers formed on the pedestal. Also, the initial oxide layer is a dielectric material that provides a barrier on the aluminum surfaces of the reaction chamber to prevent outgassing. In some embodiments, the initial oxide layer is a silane based oxide layer with a thickness in the range of 0.5pm to 1 pm.

[0041] As used herein, a “ministack film” refers to a stack of materials layers that is typically formed last in the layered undercoat. The ministack film prepares the reaction chamber to have a similar environment to that of the device being deposited on the wafer. Typically, the ministack film has a stack that matches the stack of layers being deposited on the wafer, but generally with substantially thinner layers. The ministack film generally includes P pairs of layers, each pair having an oxide layer (e.g., silicon-based oxide layer or silane-based oxide layer) and a nitride layer (e.g., silicon-based nitride layer or silane-based nitride layer). P can be any suitable number of pairs (e.g., 3, 4, 5, etc.). In one example, a ministack film includes 5 pairs of thin oxide layers and nitride layers. In another example, a ministack fdm includes 3 pairs of oxide layers and nitride layers. In one aspect, the thickness of each layer in a ministack film may be in the range of 20-30 nm thick. The ministack film may be deposited in a similar process as used to deposit bilayers of a layered undercoat. The ministack film is employed to prepare the chamber environment for when a wafer is introduced.

[0042] As used herein, an “electrostatic chuck” (ESC) refers to a chuck that uses electrostatic force to clamp a substrate to the chuck during processing. The ESC may use one or more electrodes. Voltages may be applied to the one or more electrodes. The applied voltage may cause current to flow, thereby causing charge to migrate through a dielectric layer between theAttorney Docket No. LAM1P042WO-11884-1WO chuck and the substrate being processed. Opposite charges accumulated at an electrode relative to the substrate therefore causing the substrate to be gripped or clamped to the chuck by the electrostatic force. In some cases, the one or more electrodes may be integrated into the ESC, or may be separate from the ESC.

[0043] In certain embodiments, an ESC may refer to the one or more electrodes that generate the electrostatic force. In some embodiments, the ESC may employ a plasma in the circuit. In some embodiments, an ESC may be of a monopolar design that employs one or more electrodes to concurrently apply the same potential to the substrate. In other embodiments, the ESC may be of a multipolar design (e.g., bipolar, tripolar, etc.) to apply different potentials to the substrate. For example, an ESC may be a bipolar design that employs two electrodes to concurrently apply opposing potentials to the substrate.

[0044] A “platen” as used herein refers to a top surface of a pedestal / ESC on which a substrate undergoing fabrication is positioned. There may be a gap between the substrate and the platen surface (e.g., the upper surface), which is generally referred to herein as “<i.”

[0045] A “pedestal” as used herein may refer to a structure or housing that supports, or includes, the platen.

[0046] The terms “wafer” and “substrate” may be used interchangeably. Those of ordinary skill in the art understand that these terms can refer to a substrate during any of many stages of electronic device fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, or 300 mm, or 450 mm. Besides semiconductor devices, other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components such as backplanes for pixelated display devices, flat-panel displays, micro-electromechanical devices (e.g., actuators and sensors), image sensors (e.g., complementary metal-oxide-semiconductor (CMOS) sensor), and the like. The work piece may be of various shapes, sizes, and materials.

[0047] ‘ ‘Wafer bow” as used herein may refer to a deformation of a wafer. The deformation may have radial and / or azimuthal components. Examples of types of wafer bow include dome shapes, bowl shapes, and saddle shapes. Wafer bow may occur during fabrication, for example, as a result of stress to the wafer during deposition of materials on an active surface of a wafer. Wafer bow may occur during various types of fabrication, such as when large stacks of materials are deposited.Attorney Docket No. LAM1P042WO-11884-1WO

[0048] An “electronic device fabrication operation’' as used herein is an operation performed during fabrication of electronic devices (e.g., semiconductor devices). As referred to herein, such an electronic device fabrication operation is sometimes simply referred to as a “process” or as “processing.” Examples of processing include deposition of a material on a substrate, selectively etching material from a substrate, and ashing of photoresist on a substrate. Typically, the overall fabrication process includes multiple electronic device fabrication operations, each performed in its own fabrication tool such as a plasma reactor, an electroplating cell, a chemical mechanical planarization tool, a wet etch tool, and the like. Categories of electronic device fabrication operations include subtractive processes, such as etch processes and planarization processes, and material additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etch processes, a substrate etch process includes processes that etch a mask layer or, more generally, processes that etch any layer of material previously deposited on and / or otherwise residing on a substrate surface. Such an etch process may etch a stack of layers in the substrate.

[0049] As used herein, “manufacturing equipment” refers generally to equipment in which a manufacturing process takes place. Manufacturing equipment often includes a process chamber in which the workpiece resides during processing. Typically, when in use, manufacturing equipment performs one or more semiconductor device fabrication operations. Examples of manufacturing equipment for semiconductor device fabrication include deposition reactors such as electroplating cells, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and subtractive process reactors such as dry etch reactors (e.g., chemical and / or physical etch reactors), wet etch reactors, and ashers.

[0050] In certain examples herein, manufacturing equipment may be referred to as a “process chamber.” In some examples, the process chamber may be a sealed enclosure in which a substrate is immobilized during processing. The process chamber may include components associated with delivery of and removal of gases. It may also include components associated with generating a plasma and controlling properties of the plasma within the chamber. It may include components for controlling the pressure, including pulling a vacuum within the chamber. In the context of this disclosure, the process chamber may include a pedestal on which the substrate sits while it is being processed. A pedestal may be outfitted with a chuck such as an ESC to hold the wafer in position during processing.Attorney Docket No. LAM1P042WO-11884-1WOII. Introduction

[0051] Semiconductor device fabrication often involves deposition of a stack of layers or films on a wafer. The wafer may be supported by a pedestal during deposition and various other processing operations. A chuck such as an electrostatic chuck (ESC) or a vacuum chuck may be employed to apply a clamping force to the wafer to secure it to a pedestal in a reaction chamber used to process semiconductor wafers. Typically, most deposition and other processing occurs on one side of the wafer, often referred to as the front face or frontside of the wafer. As the deposited layers or films are built up on one side of the wafer, bending stresses may be induced through the thickness causing the wafer to bow. For example, the frontside layers may be in tension having an internal tensile strain and the backside layers may be in compression having an internal compression strain inducing bending stresses that may cause bowing. Bowing is especially likely to occur where thick stacks of different types of materials or films are deposited, for example, in certain 3D-NAND structures.

[0052] Where bowing is significant, processing operations may be affected. For instance, wafers with 3D-NAND structures or other thick stacks of different types of material films might have significant bowing that require a higher clamping force than might be needed for a wafer having less complexity and / or a thinner structure. If the clamping force applied to the backside of the wafer is not sufficient and the wafer fails to chuck correctly, the wafer may be subjected to nonuniform heating or other inadequate process conditions. Moreover, some processing steps (e.g., photolithography) are precise and produce poor results if the wafer is not substantially flat during processing. The problem may be manifest as lithography defocus.

[0053] Generally, the amount of clamping force employed is designed to secure the backside of the wafer against the substrate-facing surface of the pedestal during various processing operations. When processing wafers with a significant bow, additional clamping force may be required to keep the wafer substantially flat to secure it against the substrate-facing surface. This additional clamping force can cause an increased force to the backside of the wafer which could lead to an increased potential for backside damage to the wafer. Backside damage can result in integration issues (e.g., frontside lithographic overlay mismatches) and in some cases, breakage of the wafer reducing product yield.

[0054] Certain embodiments herein pertain to techniques that advantageously control backside damage to wafers. Controlling backside damage can enable the implementation of increased clamping forces allowing for the processing of wafers with complex and non-uniform structures and materials such as, e.g., 3D-NAND structures. One technique for controlling backsideAttorney Docket No. LAM1P042WO-11884-1WO damage is to form a layered undercoat of material layers with different stiffness / toughness on a substrate support pedestal in a reaction chamber. In various embodiments, the layered undercoat includes one or more bilayers, each bilayer including two material layers (e.g., oxide layer and nitride layer) with differing stiffness / toughness such that each bilayer provides multiple mechanisms for arresting and / or deflecting cracks in the undercoat to seek to prevent the cracks from reaching the substrate-facing surface of the pedestal. Examples of these crack arresting / deflecting mechanisms are discussed in detail below with respect to FIG. 5.

[0055] Other backside damage techniques could be used. For example, a sacrificial film could be deposited on the backside of the wafer. However, forming this backside sacrificial film would involve a special tool and an additional integration step. That is, a special tool would be needed to deposit backside film on the wafer prior to production film deposition. After the deposition step, the backside film will need to be removed either with wet etching or CMP process.

[0056] As used herein, an “undercoat” refers to a layer of material formed on the upper surface of the bare pedestal and / or other interface surfaces of the reaction chamber. Undercoats may be employed to minimize any particle contamination that could arise from having bare chamber surfaces. Often, these particles are metallic particles originating from internal surfaces in the reaction chamber. For example, the particles may originate from internal chamber walls, ceiling, showerhead, substrate support, lift pins, gas lines, nozzles, etc. In a particular example, the reaction chamber and / or components therein are made of aluminum, for example aluminum 6061-T6 (which may include aluminum and small amounts of other materials such as chromium, copper, iron, magnesium, manganese, silicon, titanium, zinc, etc.). In many cases, the particles are generated as the reaction chamber is exposed to plasma or other harsh processing conditions. The particles may fall onto the surface of a substrate during processing, thereby causing undesirable film impurities and increasing the likelihood of device failure.

[0057] Typically, an undercoat is deposited in situ while there is no substrate present in the reaction chamber. The undercoat forms on internal chamber surfaces that are exposed to (a) the reactants that form the undercoat, and (b) the energy to drive the reaction between the reactants. In some cases, one or more internal chamber surfaces may be masked to prevent deposition of the undercoat thereon. Undercoats are further described in U.S. Patent Application No. 14 / 089,653, filed November 25, 2013 (now U.S. Patent 9,745,658), and titled “CHAMBER UNDERCOAT PREPARATION METHOD FOR LOW TEMPERATURE ALD FILMS,” which is hereby incorporated by reference in its entirety.Attorney Docket No. LAM1P042WO-11884-1WO

[0058] In previous designs, undercoats mainly consisted of silicon oxide (e.g., silane-based or aTetraethyl orthosilicate-based (TEOS-based) silicon dioxide) formed on the internal reaction chamber surfaces. For example, an undercoat may have been a single-layer of silicon oxide material. A silicon oxide was generally used for its density and adhesion properties that provide suitable adherence of the undercoat to the pedestal. Also, the silicon oxide is a dielectric material that provides a barrier on the aluminum surfaces of the reaction chamber to prevent outgassing. Also, a silicon oxide material has similar hardness to the silicon of the wafers at room temperature and has two times (2x) lower modulus, which will act as a buffer between the wafer and pedestal material. The homogeneous undercoat is also easier to deposit prior to process.

[0059] FIG. 1A is a schematic drawing of a cross-sectional view of a portion of a pedestal 112 having a single-layer silicon oxide undercoat 152 with a substrate-facing surface 115. The pedestal 112 includes a minimum-contact area (MCA) portion 114 having a plurality of asperities 113.

[0060] As used herein, an “asperity” generally refers to a high spot such as a bump at the surface of a material layer. The number of asperities and the morphology of the asperities may be associated with the surface roughness of the material layer. One or more asperities of an undercoat may make contact with a backside surface of a wafer clamped to the substrate-facing surface of the pedestal. As used herein, a “minimum-contact area” portion or “MCA” portion refers to a portion of a bare pedestal (e.g., pedestal without the undercoat after a chamber clean process) at an upper surface of the pedestal that faces the backside of the wafer during wafer processing. The MCA portion may have one or more asperities in the upper surface. The number of asperities may be directly related to the surface roughness of the pedestal.

[0061] In FIG. 1A, the single-layer silicon oxide undercoat 152 is a conformal undercoat with generally uniform thickness that conforms to the upper surface of the MCA portion 114. In this example, the roughness in the material layer of the MCA portion 114 is showing through the conformal undercoat 152 such that the asperities 113 in the MCA portion 114 match (in location and shape) asperities 153 in the single-layer silicon oxide undercoat 152.

[0062] FIG. IB is a schematic drawing of a cross-sectional view of a portion of a pedestal 122 having a single-layer silicon oxide undercoat 154 and a substrate-facing surface 116. The pedestal 122 includes an MCA portion 114 having a plurality of asperities 113. The single-layer silicon oxide undercoat 154 is a conformal undercoat that conforms to the upper surface of the MCA portion 114. In this example, the thickness is not uniform and the roughness of the singlelayer silicon oxide undercoat 154 is reduced as compared to the roughness of the MCA portionAttorney Docket No. LAM1P042WO-11884-1WO114. The asperities 113 in the MCA portion 114 still match asperities 155 in the single-layer silicon oxide undercoat 154. However, the conformal single-layer silicon oxide undercoat 154 in FIG. IB provides a substrate-facing surface 116 that is smoother than the conformal single-layer silicon oxide undercoat 152 of FIG. 1A. The asperities 155 of the single-layer silicon oxide undercoat undercoat 154 are less pronounced (smoother) than the asperities 113 of the MCA portion 114.

[0063] FIG. 1C is a schematic drawing of a cross-sectional view of a portion of a pedestal 132 having a single-layer silicon oxide undercoat 156 and a substrate-facing surface 117. The pedestal 132 includes an MCA portion 114 having a plurality of asperities 113. The single-layer silicon oxide undercoat 156 is a fill undercoat providing a smooth substrate- facing surface 117 without asperities. The single-layer silicon oxide undercoat 156 may be polished in some cases. The fill single-layer silicon oxide undercoat 156 substantially reduces the roughness of the MCA portion 114.

[0064] Without being bound to theory or to a particular mechanism of backside cracking, it is believed that more asperities in the MCA of a pedestal lead to more cracking on the backside of a silicon wafer and / or that having a fill undercoat consisting mainly of silicon oxide with a polished upper surface may not be effective in reducing backside cracking. For example, silicon oxide undercoats having larger grain size (e.g., 5pm) have been shown to have better backside cracking performance than silicon oxide undercoats having smaller grain size (e.g., 2pm).

[0065] Silicon oxide is a relatively soft material with hardness typically in a range between 650- 1380 ksi, which is similar in hardness to silicon. Silicon oxide undercoats may be easily cracked. For example, pressure applied by an electrostatic chuck to secure a wafer onto a substrate-facing surface of a pedestal may cause pressure at asperities in the undercoat. The pressure at these asperities may cause cracking in the undercoat, e.g., between the asperities in the undercoat and the asperities in the MCA. For example, a crack may be initiated in the undercoat at the interface with the asperities in the MCA and the crack may propagate through the undercoat to corresponding asperities at the substrate-facing surface of the undercoat. Without being bound to theory, it is believed that cracking of the undercoat may create additional local asperities (e.g., additional particles created, delamination of layers, and other roughness changes) and these local asperities in the undercoat may indent the wafer and / or cause cracking in the wafer.

[0066] FIG. 2 depicts two (top and bottom) schematic drawings of a cross-sectional view of a portion of a wafer 230 and a portion of a pedestal 212 having a single-layer silicon oxide undercoat 252. The top drawing depicts an instant in time when an electrostatic chuckingAttorney Docket No. LAM1P042WO-11884-1WO pressure (OESC) is applied to the wafer 230 denoted by an arrow. The bottom drawing depicts an instant in time after the electrostatic chucking pressure (OESC) is released. FIG. 2 also includes an enlarged portion of the bottom drawing. The pedestal 212 includes a substrate-facing surface 215 that faces a backside surface 231 of the wafer 230. The pedestal 212 includes an MCA 214 having a plurality of asperities 213. The single-layer silicon oxide undercoat 252 is a conformal undercoat with non-uniform thickness. The asperities 213 in the MCA 214 are showing through the single-layer silicon oxide undercoat 252. The asperities 213 in the MCA 214 match the asperities 255 in the single-layer silicon oxide undercoat 252.

[0067] The top drawing in FIG. 2 illustrates an instant when an electrostatic chucking pressure (OESC) is applied to the wafer 230. Subsequently, the backside surface 231 of the wafer 230 may contact at least the asperities 255 of the single-layer silicon oxide undercoat 252. At least a portion of electrostatic pressure applied to the wafer 230 is transferred to the asperities 255 of the single-layer silicon oxide undercoat 252 causing the single-layer silicon oxide undercoat 252 to crack at the locations of the asperities 213 in the MCA 214. The bottom drawing in FIG. 2 illustrates an instant after cracks 257 in the single-layer silicon oxide undercoat 252 have been created. In some cases, the cracking in the single-layer silicon oxide undercoat 252 may cause the creation of local asperities 253 in the single-layer silicon oxide undercoat 252. For example, the cracking may cause material from the single-layer silicon oxide undercoat 252 to be displaced. As another example, the single-layer silicon oxide undercoat 252 may delaminate from the MCA 214 causing a local deformation at the substrate-facing surface 215. These local asperities 253 can cause a change in the roughness of the substrate-facing surface 215. In some instances, one or more of these local asperities 253 may indent the backside surface 231 of the wafer 230 and cause cracking in the wafer 230.

[0068] FIG. 3A depicts a schematic drawing of a cross-sectional view of a portion of a pedestal 312 having a single-layer silicon oxide undercoat 352. FIG. 3A illustrates an instant when a downward chucking force (e.g., applied by an electrostatic chuck, a vacuum chuck, etc.) applied to the wafer 230 is transferred to a substrate-facing surface 315 of the pedestal 312. The pedestal 312 is shown having an MCA asperity 313 in the MCA portion of the pedestal 312. It would be understood the MCA of the pedestal 312 also includes material at least to the left and right of the MCA asperity 313, which is not illustrated for simplicity. FIG. 3B depicts another schematic drawing of the cross-sectional view of the portion of the pedestal 312 shown in FIG. 3A after the chucking force has caused a crack 357 to form in the single-layer silicon oxide undercoat 352 at the location of the MCA asperity 313.Attorney Docket No. LAM1P042WO-11884-1WO

[0069] Certain embodiments herein pertain to techniques for forming a layered undercoat on a pedestal that has mechanisms for preventing cracks from propagating to the substrate- facing surface to avoid creating local asperities in the outward substrate-facing surface of the undercoat. The layered undercoat includes one or more bilayers, each bilayer having two material layers having different stiffness properties. For instance, each bilayer may include a first layer of a first material and a second layer of a second material having a higher elastic modulus than the first material. An example of a bilayer is a layer of silicon oxide and a layer of silicon nitride where silicon nitride typically has three times the stiffness than silicon oxide. Implementing these techniques can advantageously control backside damage to wafers, which may enable the implementation of higher clamping forces required for processing of complex and non-uniform structures and materials such as, e.g., 3D-NAND structures.

[0070] FIG. 4 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal 412 having a layered undercoat 452 formed on an upper surface of an MCA portion 414 of the pedestal 412, according to an embodiment. The MCA portion 414 has a plurality of asperities 413. The layered undercoat 452 has an adhesion material layer 461, a first bilayer 462 and a second bilayer 465. The adhesion material layer 461 may be a silicon oxide layer that has properties optimized for adhesion to the MCA portion 414. For example, an adhesion material layer 461 may be a silane-based oxide layer. The adhesion material layer 461 is depicted as a fill layer providing a smooth upper surface. In other cases, the adhesion material layer 461 may be a conformal layer that has asperities matching the asperities of the MCA portion 414. The first bilayer 462 includes a first material layer 463 and a second material layer 464. The first material layer 463 is made of a material that is more stiff / tough than the stiffness / toughness of the second material layer 464. For example, the first material layer 463 may be a silicon nitride layer (e.g., SiNx layer) or a silicon carbon layer (e.g., silicon carbide (SiC) layer) and the second material layer 464 may be a silicon oxide layer (e.g., silane-based silicon dioxide and / or a TEOS-based silicon dioxide layer). The second bilayer 465 includes a first material layer 466 and a second material layer 467. The first material layer 466 is made of a material that is more stiff / tough than the second material layer 467. For example, the second material layer 467 may be a silicon oxide layer and the first material layer 466 may be a silicon nitride or silicon carbon layer. In another implementation, the order of the material layers in one or more of the bilayers may be reversed such that the first material layer 463 is disposed on the second material layer 464 and / or the first material layer 466 is disposed on the second material layer 467.

[0071] Without beyond bound by theory, it is believed that a higher stiffness layer in each bilayer may arrest or slow down the propagation of a crack at the interface between the twoAttorney Docket No. LAM1P042WO-11884-1WO layers and another layer by either stopping the crack at the interface or deflecting the crack into the interface such that it does not reach the substrate-facing surface. At each interface of a bilayer, the crack may be arrested and / or deflected before reaching the substrate-facing surface. Thus, an undercoat with multiple bilayers has at least two crack arresting / deflecting mechanisms at each bilayer that can prevent propagation of a crack to the substrate-facing surface.

[0072] FIG. 5 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal 512 having a layered undercoat 552 with two bilayers 562, 562 and an adhesion material layer 561 (e.g., a silane-based oxide) formed on an upper surface of an MCA portion 514 of the pedestal 512, according to an embodiment. The layered undercoat 552 includes a first interface 568 between the first bilayer 562 and the adhesion material layer 561 and a second interface 569 between the second bilayer 565 and the first bilayer 562. The adhesion material layer 561 is depicted as a fill layer providing a smooth upper surface. In another implementation, the adhesion material layer 561 may be a conformal layer.

[0073] In FIG. 5, the first bilayer 562 includes a first material layer 563 and a second material layer 564. The first material layer 563 includes material that is more stiff / tough than the material of the second material layer 564. For example, the first material layer 563 may comprise silicon nitride (e.g., SiNx) or silicon carbon (e.g., silicon carbide (SiC)) and the second material layer 564 may comprise silicon oxide (e.g., silane-based silicon dioxide and / or a TEOS-based silicon dioxide). The second bilayer 565 includes a first material layer 566 and a second material layer 567. The first material layer 566 includes material that is more stiff / tough than the second material layer 567. For example, the second material layer 567 may comprise silicon oxide and the first material layer 566 may comprise silicon nitride or silicon carbon. In another implementation, the order of the material layers in one or more of the bilayers may be reversed such that the first material layer 563 is disposed on the second material layer 564 and / or the first material layer 566 is disposed on the second material layer 567.

[0074] FIG. 5 illustrates that the layered undercoat 552 with two bilayers 562, 565 has at least four mechanisms for arresting or deflecting a crack initiated at an MCA asperity 513 in the MCA portion 514 to prevent propagation to a substrate-facing surface 515 of the pedestal 512. According to one mechanism, the higher stiffness first material layer 563 of the first bilayer 562 may arrest the crack 557 at the first interface 568 with the adhesion material layer 561 so that the crack 557 does not reach the substrate-facing surface 515. According to another mechanism, the higher stiffness first material layer 563 of the first bilayer 562 may deflect the crack 557 at the first interface 568 to travel along the first interface 568 so that the crack 557 does not reach the substrate-facing surface 515. If the crack 557 does propagate past the first interface 568, theAttorney Docket No. LAM1P042WO-11884-1WO higher stiffness first material layer 566 of the second bilayer 565 may arrest the crack 557 at the second interface 569 and / or deflect the crack 557 to travel along the second interface 569, according to two additional mechanisms. One or more of these mechanisms may be employed to prevent the crack from propagating to the substrate-facing surface 515 of the pedestal 512.

[0075] Without being bound by theory, if a crack forms in the soft (less stiff) layer (e.g., an oxide layer) of a bilayer above an MCA asperity and the crack approaches the interface with the stiffer material (e.g., nitride layer) in the bilayer, it is more difficult for the crack to propagate through the stiffer material in the bilayer. The crack either stops at the interface or deflects along the interface, which is the weaker link / path. For control of backside defects, it may be preferable that the crack deflects along the interface rather than grow toward the upper surface. If the crack does continue to grow through the stiffer material in the bilayer, it generally grows at an angle to the interface, which decreases the stress at the crack tip slowing down crack propagation. With each bilayer interface, the crack may be stopped or deflected. With enough bilayers (e.g., 2, 3, or more bilayers), the crack is likely to be stopped / deflected at an interface.III. Layered Undercoats- Layered undercoat with one or more bilayers

[0076] In various embodiments, a layered undercoat with one or more bilayers may be formed on the upper surface of a bare pedestal to any number of bilayers and total thickness. In one example, a layered undercoat may include at least two bilayers. In another example, a layered undercoat may include three or more bilayers. Generally speaking, each bilayer has a first material layer and a second material layer where the first material layer has a different stiffness / toughness than the first material layer. One example of a bilayer includes a layer of silicon oxide (e.g., silane-based silicon dioxide and / or a TEOS-based silicon dioxide) and a layer of silicon nitride (e.g., SiNx) or silicon carbon (e.g., silicon carbide (SiC)). In some implementations, the thickness of a layer of silicon oxide in a bilayer may be in a range of 100 nm to 2000 nm. In some implementations, the thickness of a layer of silicon nitride in a bilayer may be in a range of 100 nm to 2000 nm. In some implementations, the thickness of a layer of silicon carbon in a bilayer may be in a range of 100 nm to 2000 nm. In some implementation, the total thickness of the layered undercoat is between 100 nm and 2000 nm. In an implementation with a layered undercoat including one or more bilayers of silicon oxide and a silicon nitride / carbide, the total thickness of the undercoat is between 0.5pm and about 10pm. In another implementation with a layered undercoat including two or more bilayers of silicon oxide and a silicon nitride / carbide, the total thickness of the undercoat is about 2.5pm. In anotherAttorney Docket No. LAM1P042WO-11884-1WO implementation with a layered undercoat including two or more bilayers of silicon oxide and a silicon nitride / carbide, the total thickness of the undercoat is less than 6.2pm.

[0077] FIG. 6 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal 612 having a layered undercoat 652 with a single bilayer 662, according to an embodiment. The bilayer 662 is disposed on an upper surface of an MCA 614 and has first material layer 663 and a second material layer 664. The first material layer 663 includes material that may be more stiff / tough than the material of the second material layer 664. In another implementation, the layered undercoat 652 may have one or more additional layers such as one or more material layers disposed between the bilayer 662 and the MCA 614 such as one or more SiH4 based oxide layers or one or more material layers disposed between the bilayer 662 and a substrate-facing surface 615 of the pedestal 612.

[0078] FIG. 7 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal 712 having a layered undercoat 752 with two bilayers 762, 765, according to an embodiment. The first bilayer 762 is disposed on an upper surface of an MCA 714 of the pedestal 612 and has first material layer 763 and a second material layer 764. The second bilayer 765 is disposed on the first bilayer 762 and has first material layer 766 and a second material layer 767. The first material layer 763 of the first bilayer 762 includes material that may be more stiff / tough than the material of the second material layer 764 and the first material layer 766 of the second bilayer 765 includes material that may be more stiff / tough than the material of the second material layer 767. In another implementation, the layered undercoat 752 may have one or more additional layers such as one or more material layers disposed between the first bilayer 762 and the MCA 714 or one or more material layers disposed between the second bilayer 765 and a substratefacing surface 715 of the pedestal 712.

[0079] Having multiple bilayers in a layered undercoat can act as a stress buffer relieving stress as a crack propagates through each bilayer. Each additional bilayer increases the number of crack arresting / defecting mechanisms. Any suitable number of bilayers (e.g., 2, 3, 4, etc.) can be employed. In some implementations, the layered undercoat has at least two bilayers. In addition, in some cases, a minimum total thickness of all the bilayers and / or minimum thickness of the stiffer material layers in the bilayers may be needed to maximize the effectiveness of the crack arresting mechanisms.

[0080] FIG. 8 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal 812 having a layered undercoat 852 with three bilayers 862, 865, 868, according to an embodiment. The first bilayer 862 is disposed on an upper surface of an MCA 814 of theAttorney Docket No. LAM1P042WO-11884-1WO pedestal 812 and has first material layer 863 and a second material layer 864. The second bilayer865 is disposed on the first bilayer 862 and has first material layer 866 and a second material layer 867. The third bilayer 868 is disposed on the second bilayer 865 and has first material layer 869 and a second material layer 870. The first material layer 863 of the first bilayer 862 includes material that may be more stiff / tough than the material of the second material layer 864, the first material layer 866 of the second bilayer 865 includes material that may be more stiff / tough than the material of the second material layer 867, and the first material layer 869 of the third bilayer 868 includes material that may be more stiff / tough than the material of the second material layer 879. In another implementation, the layered undercoat 852 may have one or more additional layers such as one or more material layers disposed between the first bilayer 862 and the MCA 814 or one or more material layers disposed between the second bilayer 865 and a substratefacing surface 815 of the pedestal 812.

[0081] FIG. 9 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal 912 having a layered undercoat 952 with bilayers 962(1),. . .,962(N) sequentially stacked one on top of another on an upper surface of an MCA portion 914 of a pedestal 912, according to an embodiment. N can be any suitable number (e.g., 2, 3, 4, 5,. . .30). Each of the bilayers 962(1),. . ,,962(N) includes a respective first material layer 963 and a second material layer 964. The first material layer 963 and second material layer 964 have different stiffness / toughness properties. In another implementation, the layered undercoat 952 may have one or more additional layers such as one or more material layers disposed between the first bilayer 962(1) and the MCA portion 914 or one or more material layers disposed between the nth bilayer 962(N) and a substrate-facing surface 915 of the pedestal 912.

[0082] In some embodiments, a layered undercoat may include one or more layers between the upper surface of the pedestal (e.g., bare upper pedestal surface after a chamber clean) and one or more precoat layers (e.g., bilayers). For example, an idle coat (ICT) layer and / or an initial oxide layer may be formed on the bare pedestal and the one or more precoat layers formed thereon. An example of an initial oxide layer is a silane-based oxide layer such as a SiH4-based oxide layer. In addition or in an alternative embodiment, a ministack film may be formed on the one or more precoat layers.- Layered undercoat with ICT layer, initial oxide layer, one or more precoat layers, and ministack film

[0083] FIG. 10 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal 1012 having a layered undercoat 1052 formed on an upper surface of a pedestal 1012 after, e.g.,Attorney Docket No. LAM1P042WO-11884-1WO a chamber clean process, according to various embodiments. Layered undercoat 1052 includes an idle coat (ICT) layer 1061, an initial oxide layer 1062, M precoat layers 1060M and a ministack film 1069. The ICT layer 1061 may comprise Silane-based silicon oxide material and / or may have a thickness in the range of 0.5 pm to 1 pm.

[0084] The initial oxide layer 1062 (also sometimes referred to as the “UCT” layer) functions to paste down any layers on the interior chamber surfaces to prevent material from flaking off and potentially causing defects on the wafers being processed. The initial oxide layer 1062 also has density and adhesion properties that provide suitable adherence of the layers subsequently formed thereon to the pedestal. Also, the initial oxide layer 1062 is a dielectric material that provides a barrier on the aluminum surfaces of the reaction chamber to prevent outgassing. The initial oxide layer 1062 may be a silane based oxide layer with a thickness in the range of 0.5 pm to 1 pm.

[0085] The ministack film 1069 includes P pairs of layers, each pair having an oxide layer (e.g., silicon-based oxide layer or silane-based oxide layer) and a nitride layer (e.g., silicon-based nitride layer or silane-based nitride layer). P may be any suitable number (e.g., 3, 4, 5, etc.). In some cases, the thickness of each layer in ministack film 1069 may be in the range of 20-30 nm thick. In certain implementations, the precoat layers 1060M layer(s) include one or more bilayers, each bilayer having two material layers having different stiffness / toughness. M may be any suitable number (e.g., 1, 2, 3, 4, 5,... ,30).1) Layered undercoat with thin silicon-based nitride precoat layer

[0086] FIG. 11 is a schematic drawing of a cross-sectional view' of a portion of a pedestal 1112 having a layered undercoat 1152 formed on an MCA portion 1114 of a pedestal 1112, according to an embodiment. The layered undercoat 1152 includes an idle coat (ICT) layer 1161, a silane- based oxide layer 1162, a bilayer 1065 including a silicon-based oxide layer 1163 and a silicon- based nitride layer 1164, and a ministack film 1169. The silicon-based oxide layer 1163 may have a thickness in the range of 1 pm to 2 pm and the thickness of the silicon-based nitride layer 1164 may be in a range of 100 nm to 500 nm.

[0087] The idle coat (ICT) layer 1161, silane-based oxide layer 1162, and ministack film 1169 are similar or analogous to elements shown in FIG. 10. For the sake of brevity, the prior discussion of such similar or analogous elements with regard to FIG. 10 may be assumed to be equally applicable, unless indicated otherwise in the following discussion, to the similar or analogous counterparts of those elements in FIG. 11 that share the same last two digits in their respective callouts as in FIG. 10.Attorney Docket No. LAM1P042WO-11884-1WO

[0088] One implementation of the layered undercoat 1152 shown in FIG. 11 is the layered undercoat 1552 in FIG. 15. This implementation is referred to in FIG. 14A and FIGS. 19A-C as “Undercoat (A).” FIG. 15 depicts a graph of estimated layer thicknesses and trace deposition times (seconds) of a layered undercoat 1552 including an idle coat (ICT) layer 1561, a silane- based oxide layer 1562, two precoat layers 1560 including a silicon-based oxide layer 1563 and a silicon-based nitride layer 1564, and a ministack film 1569, according to an embodiment. In this implementation, layered undercoat 1552 has an estimated thickness of 2.63 um. The ministack film 1569 has five pairs of layers, each pair having a silicon-based oxide and a silicon-based nitride. The ministack film 1569 has an estimated thickness of 0.24 pm. Silicon-based nitride layer 1264 has an estimated thickness of about 0.38 pm and the silicon-based oxide layer 1263 has an estimated thickness of about 0.11 pm. Idle coat (ICT) layer 1561 has an estimated thickness of 0.32 pm and silane-based oxide layer 1562 has an estimated thickness of 1.57 pm. In one example, the layered undercoat 1552 shown in FIG. 15 is formed on a pedestal polished with a 3% ceramic infused polish (CIP) procedure, which is referred to as “Undercoat (A) with 3% CIP5”in FIG. 14A. In another example, the layered undercoat 1552 shown in FIG. 15 is formed on a pedestal polished with a 25% CIP procedure, which is referred to as “Undercoat (A) with 25% CIP5”in FIG. 14A.

[0089] In another implementation, the layered undercoat 1552 in FIG. 15 has a UCT 1562 with a thickness of 4.71 pm (3 x 1.57 pm), which is three times the estimated thickness of the UCT shown in the graph depicted in FIG. 15. This implementation is referred to in FIG. 14A as “3XUCT.”

[0090] In some implementations, the layered undercoat 1552 in FIG. 15 or layered undercoat 1152 in FIG. 11 may have another layer on top of the ministack film. For example, the layered undercoat may have an atomic oxide (AtOx) layer deposited on top of the ministack film. The AtOx layer may be a silane-based silicon oxide layer. In one implementation, the layered undercoat 1552 in FIG. 15 has a AtOx layer deposited on ministack film 1569. This implementation is referred to in FIG. 14A as “AtOx_Cap.”

[0091] Another implementation of the layered undercoat 1152 shown in FIG. 11 has a silicon- based nitride layer with a thickness in the range of 1.5pm to 2.5 pm. This implementation is referred to in FIG. 14A as “10XBSLNSLN_PCT.”

[0092] Another implementation of the layered undercoat 1152 shown in FIG. 11 has a silicon- based nitride layer with a thickness in the range of 3pm to 5 pm. This implementation is referred to in FIG. 14A as “20XBSLNSLN_PCT.”Attorney Docket No. LAM1P042WO-11884-1WO2) Layered undercoat with thick silicon based nitride precoat layer

[0093] FIG. 12 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal 1212 having a layered undercoat 1252 formed on an MCA portion 1214 of a pedestal 1212, according to an embodiment. Layered undercoat 1252 includes an idle coat (ICT) layer 1261, a silane-based oxide layer 1262, two precoat layers 1260 including a silicon-based oxide layer 1263 and a silicon-based nitride layer 1264, and a ministack film 1269. Silicon-based nitride layer 1264 has a larger thickness than the thickness of the silicon-based oxide layer 1263. The thickness of the silicon-based oxide layer 1263 may be in a range of 0.5pm to 1 pm and the thickness of the silicon-based nitride layer 1264 may be in a range of 1.5pm to 2.5 pm.

[0094] The idle coat (ICT) layer 1261, silane-based oxide layer 1262, silicon-based oxide layer 1263, silicon-based nitride layer 1264, and ministack film 1269 are similar or analogous to elements shown in FIGS. 10 and 11. For the sake of brevity, the prior discussion of such similar or analogous elements with regard to FIG. 10 and 11 may be assumed to be equally applicable, unless indicated otherwise in the following discussion, to the similar or analogous counterparts of those elements in FIG. 12 that share the same last two digits in their respective callouts as in FIG. 10 and 11.3) Layered undercoat with three bilayers

[0095] FIG. 13 depicts a schematic drawing of a cross-sectional view of a portion of a pedestal 1312 having a layered undercoat 1352 including an idle coat (ICT) layer 1361, a silane-based oxide layer 1362, precoat layers 1360 including three bilayers 13651, 13652, and 1365s, and a ministack film 1369 formed on an MCA portion 1314 of the pedestal 1312, according to an embodiment. The idle coat (ICT) layer 1361 and silane-based oxide layer 1362 are similar or analogous to elements shown in FIGS. 10 and 11. For the sake of brevity, the prior discussion of such similar or analogous elements with regard to FIG. 10 and 11 may be assumed to be equally applicable, unless indicated otherwise, to the similar or analogous counterparts of those elements in FIG. 13 that share the same last two digits in their respective callouts as in FIG. 10 and 11.

[0096] Bilayer 13651 includes a silicon-based oxide layer 13631 and a silicon-based nitride layer 13641. Bilayer 13652 includes a silicon-based oxide layer 13632 and a silicon-based nitride layer 13642. Bilayer 1365a includes a silicon-based oxide layer 1363a and a silicon-based nitride layer 1364a. The thickness of each of the silicon-based oxide layers 13631, 13632, and 1363a may be in a range of 100 nm to 2000 nm. The thickness of each of the silicon-based nitride layers 13641, 13642, and 1364a may be in a range of 100 nm to 2000 nm.

[0097] One implementation of the layered undercoat 1352 shown in FIG. 13 is the layeredAttorney Docket No. LAM1P042WO-11884-1WO undercoat 1652 in FIG. 16. This implementation is referred to in FIG. 14A and FIGS. 19A-C as“Undercoat (B).” FIG. 16 depicts a graph of an example estimated layer thicknesses and trace deposition times (seconds) of the layered undercoat 1652, according to an embodiment. Layered undercoat 1652 (sometimes referred to as “Undercoat (B)”) includes an idle coat (ICT) layer 1661, a silane-based oxide layer 1662, precoat layers 1660 including three bilayers 16651, 16652, 1665s, and a ministack film 1669. Ministack film 1669 has five pairs of layers, each pair having a silicon-based oxide layer and a silicon-based nitride layer. Ministack film 1669 has an estimated thickness of 0.24 pm.

[0098] Bilayer 16651 includes a silicon-based oxide layer 16631 and a silicon-based nitride layer 16641. Bilayer 16652 includes a silicon-based oxide layer 16632 and a silicon-based nitride layer 16642. Bilayer 1665s includes a silicon-based oxide layer 1663s and a silicon-based nitride layer 1664s. The thickness of each of the silicon-based oxide layers 16631, 16632, and 1663s may be in a range of 100 nm to 2000 nm. The thickness of each of the silicon-based nitride layers 16641, 16642, and 1664s may be in a range of 100 nm to 2000 nm.4) Layered undercoat with only oxide precoat layers (O-PCT Only Undercoat)

[0099] FIG. 17 depicts a graph of estimated layer thicknesses ( m) and trace deposition times (seconds) of a layered undercoat 1752 with only oxide precoat layers, according to an embodiment. The layered undercoat 1752 of this implementation is referred to as “Undercoat (C)” or “O-PCT Only” in FIGS. 19A-19C. The layered undercoat 1752 includes an idle coat (ICT) layer 1761, a silane-based oxide layer 1762, a silicon-based oxide precoat layer 1760, and a ministack film 1769. In this example, the silicon-based oxide layer 1763 is formed during six (6) deposition cycles with a total estimated thickness of 4.08 pm. In other implementations, silicon-based oxide layer 1763 may have other suitable thicknesses. For example, the silicon- based oxide layer 1763 may have a thickness in the range of 100 nm to 2000 nm. Ministack film 1669 has five pairs of layers, each pair having a silicon-based oxide layer and a silicon-based nitride layer. Ministack film 1669 has an estimated thickness of 0.24 pm.

[0100] The idle coat (ICT) layer 1761 and silane-based oxide layer 1762 may be similar or analogous to elements shown in FIG. 10. For the sake of brevity, the prior discussion of such similar or analogous elements with regard to FIG. 10 may be assumed to be equally applicable, unless indicated otherwise in the following discussion, to the similar or analogous counterparts of those elements in FIG. 17 that share the same last two digits in their respective callouts as in FIG. 10.Attorney Docket No. LAM1P042WO-11884-1WO5) Layered undercoat with only nitride precoat layers (N-PCT Only Undercoat)

[0101] The layered undercoat 1652 includes an idle coat (ICT) layer 1661, a silane-based oxide layer 1662, a silicon-based nitride layer 1663, and a ministack film 1669. In this example, the silicon-based nitride layer 1663 is formed during six (6) depositions with an estimated thickness of 0.402 m. In other implementations, silicon-based nitride layer 1663 may have other suitable thickness. For example, the silicon-based nitride layer 1663 may have a thickness in the range of 100 nm to 2000 nm.

[0102] FIG. 18 depicts a graph of estimated layer thicknesses ( m) and trace deposition times (seconds) of a layered undercoat 1852 with only nitride precoat layers, according to an embodiment. The layered undercoat 1852 of this implementation is referred to as “Undercoat (D)” or “N-PCT Only” in FIGS. 19A-19C. The layered undercoat 1852 includes an idle coat (ICT) layer 1961, a silane-based oxide layer 1862, a silicon-based nitride layer 1863, and a ministack film 1669. In this example, the silicon-based nitride layer 1663 is formed during six (6) depositions with an estimated thickness of 0.402 pm. In other implementations, silicon-based nitride layer 1663 may have other suitable thicknesses. For example, the silicon-based nitride layer 1663 may have a thickness in the range of 100 nm to 2000 nm. Ministack film 1669 has five pairs of layers, each pair having a silicon-based oxide layer and a silicon -based nitride layer. Ministack film 1669 has an estimated thickness of 0.24 pm.

[0103] The idle coat (ICT) layer 1761 and silane-based oxide layer 1762 may be similar or analogous to elements shown in FIG. 10. For the sake of brevity, the prior discussion of such similar or analogous elements with regard to FIG. 10 may be assumed to be equally applicable, unless indicated otherwise in the following discussion, to the similar or analogous counterparts of those elements in FIG. 17 that share the same last two digits in their respective callouts as in FIG. 10.Experimental Data of Backside Defect Reduction with layered undercoats

[0104] FIG. 14A depicts a bar chart of experimental data showing the number of backside defects detected in wafers processed on pedestals having various undercoats where the wafers were secured during processing by either a clamping force from an electrostatic chuck applying 300 volts or a clamping force from an electrostatic chuck applying 900 volts, according to embodiments. The undercoats tested include (i) undercoat 1552 in FIG. 15 where a 3% CIP procedure was used to polish the pedestal before depositing the undercoat 1052, (ii) undercoat 1552 where a 25% ceramic infused polish procedure was applied to the pedestal, (iii), undercoat 1552 with a UCT having a thickness of 4.71 pm (3 x 1.57 m), (iv) undercoat 1552 with aAttorney Docket No. LAM1P042WO-11884-1WO silicon-based nitride layer having a thickness in the range of 1.5(im to 2.5 pm (v) undercoat (B) with three bilayers 16651, 16652, and 1665a as shown in FIG. 16, (vi) undercoat 1552 with an additional AtOx layer deposited on ministack film 1569, and (vii), undercoat 1552 with a silicon- based nitride layer having a thickness in the range of 3pm to 5pm. As shown, undercoat (B) with three bilayers had the lowest number of defects for the clamping force from a 300 V electrostatic chuck.

[0105] FIG. 14B depicts a plot of experimental data of the total number of backside defects in wafers processed on pedestals for implementations of undercoat 1152 in FIG. 11 with various estimated total thicknesses, according to embodiments. The different thicknesses are based on varying the thickness of the silicon-based nitride layer 1164. A 25% ceramic infused polish procedure was applied to the pedestals before applying the undercoats 1152. The experimental data in the plot shows that increasing the thickness of the silicon-based nitride layer 1164 results in substantially lower backside defects where a clamping force from a 900 v electrostatic chuck was applied during processing up to the greatest thickness (above 7pm) tested. The experimental data also shows that increasing the thickness of the silicon-based nitride layer 1164 results in substantially lower backside defects where a clamping force from a 300 v electrostatic chuck was applied during processing up to the greatest thickness (above 7 m) tested. At the greatest thickness, the number of defects increases for both clamping force instances. These results show that increasing the thickness of the stiffer material layer may not alone decrease the number of defects in some cases. Thickness and number of bilayers may also be factors in decreasing backside defects.

[0106] FIGS. 19A-19B include experimental data derived from processing wafers on pedestals with different layered undercoats, according to embodiments. The four layered undercoats tested include: 1) undercoat 1552 or “Undercoat (A)’’ depicted in FIG. 15, 2) undercoat 1652 or “Undercoat (B)” with three bilayers depicted in FIG. 16, 3) undercoat 1852 with nitride only precoat (N-PCT only) layer 1860 or “Undercoat (C)” depicted in FIG. 18, and 4) undercoat 1752 with oxide only precoat (O-PCT only) layer 1760 or “Undercoat (D)” depicted in FIG. 17. The four layered undercoats were formed on pedestals polished with either a 3% CIP procedure or a 25% CIP procedure. During testing of each layered undercoat, a deposition process is performed to deposit a 122 pair stack on the frontside of the wafer while the wafer is secured to the pedestal with a 900v electrostatic chucking force. The wafer is then flipped and the backside of the wafer is scanned. The scans are used to determine defects / indentations in the backside of the wafer and to differentiate between different defects / indentations to classify as cracks or as scratches. Based on this evaluation, the number of cracks is counted. An estimated probability of backsideAttorney Docket No. LAM1P042WO-11884-1WO cracking in the wafers (estimated backside cracking probability) is calculated as the proportion of the number of cracks to the total number of detected defects. An estimated number of cracks is calculated as the estimated cracking probability multiplied by the total number of detected defects.

[0107] FIG. 19A depicts a bar chart of the estimated backside cracking probability (%) of wafers processed while secured to pedestals with four different undercoats formed thereon where the pedestals are polished with either a 3% CIP procedure or with a 25% CIP procedure, according to embodiments. The results show that undercoat (B) with three bilayers resulted in the lowest probability of backside cracking in the wafer for both pedestals polished with 3% CIP procedure and 25% CIP procedure.

[0108] FIG. 19B depicts a bar chart of the total number of detected defects on the backside surface (backside defects) of the wafers processed on pedestals with four different layered undercoats and that have either been polished with a 3% CIP procedure or a 25% CIP procedure, according to embodiments. The experimental data in FIG. 19B shows that for pedestals polished with a 3% CIP process, the layered undercoat (B) with three bilayers resulted in a 60% reduction of backside defects as compared with layered undercoat (A). The experimental data also shows that for pedestals polished with a 25% CIP procedure, the layered undercoat (B) with three bilayers resulted in a 70% reduction of backside defects as compared with layered undercoat (A). Using undercoat (C) with a nitride only precoat layer (N-PCT) 1860 resulted in a 60% reduction of defects as compared with using undercoat (A) on pedestals polished with a 3% CIP procedure and resulted in a 34% reduction of defects as compared with using undercoat (A) on pedestals polished with a 25% CIP procedure. Using undercoat (D) with oxide only precoat layer (O-PCT) 1760 resulted in a 35% reduction of defects as compared with using undercoat (A) on pedestals polished with a 3% CIP procedure and resulted in a 31% reduction of defects as compared with using undercoat (A) on pedestals polished with a 25% CIP procedure. Overall, the undercoat (B) with three bilayers resulted in the lowest number of backside defects on wafers processed by pedestals polished with both 3% CIP procedure and a 25% CIP procedure.

[0109] FIG. 19C depicts a bar chart of the estimated total cracks in wafers processed on pedestals with four different layered undercoats and that have either been polished with a 3% CIP procedure or a 25% CIP procedure, according to embodiments. As shown, pedestals with undercoat (B) having three bilayers resulted in the lowest estimated number of cracks in wafers for both the instances where the pedestals were polished with a 3% CIP procedure and with a 25% CIP procedure.Attorney Docket No. LAM1P042WO-11884-1WO

[0110] These results in FIGS. 19A-19C also show that having multiple bilayers reduces backside cracking more effectively than increasing the thickness of the oxide material layer in the case of O-PCT only undercoat or increasing the thickness of the nitride material layer alone in the case of N-PCT only undercoat.IV. Methods of depositing layered undercoats

[0111] As discussed above, having multiple bilayers in a layered pedestal undercoat can advantageously act as a stress buffer to relieve stress as a crack propagates through each bilayer in a layered undercoat. Each additional bilayer increases the number of crack arresting / defecting mechanisms at the interface. In certain embodiments, the methods for depositing layered undercoats include depositing multiple bilayers to a minimum number of bilayers, minimum total thickness of all bilayers, and / or minimum thickness of the stiffer material layer in the bilayers. Some examples of minimum numbers of bilayers that may be employed are 2, 3, and 4. In some cases, the minimum total thickness of all the bilayers of a layered undercoat may be in the range of 100 nm to 2000 nm. Some examples of minimum total thickness of all bilayers in a layered undercoat are 500 nm to 10000 nm. In some cases, the stiffer material layer (e.g., a nitride layer) in the bilayers may have a minimum thickness in the range of 100 nm to 2000 nm. Some examples of minimum thicknesses of the stiffer material layer are 100 nm.

[0112] FIG. 20 is a flowchart depicting a method of in-situ deposition of a layered undercoat on an upper surface of a pedestal of each process station in a reaction chamber, according to various embodiments. The reaction chamber may be a single station or multi-station reaction chamber (e.g., process chamber 2200 in FIG. 22). The layers of the layered undercoat are deposited in situ while there is no substrate present in the reaction chamber. The undercoat may be formed on internal chamber surfaces that are exposed to (a) the reactants that form the undercoat, and (b) the energy to drive the reaction between the reactants. In some cases, one or more internal chamber surfaces may be masked to prevent deposition of the layered undercoat thereon. The layers of the layered undercoat may be deposited through chemical vapor deposition (CVD) techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or plasma enhanced atomic layer deposition (PEALD), or through direct metal deposition (DMD), etc. These examples are not intended to be limiting.

[0113] At optional (denoted by dashed line) operation 2002, an in-situ chamber clean process is performed to remove built-up residues (e.g., silicon oxide and / or silicon nitride residues) that have been built up on interior surfaces of the reaction chamber. The chamber components can beAttorney Docket No. LAM1P042WO-11884-1WO cleaned using wet or dry chemistry (with or without plasma) to remove the residues. In one example, the chamber clean process includes exposing the single or multi-station reaction chamber to a halogen-based species to remove material from the upper surface of the pedestal of each process station. In one aspect, exposing the single or multi-station reaction chamber to a halogen-based species also removes material from one or more additional interior surfaces of the single or multi-station reaction chamber.

[0114] In one example of an in-situ chamber clean process, the reaction chamber is exposed to plasma generated (directly or remotely) from at least one of F2, NF3, or a different fluorine- containing cleaning reactant. In another example, the reaction chamber (or a relevant coated chamber component) may be exposed to wet chemistry to remove the byproduct material. Example wet chemistries include, but are not limited to, various acids and bases, alcohols, water, deionized water, acetone, etc. Some particular examples include ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), hydrochloric acid (HC1), hydrofluoric acid (HF), nitric acid (HNO3), isopropyl alcohol (C3H8O), etc. The chamber components may be exposed to the wet chemistry or dry chemistry (e.g., plasma) for a duration between about 0.5 seconds and 24 hours, depending on the technique that is used. In some cases, the duration may be between about 0.5 seconds and 2 minutes, or between about 1-30 seconds, or between about 1-15 minutes, or between about 1-60 minutes, or between about 1-24 hours. In some cases, the duration may be at least about 0.5 seconds, at least about 1 second, at least about 10 seconds, at least about 30 seconds, at least about 1 minute, at least about 10 minutes, at least about 30 minutes, or at least about 1 hour. In these or other cases, the duration may be about 24 hours or less, about 1 hour or less, about 30 minutes or less, about 10 minutes or less, about 1 minute or less, about 30 seconds or less, or about 10 seconds or less.

[0115] After a chamber clean process, an ICT layer may be deposited on the chamber surface to protect the internal surfaces of the reaction chamber so that the reaction chamber will not be idling (before device deposition process) without accumulation to protect surface. At idle, chamber is in vulnerable state. ICT layer protects the chamber surface. This step is performed before the chamber is placed in idle mode before deposition of electronic device.

[0116] At optional (denoted by dashed line) operation 2004, one or more silane-based oxide layers (e.g., SiH4 layers) of the layered undercoat are formed on at least the upper surface of the pedestal of each process station in the reaction chamber. For example, a silane-based oxide ICT layer may be deposited on one or more internal chamber surfaces to protect the surfaces during idle. The ICT layer is deposited before the reaction chamber is placed in idle mode before deposition of an electronic device. The ICT layer may have a thickness in the range of 0.5pm toAttorney Docket No. LAM1P042WO-11884-1WO1 pm. An example of process conditions for depositing the ICT layer include (i) SiH4 as a nitride precursor with 900 seem, (ii) NH3 as an oxidizer with 24 slm, (iii) HF at 3000 W and LF at 1000W, (iv) pressure at 4.5 torr and (v) temperature at 560C. As another example, an initial oxide layer of silane-based oxide may be deposited on one or more internal surfaces of the reaction chamber. The initial silane-based oxide layer may have a thickness in the range of 0.5pm to 1 pm. An example of process conditions for depositing the silane-based oxide include (i) SiH4 as a nitride precursor with 900 seem, (ii) NH3 as an oxidizer with 24 slm, (iii) HF at 3000 W and LF at 1000W, (iv) pressure at 4.5 torr and (v) temperature at 560C.

[0117] The layered undercoat also includes at least two bilayers, each bilayer having a first and second material layers with different stiffness / toughness properties. For instance, each bilayer may have a first layer of a first material and a second layer of a second material where the second material has a higher elastic modulus than the first material. An example of a bilayer is a layer of silicon oxide and a layer of silicon nitride or silicon carbide.

[0118] At operation 2006, a first material layer of a bilayer of the layered undercoat is deposited on at least the upper surface of the pedestal of each process station in the reaction chamber. In some cases, the first material layer is also deposited on additional internal surfaces. In one implementation, the first material layer is a silicon nitride layer (e.g., SiNx layer) or a silicon carbon layer (e.g., silicon carbide (SiC) layer). The silicon nitride layer may have a thickness in a range of 100 nm to 2000 nm. The silicon carbon layer may have a thickness in a range of 100 nm to 2000 nm. The first material layer may be deposited using a first set of reaction conditions. In an implementation where the first material layer is a silicon nitride layer, an example of the first set of reaction conditions includes (i) SiH4 as a nitride precursor with 900 seem, (ii) NH3 as an oxidizer with 24 slm, (iii) HF at 3000 W and LF at 1000W, (iv) pressure at 4.5 torr and (v) temperature at 560C. In an implementation where the first material layer is a silicon carbide layer, an example of the first set of reaction conditions includes (i) SiH4 as a carbide precursor with 900 seem, (ii) CO2 as an oxidizer with 24 slm, (iii) HF at 2000 W and LF at 1000W, (iv) pressure at 1 torr and (v) temperature at 450C.

[0119] At operation 2008, a second material layer of the bilayer of the layered undercoat is deposited on at least the upper surface of the pedestal of each process station in the reaction chamber. In some cases, the second material layer is also deposited on additional internal surfaces. The first material layer generally has higher stiffness / toughness properties than the second material layer. In one implementation, the second material layer is a silicon oxide layer such as, e.g., a silane-based silicon dioxide and / or a TEOS-based silicon dioxide. The second material layer may be deposited using a second set of reaction conditions. In an implementationAttorney Docket No. LAM1P042WO-11884-1WO where the second material layer is a s TEOS-based silicon dioxide layer, an example of the second set of reaction conditions includes: (i) TEOS as an oxide precursor with 10 ml / min, (ii) oxygen at 14 slm, (iii) HF=300W and LF=2200W at 560C, and (i) pressure at 2 torr. In an implementation where the second material layer is a silane-based silicon dioxide layer, operation 2008 includes (i) flowing a silicon-containing reactant in vapor phase into the single or multistation reaction chamber under a second set of reaction conditions allowing the silicon- containing reactant to adsorb onto the upper surface of the pedestal and (ii) after (i), flowing an oxygen-containing reactant in vapor phase into the single or multi-station reaction chamber, and exposing the upper surface of the pedestal to plasma to drive a surface reaction between the silicon-containing reactant and the oxygen-containing reactant to form the silicon oxide layer. In other implementations, the order of depositing the first material layer and the second material layer may be reversed.

[0120] Operations 2006 and 2008 are repeated until the number of bilayers are equal to, or more than, a minimum number of bilayers, the total thickness of the deposited bilayers is equal to, or more than, a minimum thickness, and / or the total thickness of first material layers is equal to, or more than, a minimum thickness. Some examples of minimum numbers of bilayers are 2, 3, and 4. In one aspect, the minimum number of bilayers is at least 2 bilayers. The minimum number of bilayers may be in the range of 2-5. Some examples of minimum thickness of the bilayers are 500 nm, lOOOnm and 1500 nm. The minimum thickness of the bilayers may be in the range of 100 nm and 2000 nm. Some examples of minimum thickness of the first material layers are 500 nm, 1000 nm, and 1500 nm. The minimum thickness of the first material layers may be in the range of 100 nm to 2000 nm.

[0121] At operation 2010, it is determined whether the bilayers deposited in one or more cycles of operations 2006 and 2008 are of a number equal to, or greater than, the minimum number of bilayers, have a thickness equal to, or greater than, the minimum thickness of the bilayers, and / or the thickness of the first material layers is equal to, or greater than, the minimum thickness of the first material layers in the bilayers (collectively referred to as “the minimum criteria”). The thickness of the bilayers may be determined based on estimated thicknesses of the first material layer and second material layer multiplied by the number of cycles of depositions performed in operations 2008 and 2008. If it is determined the minimum criteria is met, the method proceeds to operation 2012. If it is determined that the minimum criteria is not met, the method returns to operation 2006 to deposit another first material layer.

[0122] The determination in operation 2010 and / or other operations of the method may be performed by executing instructions in system control software. In some embodiments, systemAttorney Docket No. LAM1P042WO-11884-1WO control software may include input / output control (IOC) sequencing instructions for controlling various parameters of the operations of the method. Other computer software and / or programs stored on memory (e.g., mass storage device 2194 and / or memory device 2196 associated with system controller 2190) may be employed. Examples of programs or sections of programs for this purpose include a bilayer control program, a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0123] At operation 2012, a ministack film is deposited on at least the upper surface of the pedestal. In some cases, the ministack film is also deposited on additional internal surfaces. The ministack film may have a stack of material layers that matches, or substantially matches, the stack of material layers of the electronic device deposited onto the substrate in operation 2018, but with substantially thinner layers. For example, the thickness of each layer in a ministack film may be in the range of 20-30 nm thick. The ministack film generally includes P pairs of layers, each pair having an oxide layer (e.g., silicon-based oxide layer or silane-based oxide layer) and a nitride layer (e.g., silicon-based nitride layer or silane-based nitride layer). P can be any suitable number of pairs (e.g., 3, 4, 5, etc.). In one example, a ministack film includes 5 pairs of thin oxide layers and nitride layers. In another example, a ministack film includes 3 pairs of oxide layers and nitride layers. The ministack film may be deposited in a similar process as used to deposit the first material layer and second material layers of the bilayer discussed above.

[0124] At optional (denoted by dashed line) operation 2014, any excess reactant is purged from the reaction chamber. Such purging may be accomplished by evacuating the reaction chamber and / or sweeping the first reaction chamber with another gas (e.g., an inert gas in many cases). Purging the reactant from the reaction chamber minimizes the risk of an unwanted gas phase reaction between the reactant and another reactant. Such purging may not be necessary (and may therefore be omitted) in certain cases where the reaction is driven by plasma.

[0125] After the deposition operations, the reaction chamber is allowed to cool and / or is actively cooled. At operation 2016, the substrate is received onto the pedestal in a cool reaction chamber. For example, the reaction chamber at a temperature in a range of 50C to 100C may be considered a cool reaction chamber. The substrate may be transferred to the pedestals using a wafer handing system such as, e.g., the wafer handling system 2150 in FIG. 21.

[0126] At optional (denoted by dashed line) operation 2018, operations are performed to fabricate an electronic device on the substrate on the pedestal of each process station. These operations include deposition operations to form one or more stacks of material layers on theAttorney Docket No. LAM1P042WO-11884-1WO frontside of the substrate. The materials in the stacks may be deposited through chemical vapor deposition (CVD) techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or plasma enhanced atomic layer deposition (PEALD), or through direct metal deposition (DMD), etc. These examples are not intended to be limiting.

[0127] The frontside stacks may be deposited on substrates to any number of layers and thicknesses. In an example, the stack may include about 20 or more layers, and have a total thickness of about 2 pm to about 4 pm. In some cases, multiple-layer stacks may include about one hundred or more layers. In some embodiments, multiple-layer stacks may have about five hundred or more layers. In some embodiments, the multiple-layer stacks may have about one thousand or more layers. Such stacks may have a thickness of about 4 pm to 12 pm, for example.- In situ process on a batch basis

[0128] The wafers that are processed in a particular reaction chamber in between subsequent chamber cleaning operations are referred to as a batch. The wafers in a batch are processed serially over time. In other words, the batch processing described herein is different from batch processing where all substrates in the batch are processed simultaneously. In the batch processing used herein, at least some of the substrates within the batch are processed at different times. However, it is understood that certain reaction chambers such as the multi-station processing tool 2100 described in Section V are configured to process multiple substrates simultaneously, and that in such cases, certain substrates within a batch can be processed simultaneously. In one example, a layered undercoat is formed on one or more internal surfaces of a freshly cleaned reaction chamber and the reaction chamber is used to deposit film on one wafer at a time, and the reaction chamber is cleaned after the batch of wafers (e.g., 200 wafers) is processed. In one case, the batch includes 200 wafers. In this case, the batch includes the 200 wafers that were processed between subsequent chamber cleans. In another example, a layered undercoat is formed on one or more internal surfaces of a freshly cleaned reaction chamber and the reaction chamber is used to deposit film on two wafers at a time. In one case, the batch of wafers includes 200 wafers and the reaction chamber is cleaned after 400 wafers are processed. In this case, the batch includes the 400 wafers that were processed between subsequent chamber cleans.Attorney Docket No. LAM1P042WO-11884-1WO

[0129] In some cases, a batch of wafers includes at least about 25 wafers, at least about 50 wafers, at least about 100 wafers, or at least about 200 wafers. In these or other cases, a batch of wafers may include up to about 400 wafers, or up to about 200 wafers. In various embodiments, the batch may include between about 200-400 wafers, though many batch sizes may be used. An ideal batch size may depend on a number of factors including, but not limited to, the composition of film being deposited (or otherwise processed), the thickness of film being deposited (or otherwise processed), etc.

[0130] In certain implementation, a layered undercoat is formed on one or more internal surfaces of a reaction chamber in an in situ process on a batch basis between chamber clean operations. For example, in one implementation of the method shown in FIG. 20, operations 2014, 2016, and 2018 are performed multiple times to process a batch of wafers. Once the batch is complete, the method returns to operation 1602 to perform a chamber clean procedure.V. Single and multi-station processing tools

[0131] Semiconductor processing may include the deposition of one or more layers of film onto a substrate, such as chemical vapor deposition (“CVD”), plasma-enhanced CVD (“PECVD”), atomic layer deposition (“ALD”), low pressure CVD, ultra-high CVD, physical vapor deposition (“PVD”), and conformal film deposition (“CFD”). For instance, some CVD processes may deposit a film on a wafer surface by flowing one or more gas reactants into a reactor which form film precursors and by-products. The precursors are transported to the wafer surface where they are adsorbed by the wafer, diffused into the wafer, and deposited on the wafer by chemical reactions which also generate by-products that are removed from the surface and from the reactor. As another example, some deposition processes involve multiple film deposition cycles, each producing a “discrete” film thickness. ALD is one such film deposition method, but any technique which puts down thin layers of film and which is used in a repeating sequential matter may be viewed as involving multiple cycles of deposition. As device and features size continue to shrink in the semiconductor industry, and also as 3D devices structures (e.g., 3D-NAND structures) become more prevalent in integrated circuit (IC) design, the capability of depositing thin conformal films (films of material having a uniform thickness relative to the shape of the underlying structure, even if non-planar) continues to gain importance.

[0132] The methods of depositing layered undercoats and the semiconductor fabrication chambers described herein may be implemented in a multi-station or a single station tool. For example, in certain cases, the 300 mm Novellus Vector™ tool having a 4-station deposition scheme may be employed. The various implementations may also be practiced on tools designedAttorney Docket No. LAM1P042WO-11884-1WO to process 450 mm substrates or other sizes of substrates. It is possible to index the wafers after each deposition and / or post-deposition plasma treatment until all the depositions and treatments are completed, or multiple depositions and treatments may be conducted at a single station before indexing the wafer. It has been shown that film stress is the same in either case. However, conducting multiple depositions / treatments on one station may be substantially faster than indexing following each deposition and / or treatment.

[0133] One or more process stations may be included in a processing tool. FIG. 21 shows a schematic view of an embodiment of a multi-station processing tool 2100 for depositing films on semiconductor substrates using any number of processes. The multi-station processing tool 2100 includes an inbound load lock 2102 and an outbound load lock 2104, either or both of which may include a remote plasma source. A robot 2106 at atmospheric pressure is configured to move wafers from a cassette loaded through a pod 2108 into inbound load lock 2102 via an atmospheric port 2110. A wafer is placed by the robot 2106 on a pedestal 2111 in the inbound load lock 2102, the atmospheric port 2110 is closed, and the load lock is pumped down. Where the inbound load lock 2102 includes a remote plasma source, the wafer may be exposed to a remote plasma treatment in the load lock prior to being introduced into a processing chamber 2114. Further, the wafer also may be heated in the inbound load lock 2102 as well, for example, to remove moisture and adsorbed gases. Next, a chamber transport port to processing chamber 2114 is opened, and another robot (not shown) places the wafer into the reactor on a pedestal of a first station shown in the reactor for processing. While the embodiment depicted in FIG. 21 includes load locks, it will be appreciated that, in some embodiments, direct entry of a wafer into a process station may be provided.

[0134] The depicted processing chamber 2114 includes four process stations, numbered from 1 to 4 in the embodiment shown in FIG. 21. Each station has a heated pedestal (shown at 2112 for station 1), and gas line inlets. It will be appreciated that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between an ALD and plasma-enhanced ALD process mode. Additionally or alternatively, in some embodiments, processing chamber 2114 may include one or more matched pairs of ALD and plasma-enhanced ALD process stations. While the depicted processing chamber 2114 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments a processing chamber may have three or fewer stations.Attorney Docket No. LAM1P042WO-11884-1WO

[0135] It should be understood that the various references to RF power settings of the present disclosure are generally intended, unless otherwise indicated, to refer to the RF power setting per wafer. In embodiments involving multiple process stations in a multi-station processing tool, one or more RF power sources may be provided that serve multiple process stations (e.g., simultaneously and / or sequentially). In embodiments in which a single RF power source serves multiple process stations, the per-wafer power setting of the RF power source may be multiplied by the number of process stations being simultaneously provided with plasma at a desired power level. In other words, when the present disclosure describes an RF power setting of 300 watts, it should be understood that the RF power setting reflects a per-wafer value of 300 watts and that, in multi-station processing tools, the actual RF power setting of the RF power source may be the per-wafer power setting multiplied by the number of stations.

[0136] Moreover, it should be understood that the various references to RF power settings of the present disclosure are generally intended, unless otherwise indicated, to refer to the RF power setting used with a 300-mm wafer. The RF power settings described herein may be adjusted when depositing material on substrates or wafers having dimensions other than that of a 300-mm wafer.

[0137] FIG. 21 depicts an embodiment of a wafer handling system 2150 for transferring wafers within processing chamber 2114. In some embodiments, wafer handling system 2150 may transfer wafers between various process stations and / or between a process station and a load lock. It will be appreciated that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. FIG. 21 also depicts an embodiment of a system controller 2190 employed to control process conditions and hardware states of multi-station processing tool 2100. System controller 2190 may include one or more memory devices 2196, one or more mass storage devices 2194, and one or more processors 2192. Processor 2192 may include a CPU or computer, analog, and / or digital input / output connections, stepper motor controller boards, etc.

[0138] In some embodiments, system controller 2190 controls all of the activities of multistation processing tool 2100. System controller 2190 executes system control software 2198 stored in mass storage device 2194, loaded into memory device 2196, and executed on processor 2192. Alternatively, the control logic may be hard coded in the system controller2190. Applications Specific Integrated Circuits, Programmable Logic Devices (e.g., field- programmable gate arrays, or FPGAs) and the like may be used for these purposes. In the following discussion, wherever “software” or “code” is used, functionally comparable hard coded logic may be used in its place. System control software 2198 may include instructions forAttorney Docket No. LAM1P042WO-11884-1WO controlling the timing, mixture of gases, gas flow rates, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor position, and other parameters of a particular process performed by multi-station processing tool 2100. System control software 2198 may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operation of the process tool components used to carry out various process tool processes. System control software 2198 may be coded in any suitable computer readable programming language.

[0139] In some embodiments, system control software 2198 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and / or programs stored on mass storage device 2194 and / or memory device 2196 associated with system controller 2190 may be employed in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0140] A substrate positioning program may include program code for process tool components that are used to load the substrate onto pedestal 2112 and to control the spacing between the substrate and other parts of multi-station processing tool 2100.

[0141] A process gas control program may include code for controlling gas composition (e.g., iodine-containing silicon precursor gases, and nitrogen-containing gases, carrier gases and purge gases as described herein) and flow rates and optionally for flowing gas into one or more process stations prior to deposition in order to stabilize the pressure in the process station. A pressure control program may include code for controlling the pressure in the process station by regulating, for example, a throttle valve in the exhaust system of the process station, a gas flow into the process station, etc.

[0142] A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas (such as helium) to the substrate.

[0143] A plasma control program may include code for setting RF power levels applied to the process electrodes in one or more process stations in accordance with the embodiments herein.

[0144] A pressure control program may include code for maintaining the pressure in the reaction chamber in accordance with the embodiments herein.Attorney Docket No. LAM1P042WO-11884-1WO

[0145] In some embodiments, there may be a user interface associated with system controller 2190. The user interface may include a display screen, graphical software displays of the apparatus and / or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

[0146] In some embodiments, parameters adjusted by system controller 2190 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), etc. These parameters may be provided to the user in the form of a recipe, which may be entered utilizing the user interface.

[0147] Signals for monitoring the process may be provided by analog and / or digital input connections of system controller 2190 from various process tool sensors. The signals for controlling the process may be output on the analog and digital output connections of multistation processing tool 2100. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0148] System controller 2190 may provide program instructions for implementing the abovedescribed deposition processes. The program instructions may control a variety of process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control the parameters to operate in-situ deposition of film stacks according to various embodiments described herein.

[0149] The system controller 2190 will typically include one or more memory devices 2196 and one or more processors configured to execute the instructions so that the apparatus will perform a method in accordance with disclosed embodiments. Machine-readable media containing instructions for controlling process operations in accordance with disclosed embodiments may be coupled to the system controller 2190.

[0150] In some implementations, the system controller 2190 is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems.Attorney Docket No. LAM1P042WO-11884-1WOThe system controller 2190, depending on the processing conditions and / or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0151] Broadly speaking, the system controller 2190 may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the system controller 2190 in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0152] The system controller 2190, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the system controller 2190 may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the system controller 2190 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may beAttorney Docket No. LAM1P042WO-11884-1WO specific to the type of process to be performed and the type of tool that the system controller 2190 is configured to interface with or control. Thus, as described above, the system controller 2190 may be distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0153] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an PEALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0154] As noted above, depending on the process step or steps to be performed by the tool, the system controller 2190 might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.VI. Clamping

[0155] Pedestal designs disclosed herein are configured to receive wafers in plasma-enhanced chemical vapor deposition (PECVD) processing tools and other contexts. These pedestal designs may incorporate one or more clamping elements that allow a wafer to be drawn flat against a clamping region of the pedestal. In some examples, the clamping elements include an electrostatic chuck (ESC). Monopolar and bipolar designs are two examples of an ESC that can be used. In other examples, the clamping elements include a vacuum chuck.- Electrostatic Chuck (ESC)

[0156] FIG. 22 is a block diagram illustrating a side view of a process chamber 2200, according to various embodiments. Process chamber 2200 may be used in conjunction with systems or components used for various plasma processing techniques, such as plasma-enhancedAttorney Docket No. LAM1P042WO-11884-1WO chemical vapor deposition (PECVD), plasma etching, plasma stripping or ashing, sputtering, plasma spraying, and the like. Process chamber 2200 includes a pedestal 2212 configured to support a substrate 2230. Pedestal 2212 includes an electrostatic chuck (ESC) 2218 embedded in the body of the pedestal 2212.

[0157] In some embodiments, an ESC may include a collection of electrodes with one or more clamping electrodes and / or one or more blocking electrodes. For example, in FIG. 22, ESC 2218 has a collection of electrodes including clamping electrodes 2214 and 2215 and a blocking electrode 2216. Blocking electrode 2216 and clamping electrodes 2214, 2215 may be electrically connected to one or more electrical leads 2284. The one or more electrical leads 2284 are configured to electrically connect, either directly or indirectly, to at least one radio frequency (RF) power supply 2282, which may provide direct current (DC) and / or RF power to the electrodes.

[0158] In some implementations, the clamping electrodes (e.g., clamping electrodes 2214, 2215) and / or the blocking electrode (e.g., blocking electrode 2216) of an ESC may be a thin sheet of electrically conductive material, e.g., metal, machined to have shapes as described herein. In some implementations, an electrode may have multiple components. In some implementations, the electrodes may have slots or holes or be made of a mesh that allow the movement of particles therethrough; this may reduce the risk of delamination after sintering, as the ceramic particles may sinter through the electrodes rather than merely around them. In some implementations, the electrodes may be a metallic mesh, e.g., a woven mesh having multiple metal strands that overlap and are electrically connected. Regardless of the particular details of the electrode material, the electrodes may be machined into shapes such as are discussed herein.

[0159] Returning to FIG. 22, ESC 2218 is an example of a monopolar design having two clamping electrodes 2214 and 2215 that apply identical voltages to substrate 2230 to pull (clamp) substrate 2230 against pedestal 2212 during operation. In an alternate example, ESC 2218 may be a bipolar design where clamping electrodes 2214 and 2215 have opposite voltages (e.g., -500 V and +500 V) to pull substrate 2230 against pedestal 2212.

[0160] Returning to FIG. 22, generally, blocking electrode 2216 (also may be known as an “outer electrode,’- “edge electrode,’- or “averaging electrode’-) may improve the uniformity of processing operations performed on the substrate. In some embodiments, blocking electrode 2216 may extend around clamping electrodes 2214, 2215. In some embodiments, blocking electrode 2216 may have an annular shape or an annular portion associated with blockingAttorney Docket No. LAM1P042WO-11884-1WO electrode 2216. In some implementations, the annular portion, when viewed from above, may encircle clamping electrodes 2214, 2215.

[0161] In certain instances, a blocking electrode may average anomalies associated with the positive and negative polarities of the clamping electrodes, smoothing the interaction of the clamping electrodes with the substrate. The blocking electrode may also interact with a plasma above the substrate during substrate processing operations to improve processing uniformity. More specifically, RF power provided to the blocking electrode (e.g., blocking electrode 2216) may control the area where a plasma forms, particularly the radius of the plasma. As plasma processes may have non-uniformities from center-to-edge resulting from the plasma, the RF power delivered to the blocking electrode (e.g., blocking electrode 2216) and the clamping electrodes (e.g., 2214, 2215 clamping electrodes) may be tuned to control the plasma and improve uniformity.

[0162] In some embodiments, a pedestal with an ESC (e.g., ESC 2218) may be configured to support and hold a substrate (e.g., substrate 2230) provided to a substrate processing environment, e.g., process chamber 2200. It should be understood that the process chamber 2200 and pedestal 2212 described with reference to FIG. 22 may be designed for a 300-mm wafer according to one implementation. Suitable modifications may be made to scale various elements for larger or smaller wafers (e.g., the electrodes may be scaled to correspond with the wafer diameter to be processed).

[0163] Returning to FIG. 22, a ring 2224, e.g., an edge ring or exclusion ring, may also be positioned on pedestal 2212. In some implementations, ring 2224 may be a ceramic ring placed so as to protect, e.g., the pedestal / ESC in the process chamber from damage from the plasma and / or may assist in controlling the plasma. In some implementations, ring 2224 may be a replaceable component.

[0164] In FIG. 22, a showerhead 2204 may be positioned above the pedestal 2212. During processing operations, process gases may be flowed through showerhead 2204 toward substrate 2230. In some embodiments, a plasma 2220 may be formed above substrate 2230 during operation. In some embodiments, the showerhead 2204 may include or otherwise be coupled to a plasma generation system (not shown) that may be used to generate plasma 2220. Showerhead 2204 (or a plasma generator system) and ESC 2218 (including the clamping electrodes and blocking electrode) may be electrically coupled to RF power supply 2282 and a matching network 2280 for powering plasma 2220. During operation, RF power supply 2282 and matching network 2280 may be operated at any suitable power that can form plasma 2220 with a desiredAttorney Docket No. LAM1P042WO-11884-1WO composition of species. Plasma 2220 may have a plasma edge region 2222 that is positioned proximate an outer edge of substrate 2230.

[0165] In some embodiments, to control a manner in which an RF power supply operates, a controller may be operatively coupled therewith. In FIG. 22, for example, a controller 2290 is operatively coupled to RF power supply 2282 to control one or more of its operations. The controller (e.g., controller 2290) may be an analog controller, a discrete logic controller, a programmable array controller (PAL), a programmable logic controller (PLC), a microprocessor, a computer, or any other device capable of carrying out operations for effecting processing operations. In some exemplary implementations, the controller may be configured to determine a magnitude of power to be supplied to the showerhead, clamping electrodes, and blocking electrodes, and provide commands to the RF power supply. Returning to FIG. 22, in addition to controlling the RF power supply 2282, controller 2290 may also be operatively coupled to a gas distribution system 2299 and may be configured to provide commands thereto to supply a prescribed amount of processing gas towards substrate 2230.

[0166] In some embodiments, gas distribution system 2299 may also be coupled to one or more gas sources and may include one or more corresponding valves or other flow control components (e.g., mass flow controllers and / or liquid flow controllers). In some embodiments, controller 2290 may be connected to the one or more valves or other flow control components to cause them to switch states and thereby allow different gases or combinations of gases to be flowed at different times and / or flow rates. In some embodiments, the one or more gas sources may be fluidically connected to a mixing vessel to allow for blending and / or conditioning of process gases prior to flow over the wafer.

[0167] In some implementations, RF power supply 2282 may be a radio frequency (RF) energy source or other source of energy capable of supplying power to and energizing electrodes to form an electric field. In some exemplary embodiments, RF power supply 2282 may include an RF generator (not shown) that is configured to operate at a desired frequency. For example, the RF generator may be configured to operate within a frequency range of 0.2 MHz to 20.0 MHz. In some exemplary embodiments, the RF generator may operate at 13.56 MHz. In some exemplary embodiments, RF power supply 2282 may include matching network 2280 disposed between the RF generator and one or more elements described herein, e.g., the plasma generator system or ESC 2218. The matching network 2280 may be an impedance matching network that is configured to match an impedance of the RF generator to an impedance of electrodes connected to the RF generator. In this regard, matching network 2280 may be made up of a combination of components, such as a phase angle detector and a control motor; however, in other embodiments,Attorney Docket No. LAM1P042WO-11884-1WO it will be appreciated that the matching network may include other or additional components as well.

[0168] In some embodiments, pedestals, including pedestal 2212, may be manufactured using a sintering process. The clamping electrodes 2214, 2215 and the blocking electrode 2216, as well as other elements in the pedestal / ESC and electrical connectors, e.g., metal wires, may be positioned in a powder that may be heated and / or compressed to sinter the powders together, forming a pedestal having the components noted above embedded within. The powder may be a ceramic, e.g., alumina or alumina nitride, that forms a single piece during sintering. In some embodiments, the powder may be in an “unfired” state that may be easily machinable. A pedestal / ESC may be built by layering components and powder together and then firing the entire ESC to sinter the ceramic powder. As the sintering process results in expansion and contraction of various elements in the pedestal and thus movement of those elements (and potential defects due to such movement), manufacturing may be simplified by aligning components in fewer planes. Thus, clamping electrodes 2214, 2215 and blocking electrode 2216 may be co-planar to reduce manufacturing costs. Furthermore, connections to the components, e.g., electrical connections to clamping electrodes 2214, 2215 and blocking electrode 2216, may be positioned along a vertical central axis to reduce manufacturing complexity.- Vacuum Chuck

[0169] In some embodiments, a vacuum chuck may be employed to secure the wafer to the pedestal. The vacuum chuck is configured to apply a vacuum force to hold the semiconductor substrate during the one or more electronic device fabrication operations.CONCLUSION

[0170] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

Attorney Docket No. LAM1P042WO-11884-1WOCLAIMSWhat is claimed is:

1. A method of in-situ deposition of a layered undercoat on an upper surface of a pedestal of each process station in a single or multi-station reaction chamber, the method comprising:(a) depositing a first material layer of a bilayer of the layered undercoat on the upper surface of the pedestal of each process station;(b) depositing a second material layer of the bilayer of the layered undercoat on the upper surface of the pedestal of each process station, wherein the second material layer has a higher elastic modulus than the first material layer; and(c) repeating (a) and (b) until the layered undercoat reaches at least a minimum thickness of bilayers and / or at least a minimum number of bilayers.

2. The method of claim 1 , wherein the minimum thickness of bilayers is between 100 nm and 2000 nm.

3. The method of claim 1 , wherein the minimum number of bilayers is at least two bilayers.

4. The method of claim 1 , further comprising depositing one or more silane-based oxide layers on the upper surface of the pedestal of each process station.

5. The method of claim 1 , further comprising (d), after (c), purging the single or multi-station reaction chamber.

6. The method of claim 4, further comprising, after (d), receiving a substrate at the pedestal of each process station.

7. The method of claim 6, further comprising applying an electrostatic clamping force or a vacuum clamping force to the substrate.

8. The method of claim 6, further comprising conducting one or more electronic device fabrication operations on the substrate at the pedestal of each process station.Attorney Docket No. LAM1P042WO-11884-1WO9. The method of claim 1 , wherein (a) and (b) include depositing the first material layer and the second material layer on one or more additional interior surfaces of the single or multi-station reaction chamber.

10. The method of claim 1 , further comprising performing a chamber clean process to remove material from the upper surface of the pedestal of each process station.

11. The method of claim 10, wherein performing the chamber clean process comprises exposing the single or multi-station reaction chamber to a halogen-based species to remove the material from the upper surface of the pedestal of each process station.

12. The method of claim 11, wherein exposing the single or multi-station reaction chamber to the halogen-based species also removes the material from one or more additional interior surfaces of the single or multi-station reaction chamber.

13. A method of in-situ deposition of a layered undercoat on an upper surface of a pedestal of each process station in a single or multi-station reaction chamber, the method comprising:(a) depositing a silicon oxide layer of a bilayer of the layered undercoat on the upper surface of the pedestal of each process station;(b) depositing a silicon nitride layer or a silicon carbon layer of the bilayer of the layered undercoat on the upper surface of the pedestal of each process station; and(c) repeating (a) and (b) until the layered undercoat reaches at least a minimum thickness of bilayers and / or reaches at least a minimum number of bilayers.

14. The method of claim 1 , wherein the minimum thickness of the layered undercoat is between about 100 nm and 2000 nm.

15. The method of claim 13, wherein the minimum number of bilayers is at least two bilayers.Attorney Docket No. LAM1P042WO-11884-1WO16. The method of claim 13, wherein: the silicon oxide layer comprises one or more of a silane-based silicon dioxide material or a TEOS-based silicon dioxide material; the silicon nitride layer comprises a SiNx material; and / or the silicon carbon layer comprises a silicon carbide (SiC) material.

17. The method of claim 13, wherein the silicon oxide layer of the bilayer is deposited using a second set of reaction conditions and the silicon nitride layer or the silicon carbon layer is deposited using a first set of reaction conditions.

18. The method of claim 17, wherein the second set of reaction conditions comprise: (i) TEOS as an oxide precursor with 10 ml / min, (ii) oxygen at 14 slm, (iii) HF=300W and LF=2200W at 560C, and (i) pressure at 2 torr.

19. The method of claim 17, wherein the first set of reaction conditions include (i) SiH4 as a nitride precursor with 900 seem, (ii) NH3 as an oxidizer with 24 slm, (iii) HF at 3000 W and LF at 1000W, (iv) pressure at 4.5 torr and (v) temperature at 560C.

20. The method of claim 13, further comprising performing a chamber clean process to remove material from the upper surface of the pedestal of each process station.

21. The method of claim 20, wherein performing the chamber clean process comprises exposing the single or multi-station reaction chamber to a halogen-based species to remove the material from the upper surface of the pedestal of each process station.

22. The method of claim 21, wherein exposing the single or multi-station reaction chamber to the halogen-based species also removes the material from one or more additional interior surfaces of the single or multi-station reaction chamber.

23. The method of claim 13, wherein (a) and (b) also deposit the silicon oxide layer and the silicon nitride layer or a silicon carbon layer on one or more additional interior surfaces of the single or multi-station reaction chamber.Attorney Docket No. LAM1P042WO-11884-1WO24. The method of claim 13, further comprising depositing one or more silane-based oxide layers on the upper surface of the pedestal of each process station.

25. The method of claim 13, further comprising (d), after (c), purging the single or multi-station reaction chamber.

26. The method of claim 25, further comprising, after (d), receiving a substrate at the pedestal of each process station.

27. The method of claim 26, further comprising applying an electrostatic clamping force or a vacuum clamping force to the substrate.

28. The method of claim 26 or claim 27, further comprising conducting one or more electronic device fabrication operations on the substrate at the pedestal of each process station.

29. The method of claim 13, wherein (b) comprises: flowing a silicon-containing reactant in vapor phase into the single or multi-station reaction chamber under a second set of reaction conditions allowing the silicon-containing reactant to adsorb onto the upper surface of the pedestal; and(ii) after (i), flowing an oxy gen-containing reactant in vapor phase into the single or multistation reaction chamber, and exposing the upper surface of the pedestal to plasma to drive a surface reaction between the silicon-containing reactant and the oxygen-containing reactant to form the silicon oxide layer.

30. A semiconductor fabrication chamber, comprising: one or more process stations; and a pedestal in each of the one or more process stations, each pedestal having a body comprising: a first upper surface; and a layered undercoat disposed on the first upper surface, the layered undercoat configured to support a semiconductor substrate during one or more electronic device fabrication operations, the layered undercoat comprising a plurality of bilayers, each of the bilayers comprising a first material layer and a second material layer, the second material layer having a higher elastic modulus than the first material layer;Attorney Docket No. LAM1P042WO-11884-1WO a chuck within, or connected to, the body of the pedestal, the chuck configured to apply a clamping force to hold the semiconductor substrate in place during the one or more electronic device fabrication operations; a showerhead above the pedestal electrically connected to an electrical ground; and a radio frequency (RF) power supply electrically connected to the showerhead of each process station.

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