Methods and systems for decoding forward error correction codes using parallel error locator polynomial evaluation circuits

Abstract

Methods and systems are described for receiving data bits and redundancy bits of a forward error correction, FEC, codeword, applying a check matrix to the bits of the FEC codeword to generate a set of syndromes, the set of syndromes comprising (i) single-bit parity syndromes generated by respective logical bitwise-XORs of bits in respective sections of the FEC codeword and (ii) first-order and higher-order multi-bit syndromes having values from a finite field, determining two errors occurred in the received bits of the FEC codeword, and further determining the two errors occur in a same section of the received FEC codeword, generating corresponding error positions for each error based on (i) the first-order syndrome associated with the same section of the received FEC codeword and (ii) the higher-order syndrome and correcting each data bit of the FEC codeword having an error in the corresponding error position.

Description

KDU-01008W001METHODS AND SYSTEMS FOR DECODING FORWARD ERROR CORRECTION CODES USING PARALLEL ERROR LOCATOR POLYNOMIAL EVALUATION CIRCUITSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 684,635, filed August 19, 2024, naming Amin Shokrollahi, entitled “Methods and Systems for Decoding Forward Error Correction Codes using Parallel Error Locator Polynomial Evaluation Circuits”, which is hereby incorporated by reference in its entirety for all purposes.REFERENCES

[0002] The following references are herein incorporated by reference in their entirety for all purposes:

[0003] U.S. Patent No. 10,666,297, granted May 26, 2020, naming Amin Shokrollahi, entitled “Pipelined Forward Error Correction for Vector Signaling Code Channel”, hereinafter identified as [Shokrollahi],

[0004] U.S. Provisional Application No. 63 / 550,320, filed February 6, 2024, naming Jay arama Shenoy, entitled “Programmable Memory Fabric”, hereinafter identified as [Shenoy],

[0005] U.S. Provisional Application No. 63 / 648,161, filed May 15, 2024, naming Amin Shokrollahi, entitled “Dual In-Line Memory Module Error Correction Using Interleaved Error Correction Codes”, hereinafter [Shokrollahi],

[0006] U.S. Provisional Application No. 63 / 662,820, filed June 21, 2024, naming Amin Shokrollahi, entitled “Dual In-Line Memory Module Error Correction Using Interleaved Error Correction Codes”, hereinafter [Shokrollahi II],BACKGROUND

[0007] Data centers support business applications through e.g, data storage (management, backup, recovery), productivity applications, e-commerce transactions, online gaming, and machine leaming / artificial intelligence (Al) based applications. Data centers face multiple challenges when striving for improved performance and reduced total cost of ownership (TCO). Specifically, with cloud computing and artificial intelligence (Al) based applications, the demand for additional memory continues to increase. Three main issues act as roadblocks for data centers. The first is a three order of magnitude difference in latency between direct- attached dynamic random access memory (DRAM) and solid-state drives (SSDs). The secondKDU-01008W001 is the number of cores in multi-core processors that are outscaling the main memory channels, leaving processing cores absent memory bandwidth. The third is a growing problem of underutilized or stranded memory resources in accelerated computing with accelerators having their own direct attached memory.

[0008] Double Data Rate (DDR) memory is the predominant memory in personal computers (PCs), as well as server boards. Specifically, low-power DDR (LPDDR) is a type of DRAM that consumes less power and is targeted for mobile computers and devices such as mobile phones. LPDDR typically includes wider interfaces than its DDR4 and DDR5 counterparts, including interfaces of 16-bits and 32-bits, and accessing data in bursts of 16 or 32 transfers. Forward Error Correction (FEC) is a technique to improve data integrity stored in DRAMs both in link ECC applications (end to end ECC) as well as on-die ECC. Robust FEC codes are desired to reduce the probability of silent data corruption (SDC), with minimized increases in power consumption and latency.BRIEF DESCRIPTION

[0009] Methods and systems are described for receiving data bits and redundancy bits of a forward error correction, FEC, codeword, applying a check matrix to the bits of the FEC codeword to generate a set of syndromes, the set of syndromes comprising (i) single-bit parity syndromes generated by respective logical bitwise-XORs of bits in respective sections of the FEC codeword and (ii) first-order and higher-order multi-bit syndromes having values from a finite field, determining two errors occurred in the received bits of the FEC codeword, and further determining the two errors occur in a same section of the received FEC codeword, generating corresponding error positions for each error based on (i) the first-order syndrome associated with the same section of the received FEC codeword and (ii) the higher-order syndrome and correcting each data bit of the FEC codeword having an error in the corresponding error position.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a block diagram of a system employing FEC, in accordance with some embodiments.

[0011] FIG. 2 illustrates a FEC decoder including a plurality of parallel error locator polynomial evaluation circuits used to evaluate the error locator polynomial using every field element in a single clock cycle.KDU-01008W001

[0012] FIG. 3 is a block diagram of error case selection logic configured to select between 3 and four error cases, in accordance with some embodiments.

[0013] FIG. 4 is a block diagram of error case selection logic configured to select between two and three error cases, in accordance with some embodiments.

[0014] FIG. 5 is a block diagram of error case selection logic configured to select between two and one error cases, in accordance with some embodiments.

[0015] FIG. 6 is a block diagram for generating two error values, in accordance with some embodiments.

[0016] FIG. 7 is a block diagram for determining error position in a one-error case, in accordance with some embodiments.

[0017] FIG. 8 is a block diagram illustrating pipelined stages of a FEC decoder, in accordance with some embodiments.

[0018] FIG. 9A is a block diagram of one instance of an error locator polynomial evaluation circuit hard-wired with binary expansions of exponential powers of an integer a,, in accordance with some embodiments.

[0019] FIG. 9B is a block diagram of an instance of an error locator polynomial evaluation circuit hard-wired with exponential powers of a given primitive element oti, in accordance with some embodiments.

[0020] FIG. 10 is a block diagram of an error value solving circuit, in accordance with some embodiments.

[0021] FIG. 11 A illustrates a check matrix for a binary single error correcting code.

[0022] FIG. 11B illustrates a check matrix for a binary dual error correcting code.

[0023] FIG. 12A illustrates a check matrix for a binary triple error correcting code.

[0024] FIG. 12B illustrates a check matrix for a binary quad-error correcting code.

[0025] FIG. 13 is diagram of a check matrix of an extended binary FEC code, in accordance with some embodiments.

[0026] FIG. 14 is a check matrix for a dual error correct triple error detect (DECTED) [279, 256] code having 256 data bits and 23 redundant data bits.

[0027] FIG. 15 is a check matrix for a dual error correct triple error detect (DECTED) [544, 512] code having 512 data bits and 32 redundant data bits.

[0028] FIGs. 16-19 are flowcharts of error case selection logic for the [544,512] code, in accordance with some embodiments.KDU-01008W001

[0029] FIG. 20 is a check matrix for a triple error correct quad error detect (TECQED) [287, 256] code having 256 data bits and 31 redundant data bits.

[0030] FIG. 21 is a check matrix for a quadruple error correct [295, 256] code having 256 data bits and 39 redundant data bits.

[0031] FIG. 22 is a block diagram of an FEC decoder for an extended binary FEC code, in accordance with some embodiments.

[0032] FIG. 23 is a flowchart of a method, in accordance with some embodiments.DETAILED DESCRIPTION

[0033] Described below are low-latency codes that encode and decode FEC blocks using combinatorial logic. Specifically, operations are performed in Galois Field 256 “GF(256)” utilizing combinatorial logic circuits to perform syndrome computation, error case selection, calculation of coefficients of the error locator polynomial, and root finding for quadratic, cubic, and quartic equations to solve for error positions. It should be noted that the principles described herein apply to fields of other sizes as well. The codes described herein correct single bit(s) in a received vector. [INSERT CITE] describes similar coding theory for symbol -based codes for correcting multiple multi-bit symbols.Combinatorial Logic in GF(2n)

[0034] Multiplication and division may both be performed using combinatorial logic circuits. One way to derive multiplication is by means of the Frobenius companion matrix of f(x). If f(x) =fo +fix + ... + fn-ix^+x”, then the Frobenius Companion matrix of f(x) is defined as:

[0035] Where In-i is the (n - 1) x (n - 1) identity matrix. The significance of the companion matrix lies in the following: if h(x) = ho + hix + . . . + hn-ix"'1and g(x) = gO + . . . + gn-lxn-1 are polynomials over GF(2n), then

[0036] is the vector of coefficients of the product h(x) ... g(x) mod f(x). With this the combinatorial circuits for multiplication in F2n- One example for GF(32) is given below:KDU-01008W001

[0037] In the example of GF(32), represented by the irreducible polynomial f(x) = x5+x3+l, the Frobenius companion matrix is:

[0038] To obtain the combinatorial logic circuits for the multiplication of elements (xO, x4) and (yO, ..., y4), the following vector is computed:

[0039] Therefore, (xo, . . . , X4) • (yo, . . . , y4) = (zo, . . . ,24), where zo = yoxo + (y 1 + y4)x4 + y2X3 + y4Xi + y3X2Z1 = yixo + y2X4 + y3X3 + yoxi + y4X2Z2 = y2Xo + (yi + y3 + y4)x4 + (y2 + y4)x3 + (y 1 + y4)xi + (yo + ys)x2Z3 = ysxo + (y2 + y4)x4 + (yo + ys)x3 + y2Xi + (yi + y4)x2Z4 = y4Xo + (yo + ys)x4 + (yi + y4)x3 + ysxi + y2X2

[0040] In the above, addition is to be understood as the XOR operation and multiplication is understood as the logical AND operation.

[0041] The same principles above may be applied to perform operations in GF(256), which would correspond to eight-bit symbols. Suppose that GF(256) is represented by the irreducible polynomial f(x) = x8 +x7 +x5 +x+l with Frobenius companion matrix:KDU-01008W001

[0042] From the same principle above, the following formulas (or circuits) for the entries of (xo, . . . ,x?) • (yo, . . . ,y?) = (zo, . . . ,z?): zo - yoxo + (y4 + ys + ye)x4 + (ys + y4 + ys + y?)xs + (ys + ye + y?)x3 + y?xi + (y2 + ys + y4 + ye)x6 + (ye + y?)x2 + (yi + (y2 + ys + ys))x? zi = yixo + (y4 + y?)x4 + (ys + ye + y?)xs + ysX3 + (yo + y?)xi + (y2 + ys + ye + y?)xe + yeX2 + (yi + y4 + ys + ye)x?Z2 = y2Xo + ysX4 + (y4 + y?)xs + yeX3 + yixi + (ya + ye + y?)xe + (yo + y?)x2 + (y2 + ys + ye + y?)x7Z3 = ysxo + yeX4 + ysxs + (yo + y?)x3 + y2Xi + (y4 + y?)xe + yiX2 + (y3 + ye + y?)x?Z4 = y4Xo + (yo + y?)x4 + yexs + yiX3 + ysxi + ysxe + y2X2 + (y4 + y?)x? zs = ysxo + (yi + y4 + ys + ye)x4 + (yo + y3 + y4 + ys)xs + (ya + ys + ye + y?)x3 + (y4 + y?)xi+(y2 + y3 + y4)xe + (ya + ye + y?)x2 + (yi + yi + ys)x? ze = yexo + (y2 + ys + ye + y?)x4 + (yi + y4 + ys + ye)xs + (y3 + ye + y?)x3 + ysxi + (yo + y3 + y4 + ys)x6 + (y4 + y?)x2 + (y2 + y3 + y4)x? z? = y?xo + (ya + y4 + ys + y?)x4 + (y2 + y3 + y4 + ye)xs + (y4 + ys + ye)x3 + (ye + y?)xi + (y i + y2 + y3 + ys)xe + (ys + ye + y?)x2 + yo + (yi + yi + y4)x?

[0043] To perform division operations utilizing combinatorial logics, some embodiments multiple by the binary reciprocal of a non-zero element. Circuits for determining the binary reciprocal of a non-zero element are described below. The multiplicative structure of the finite field suggests that the matrix associated with the inverse of an element (xo, ...xn.i) is the matrix:KDU-01008W001

[0044] To calculate the inverse, the adjoint of the matrix is used which is equal to the inverse up to the determinant which is xov xi...v xn-i, the logical OR of the variables xo, . . . , xn-i- As such, it is 1 unless all the x; are zero, in which case the reciprocal element doesn't exist. Once the adjoint is computed, we multiply the vector (1, 0, . . . , 0) with its transpose from the left to obtain formulas for the reciprocal of the element (xo, . . . , xn-i). In other words, the reciprocal equals the first column of the adjoint matrix. The inverse (zo, . . . , zn-i) of a nonzero element (xo, . . . , xn-i) are given below for both GF(32) as well as GF (256). zO = (((xl + x2)x3 + xl)x4 + ((x2xl + x2)x3 + xl x2))x0 + (x2xlx3 + xl)x4 + x2xlx3 + x2xl + x2 zl = ((x3 + x2xl)x4 + (x2xlx3 + (x2xl + x2)))x0 + ((x2xlx3 + x2xl)x4 + (x2xlx3 + xl)) z2 = (x2xlx4 + ((xl + x2)x3 + (xl + x2)))x0 + (((x2xl + x2)x3 + x2)x4 + (xlx3 + x2xl)) z3 = (((xl + x2)x3 + x2)x4 + (x2xlx3 + (xl + x2)))x0 + ((x2x3 + xl x2)x4 + ((x2xl + x2)x3 + x2)) z4 = ((x2x3 + x2xl)x4 + (xlx3 + x2xl))x0 + (((x2xl + x2)x3 + (xl + x2))x4 + (xl x2x3 + x2xl))

[0045] In the same manner, formulas for the inverse (zo, ...,z) of (xo, ...,x) may be determined.For brevity, the formula for only zo is given below. z0= ((((((x6 + x7)x5 + x6 + x7)x4 + x7x6x5)x3 + (((x7x6 + x7)x5>+ x7x6)x4 + (x6x5 + l)))x2 + (((x7x6x5 + x7x6)x4 + (x7x6x5+ x7))x3 + ((x7x5 + (x6 + x7))x4 + ((x7x6 + x7)x5 + x6))))xl+ ((((x7x6x5 + x7x6)x4 + (x6x5 + x6))x3 + (((x7x6 + x7)x5+ l)x4 + (x7x6x5 + x7x6)))x2 + ((((x7x6 + x7)x5 + l)x4 + (x5+ x7x6))x3 + (((x6 + x7)x5 + x7)x4 + (x7x6x5 + (x7x6+ x7))))))x0 + (((((x7x6 + x7)x5x4 + (x6x5 + x7x6))x3+ (((x7x6 + x7)x5 + x7x6)x4 + ((x7x6 + x7)x5 + x7x6)))x2+ (((x6x5 + x7x6)x4 + (x7x5 + x7))x3 + ((x6x5 + x7x6)x4+ (x7x5 + x7))))xl + ((((x7x6x5 + x7x6)x4 + ((x6 + x7)x5+ x7x6))x3 + ((x7x6 + x7)x4 + ((x7x6 + x7)x5 + (x6 + x7))))x2+ (((x6x5 + (x7x6 + x7))x4 + ((x6 + x7)x5 + x7x6))x3+ ((x7x6x5 + x6)x4 + (x7x6x5 + (x7x6 + x7))))))

[0046] While the above formulas may appear complex, particularly for division, they are readily implementable as efficient combinatorial logic circuits. Moreover, many algorithmsKDU-01008W001 described herein utilize few division operations. It is also noted that the above formulas may be further optimized, and that the formulas given above should not be considered limiting. In some embodiments, combinatorial logic circuits for computing square and cubes of an element are given below over GF (256).

[0047] The entries zo, ...,ZT) of the square of (xo, ... ,XT) are given by: zo = xo + X4 + X5 + X6;Z] = X4 + X6,'Z2 = X] + X6 + X?;Z3 = X5 + X7;Z4 = X2 + X7,'Z5 = X4 + X5;Z6 = X5 + X3;Z7 = X4,'

[0048] Similarly, the entries zo, ...,Z7) of the cube of xo, ....x?) are given by:

[0049] In the following description, encoding and decoding of FEC-blocks of data are described that utilize multiplication, division, squaring, and cubic operations for calculating syndromes of a code, selecting an error case, calculating the error polynomials from the syndromes, and finding error positions that correspond to the roots of the error polynomial. In some embodiments, the roots are calculated using root-finding combinatorial logic, while alternative embodiments employ parallel evaluation circuits to determine the roots of the error locator polynomial. The combinatorial logic circuits may be created via register transfer level (RTL) code, or other synthesis tools.Low-Latency FEC Codes

[0050] Described below are low-latency codes that encode and decode FEC blocks using combinatorial logic, as opposed to generalized Reed Solomon (RS) codes that rely on Berlekamp-Massey for finding the error locator polynomial, the Chien search for finding theKDU-01008W001 roots of the error locator polynomial, and extensive lookup tables for finding the error locations. FIG. l is a block diagram of a communications channel employing FEC. As shown, an original message M is encoded to generate a valid codeword C of the FEC code. The codeword is transmitted via the channel and received vector R = C+E, which is the codeword with some potential error. The decoder in FIG. 1 includes combinatorial logic broken into subblocks for (i) syndrome generation, (ii) error case selection, (iii) error solver and (iv) error correction. For a systematic code, the syndrome generation combinatorial logic combines the received symbols according to the encoding matrix and generates syndromes that represents a comparison of the redundancy symbols received in vector R to the redundancy symbols generated by the decoder.

[0051] The FEC codes herein utilize the following check matrix:

[0052] Where ai is the element of the field corresponding to the vector representation equal to the binary representation of the integer i. Using the above check matrix yields an error-locator polynomial in which the roots correspond directly to the symbol position index(es) that contain the errors. In the above description, the symbols of the (n,k) FEC codes are 8-bit bytes, and thus the check matrix used above is over Galois Field 256 (GF(256)). Combinatorial logic equations for multiplication, division, finding squares, and cubes in GF(256) have been described above. Such combinatorial logic circuits may be utilized to implement the calculation of syndrome values of the code, combining the syndrome values to generate the coefficients of an error locator polynomial, evaluate the error locator polynomial at each unique field element of the code, and solve for the error values.Encoding

[0053] The encoding matrix can be found by taking the last k columns of the check matrix, inverting it, and multiplying it by the check matrix H(n,k) to yield (Hi|I„-^), where Hl is the encoding matrix:KDU-01008W001

[0054] In the particular example of a (12,8) FEC code, we have:and (' i l l 1 \: / 180 87 36 56 63 52 216 234 1 0 0 09 10 11 12rr / ,3 o. i 104 236 120 92 84 75 221 159 0 1 0 065 68 69 80 I ' ' 179 88 85 104 102 139 127 251 0 0 1 0172 77 2 134 / \ 110 226 8 13 12 245 123 143 0 0 0 1

[0055] The left 8 columns of the matrix on the right correspond to the encoding matrix Hl. The encoding matrix may be implemented using combinatorial logic to generate the redundancy symbols for storage in the redundancy DRAMs.Decoding

[0056] Assume transmitted codeword c = (co, ...,cn-i) is received as vector y = (yo, ...,yn-i), with up to (n-k) / 2 errors in y. Suppose r = n-k. Decoding begins with computing the syndromes of the code So,...,Sr-i:

[0057] The computation of the syndromes can be performed using similar combinatorial logic circuits as the encoder, because the output of the algorithms are computed solely from the elements of y without the use of memory or feedback.

[0058] Suppose during the transmission of a codeword of C(n,k) that e errors have occurred, and further suppose that syndromes So,...,Sr-i have been computed. From the syndromes, the error locator polynomial may be determined. Specifically, an error locator polynomial h(x) may take the form of: h(x) = hnxn+ hn~ixn l+ ... + hix + ho

[0059] Where hn, hn-i, ..., hi, ho are coefficients of the error locator polynomial. It is noted that the computation of particular coefficients is dependent on the particular error case. ForKDU-01008W001 example, the hi coefficient may be computed differently for the three- and four-error cases. The following are formulas for the error-locator polynomial h(x) based on the syndromes for various error cases. Specifically, the one-error case is a linear polynomial, the two-error case is a quadratic error locator polynomial, the three-error case is a cubic error locator polynomial, and the four-error case is a quartic error locator polynomial. While not explicitly shown, error locator polynomials may exist for quintic and higher orders as well. if e = 1, then: h(x) = Sox + Si if e = 2, then: h(x) = (S0S2 + Sl2)x2+ (SOS3 + SlS2)x + (S1S3 + S22) if e = 3, then: h(x) = ((S2S4 + S23)S0 + (S12S4 + S23))X3+ ((S3S4 + S2S5)S0 + (S2S1S4 + (S12S5 + (S 1 S32+ S22S3))))X2+ ((S5S3 + S42)S0 + (S5 S2 + S4S3)S1 + S4S22+ S32S2)x + S1S42+ (S1S3 + S22)S5 + S33if e = 4, then h(x) = h4x4+ h3x3+ h2x2+ hlx + ho where

[0060] In the decoder, the algorithm uses combinatorial logic to calculate the coefficient of the highest power of x in the maximum error case. For the 4-error case, this would be the coefficient h4. If h4 is non-zero, then there are four errors present and the algorithm continues calculating the rest of the coefficients of the error polynomial h(x) based on the syndromes. If Av is zero, then there are less than four errors and the algorithm calculates the coefficient for the highest power of x for the next-highest error case. The algorithm steps through calculating the highest power of x for each error case until the first non-zero term is calculated, which indicates the number of errors and thus the error polynomial may be calculated using the syndromes viaKDU-01008W001 combinatorial logic. Once the error polynomial is determined the roots may be found using combinatorial logic. As mentioned above, the roots correspond to the binary expansion of the column(s) of the check matrix for the symbol containing the error, and thus no Chien search is required thus reducing latency.

[0061] FIG. 2 illustrates a block diagram of a FEC decoder, in accordance with some embodiments. As shown, the FEC decoder includes similar block as the decoder shown in FIG. 1, with additional detail regarding the error solver. As shown, the decoder is configured to received the codeword vector and to compute the syndromes form the received codeword vector. Computing the syndromes includes applying the check matrix to the codeword, which may be performed e.g., using combinatorial logic. The error case selection and error locator polynomial coefficient generator is configured to receive the computed syndromes (i) determine an error case, and (ii) compute coefficients of an error locator polynomial associated with the determined error case.

[0062] As indicated by the name, error case selection circuit determines how many errors are present in received vector R. FIGs. 3-7 are block diagrams of sections of the error case selection circuit. The sections of error case selection circuit are implementable using combinatorial logic, e.g., GF(256) combinatorial logic circuits. In some embodiments, the error case selection circuit incrementally generates the coefficient of the highest power of x for the error locator polynomial of the maximum error case first. If the coefficient is non-zero, then the maximum error case is selected and the remaining coefficients are generated. If the coefficient is zero, then the logic moves on to the next-highest error case and generates the coefficient for the highest power of x again. The process repeats until the number of errors is determined. Further, the error case selection circuit may analyze the syndromes to isolate the sections of an extended FEC code, described in more detail below.

[0063] In the particular example below, the (86,80) symbol-based code is considered over GF(256), however such a code should not be considered limiting as any of the previously- described codes are handled in similar ways. The codes which correct e.g., only one or two errors may either omit or otherwise disable the logic specific to the three- and four-error correcting codes. A given memory controller may have configurability to employ multiple codes.

[0064] In FIG. 3, the calculated syndromes are received. If all the syndromes are zero, then no errors are present in R, and the select O signal is asserted. Combinatorial logic is used to generate the coefficient A4 from the syndromes, using the equations given above. If the syndromes include at least one non-zero element and A4 is non-zero, then the select_4ECCKDU-01008W001 signal is asserted, and the error solver evaluates the degree-4 polynomial over all field elements. If A4 is zero, then the logic moves to the 3 ECC equation solver to determine if three, two, or one error are present.

[0065] FIG. 4 is a block diagram of the error case selection circuit for identifying the 3 -error case, in accordance with some embodiments. FIG. 4 is more detailed with respect to FIG. 4, as the coefficient for the 3-error case error locator polynomial is less complex than the 4-error case. As shown, the syndromes are checked and if all syndromes are zero then the select O signal is asserted. This step may have already been determined in the previous FIG. 3, and is shown again for illustrative purposes that a circuit that corrects up to three errors would include similar logic for checking the syndromes. A3 is calculated from the syndromes, shown in FIG. 4 with functional arithmetic operations, each of which may take the form of the GF(256) combinatorial logic circuits previously described for such operations. The combinatorial shown implements the following equation:— So. (S2.S4+ S3 ) + S4.S4+ S2

[0066] If A3 is non-zero, then the error case selection circuit asserts the select_3ECC signal, indicating that three errors are present. The error case selection circuit proceeds to calculate the remaining coefficients, and provides the coefficients to the error solver circuit to evaluate the error locator polynomial at each field index. If A3 is zero, then the algorithm proceeds to check the 2-error case.

[0067] FIG. 5 includes combinatorial logic for calculating A0, Al, and A2 using the following equations:

[0068] If A2 is zero, then the select_lECC signal is asserted; otherwise the select_2ECC is asserted indicating that two errors are present. FIG. 5 further depicts the portion of the error solver circuit for finding the two error positions. FIG. 6 illustrates combinatorial logic for the quadratic equation solver used for solving the error values for each of the two errors, which is based on the error positions and the syndromes SO and SI. The remaining equations for solving error values are described in further detail below. As shown, the multiplexers in FIG. 5 selectively output the two-error corrections based on the received selection signal error_case_2KDU-01008W001(and output ‘0’ otherwise). FIG. 7 illustrates combinatorial logic used for identifying the error position in a one-error case, in accordance with some embodiments.

[0069] Once the error locator polynomial is determined of the form A4X4+ A33+A22+AI +T4O, the error solver circuit is configured to (i) find the position of each error and (ii) to find the error value of each error. In the case of binary codes, the error value may correspond to a bitflip. Binary codes are described in more detail below. Error values for symbol-based codes correspond to error masks applied to a given symbol to correct any number of bits in the symbol.

[0070] Referring back to FIG. 2, the error solver circuit includes n instances of error locator evaluation circuits in parallel; each error locator evaluation circuit configured to evaluate the determined error locator polynomial at a respective field index of the code. In some embodiments, the entire error correction process may happen during a single clock cycle. The received codeword vector ‘R’ may be fully received and stored in a buffer, for example. The codeword vector ‘R’ is read, using a latch operating according to a first clock cycle. The codeword vector ‘R’ is thus provided as an input to the aggregated FEC combinatorial logic circuit made up of e.g., the components shown in FIG. 2. The elements of ‘R’ are provided to the gates that make up the syndrome computation logic, the outputs of which are provided as inputs to the gates making up the error case selection and error locator polynomial generation logic, and so on. The entirety of the gates making up the aggregated FEC combinatorial logic circuit eventually settle, all within the time before the next clock cycle, upon which the corrected data vector is output. The evaluation of the error locator polynomial with parallel circuits is a key component for ensuring that the aggregated FEC combinatorial logic circuit settles within the period of the clock.

[0071] It should be noted that some embodiments may pipeline the various stages. FIG. 8 illustrates exemplary stages of the circuit in which pipelined flops may be included, and thus the operations of the error correction algorithm are broken up into the following steps:(i) the codeword is provided to syndrome computation logic which generates the syndromes from the codeword value;(ii) the error case selection logic is configured to combine the syndromes to determine an error case;(iii) the coefficients of the error locator polynomial are generated from the syndromes based on the error case;KDU-01008W001(iv) the coefficients are provided to each error locator evaluation circuit to simultaneously evaluate the error locator polynomial at each unique field element, and(v) the error values are solved based on the syndromes and the roots of the error locator polynomial and(vi) the errors are corrected in the codeword.

[0072] Each evaluation circuit is associated with a respective symbol location in the received codeword vector, and performing the evaluations in parallel enables the error correction to be performed in a single pipelined stage, significantly reducing latency compared to iterative counterparts. Any error locator evaluation circuits that return a value of ‘0’ responsive to the evaluation of the respective field index corresponds to a root of the error locator polynomial, and thus corresponds to the position of an error in the codeword. This is an alternative approach to root finding combinatorial logic, as well as the Chien search, which is an iterative process of checking each field element a, a2, a3, and so on by iteratively computing the next element a1of the field to determine which elements of the field correspond to roots of the error locator polynomial (which are then be mapped to error positions). Rather, the embodiment of FIG. 2 evaluates the error locator polynomial at every field element, by applying the coefficients of the error locator polynomial to an evaluation matrix:Where P = [P0,Pi . Pn-2. Pn-i],

[0073] Each Pi is e.g., an 8-bit value (assuming the code is over GF(256)). It is noted that in this particular example, the evaluation matrix conveniently corresponds to the check matrix H described above. Further, while all elements of the check matrix are present in the evaluation matrix, it should be noted that some rows of the evaluation matrix may not be utilized depending on the error case, e.g., if three errors occur then the last row of the elements raised to the fourth power are unused. As described above, in the case of three errors, the coefficient of A4 is equal to zero, thus zeroing out the effect of the fourth-power row. Functionally, this is described in more detail below. Further it should be noted that it is not required that the evaluation matrix be directly correspondent with the check matrix. The evaluation matrix and the error locator evaluation circuitry, however, maintains the property in that each evaluationKDU-01008W001 performed according to the evaluation matrix is associated with a corresponding column of the check matrix, specifically identified by the element at in the check matrix H above. It is this correspondence that provides the error position finding capability of the circuitry of FIG. 2.

[0074] FIG. 9 A illustrates a block diagram of one error locator evaluation circuit, in accordance with some embodiments. The error locator evaluation circuit #i is shown, which includes the index value a, as well as all the second, third, and fourth order powers of a;. These particular values may be predetermined and specific to each error locator evaluation circuit, and may be represented as a hard-wired input of ‘ l’s and ‘0’s to a logic circuit. The error locator evaluation circuit z is further configured to receive the coefficients of the error locator polynomial previously generated by the error case selection and coefficient generator circuit. The error locator evaluation circuit is configured to evaluate A+Y-4+ A3X3+A2X2+AIX+T4O for x = a, and to output an asserted flag signal flag i if all 8 bits of P i are 0. Each evaluation occurs simultaneously during e.g., a clock cycle, which significantly reduces the latency of finding the error positions compared to the iterative Chien search as described above. It is noted that each element of the second row of the check matrix is a unique element of the field, and is associated with an evaluation of the error locator polynomial for a specific position index of the codeword.

[0075] In some embodiments, the circuit of FIG. 9A may be further configured to include a fifth-power of a, (i.e., a / ) multiplied by a corresponding coefficient of a quintic error locator polynomial (i.e., A4X4+ A3X3+A2X2+ Aix+^o).

[0076] As described above, the entire aggregated FEC combinatorial logic circuit may be configured to perform the error correction during a single clock cycle. Thus, the input coefficients of the error locator polynomial will eventually settle from logic operating on the syndrome values. In the error cases having less errors than the maximum tolerable errors, higher order coefficients of the error locator polynomial (i.e., those being associated with the higher error cases) will be zero in the parallel evaluation circuits shown in FIGs. 9 A and 9B.

[0077] It should be noted that while the selection of the check matrix H described above is advantageous, the above-described error locator evaluation circuit may be implemented using other check matrices as well. For a Reed-Solomon code, the check matrix may be represented by:KDU-01008W001

[0078] As previously described, the Chien search evaluates the error locator polynomial at the first column of the above matrix, multiply the input by the primitive element a, repeat the evaluation, and continue iteratively multiplying the input by the primitive element a and evaluating until every column of the above matrix has been evaluated. Particular powers of ci correspond to roots of the error locator polynomial, which subsequently are looked up using a lookup table to find the positions of the error. On the contrary, the embodiment of FIG. 2 identifies the positions directly.

[0079] FIG. 9B illustrates an error locator evaluation circuit similar to FIG. 9A, however the inputs ai and the corresponding powers of ai are replaced with the primitive element a' and the higher order exponential powers of a'. Similar to the previous check matrix H, the elements of the matrix above may be pre-computed and hard-wired in each evaluation circuit. Another similarity is that each element of the second row of the check matrix is a unique field element, and the combination of the elements in any given column corresponds to a unique evaluation of the error locator polynomial. Further, coefficients of an error locator polynomial may be determined, using e.g., the Berlekamp-Massey algorithm. Similar to above, any error locator evaluation output corresponding to the element ‘0’ of the field corresponds to a root, and the position of the error is similarly identified.

[0080] Once the error positions are identified, the error positions are provided to an error value solving circuit, which may include combinatorial logic configured to implement operations in the field GF(256). FIG. 10 is a block diagram of such an error value solving circuit. In some embodiments, the logic of FIG. 10 may be pipelined as previously described. As shown, the syndromes [SO: S3] are received, as well as the flags from the parallel instantiations of the error locator evaluation circuits. The error value solver circuit may include logic to create the multibit values identifying error positions (a,b,c,d) based on the asserted flags from the error locator evaluation circuitry. Shown in FIG. 10 are block diagrams for each error case. The output of the error value circuit include the positions ‘pos’ (a,b,c,d) and corresponding eight-bit error values (A, / ?, 5). As shown, the outputs are of the form (pos, val) = (a, X), (b, 0), (c, y), and (d,5).

[0081] In the one-error case, the error value corresponds to the syndrome value SO, and the error position is identified by the division of SI by SO. Such an operation may be computationally inexpensive. Thus, some embodiments may skip the parallel search for error positions in the one-error case, as a single divide in GF(256) may be utilized to find the errorKDU-01008W001 position. Other embodiments may perform the error location and value solving in the same manner, regardless of the number of errors.

[0082] In the two error case, the error positions (a,b) are provided, along with the syndromes SO and SI. A block diagram is illustrated to show the computation of 2 and / ?, specifically implementing the calculations:2 = (bSo + Si) / (a + b)P = 2 + So

[0083] From this algorithm, a and b correspond to the positions of the symbols having errors, and 2 and / ? correspond to the error values of the symbols in positions a and b respectively. Each computation block may be implemented using GF(256) combinatorial logic circuits as described above.

[0084] In the three-error case, the error positions (a,b,c) are provided, along with the syndromes SO, SI, and S2. Combinatorial logic circuits are configured to compute A, / ?, and according to the following equations:A = (bcSo + (b + c)Si + S2) / ((a + b) (a + c)) / ? = (acSo + (a + c)Si + S2) / ((a + b)(b + c))Y = So + a + / 3

[0085] From this algorithm, a, b, and c correspond to the positions of the symbols having errors, and 2, / ?, and / correspond to the error values of the symbols in positions a, b, and c respectively.

[0086] Lastly, the four error correcting case is similarly given below to compute the error values 2, P, Y 8) for positions a,b,c,d, respectively:2 = (dcbSo + ((c + d)b + dc)Si + (b + c + d)S2+ S3) / ((b + c)(b + d)(c + d)).P = (dcaSo + ((c + d)a + dc)Si + (a + c + d)S2+ S3) / ((a + c)(a + d)(c + d)). Y= (dbaSo + ((b + d)a + db)Si + (a + b + d)S2+ S3) / ((a + b)(a + d)(b + d)). 8 = So + 2 + P + Y~

[0087] In the above examples, the combinatorial logic used may be non-iterative, or in other cases it may be pipelined. The combinatorial logic of the FEC circuit may be arranged in stages. Further, the ability to correct errors beyond four errors in a received input vector may be performed by generating quintic or higher error-locator polynomials, using the concepts previously described with respect to computing the matrix Mt. The parallel error locator polynomial evaluation circuits may be configured to identify five or more error positions in the received codeword vector, with the tradeoff of additional redundancy added to each codeword,KDU-01008W001 thereby increasing the length of the codeword or reducing the amount of data within each codeword if codeword length remains the same.

[0088] For example, for a given FEC code, the combinatorial logic may include a syndrome calculation combinatorial logic circuit configured to receive bits of the symbols of the given FEC code as inputs to a plurality of gates, and to compute the syndrome values using a series of gates wherein the outputs of the syndrome calculation combinatorial logic circuit are a plurality of bits that correspond to the syndrome values. These bits may then be presented to an error locator polynomial combinatorial logic circuit, which utilizes a series of gates to implement the equations previously described to generate the coefficients of the error locator polynomial, represented as a set of bits. The syndrome values may be calculated as the symbols are read from e.g., a dynamic random-access memory (DRAM) device. Alternatively, the syndrome values may be calculated once the entire FEC codeword has been read out of the DRAMs.

[0089] The above table are preliminary synthesized combinatorial circuits for the decoding portions of the FEC circuit and may be further optimized. The encoding portions of the FEC circuit are less complex and involve far fewer logic gates and shorter critical path. In some embodiments, the various combinatorial logic stages of the FEC decoder may be pipelined if latency requirements allow.Binary Codes

[0090] The embodiments described above apply similarly to binary codes. In the binary codes described herein, the entries of the check matrix are bits, and described in more detail below. The check matrix is defined through arithmetic in the finite field, specifically the syndromes are grouped such that they are processed using arithmetic in a larger field than GF(2). For purposes of description below, the element integer j with 0 < j < 2mwe denote by el( / ) the element corresponding to j in the finite field, and for an element a in the finite field by bin(a) the corresponding binary vector. Hence, bin(el( / )) is the m-bit binary representation of j.

[0091] The check matrix of a binary code of length n < 2m capable of correcting e errors is a binary matrix with e*m rows and n columns defined as:KDU-01008W001

[0092] For simplicity, all-zero rows may be removed, and the maximum number of rows is e*m. Further, it should be noted that it is not necessary that the enumeration of the columns begin with ‘ 1’. Also, any elements of the underlying field may be used, the above check matrix is one implementation in which the indices map to elements in the corresponding columns.In an example below, the code is over GF(256) and given by the polynomial x8+ x7+ x5+ x + 1. The binary expansion of an integer between 0 and 255 is an 8-bit vector with the first component being the least significant bit and the last component being the most significant bit. For example, the element (in polynomial representation) x7+ x + 1 corresponds to the integer 27+ 2 + 1 = 131 and has bit-representation [1,1, 0,0, 0,0, 0,1], The codes below are length 32 however such a size should not be considered limiting. The number of correctable errors in the code is associated with the number of powers used in the matrix. For example, a check matrix including the first power may be configurable to correct one error; a check matrix including the first and third powers may be configurable to correct up to two errors; a check matrix including the first, third, and fifth powers may be configurable to correct up to three powers; and a check matrix including the first, third, fifth, and seventh powers may be configurable to correct up to four powers. It is noted that in the check matrix B above, only the odd powers are included as any even-powered values may be derived from the odd powers - thus excluding the explicit calculation of the even powers reduces the circuit complexity as well as the redundancy overhead. Further, a parity row may be included to provide error detection.

[0093] The check matrix for a single error correcting code is given in FIG. 11A and shares similarities with a Hamming code. In FIG. 11 A, two all-zero rows have been removed, and each column corresponds to a binary expansion of integer j. The first row is the LSB and the last row is the MSB.

[0094] FIG. 1 IB illustrates a check matrix for a two-error correcting code, adding the 3rdpowers of each element. In every column, the bottom 8 bits represent the third power of the element given by the upper 6 bits.

[0095] FIGs. 12A and 12B illustrates check matrices for three and four error correcting codes, respectively. The check matrix for the three-error correcting code adds the fifth power of the elements and the check matrix for the four-error correcting code adds the seventh power of the elements.

[0096] The encoding procedure for binary codes includes identifying a set of columns of the check matrix whose rank is the same as the rank of the check matrix. The inverse of such a matrix is multiplied by the check matrix to obtain the encoding matrix. FIG. 2 illustrates a check matrix for a code of length 144 having 128 data bits and 16 redundancy bits, and isKDU-01008W001 configured to correct up to two errors. In the check matrix of FIG. 2, it may be determined that columns [5, 8, 31, 47, 52, 58, 59, 67, 79, 82, 88, 90, 98, 110, 111, 128] are linearly independent, and may be utilized as the positions of the redundant bits. It should be noted that there may be other sets of 16 columns that are linearly independent, and such sets may be chosen instead. A 16x16 matrix is formed from these 16 columns; inverted; and multiplied by the original check matrix to yield the encoding matrix shown in FIG. 3. As shown in FIG. 3, the redundant positions are highlighted and form an identity matrix within the encoding matrix. The data vector is applied to the non-highlighted (i.e., non-redundancy) portion of the encoding matrix to generate the 16 redundancy data bits. The 16 redundancy data bits may be inserted in the redundancy positions, or alternatively transmitted separately - as long as the decoder is configured to apply the redundancy bits to the correct inputs of the combinatorial logic for generating the syndromes.Decoding

[0097] Similar to above, the embodiments described herein utilize a decoding process that includes evaluating the error locator polynomial in parallel, wherein each evaluation is associated with a respective bit position of the received codeword vector. The decoding process involves (i) syndrome computation (binary operation on GF (2) elements), (ii) computing the coefficients of the error-locator polynomial (computation over finite field), and (iii) evaluating the error locator polynomial for each bit position of the received codeword. The primary difference between the symbol-based code and binary code is that each error is corrected by a bit-flip, and thus the circuitry no longer needs to calculate an error value associated with the identified error position. The 1 -error case involves syndrome computation only, as the syndrome provides the error location directly.

[0098] Correcting two errors includes multiplying the binary check matrix B with the n received bit-values to obtain up to 2*m bits of syndromes. The number of bits of syndromes is equal to the number of rows of the check matrix B. The 2*m bit syndrome vector is interpreted as having elements of the field GF(2m), and call them SI and S3. The next step is to find a nonzero root R of the quadratic equation X2+ X + (1 +S3 / S13). Similar evaluation logic may be used that was previously described with respect to FIG. 8. It will be noted that while the check matrix for the binary code omits the squared version of the binary expansions of the integers fl / , the squared (and potentially fourth) power elements are still used in the evaluation as shownKDU-01008W001 in FIG. 8. Once the error positions are determined, the bits at the determined error positions are flipped to complete the decoding.Extended Low-Latency EEC Codes

[0099] In some embodiments, it is preferable to encode blocks of data having a certain size, e.g., in compute and memory applications. For example, a single memory cache line is often 64 bytes = 512 bits (or another similar granularity depending on the processor). In such embodiments, an entire block of data is fetched or written, rather than a partial block thus requiring additional reads / writes. Codes herein are described in which the length of the code extends beyond the field of computations. For example, a first code is described having combinatorial operations in GF(256) that encodes 256 bits of data using 23 redundant bits, for a total length of 279 bits. Such a code performs double error correction with single error detection (DECTED) Another example is given that protects 512 bits of data with 32 redundant bits and provides double error correction (with triple error detection). The first code described below include direct computation of the error position, as well as a length for protecting 256 bits (ideal size in many computing applications) with 23 redundant bits. The number of redundant bits may be extended into 24 by e.g., zero padding in some cases. FIG. 7 is a diagram of the check matrix, in accordance with some embodiments. The sections A, B, and C are defined out below:C = ( bm(el(l )) bin(el(2)) bin(el(23)) ) .

[0100] Columns 128 192, 224, 240, 248, 252, 254, 255, 256, 261, 262, 263, 267, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278 are linearly independent (counting from 0). Positions outside this set are used as information positions while positions in the set are redundant positions.

[0101] The decoding algorithm begins with computing the syndromes. A binary vector v is received having 279 bits which is assumed to be at most Hamming distance 2 away from aKDU-01008W001 codeword. Thus, at most two bit-errors are in vector v. The code corrects up to two error and returns a decoding error if three errors occur (as well as many other cases of more than two errors), thus limiting the probability of silent data corruption. The check matrix of FIG. 33 is multiplied by the receive vector v to yield 23 bits of syndromes s = [s0... s22]. The bits of syndromes are grouped into:50 := SO;51 = [sl,...,s9], S3 = [sl0,...,sl7],54 = sl8,55 = [sl9,...,s22, 0,0,0],

[0102] SI, S3, and S5 are interpreted as elements of GF(256) while SO and S4 are bits. The following decoding algorithm identifies positions having error:► _ / * No errors if all syndromes are 0 * / ► if SO == 0 && SI == 0 && S3 == 0 && S4 == 0 then return(“No error”) endif► if SO != 0, / * Only one error * / ► _ / * Check that there is really have one error. * / ►then retum(“Decoding Error”) endif► if ( S5 4- 0 && SI 4- S5 return(“Decoding Error”) endif► retum( [S4*255 + int(Sl)])► else / * Now SO == 0, so there are 2 errors * / ► if S 1 == 0 then / * Can only happen if one of the errors is in position 0-255 and the other not * / ► if S3 0 then return(“Decoding Error]) endif► if S4 == 0,then return(“Decoding Error]) endif► retum([int(S5), 255+int(S5)])► else / * Now there are two errors and SI != 0. Find the pseudo error positions * / KDU-01008W001► evaluate X2+ S1*X + (S3+S13) / S1 = 0 for all positions 0-255 of a given codeword section► if not solvable then return(“Decoding Error]) endif► Denote the solutions of the equation by a and b► indices = [toint(a), toint(b) ];► if S4 0 then / * One error at index 0 - 255, another at index 256 and bigger► if S5 == 0 then return(“Decoding Error]) endif► retum( [int(S5)+255, int(S5+Sl)]) );► else / * Now S4 == 0, so either both errors have index < 255 (iff S5 == 0), or both have index >= 255 (iff S5 != 0 ) * / ► if S5 == 0 then return( [toint(a), toint(b)]) endif► / * In this case S5 is nonzero and both errors are at index >= 256 * / ► if SI != S5 then retum(“Decoding Error]) endif► retum( [ 255+int(a), 255+int(b)])

[0103] A decoding example is given in Appendix I.

[0104] The construction of the above matrix is one particular example, and the concepts may be generally expanded to increase the length of a code with respect to the field in which the code is designed. First the properties of the matrix shown in FIG. 13 are analyzed below:

[0105] As shown, the matrix of FIG. 13 includes the subsections A, B, and C defined above, and the number of columns (279) exceeds the field in which the elements of the matrix defined by (GF(256)). As previously mentioned, such a property is desirable in e.g., memory and compute applications where blocks of data bits having multiples of 8, 16, 64, etc are desired. The number of redundant bits is shown as being 23, however this may be extendable to 24 (another multiple of 8) using zero-padding to make storage in e.g., cells of a DRAM more consistent with conventional practice.

[0106] As shown, the matrix includes an all-one row in the first row. This all-one row assists in determining if one or two errors occurred by providing a parity check on the codeword. The syndromes represent the error vector multiplied by the check matrix, as the syndromes resulting from a valid codeword multiplied by the check matrix is zero. In a first example, assuming notKDU-01008W001 all syndromes are equal to zero (and thus an error has occurred), if SO = 1, then it may be assumed an odd number of errors have occurred, as an error vector having an odd number of errors being bit- wise XOR’d with itself would return a ‘ 1’. The decoding algorithm above includes some fail-safe checks to ensure that only one error has occurred and returns a decoding error if errors in multiples of three have occurred, thus reducing the probability of SDC. If 80=0, however, then it may be assumed two errors have occurred, as the error vector having two positions of ‘ 1’ being bit-wise XOR’d with itself would produce a ‘0’ in the SO position. In some embodiments, detection of four errors may return a decoding error, however it may be assumed that the probability of four errors occurring is quite low.

[0107] Another property of the matrix in these codes is the utilization of binary expansions of the integers in the field, which allows for direct computation of the positions in the received codeword vector containing error. As previously defined, the first 256 columns (A) include the binary expansions of every element 1-256 of GF(256) (rows 2-9) as well as the cubed versions of these elements (rows 10-17). It is worth noting again here that the even powered versions of these elements are not needed as the syndromes for the even-powered elements can be determined directly by squaring the syndromes of the odd-powered elements, if needed. Specifically, a syndrome associated with the squared elements of GF(256) are derivable from SI2. The syndrome that may be associated with elements of GF (256) to the fourth power, is derivable from SI4. Thus, extra redundancy overhead is not needed to transmit the even- powered elements directly. In section ‘B’ of the matrix, the binary expansion of elements 1-23 are reused. Thus, identifying the symbol position indices that map directly to error positions comes with a caveat. If the syndrome SI of any errors falls between 1-23 inclusive, then the decoding algorithm determines which section of the received vector the error occurred: in the first 256 locations or the last 23 locations. By design, the matrix of FIG. 7 has the property of including a section of ‘0s’ in rows 1-256 (below section A), and section ‘C’ which occupies the same columns of ‘B’, and calculation of additional syndromes S3, S4, and S5 assist in determining the error position.

[0108] In the case of one error, the algorithm includes some additional checks to ensure that one error has occurred, as opposed to e.g., 3 errors. Such checks include ensuring that SI3= S3 (if not, then a decoding error is returned). Another check is to ensure that if syndrome S5 is analyzed, which is associated with rows 18-23. It is expected that if the error occurs in the section of the received vector associated with the columns occupied by section B, then S5(indicating an error in position index 256-278). It is expected in the case that if one error has occurred, then S5 should equal SI as they correspond to the same binary expansion of anKDU-01008W001 integer between 1 and 23. However, if S5 SI, then it is an indication that three or more errors have occurred and a decoding error is returned.

[0109] As one error has been confirmed from the above check procedures, then the algorithm returns S4*255 + int(Sl). In this equation, S4 (generated using the second all-one row occupying row 18 in columns 257-279) is used to indicate if the error has occurred in section A or B. Specifically, if one error has occurred and S4 = 1, then the error has occurred somewhere in position 256-278 of the received vector, and SI will be an integer between 1-23. Thus, the error position is an offset of between 1-23 from 255. If S4 = 0, then the error occurred in the first 256 position indices, the error position index corresponding to the integer value of SI, which is between 0-255. Thus, in some embodiments, the second all-one row is utilized to discern whether the one error occurs in a position in the first 256 position indices 0-255 indices or the last 23 position indices 256-278.

[0110] As mentioned above, syndrome SO associated with the first all-one row spanning all 279 columns assists in determining the one and two error cases. If S0=0, then it is likely that two errors have occurred, and the decoding algorithm discerns which of the following scenarios occurs:(i) Both errors in the first 256 positions (section ‘A’)(ii) Both errors in the last 23 positions (Section ‘B’)(iii) One error in each of the first 256 and last 23 positions.[OHl] One special case to analyze is when SI = 0, and there is one error in each of the first 256 and the last 23 positions, specifically in the positions identified by the same binary expansion a given integer in sections ‘A’ and ‘B’. For example, if two errors occur, one at position a and the other at position 255+a, then the syndrome SI would end up canceling itself out and appearing as ‘O’, when in fact two errors have occurred. Thus, the decoding algorithm checks (i) if S30, return decoding error (as the S3 syndrome should similarly cancel out if only two errors have occurred), and (ii) if S4 == 0, return decoding error (if two errors occur, only one of which is in the last 23 positions, the S4 must necessarily be ‘ 1’). If neither of these decoding errors occur, then the algorithm returns the integer value of S5: int(S5) and 255 + int(S5). Looking at the check matrix, the syndrome S5 is generated based on the binary expansions of integers 1-23 for the last 23 positions of the received error vector, without the effect of the first 256 positions of the received error vector. Thus, in this particular case, the decoding algorithm identifies the error positions, both of which are a function of S5.

[0112] If there are two errors and SI 0, then the roots of quadratic X2+ S1*X + (S3+S 13) / S 1 = 0 are solved using e.g., parallel error locator polynomial evaluation circuits. If the quadraticKDU-01008W001 is not solvable, a decoding error is returned. The positions within the codeword subsection correspond to indices a and b. Indices a and b may correspond to the positions of the errors within a particular codeword section that is identifiable through analysis of the syndrome values. S4 is analyzed again to narrow down to one of the three cases (i)-(iii) above. If S4 0 then one error is in the first 256 positions and one error is in the last 23 positions (case (iii)). As long as S5 0, then the error positions are int(S5) +255 and int(S5+Sl).

[0113] S4 equal to zero either indicates no errors occurred in the last 23 positions or both errors occurred in the last 23 positions. If S5 == 0, then no errors occurred in the last 23 positions, and both occurred in the first 256 positions (case i). The positions of the errors correspond to the integer roots a and b.

[0114] If S5 0, then both errors occurred in the last 23 positions (case (ii)). The decoding algorithm includes a check to ensure the SI is equal to S5 (and returns a decoding error if this is not the case). This is due to the received error vector containing both errors in the last 23 positions, and the syndromes SI and S5 should be computed the same when multiplying the received error vector by the rows associated with matrix sections B and C respectively. The decoding algorithm returns the positions corresponding to 255 offset by the indices a and Z>: 255+int(a), 255+int(b).

[0115] To summarize, the check matrix of FIG. 13 includes multiple properties to extend the length of the code past the size of the finite field. Specifically, the check matrix includes a range of indices shared in columns of first and second sections, denoted ‘A’ and ‘B’ . The check matrix includes a first all-one row spanning all columns of the check matrix to determine a number of errors. The check matrix includes rows that differentiate the first and second sections ‘A’ and ‘B’ to distinguish error positions when the syndrome denotes a position that falls into the shared range of indices. In FIG. 13, these sections include an all-zero section sharing columns with the first section ‘A’ and a section ‘C’ sharing columns with the second section ‘B’. The section ‘C’ also includes the shared indices used to determine error position indices in the two error case. Specifically, the construction of ‘C’ avoids a decoding failure in the unique case that the symbol position indices of two errors are unrecoverable from SI alone, as the two errors occurred in columns of ‘A’ and ‘B’ that share the same binary expansion of a given integer. The check matrix further includes a second all-one row local to section ‘B’ . The second all-one row assists in discerning where error positions occur in the two-error case, specifically the cases (i)-(iii) above.

[0116] The check matrix of FIG. 13 and definitions of A, B, and C described above are one particular implementation, and it should be noted that similar matrices may be developed forKDU-01008W001 codes of different lengths, and / or codes having elements of a different finite field. For example, a similar code may be developed over e.g., GF(128), GF(64), GF(512), GF(1024), etc.

[0117] In some embodiments, the code rate of the specific code given above may be increased by e.g., adding rows and columns to the check matrix of FIG. 13. For example, the total number of columns may be increased to 512, and section B may include binary expansions of integers 1-255. To account for this, three additional rows may be added to section ‘C’, to accommodate the range of the binary expansions of integers 1-255. The all-one row. In some embodiments, additional rows may be included to add additional powers of the position indices to perform e.g., three error correction.

[0118] FIG. 14 is a modified version of the check matrix of FIG. 13. Specifically, the check matrix includes an additional section of all-zeros in the top right portion of the matrix to simplify the decoding process. It should be noted that the decoding algorithm may change slightly, however many of the properties remain the same in the ability of the code to identify error position indices in the range of 0:255, as well as the ability to isolate in which section of the received vector any error(s) occur. The sections of the received vector map to corresponding sets of columns. For example, the first section of the received vector maps to the first 256 columns of the check matrix while the second section of the received vector maps to the last 23 columns of the check matrix. Further, in the case of one error in each section, the error positions may be directly identified by the first-order syndromes.

[0119] As noted above, the redundant positions are intermixed with the data bit positions in the check matrix (as opposed to them all being at the end). That is to say, the application of the check matrix to the received vector indicates that redundant bits may be dispersed throughout the data bits of the received vector. It should be noted, however, that the FEC codewords are still systematic in that they contain the original data. Some embodiments may transmit / receive the data bits and redundant bits separately, e.g., over separate interfaces, while alternative embodiments may interject the redundant bits in the redundant positions of the codeword vector. Some applications, such as DRAM storage, may prefer that the data bits are stored together in dedicated data cells of a DRAM die with the redundant bits being stored in dedicated redundancy cells of the DRAM. Thus, rewiring may be utilized in the FEC decoder to insert redundant bits in the correct positions during calculations of the syndromes. In alternative embodiments, the redundant and data bits may be stored in order according to the check matrix, and the decoder extracts the data bits from the received vector from the data bit positions after any potential error correction.KDU-01008W001

[0120] FIG. 15 is a check matrix for a DECTED code similar to that of FIG. 14, however, the length of the code has been extended to encode 512 bits with 32 redundant bits. As shown, the check matrix includes three sections of columns having (i) binary expansions of the integers in the field GF(256), (ii) a parity row, and (iii) a section of the elements of GF(256) raised to the third power. The “sections” of the check matrix are applied to respective sections of the received FEC codeword. As shown in FIG. 15, the check matrix includes a first section that spans 256 columns, a second section that spans 256 more columns, and a third section that spans 32 columns. Thus, a section may be limited by the number of finite field in which the combinatorial logic operates. In this particular example, the finite field GF(256) includes 256 unique elements and thus each section may include a maximum of 256 columns. The combinatorial decoding logic circuit for decoding the (544, 512) code may be implemented to execute the decoding algorithm illustrated in FIGs. 16-19. The combinatorial logic analyses the syndromes to determine how many errors occurred in the received vector, as well as the sections in which each error occurs. Lastly, the combinatorial decoding logic circuit is configured to determine the error positions for each error.

[0121] FIG. 16 illustrates an algorithm carried out by an error case logic circuit that is part of the combinatorial decoding logic circuit for determining an error case, in accordance with some embodiments. As shown, the decoding process begins with the syndrome vector S, where S = [SO, Sl[7:0], S3[7:0], S4, S5[7;0], S6, and S7[7:0]]. Specifically, the bits SO, S4, and S6 are respective single-bit parity syndromes associated with the first, second and third sections, respectively, of the check matrix of FIG. 15. SI, S5, and S7 are first-order multi-bit syndromes associated with the first, second, and third sections of the matrix respectively. S3 is a third- order multi-bit syndrome associated with the rows of the check matrix having elements of the finite field raised to the third power. In step 1605, if the syndrome vector S is zero, i.e., all syndromes are zero, then the algorithm returns that no error occurred at step 1610. Subsequently, the error case logic circuit is configured to analyze the single-bit parity syndromes in step 1615. If the logical XOR of the three single-bit parity syndromes is nonzero, the logic circuit moves to step 1620, where the error case logic circuit performs a check to determine if the syndrome vector S corresponds to any one column of the check matrix H, which is to be expected if one error is truly present. If the check 1620 is yes, then the error case logic circuit determines 1625 one error occurred. If S does not correspond to a column of H, then the algorithm returns 1630 a decoding error, as it is the case that three or more errors have occurred.KDU-01008W001

[0122] Back at step 1615, if the logical XOR of SO, S4, and S6 is equal to zero, then the algorithm determines 1635 two errors have occurred in the received vector. If any of the first- order multi-bit syndromes SO, S4, and S6 are non-zero, then the error case logic circuit determines 1645 that the two errors occur in different sections. If all three single-bit parity syndromes are zero, then the error case logic circuit checks 1650 that two of the first-order multi-bit syndromes are zero (and thus the errors occurred in the section associated with the singular non-zero first-order multi -bit syndrome). If the check at 1650 is “No”, then the error case logic circuit determines 1655 that two errors are present and that they occur in the same section. If the check at 1650 is “Yes”, then the error case logic circuit returns a decoding error as three or more errors have occurred (i.e., two or more of the first-order multi-bit syndromes are non-zero).

[0123] FIG. 17 illustrates an algorithm carried out by an error correction logic circuit part of the combinatorial decoding logic circuit for the one-error case 1625 as determined by the error case logic circuit. As shown, the one error case analyses each single-bit parity syndrome to determine which section the single error occurs in. If SO 0, then the error occurs in the first section of the received codeword vector. The error position is thus determined by the integer value of SI, due to the construction of the check matrix having column indices that correspond to sequential integers. Similarly, if S4 0, then the error is in the second section of the received codeword vector associated with the second section of the check matrix. The error position corresponds to the integer value of S5 offset by 256. If S6 0, then the error is in the third section of the received codeword vector associated with the third section of the check matrix. The error position corresponds to the integer value of S7 offset by 512. As previously mentioned, the correction of the error corresponds to a bit flip in the determined position.

[0124] FIG. 18 illustrates an algorithm carried out by the error correction logic circuit for the two error case, specifically in which the two errors occur in different sections of the received codeword vector 1645. The error correction logic circuit checks which two single-bit parity syndromes are non-zero, indicating which sections the errors occur. For example, if SO 0 and S4 * 0, then the errors occur in the first and second sections of the received codeword vector, the positions of which correspond to the integer values of SI, and S5+256. Similarly, if SO 0 and S6 0, then the errors occur in the first and third sections of the received codeword vector, the positions of which correspond to the integer values of SI and S7+512. Lastly, if S4 0 and S6 * 0, then the errors occur in the second and third sections of the received codeword vector, the positions corresponding to the integer values of S5+256 and S7+512. Thus, in the two-errorKDU-01008W001 case 1645 in which the two errors are in different sections of the received codeword vector, determination of the error positions is straightforward by way of analysis of the single-bit parity syndromes and the first-order multi-bit syndromes.

[0125] FIG. 19 illustrates an algorithm carried out by the error correction logic for when the two errors occur in the same section 1655. The error correction logic analyses the first-order multi-bit syndromes to determine in which section of the received codeword vector the error occurs. If SI ^ 0, then the errors are in the first section. If S5 0, then the errors are in the second section. If S7 0, then the errors are in the third section. Depending on the section, a quadratic equation is solved using combinatorial logic to find the roots of the equation X2+ X + (1 + s3 / s 13), where s3 is the third-order multi-bit syndrome S3, and where si is the first-order multi -bit syndrome associated with the first, second or third section SI, S5, and S7, respectively. The error positions correspond to the roots of the quadratic a and Z>, offset by 0, 256, or 512 depending on if the errors occur in the first, second, or third section, respectively.

[0126] FIG. 21 is a check matrix for a triple error correct quad error detect (TECQED) code. Specifically, the code includes 256 data bits, but adds an additional 8 redundancy bits (for a total of 31) to provide an extra level of error correction. The check matrix of FIG. 21 is similar to that of FIG. 14; the TECQED check matrix includes an additional set of rows comprising the elements of Ho:255 raised to the fifth power. A fifth-order multi-bit syndrome is generated using the additional set of rows, increasing the number of correctable errors from two to three. The check matrix of FIG. 14 may be even further extended by adding rows associated with e.g., a 7thpower to provide quad error correction through use of a seventh-order multi-bit syndrome. Further, it should be noted that in some embodiments, negative powers of the elements may be used as well (e.g., H-1o:255 would effectively correspond to the inverse of HO:255). The powers selected may be determined based on factors including e.g., complexity, latency, and / or power consumption.

[0127] The table below illustrates a comparison of simulated RTL results of the parallel evaluation implementation with the quadratic equations solver method for the (544, 512) code, previously described in [Shokrollahi II]:KDU-01008W001

[0128] Based on the 650ps latency, it is seen that the combinatorial logic will settle well within the period of e.g., a 1GHz system clock cycle having a period of Ins. While it is expected for the gate count to increase (and thus the area occupied by the gates and the power dissipated by the additional gates) due to the inclusion of e.g., 256 parallel evaluation circuits (or 68 parallel evaluation circuits for e.g., the (68,64) symbol-based code, the latency is nearly halved compared to the quadratic equation solver techniques. Thus, the parallel evaluation method may thrive in environments where reduced latency is critical, and in designs in which area and power dissipation are relaxed.

[0129] The check matrix of FIG. 20 includes similar properties previously described for identifying error positions. The check matrix includes the binary expansions sections raised to powers for solving systems of equations of syndromes to compute symbol position indices in the range of the field (e.g., GF(256)). Further, the check matrix includes rows of all-ones for computing parity of the corresponding sections of the codeword in order to determine in which sections of the received vector the computed symbol position indices apply (i.e., whether an offset is applied to the computed symbol position index to correct a bit located in a corresponding section of the received vector associated with said offset). For example, the first 256 positions do not have an offset, while the last 23 positions are offset by 256.

[0130] The decoding algorithm for the check matrix of FIG. 20 is similar to that of FIG. 14, especially in regard to the zero-, one-, and two-error cases. The error case logic circuit is configured to determine the three-error case, and specifically which section each error occurs in. Assume that the syndrome vector S is [SO, Sl[7:0], S3[7:0], S5[7:0], S6, and S7[4:0, 0 0 0]], where:50 and S6 are single-bit parity syndromes for the first and second sections of the received codeword;51 and S7 are the first-order multi-bit syndromes associated with the first and second sections, respectively;S3 is a third-order multi-bit syndrome; andS5 is a fifth-order multi-bit syndrome.

[0131] For example, SO = 1 may indicate that either one or three errors have occurred in the first section of the received codeword vector. If S is a column of the matrix H, then one error has occurred. However, if S is not a column of the matrix H, then we may assume that we have three errors in the same section (assuming the single bit parity syndrome S6 = 0, indicating noKDU-01008W001 errors in the correctable range). If all three errors occur in the same section, the error locator evaluation circuit evaluates the error locator polynomial A3X3+ A2X2+ AiX +A0 = 0 for each symbol position evaluation. In some embodiments, the evaluation includes evaluating the polynomial for “X” = “a” from z = 0 to 255. Each a, may known from the check matrix, as well as the third-powers at3. However, as previously described, the squared elements a;2may be computed.

[0132] In some embodiments, calculating the error locator polynomial coefficients for the error locator polynomial A3X3+ A2X2+ AiX +A0 = 0 from the syndromes is the same as previously described:A3 = si9+ S5*sl4+ S5*S3*sl + S33A2= si10+ S5*sl5+ S5*S3*sl2+ S33*slAi = S3*sls+ S5*sls+ S32*sl5+ S33*sl2+ S52*sl + S5*S32Ao = si12+ S32*sls+ SS2*slz+ S34

[0133] Where ‘+’ represents a bitwise XOR. Further, it should be noted that the “si” first-order multi-bit syndrome in the above equations corresponds to the first-order multi-bit syndrome of the identified section containing the three errors. For example, if the three errors are in the first section, then “SI” is substituted in for “si” in the above equations. If the three errors are in the second section, then “S7” is substituted in for “si” in the above equations. Once the coefficients are obtained then the root-finding combinatorial logic is configured to solve the cubic equation utilizing the process described above.

[0134] Another possibility for three errors is for two errors to be in one section and one error to be in the remaining section. If SO = 0, S6 = 1, and SI 0, then the error case logic circuit may determine that two errors occurred in the first section of the received codeword while the third error occurred in the second section of the received codeword. The algorithm may solve for one of the error positions being S7+256. Combinatorial logic may then be utilized to factor out the value of “S7” from the third-order multi-bit syndrome S3 to generate an intermediate third-order multi -bit syndrome S3’. In such a scenario, S3’ may be used in place of S3 to generate the coefficients of the error locator polynomial, which may subsequently be evaluated for each codeword position to identify the remaining to error positions. A similar logic may be utilized if one error is in the first section and the remaining two errors are in the second section.KDU-01008W001

[0135] FIG. 21 is a diagram of a check matrix for a four-error correcting code, in accordance with some embodiments. As shown, the check matrix is similar to the three-error correcting check matrix of FIG. 20, with the addition of a set of rows associated with the sequential column indices raised to the seventh power for formulation of a seventh-order multi-bit syndrome. In the combinatorial decoding logic, the zero-, one-, two-, and three-error cases remain similar. The four error case may be determined by analysis of the single-bit parity syndromes. Assume that the syndrome vector S is [SO, Sl[7:0], S3[7:0], S5[7:0], S7[7:0], S8, and S9[4:0, 0 0 0]], where:50 and S8 are single-bit parity syndromes for the first and second sections of the received codeword;51 and S9 are the first-order multi-bit syndromes associated with the first and second sections, respectively;S3 is a third-order multi-bit syndrome;S5 is a fifth-order multi-bit syndrome; andS7 is a seventh-order multi-bit syndrome.

[0136] If SO and S8 are both zero but the corresponding first-order multi -bit syndromes SI and S9 are non-zero, the error case logic circuit may determine that four errors occurred; two in each of the first and second sections. In such a scenario, an intermediate third-order multi-bit syndrome may be generated for each of the first and second sections by cubing SI and S9, respectively. Respective quadratic error locator polynomials may be generated for each section, and independently evaluated over the range of indices to find the roots. The error positions may then correspond to roots of each quadratic error locator polynomial offset by the constant associated with respective section.

[0137] Another four-error scenario is when a first section contains three errors and a second section contains one error. In such a scenario, the error position for the section having one error may be determined directly from the first-order multi-bit syndrome associated with the second section. Like above, the first error position may be factored out of the third- and fifth-order multi -bit syndromes to generate S3’ and S5’, after which the cubic error locator polynomial equation A3X3+ A2X2+ AiX +A0 = 0 may be determined using S3’ and S5’, and subsequently evaluated to find the roots.

[0138] Another four-error scenario occurs when all four errors occur in the same section. In such a scenario, the first-, third-, fifth-, and seventh-order multi -bit syndromes may be provided to an error locator polynomial evaluation circuit to determine the roots of the error locatorKDU-01008W001 polynomial as previously described. Subsequently the four roots are utilized to find the four error positions.

[0139] Given the quartic error locator polynomial (already normalized):A3i42 9A4J4Q x4+ — x3+ — x2+ — x + — = 0A4A4A4A4

[0140] The coefficients may be computed from the syndromes as follows:A4= si’6+ S7*sl9+ S5*S3*sl8+ (S34+ S7*S5)*sl4+ (S35+ S7*S5*S3 + S53)*sl + (S7*S33+ S52*S32)

[0141] Combinatorial logic is configured to compute the above coefficient using combinations of the multiplication, square, and cubic combinatorial logic circuits previously described. As previously described, the combinatorial logic for generating the coefficients of the error locator polynomial may include logic to (i) select the correct “si” term. To reiterate, the “si” term corresponds to the first-order multi-bit syndrome associated with the section of the received codeword identified as having four errors. Specifically in the code above, “SI” is substituted in for “si” if the errors are in the first section and “S9” is substituted in for “si” if the errors are in the second section. The coefficients of the error locator polynomial are provided to the error locator evaluation circuit to evaluate the error locator polynomial at each at in parallel to identify the roots, and subsequently the error positions of the bits containing errors in the codeword.

[0142] A check matrix such as FIG. 15 having three sections may also be expanded to include three and four error correction by adding rows associated with fifth- and seventh-power multibit syndromes as well. Similar principles above may be used to determine sections of the received codeword vector having errors and subsequent error position calculation.

[0143] FIG. 22 is a block diagram of an FEC decoder, in accordance with some embodiments. Specifically, FIG. 22 is associated with the codes described above having lengths that extend beyond the field GF(2n) used for computation. As shown, the error case selection logic implements the logic described above, such as (but not limited to) the algorithms for theKDU-01008W001(544,512) code described in FIGs. 16-19. Further, the error case selection logic may be configured to identify the following scenarios in a four-error correcting code:One error caseTwo error cases: o Both in same section o Errors in different sectionsThree Error cases: o All three in same section o Two in first section and one in second section■ Directly identify the errors in second section, factor both out of the third- order syndrome to create intermediate third-order syndrome -> use first- order and intermediate third order syndromes to compute the coefficients of a quadratic error locator polynomial and evaluate using section-specific evaluation circuit o All three in different sections- Four Error Cases: o All four in one section o Three in first section, one in second section■ Directly identify the error in the section, and factor it out of the third and fifth order syndromes to create intermediate syndromes-> use intermediate syndromes to compute coefficients of cubic error locator polynomial and evaluate with section-specific evaluation circuit. o Two in first section, two in second section■ Create two quadratic error locator polynomials and evaluate each independently using respective section-specific evaluation circuits. o Two in first section, one in second section, one in third section■ Directly identify the errors in second and third sections, factor both out of the third-order syndrome to create intermediate third-order syndrome -> use first-order and intermediate third order syndromes to compute the coefficients of a quadratic error locator polynomial and evaluate using section-specific evaluation circuit o All four errors in different sections

[0144] The complexity of the error case selection logic depends on factors such as (i) the number of correctable errors in the code, and (ii) the number of codeword sections. The errorKDU-01008W001 case selection logic is configured to use the single-bit parity syndromes, at least in part, to identify the above error cases. From there, the error case selection logic is configured to create any intermediate syndromes, and to provide the coefficients of any error locator polynomial(s) to the parallel evaluation circuits. In some embodiments, as in the case of the (544,512) code, at most one section will contain two errors. Thus, a single group of 256 parallel evaluation circuits may be utilized, wherein the syndromes used to calculate the error locator polynomial are associated with the section determined to have the errors. Thus, the same group of 256 circuits may be utilized to find the two errors, no matter which section the errors occur in. The roots of the error locator polynomial correspond to position indices of errors within the determined section, and thus the correction may be applied by flipping bits within the determined section as determined by the position indices. In some embodiments, the position index within the section may be referred to as a “local position index”, and in some cases a fixed offset associated with the determined section may be applied to each “local position index” to determine a “global position index”, which is a unique value associated with the entirety of the received set of data.

[0145] For higher error-correcting codes, e.g., four-error correcting, it may be the case that two errors occur in a first section and two errors occur in a second section. For such a code, multiple groups of parallel evaluation circuits may be utilized, as shown in FIG. 22. In FIG. 22, each group of parallel evaluation circuits may be utilized in parallel to solve for the error positions within each section having two (or more) errors. Once the error positions within each section of the codeword are identified, an error mask applicator is configured to correct the single biterrors in the received vector to recover the original message M.

[0146] FIG. 23 is a flowchart of a method 2300, in accordance with some embodiments. As shown, method 2300 includes receiving 2305 bits of a forward error correction, FEC, codeword at a syndrome computing logic circuit, the bits of the FEC codeword comprising data bits and redundancy bits. The method 2300 further includes applying 23150 a check matrix to the bits of the FEC codeword to generate a set of syndromes, the set of syndromes comprising (i) single-bit parity syndromes generated by respective logical bitwise-XORs of bits in respective sections of the FEC codeword and (ii) multi-bit syndromes having values from a finite field, the multi-bit syndromes comprising first-order syndromes each associated with respective sections of the FEC codeword and representing logical XORs of column indices, and (iii) at least one higher-order syndrome representing logical XORs of the column indices raised to a higher power. The method 2300 further includes determining 2315, using an error case selection logic circuit, two errors occurred in the received bits of the FEC codeword, and furtherKDU-01008W001 determining the two errors occur in a same section of the received FEC codeword. The method further includes generating 2320, using an error correction logic circuit, corresponding error positions for each error based on (i) the first-order syndrome associated with the same section of the received FEC codeword and (ii) the higher-order syndrome. The method 2300 further includes correcting 2325, using the error correction logic further each data bit of the FEC codeword having an error in the corresponding error position.

[0147] In some embodiments, the check matrix comprises a plurality of sections, each section of the check matrix associated with a respective section of the FEC codeword, each section of the check matrix comprising (i) a parity row, (ii) columns having sequential integer indices represented by binary expansions, and (iii) columns corresponding to the sequential integer indices raised to an odd power greater than 1.

[0148] In some embodiments, generating the corresponding error positions comprises generating, using a coefficient logic circuit, coefficients of an error locator polynomial from the first-order syndrome associated with the same section of the received FEC codeword and the higher-order syndrome. In some embodiments, the method includes applying the coefficients of the error locator polynomial to a root finding combinatorial logic circuit to find roots of the error locator polynomial. In some embodiments, the roots of the error locator polynomial correspond to column indices within the determined same section, and determining the corresponding error positions includes applying an offset to the column indices, the offset determined based on the determined same section of the received codeword. In some embodiments, determining the roots of the error locator polynomial includes solving, using a quadratic-solving circuit, the error locator polynomial. In some embodiments, finding the roots of the error locator polynomial includes performing combinatorial operations in the finite field.

Claims

KDU-01008W001CLAIMS:

1. An apparatus comprising: a syndrome computing logic circuit configured to receive bits of a forward error correction, FEC, codeword, the bits comprising data bits and redundancy bits, and to responsively apply a check matrix to the bits of the FEC codeword to generate a set of syndromes, the set of syndromes comprising (i) single-bit parity syndromes generated by respective logical bitwise-XORs of bits in respective sections of the FEC codeword and (ii) multi-bit syndromes having values from a finite field, the multi-bit syndromes comprising first-order syndromes each associated with respective sections of the FEC codeword and representing logical XORs of column indices, and (iii) at least one higher-order syndrome representing logical XORs of the column indices raised to a higher power; an error case selection logic circuit configured to determine two errors occurred in the received bits of the FEC codeword, and further configured to determine the two errors occur in a same section of the received FEC codeword; and an error correction logic circuit configured to generate corresponding error positions for each error based on (i) the first-order syndrome associated with the same section of the received FEC codeword and (ii) the higher-order syndrome, the error correction logic further configured to correct each data bit of the FEC codeword having an error in the corresponding error position.

2. The apparatus of claim 1, wherein the check matrix comprises a plurality of sections, each section of the check matrix associated with a respective section of the FEC codeword, each section of the check matrix comprising (i) a parity row, (ii) columns having sequential integer indices represented by binary expansions, and (iii) columns corresponding to the sequential integer indices raised to an odd power greater than 1.

3. The apparatus of claim 1, wherein the error correction logic circuit comprises a coefficient logic circuit configured to generate coefficients of an error locator polynomial from the first-order syndrome associated with the same section of the received FEC codeword and the higher-order syndrome.KDU-01008W0014. The apparatus of claim 3, wherein the error correction logic circuit further comprises a root finding combinatorial logic circuit, the coefficient logic circuit configured to apply the coefficients of the error locator polynomial to the root finding combinatorial logic circuit, to find roots of the error locator polynomial.

5. The apparatus of claim 4, wherein the roots of the error locator polynomial correspond to column indices within the determined same section, and wherein the error correction logic is configured to determine the error positions by applying an offset to the column indices based on the determined same section of the received codeword.

6. The apparatus of claim 4, wherein the root finding combinatorial logic circuit comprises a combinatorial quadratic-solving circuit configured to generate the roots from the coefficients.

7. The apparatus of claim 3, wherein the coefficient logic circuit and the root finding combinatorial logic circuit are configured to perform combinatorial operations in the finite field.

8. The apparatus of claim 1, wherein the data bits comprise 256 data bits and 23 redundancy bits, and wherein the error case selection circuit is configured to determine up to two errors occurred; OR the data bits comprise 512 data bits and 32 redundancy bits, and the error case selection circuit is configured to determine up to two errors occurred; OR the data bits comprise 256 data bits and 31 redundancy bits, and the error case selection circuit is configured to determine up to three errors occurred; OR the data bits comprise 256 data bits and 39 redundancy bits, and the error case selection circuit is configured to determine up to four errors occurred.

9. A method comprising: receiving bits of a forward error correction, FEC, codeword at a syndrome computing logic circuit, the bits of the FEC codeword comprising data bits and redundancy bits; applying a check matrix to the bits of the FEC codeword to generate a set of syndromes, the set of syndromes comprising (i) single-bit parity syndromes generated byKDU-01008W001 respective logical bitwise-XORs of bits in respective sections of the FEC codeword and (ii) multi-bit syndromes having values from a finite field, the multi-bit syndromes comprising first-order syndromes each associated with respective sections of the FEC codeword and representing logical XORs of column indices, and (iii) at least one higher-order syndrome representing logical XORs of the column indices raised to a higher power; determining, using an error case selection logic circuit, two errors occurred in the received bits of the FEC codeword, and further determining the two errors occur in a same section of the received FEC codeword; and generating, using an error correction logic circuit, corresponding error positions for each error based on (i) the first-order syndrome associated with the same section of the received FEC codeword and (ii) the higher-order syndrome; and correcting, using the error correction logic further each data bit of the FEC codeword having an error in the corresponding error position.

10. The method of claim 9, wherein the check matrix comprises a plurality of sections, each section of the check matrix associated with a respective section of the FEC codeword, each section of the check matrix comprising (i) a parity row, (ii) columns having sequential integer indices represented by binary expansions, and (iii) columns corresponding to the sequential integer indices raised to an odd power greater than 1.

11. The method of claim 9, wherein generating the corresponding error positions comprises generating, using a coefficient logic circuit, coefficients of an error locator polynomial from the first-order syndrome associated with the same section of the received FEC codeword and the higher-order syndrome.

12. The method of claim 11, further comprising applying the coefficients of the error locator polynomial to a root finding combinatorial logic circuit to find roots of the error locator polynomial.

13. The apparatus of claim 12, wherein the roots of the error locator polynomial correspond to column indices within the determined same section, and wherein determining the corresponding error positions comprises applying an offset to the column indices, the offset determined based on the determined same section of the received codeword.KDU-01008W00114. The apparatus of claim 12, finding the roots of the error locator polynomial comprises solving, using a quadratic-solving circuit, the error locator polynomial.

15. The method of claim 12, wherein finding the roots of the error locator polynomial comprises performing combinatorial operations in the finite field.

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