Light-emitting device and manufacturing method therefor, and display apparatus

Abstract

A light-emitting device and a manufacturing method therefor, and a display apparatus. The light-emitting device comprises: a base substrate (1), and a first electrode (2), a first carrier transport layer (3), a light-emitting layer (4), a second carrier transport layer (5) and a second electrode (6), which are stacked on the base substrate (1), wherein the first electrode (2) comprises a plurality of first through holes (H1) arranged at intervals. The light-emitting device further comprises: gate electrodes (7), which are respectively located in the first through holes (H1) and each have one end at least extending into the first carrier transport layer (3), and a first insulating layer (81), which is located between at least part of side walls of the gate electrodes (7) and side walls of the first through holes (H1) and covers part of the surfaces of the gate electrodes (7), wherein the first insulating layer (81) is configured to insulate the gate electrodes (7) from the first electrode (2), the first insulating layer (81) is further configured to at least insulate the gate electrodes (7) from the first carrier transport layer (3), and the gate electrodes (7) are configured to load a preset voltage during the operation of the light-emitting device, which preset voltage is smaller than a voltage loaded onto the first electrode (2) and is smaller than a voltage loaded onto the second electrode (6).

Description

A light-emitting device and its manufacturing method, and a display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a light-emitting device, its manufacturing method, and a display apparatus. Background Technology

[0002] Quantum dots (QDs) are excellent nanomaterials for emitting light, possessing advantages such as high quantum yield, narrow emission peaks, tunable emission spectra, and high photochemical stability. Therefore, quantum dot light-emitting diodes (QLEDs), a new generation of light-emitting devices using QDs as the emitting layer, have attracted widespread attention from academia and industry due to their self-emissive nature, low power consumption, and wide color gamut.

[0003] Currently, QLED devices generally suffer from low luminous efficiency, one important factor being the imbalance between the transport of holes and electrons within the light-emitting device. Therefore, improving the balance of electron-hole transport in light-emitting devices is a problem that urgently needs to be solved in this field.

[0004] Summary of the Invention

[0005] This disclosure provides a light-emitting device, a method for manufacturing the same, and a display device, the specific solutions of which are as follows:

[0006] This disclosure provides a light-emitting device comprising: a substrate, and a first electrode, a first carrier transport layer, a light-emitting layer, a second carrier transport layer, and a second electrode stacked on the substrate; the first electrode includes a plurality of spaced-apart first through-holes;

[0007] It also includes: a gate electrode located within the first via and extending at least one end into the first carrier transport layer, and a first insulating layer located between at least a portion of the sidewall of the gate electrode and the sidewall of the first via and covering the surface of each portion of the gate electrode; wherein the first insulating layer is configured to insulate the gate electrode from the first electrode, and the first insulating layer is further configured to insulate at least the gate electrode from the first carrier transport layer, and the gate electrode is configured to be loaded with a preset voltage when the light-emitting device is operating, the preset voltage being less than the voltage loaded on the first electrode and less than the voltage loaded on the second electrode.

[0008] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the first insulating layer conformally covers at least a portion of the surface of the gate electrode.

[0009] In one possible implementation, the light-emitting device provided in the embodiments of this disclosure further includes a second insulating layer located between the first electrode and the substrate, wherein the first insulating layer and the second insulating layer are an integral structure.

[0010] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, one end of the gate electrode extends into the first carrier transport layer.

[0011] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the overall structure of the gate electrode and the first insulating layer is a first structure, and the thickness of the first structure within the first carrier transport layer is less than the thickness of the first carrier transport layer.

[0012] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the thickness of the first structure within the first carrier transport layer is greater than half the thickness of the first carrier transport layer.

[0013] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, one end of the gate electrode extends into the second carrier transport layer.

[0014] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the overall structure of the gate electrode and the first insulating layer is a first structure, and the thickness of the first structure within the second carrier transport layer is less than the thickness of the second carrier transport layer.

[0015] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the thickness of the first structure within the second carrier transport layer is greater than half the thickness of the second carrier transport layer.

[0016] In one possible implementation, the light-emitting device provided in the embodiments of this disclosure further includes: a buffer layer located between the substrate and the second insulating layer, and a conductive connection layer located between the substrate and the buffer layer;

[0017] The buffer layer includes second through holes that correspond one-to-one with the first through holes, and the other end of each gate electrode extends through the second through hole to be electrically connected to the conductive connection layer.

[0018] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the orthographic projection shape of the second through-hole on the substrate is the same as the orthographic projection shape of the first through-hole on the substrate.

[0019] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the orthogonal projection shape of the first through hole on the substrate is circular or square.

[0020] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, a plurality of the first through holes are arranged in an array.

[0021] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the orthographic projection shape of the first through-hole on the substrate is a strip.

[0022] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the extension direction of the first through hole is a first direction, and a plurality of the first through holes are arranged at equal intervals along a second direction, wherein the second direction is perpendicular to the first direction.

[0023] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the first electrode is an anode, the second electrode is a cathode, the first carrier transport layer is a hole transport layer, and the second carrier transport layer is an electron transport layer.

[0024] The light-emitting device further includes a hole injection layer located between the first electrode and the first carrier transport layer, wherein the orthographic projection of the hole injection layer on the substrate does not overlap with the orthographic projection of the first via on the substrate.

[0025] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the first electrode is a cathode, the second electrode is an anode, the first carrier transport layer is an electron transport layer, and the second carrier transport layer is a hole transport layer.

[0026] The light-emitting device further includes a hole injection layer located between the second electrode and the second carrier transport layer.

[0027] In one possible implementation, in the light-emitting device provided in the embodiments of this disclosure, the material of the hole transport layer includes a cross-linked network structure.

[0028] Accordingly, this disclosure also provides a display device, including the light-emitting device described above in this disclosure.

[0029] Accordingly, this disclosure also provides a method for manufacturing a light-emitting device, used to manufacture the light-emitting device provided in this disclosure, the method comprising:

[0030] Multiple gate electrodes are formed at intervals on one side of the substrate.

[0031] A first insulating layer is formed covering the surface of each of the gate electrode portions;

[0032] A first electrode is formed between the first insulating layers between each of the gate electrodes, the first electrode including a plurality of first through holes for embedding each of the gate electrodes and the corresponding first insulating layers;

[0033] A first carrier transport layer is formed on the side of the first electrode away from the substrate, and the end of the gate electrode away from the substrate extends at least into the first carrier transport layer.

[0034] A light-emitting layer is formed on the side of the first carrier transport layer away from the substrate.

[0035] A second carrier transport layer is formed on the side of the light-emitting layer opposite to the substrate.

[0036] A second electrode is formed on the side of the second carrier transport layer opposite to the substrate.

[0037] In one possible implementation, the fabrication method provided in this embodiment includes forming a plurality of spaced-apart gate electrodes on one side of a substrate, specifically comprising:

[0038] A buffer layer is formed on one side of the substrate, the buffer layer including second through holes that correspond one-to-one with the first through holes;

[0039] A thin film of gate electrode material is formed on the side of the buffer layer opposite to the substrate.

[0040] The gate electrode material film is patterned to form a gate electrode located in each of the second vias, the height of which is greater than the height of the buffer layer.

[0041] In one possible implementation, the manufacturing method provided in the embodiments of this disclosure further includes, before forming the buffer layer:

[0042] A conductive connection layer is formed on one side of the substrate, and the end of each gate electrode facing the substrate is electrically connected to the conductive connection layer.

[0043] In one possible implementation, the fabrication method provided in the embodiments of this disclosure further includes, when forming the first insulating layer covering the surface of each of the gate electrode portions, forming a second insulating layer located between the first electrode and the substrate and integrally formed with the first insulating layer.

[0044] In one possible implementation, the fabrication method provided in this embodiment of the present disclosure, wherein a first electrode is formed between the first insulating layers between each of the gate electrodes, specifically includes:

[0045] A photoresist layer is formed on the side of the first insulating layer and the second insulating layer away from the substrate.

[0046] The photoresist layer is patterned to form a photoresist pattern covering the top surface and part of the side surfaces of the overall structure of the gate electrode and the first insulating layer.

[0047] A first conductive material thin film is formed on the side of the photoresist pattern facing away from the substrate.

[0048] The photoresist pattern is peeled off to form the first electrode. Attached Figure Description

[0049] Figure 1 is a schematic diagram of the structure of a light-emitting device provided in an embodiment of this disclosure;

[0050] Figure 2 is a schematic diagram of the structure of hole carriers induced in the hole transport layer when the light-emitting device shown in Figure 1 is working.

[0051] Figure 3 is a magnified view of a portion of Figure 2;

[0052] Figure 4 is a schematic diagram of the structure of another light-emitting device provided in an embodiment of this disclosure;

[0053] Figure 5 is a schematic diagram of the structure of the light-emitting device shown in Figure 4 when it is working;

[0054] Figure 6 is a magnified view of a portion of Figure 5;

[0055] Figure 7 is a top view of a MOS capacitor structure provided in an embodiment of this disclosure;

[0056] Figure 8 is a top view of another MOS capacitor structure provided in an embodiment of this disclosure;

[0057] Figure 9 is a schematic diagram of the structure of another light-emitting device provided in an embodiment of this disclosure;

[0058] Figure 10 is a schematic diagram of another light-emitting device provided in an embodiment of this disclosure;

[0059] Figure 11 is a schematic flowchart of a method for fabricating a light-emitting device according to an embodiment of this disclosure;

[0060] Figure 12A is a schematic diagram of the structure of the light-emitting device provided in the embodiment of this disclosure during the manufacturing process;

[0061] Figure 12B is another structural schematic diagram of the light-emitting device provided in the embodiments of this disclosure during the manufacturing process;

[0062] Figure 12C is another structural schematic diagram of the light-emitting device provided in the embodiments of this disclosure during the manufacturing process;

[0063] Figure 12D is another structural schematic diagram of the light-emitting device provided in the embodiment of this disclosure during the manufacturing process;

[0064] Figure 12E is another structural schematic diagram of the light-emitting device provided in the embodiment of this disclosure during the manufacturing process;

[0065] Figure 12F is another structural schematic diagram of the light-emitting device provided in the embodiment of this disclosure during the manufacturing process;

[0066] Figure 12G is another structural schematic diagram of the light-emitting device provided in the embodiment of this disclosure during the manufacturing process;

[0067] Figure 12H is another structural schematic diagram of the light-emitting device provided in the embodiment of this disclosure during the manufacturing process;

[0068] Figure 12I is another structural schematic diagram of the light-emitting device provided in the embodiment of this disclosure during the manufacturing process;

[0069] Figure 12J is another structural schematic diagram of the light-emitting device provided in the embodiment of this disclosure during the manufacturing process;

[0070] Figure 12K is another structural schematic diagram of the light-emitting device provided in the embodiment of this disclosure during the manufacturing process;

[0071] Figure 12L is another structural schematic diagram of the light-emitting device provided in the embodiment of this disclosure during the manufacturing process;

[0072] Figure 13 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0074] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "comprising" or "including," and similar terms as used in this disclosure, mean that an element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0075] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0076] Currently, due to limitations in manufacturing processes and materials, QLED light-emitting devices suffer from a serious problem: electron transport efficiency exceeds hole transport efficiency, meaning there is an imbalance between electron and hole transport. This results in low efficiency for the light-emitting devices.

[0077] To improve the electron-hole transport balance in QLED light-emitting devices, this disclosure provides a light-emitting device, as shown in FIG1, including: a substrate 1, and a first electrode 2, a first carrier transport layer 3, a light-emitting layer 4, a second carrier transport layer 5, and a second electrode 6 stacked on the substrate 1; the first electrode 2 includes a plurality of spaced first through holes H1.

[0078] It also includes: a gate electrode 7 located within the first through-hole H1 and extending at least one end into the first carrier transport layer 3, and a first insulating layer 81 located between at least a portion of the sidewall of the gate electrode 7 and the sidewall of the first through-hole H1 and covering a portion of the surface of each gate electrode 7; wherein the first insulating layer 81 is configured to insulate the gate electrode 7 from the first electrode 2, and the first insulating layer 81 is also configured to insulate at least the gate electrode 7 from the first carrier transport layer 3, and the gate electrode 7 is configured to be loaded with a preset voltage when the light-emitting device is operating, the preset voltage being less than the voltage loaded on the first electrode 2 and less than the voltage loaded on the second electrode 6.

[0079] The light-emitting device provided in this embodiment embeds a gate electrode and a first insulating layer within at least the first carrier transport layer. The gate electrode, the first insulating layer, and the first carrier transport layer form a MOS (metal-oxide-semiconductor field-effect transistor) capacitor structure perpendicular to the surface of the first electrode. This MOS capacitor structure allows control of the charge distribution in the semiconductor base (i.e., the first carrier transport layer) by changing the gate electrode voltage, thereby achieving current control. Since the preset voltage applied to the gate electrode during operation is less than the voltage applied to the first electrode and less than the voltage applied to the second electrode, the lateral electric field of the MOS capacitor structure can be used to induce free hole carriers in the first carrier transport layer (e.g., a hole transport layer), improving the conductivity of the hole transport layer, or depleting the electron carriers in the first carrier transport layer (e.g., an electron transport layer), reducing the electron concentration, and making the electron-hole transport of the light-emitting device more balanced, thereby improving the efficiency of the light-emitting device.

[0080] In some embodiments, as shown in FIG1, the material of the gate electrode 7 in the above-described light-emitting device provided in the present disclosure can be a transparent conductive material such as heavily doped polycrystalline silicon, ITO or AZO, or a metallic conductive material such as gold, aluminum, molybdenum, nickel, tungsten, titanium, etc.

[0081] In some embodiments, as shown in FIG1, the material of the first insulating layer 81 in the above-described light-emitting device provided in the present disclosure can be a high dielectric constant insulating material such as silicon oxide, silicon nitride, or hafnium oxide.

[0082] In some embodiments, in the light-emitting device provided in the present disclosure, as shown in FIG1, the first electrode 2 can be an anode, the second electrode 6 can be a cathode, the first carrier transport layer 3 can be a hole transport layer (HT), and the second carrier transport layer 5 can be an electron transport layer (ET), that is, the light-emitting device shown in FIG1 is an upright structure; wherein, the hole transport layer is used to transport holes in the anode to the light-emitting layer 4, and the electron transport layer is used to transport electrons in the cathode to the light-emitting layer 4, and electrons and holes recombine to emit light in the light-emitting layer 4.

[0083] In some embodiments, as shown in FIG1, one end of the gate electrode 7 can extend into the first carrier transport layer 3 (hole transport layer), i.e., the MOS capacitor structure is embedded in the hole transport layer. When the light-emitting device is working, the anode is generally loaded with a positive voltage, and the cathode is generally at zero potential. Therefore, a negative voltage can be loaded onto the gate electrode 7 at the same time, inducing the accumulation of a large number of free hole carriers in the hole transport layer of the light-emitting device, improving the conductivity of the hole transport layer, and thus improving the electron-hole transport balance.

[0084] In some embodiments, in the light-emitting device provided in the present disclosure, as shown in FIG1, the overall structure of the gate electrode 7 and the first insulating layer 81 is taken as the first structure A. The thickness D1 of the first structure A within the first carrier transport layer 3 (hole transport layer) can be less than the thickness D2 of the first carrier transport layer 3 (hole transport layer). In this way, the first carrier transport layer 3 (hole transport layer) is an overall planar structure, which does not affect the performance of the first carrier transport layer 3 (hole transport layer).

[0085] In some embodiments, as shown in FIG1, in the light-emitting device provided in the present disclosure, the thickness D1 of the first structure A within the first carrier transport layer 3 is greater than half the thickness D2 of the first carrier transport layer 3. This is beneficial for the MOS capacitor structure to induce a large number of free hole carriers within the first carrier transport layer 3.

[0086] Optionally, as shown in Figure 1, the first structure A can also penetrate the first carrier transport layer 3, and the thickness D1 of the first structure A within the first carrier transport layer 3 can also be less than or equal to half the thickness D2 of the first carrier transport layer 3.

[0087] Specifically, as shown in Figures 1-3, Figure 2 is a schematic diagram of the structure inducing hole carriers in the hole transport layer when the light-emitting device shown in Figure 1 is working, and Figure 3 is a partially enlarged schematic diagram of Figure 2. In this embodiment, by embedding the gate electrode 7 and the first insulating layer 81 in the hole transport layer, a MOS capacitor structure composed of the gate electrode 7, the first insulating layer 81, and the hole transport layer can be formed. When the light-emitting device is working, the anode is generally loaded with a positive voltage (e.g., 5V), and the cathode is generally at zero potential. Since the preset voltage loaded on the gate electrode 7 is less than the voltage loaded on the first electrode 2 (anode) and less than the voltage loaded on the second electrode 2 (anode), the voltage is calculated based on the voltage applied to the gate electrode 7. The voltage on the second electrode 6 (cathode), for example, the preset voltage applied to the gate electrode 7 is a negative voltage (e.g., -5V), while the voltage on the first carrier transport layer 3 (hole transport layer) is equivalent to a positive voltage. Therefore, a transverse electric field E is formed in the first insulating layer 81 in the above-mentioned MOS capacitor structure. This transverse electric field E induces hole carriers (+) in the first carrier transport layer 3 (hole transport layer). These hole carriers (+) can improve the conductivity of the hole transport layer. The hole carriers (+) are transported longitudinally under the action of the longitudinal electric field of the light-emitting device, thereby improving the electron-hole transport balance.

[0088] In some embodiments, as shown in FIG1 and FIG2, in order to reduce the potential barrier between the first electrode 2 (anode) and the first carrier transport layer 3 (hole transport layer) and improve the hole transport rate, the light-emitting device further includes a hole injection layer 9 located between the first electrode 2 and the first carrier transport layer 3. Since the hole carrier concentration of the hole injection layer 9 is high, it will shield the transverse electric field E in the MOS capacitor structure to a certain extent, thereby weakening the ability of the transverse electric field E to induce the hole transport layer to generate hole carriers. Therefore, in the embodiments of the present disclosure, the orthographic projection of the hole injection layer 9 on the substrate 1 does not overlap with the orthographic projection of the first via H1 on the substrate 1.

[0089] In some embodiments, in the light-emitting device provided in the present disclosure, as shown in FIG1, the first insulating layer 81 can conformally cover at least part of the surface of the gate electrode 7. In this way, when the first insulating layer 81 is fabricated, the first insulating layer 81 can be made thinner, which can increase the electric field strength in the first insulating layer 81 in the MOS capacitor structure formed by the gate electrode 7, the first insulating layer 81 and the first carrier transport layer 3. This is beneficial to induce a large number of free hole carriers in the first carrier transport layer 3 (e.g., a hole transport layer) or to deplete a large number of electron carriers in the first carrier transport layer 3 (e.g., an electron transport layer).

[0090] In some embodiments, as shown in FIG1, the light-emitting device provided in the present disclosure further includes a second insulating layer 82 located between the first electrode 2 and the substrate 1. The first insulating layer 81 and the second insulating layer 82 are integral structures, so that the first insulating layer 81 and the second insulating layer 82 constitute an insulating layer. An insulating layer can be formed after the gate electrode 7 to insulate the gate electrode 7 from the first electrode 2 and the first carrier transport layer 3.

[0091] In some embodiments, in the light-emitting device provided in this disclosure, as shown in FIG4, one end of the gate electrode 7 can extend into the second carrier transport layer 5 (electron transport layer). Thus, the first insulating layer 81 insulates the gate electrode 7 from the first carrier transport layer 3 and from the second carrier transport layer 5. Specifically, when the light-emitting device is operating, as shown in FIG5 and FIG6, FIG5 is a schematic diagram of the structure of the light-emitting device shown in FIG4 during operation, and FIG6 is a partially enlarged schematic diagram of FIG5. The second electrode 6 (cathode) is at zero potential, the first electrode 2 (anode) is at positive potential, and the gate electrode 7 is at negative potential. The MOS capacitor structure with the gate electrode 7 at negative potential induces hole carriers in the first carrier transport layer 3 (hole transport layer), increasing the hole carrier concentration. The MOS capacitor structure with the gate electrode 7 at negative potential depletes electron carriers in the second carrier transport layer 5 (electron transport layer), reducing the electron carrier concentration, thereby making the electron-hole transport of the light-emitting device with more electrons more balanced.

[0092] Specifically, as shown in Figures 5 and 6, It represents the fixed positive charge left after the electron carriers are exhausted.

[0093] In some embodiments, in the light-emitting device provided in the present disclosure, as shown in FIG4, the overall structure of the gate electrode 7 and the first insulating layer 81 is the first structure A. The thickness D3 of the first structure A in the second carrier transport layer 5 (electron transport layer) is less than the thickness D4 of the second carrier transport layer 5 (electron transport layer). Thus, the second carrier transport layer 5 is an overall planar structure, which does not affect the performance of the second carrier transport layer 5.

[0094] In some embodiments, in the light-emitting device provided in the present disclosure, as shown in FIG4, the thickness D3 of the first structure A located in the second carrier transport layer 5 (electron transport layer) can be greater than half of the thickness D4 of the second carrier transport layer 5 (electron transport layer). This is beneficial for the MOS capacitor structure to deplete more electron carriers in the second carrier transport layer 5.

[0095] Optionally, as shown in Figure 4, the first structure A can also penetrate the second carrier transport layer 5, and the thickness D3 of the first structure A within the second carrier transport layer 5 can also be less than or equal to half the thickness D4 of the second carrier transport layer 5.

[0096] In some embodiments, the light-emitting device provided in the present disclosure, as shown in FIG1, FIG2, FIG4 and FIG5, further includes: a buffer layer 10 located between the substrate 1 and the second insulating layer 82, and a conductive connection layer 11 located between the substrate 1 and the buffer layer 10.

[0097] The buffer layer 10 includes second through holes H2 that correspond one-to-one with the first through holes H1. The other end of each gate electrode 7 extends through the second through holes H2 to be electrically connected to the conductive connection layer 11. In this way, the gate electrodes 7 can be interconnected, and a preset voltage can be applied to each gate electrode 7 through the conductive connection layer 11.

[0098] Optionally, the material of the conductive connection layer 11 can be Ni, Al, Mo, etc.

[0099] In some embodiments, in the light-emitting device provided in the present disclosure, as shown in FIG1, FIG2, FIG4 and FIG5, the orthographic projection shape of the second through hole H2 on the substrate 1 can be the same as the orthographic projection shape of the first through hole H1 on the substrate 1, so that the shapes of the MOS capacitor structures formed are also the same. For example, the MOS capacitor structure can be a cuboid structure or a cylindrical structure.

[0100] In some embodiments, in the light-emitting device provided in the present disclosure, as shown in FIG7, FIG7 is a top view of a portion of the film layers in FIG1 and FIG4, the orthogonal projection shape of the first through hole H1 on the substrate 1 is circular, and the MOS capacitor structure formed in this way is a cylindrical structure perpendicular to the surface of the first electrode 2.

[0101] Optionally, the orthogonal projection of the first via H1 onto the substrate 1 is square, thus forming a MOS capacitor structure that is a cubic prism structure perpendicular to the surface of the first electrode 2.

[0102] In some embodiments, as shown in FIG7, in the light-emitting device provided in the present disclosure, a plurality of first through holes H1 are arranged in an array, and the vertical MOS capacitor structure formed therein is periodically distributed throughout the first electrode 2, further enhancing the content of induced free hole carriers.

[0103] In some embodiments, in the light-emitting device provided in the present disclosure, as shown in FIG8, the orthogonal projection shape of the first through hole H1 on the substrate 1 is a strip shape, and the MOS capacitor structure formed in this way is a long strip-shaped cubic pillar structure perpendicular to the surface of the first electrode 2.

[0104] In some embodiments, in the light-emitting device provided in the present disclosure, as shown in FIG8, the extension direction of the first through hole H1 is the first direction X, and the plurality of first through holes H1 are arranged at equal intervals along the second direction Y. The second direction Y can be perpendicular to the first direction X. The vertical MOS capacitor structure formed in this way is evenly distributed throughout the entire first electrode 2, which can further enhance the content of induced free hole carriers.

[0105] It should be noted that in actual implementation, the first insulating layer 81 in Figures 7 and 8 should completely cover the gate electrode 7, that is, the gate electrode 7 is not visible in the top view. The gate electrode 7 is exposed in Figures 7 and 8 only to illustrate the shape of the first through hole H1.

[0106] Optionally, the orthographic projection shape of the first through hole H1 on the substrate 1 can also be other regular or irregular shapes, and this disclosure does not limit this.

[0107] In some embodiments, in the light-emitting device provided in the present disclosure, as shown in FIG1 and FIG4, the hole transport layer (first carrier transport layer 3) can be made of at least one of poly(9,9-dioctylfluorene-CO-N-(4-butylphenyl)diphenylamine) (TFB), polyN-vinylcarbazole (PVK), poly[bis(4-phenyl)(4-butylphenyl)amine] (Poly-TPD), NPD, and CBP, and the present disclosure does not limit it.

[0108] In some embodiments of the light-emitting device provided in this disclosure, as shown in Figures 1 and 4, the material of the hole transport layer (first carrier transport layer 3) may include a cross-linked network structure. Thus, in fabricating the light-emitting layer (quantum dot material), this disclosure allows the hole transport layer to be made of a cross-linkable material, and the quantum dot material to be made of a cross-linkable material. This allows the hole transport layer to act as a sacrificial layer in the fabrication of the light-emitting layer, preventing crosstalk caused by quantum dot residue. However, in the light-emitting device, after the hole transport layer is cross-linked, a large number of hole trap states are formed, trapping holes and significantly reducing the concentration of freely moving hole carriers. This reduces the conductivity of the hole transport layer and consequently lowers the EQE efficiency of the light-emitting device. This disclosure addresses this by introducing a vertical MOS capacitor array within the anode of the light-emitting device. This MOS capacitor structure induces the accumulation of hole carriers in the hole transport layer, increasing the concentration of free hole carriers, offsetting the holes trapped by the cross-linked trap levels, increasing the hole conduction current, and improving the electron-hole transport balance.

[0109] In some embodiments, as shown in FIG9 and FIG10, the first electrode 2 can be a cathode, the second electrode 6 can be an anode, the first carrier transport layer 3 can be an electron transport layer (ET), and the second carrier transport layer 5 can be a hole transport layer (HT). That is, the light-emitting device shown in FIG9 and FIG10 is an inverted structure. The light-emitting device also includes a hole injection layer 9 located between the second electrode 6 and the second carrier transport layer 5.

[0110] Specifically, as shown in Figure 9, one end of the gate electrode 7 extends into the first carrier transport layer 3 (electron transport layer), meaning the MOS capacitor structure is embedded in the electron transport layer. When the light-emitting device is working, the second electrode 6 (anode) is at a positive potential, the first electrode 2 (cathode) is at zero potential, and the gate electrode 7 is at a negative potential. The MOS capacitor structure with the gate electrode 7 at a negative potential depletes a large number of electron carriers in the electron transport layer, reducing the electron carrier concentration and thus making the electron-hole transport of the light-emitting device more balanced.

[0111] Specifically, as shown in Figure 10, one end of the gate electrode 7 extends into the second carrier transport layer 5 (hole transport layer). Thus, when the light-emitting device is working, the second electrode 6 (anode) is at a positive potential, the first electrode 2 (cathode) is at zero potential, and the gate electrode 7 is at a negative potential. The MOS capacitor structure with the gate electrode 7 at a negative potential in the first carrier transport layer 3 (electron transport layer) depletes the electron carriers, reducing the electron carrier concentration. The MOS capacitor structure with the gate electrode 7 at a negative potential induces hole carriers in the second carrier transport layer 5 (hole transport layer), increasing the hole carrier concentration, thereby making the electron-hole transport of the light-emitting device with more electrons more balanced.

[0112] In some embodiments, the light-emitting device provided in this disclosure can be a rigid substrate or a flexible substrate. The rigid substrate can be a glass substrate or a PMMA (polymethyl methacrylate) substrate, while the flexible substrate can be a PET (polyethylene terephthalate) substrate or a PI (polyimide) substrate.

[0113] In some embodiments, in the light-emitting device provided in the present disclosure, the anode material can be ITO / Ag / ITO, and the cathode material can be a semi-transparent reflective film layer of magnesium silver (Mg:Ag) alloy.

[0114] In some embodiments, the material of the hole injection layer in the light-emitting device provided in the embodiments of this disclosure can be PEDOT, NiOx, MoOx, WOx, V2O5, CuSCN, etc., and this disclosure does not limit it.

[0115] In some embodiments, the material of the electron transport layer in the light-emitting device provided in the present disclosure can be nanoparticles such as ZnO and ZnMgO, and the present disclosure does not limit this.

[0116] In some embodiments, in the light-emitting device provided in the present disclosure, the material of the light-emitting layer can be a quantum dot material. The quantum dot material can include a quantum dot body and a quantum dot ligand, and the coordinating groups in the quantum dot body and the quantum dot ligand are connected by chemical bonds.

[0117] Specifically, the quantum dot body can be a semiconductor nanocrystal and can have various shapes such as spherical, conical, multi-armed, and / or cubic nanoparticles, nanotubes, nanowires, nanofibers, nanoplate particles, quantum rods, or quantum sheets. Here, the quantum rod can be a quantum dot with an aspect ratio (length:width ratio) greater than about 1, for example, greater than or equal to about 2, greater than or equal to about 3, or greater than or equal to about 5. For example, the quantum rod can have an aspect ratio less than or equal to about 50, less than or equal to about 30, or less than or equal to about 20.

[0118] The quantum dot body may have, for example, a particle diameter of about 1 nm to about 100 nm, about 1 nm to about 80 nm, about 1 nm to about 50 nm, or about 1 nm to 20 nm (for non-spherical shapes, the average maximum particle length).

[0119] The band gap of a quantum dot can be controlled according to its size and composition, and thus the emission wavelength can be controlled. For example, as the size of the quantum dot increases, it can have a narrow band gap and thus be configured to emit light in a relatively long wavelength region, while as the size of the quantum dot decreases, it can have a wide band gap and thus be configured to emit light in a relatively short wavelength region. For example, the quantum dot can be configured to emit light in a predetermined wavelength region of the visible light region, depending on its size and / or composition. For example, the quantum dot can be configured to emit blue light, red light, or green light, and the blue light can have a peak emission wavelength (λmax) in, for example, from about 430 nm to about 480 nm, the red light can have a peak emission wavelength (λmax) in, for example, from about 600 nm to about 650 nm, and the green light can have a peak emission wavelength (λmax) in, for example, from about 520 nm to about 560 nm.

[0120] For example, the average particle size of the quantum dots configured to emit blue light may be, for example, less than or equal to about 4.5 nm, and for example, less than or equal to about 4.3 nm, less than or equal to about 4.2 nm, less than or equal to about 4.1 nm, or less than or equal to about 4.0 nm. Within this range, for example, the average particle size of the quantum dots may be from about 2.0 nm to about 4.5 nm, for example, from about 2.0 nm to about 4.3 nm, from about 2.0 nm to about 4.2 nm, from about 2.0 nm to about 4.1 nm, or from about 2.0 nm to about 4.0 nm.

[0121] The quantum dot body may have a quantum yield of, for example, greater than or equal to about 10%, greater than or equal to about 20%, greater than or equal to about 30%, greater than or equal to about 50%, greater than or equal to about 60%, greater than or equal to about 70%, or greater than or equal to about 90%.

[0122] The quantum dot body may have a relatively narrow half-width (FWHM). Here, FWHM is the width corresponding to half the wavelength of the peak absorption point, and when the FWHM is narrow, it can be configured to emit light in a narrower wavelength region and achieve higher color purity. The quantum dots may have a FWHM of, for example, less than or equal to about 50 nm, less than or equal to about 49 nm, less than or equal to about 48 nm, less than or equal to about 47 nm, less than or equal to about 46 nm, less than or equal to about 45 nm, less than or equal to about 44 nm, less than or equal to about 43 nm, less than or equal to about 42 nm, less than or equal to about 41 nm, less than or equal to about 40 nm, less than or equal to about 39 nm, less than or equal to about 38 nm, less than or equal to about 37 nm, less than or equal to about 36 nm, less than or equal to about 35 nm, less than or equal to about 34 nm, less than or equal to about 33 nm, less than or equal to about 32 nm, less than or equal to about 31 nm, less than or equal to about 30 nm, less than or equal to about 29 nm, or less than or equal to about 28 nm. Within the range, it may have, for example, an FWHM of about 2nm to about 49nm, about 2nm to about 48nm, about 2nm to about 47nm, about 2nm to about 46nm, about 2nm to about 45nm, about 2nm to about 44nm, about 2nm to about 43nm, about 2nm to about 42nm, about 2nm to about 41nm, about 2nm to about 40nm, about 2nm to about 39nm, about 2nm to about 38nm, about 2nm to about 37nm, about 2nm to about 36nm, about 2nm to about 35nm, about 2nm to about 34nm, about 2nm to about 33nm, about 2nm to about 32nm, about 2nm to about 31nm, about 2nm to about 30nm, about 2nm to about 29nm, or about 2nm to about 28nm.

[0123] For example, the quantum dot bulk may include group II-VI semiconductor compounds, group III-V semiconductor compounds, group IV-VI semiconductor compounds, group IV semiconductors, group I-III-VI semiconductor compounds, group I-II-IV-VI semiconductor compounds, group II-III-V semiconductor compounds, or combinations thereof. The group II-VI semiconductor compounds may be selected, for example, from: binary compounds such as CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, or mixtures thereof; ternary compounds such as CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZn Te, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, or mixtures thereof; and quaternary compounds such as HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, or mixtures thereof, but not limited thereto. The III-V semiconductor compounds may be selected, for example, from: binary compounds such as GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, or mixtures thereof; ternary compounds such as GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InNP, InNAs, InNSb, InPAs, InPSb, or mixtures thereof; and quaternary compounds such as GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, or mixtures thereof, but are not limited thereto. The IV-VI group semiconductor compounds may be selected, for example, from: binary compounds such as SnS, SnSe, SnTe, PbS, PbSe, PbTe, or mixtures thereof; ternary compounds such as SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, or mixtures thereof; and quaternary compounds such as SnPbSSe, SnPbSeTe, SnPbSTe, or mixtures thereof, but are not limited thereto.The group IV semiconductors may be selected, for example, from: elemental (monological) semiconductors such as Si, Ge, or mixtures thereof; and binary semiconductor compounds such as SiC, SiGe, and mixtures thereof, but are not limited thereto. The group I-III-VI semiconductor compounds may be, for example, CuInSe2, CuInS2, CuInGaSe, CuInGaS, or mixtures thereof, but are not limited thereto. The group I-II-IV-VI semiconductor compounds may be, for example, CuZnSnSe, CuZnSnS, or mixtures thereof, but are not limited thereto. The group II-III-V semiconductor compounds may include, for example, InZnP, but are not limited thereto.

[0124] The quantum dot bulk can have a substantially uniform concentration or locally different concentration distribution, including the elemental semiconductor, the binary semiconductor compound, the ternary semiconductor compound, or the quaternary semiconductor compound.

[0125] For example, the quantum dot body may include cadmium-free (Cd) quantum dots. Cadmium-free quantum dots are quantum dots that do not contain cadmium (Cd). Cadmium (Cd) can cause serious environmental / health problems and is a restricted element under the Restriction of Hazardous Substances Directive (RoHS) in many countries, and therefore cadmium-free quantum dots can be used effectively.

[0126] As an example, the quantum dot body may be a semiconductor compound comprising at least one of zinc (Zn), tellurium (Te), and selenium (Se). For example, the quantum dot may be a Zn-Te semiconductor compound, a Zn-Se semiconductor compound, and / or a Zn-Te-Se semiconductor compound. For example, the amount of tellurium (Te) in the Zn-Te-Se semiconductor compound may be less than the amount of selenium (Se). The semiconductor compound may have a peak emission wavelength (λ maximum) in a wavelength region of less than or equal to about 480 nm, for example, about 430 nm to about 480 nm, and may be configured to emit blue light.

[0127] For example, the quantum dot bulk may be a semiconductor compound comprising at least one of indium (In), zinc (Zn), and phosphorus (P). For example, the quantum dot may be an In-P semiconductor compound and / or an In-Zn-P semiconductor compound. For example, in the In-Zn-P semiconductor compound, the molar ratio of zinc (Zn) to indium (In) may be greater than or equal to about 25. The semiconductor compound may have a peak emission wavelength (λ maximum) in a wavelength region less than about 700 nm, for example, from about 600 nm to about 650 nm, and may be configured to emit red light.

[0128] The quantum dot body may have a core-shell structure, with one quantum dot surrounding another. For example, the core and shell of the quantum dot may have an interface, and at least one element of the core or the shell may have a concentration gradient at the interface, wherein the concentration of the element in the shell decreases toward the core. For example, the material composition of the shell of the quantum dot has a higher band gap than the material composition of the core of the quantum dot, and thereby the quantum dot may exhibit a quantum confinement effect.

[0129] The quantum dot body may have a quantum dot core and a multi-layered quantum dot shell surrounding the core. Here, the multi-layered shell has at least two shells, wherein each shell may be a single composition, an alloy, and / or have a concentration gradient.

[0130] For example, the shells of a multilayered structure that are farther from the core may have a higher band gap than the shells closer to the core, and thus the quantum dot may exhibit a quantum confinement effect.

[0131] For example, a quantum dot having a core-shell structure may include, for example, a core comprising a first semiconductor compound comprising zinc (Zn) and at least one of tellurium (Te) and selenium (Se); and a shell disposed on at least a portion of the core and having a composition different from that of the core, comprising a second semiconductor compound.

[0132] For example, the first semiconductor compound may be a Zn-Te-Se based semiconductor compound comprising zinc (Zn), tellurium (Te) and selenium (Se), for example, a Zn-Se based semiconductor compound comprising a small amount of tellurium (Te), for example, a semiconductor compound represented by ZnTexSe1-x, wherein x is greater than about 0 and less than or equal to 0.05.

[0133] For example, in a first semiconductor compound based on Zn-Te-Se, the molar amount of zinc (Zn) may be higher than the molar amount of selenium (Se), and the molar amount of selenium (Se) may be higher than the molar amount of tellurium (Te). For example, in the first semiconductor compound, the molar ratio of tellurium (Te) to selenium (Se) may be less than or equal to about 0.05, less than or equal to about 0.049, less than or equal to about 0.048, less than or equal to about 0.047, less than or equal to about 0.045, less than or equal to about 0.044, less than or equal to about 0.043, less than or equal to about 0.042, less than or equal to about 0.041, less than or equal to about 0.04, less than or equal to about 0.039, less than or equal to about 0.035, less than or equal to about 0.03, less than or equal to about 0.00, or less than or equal to about 0.00. 29. Less than or equal to about 0.025, Less than or equal to about 0.024, Less than or equal to about 0.023, Less than or equal to about 0.022, Less than or equal to about 0.021, Less than or equal to about 0.02, Less than or equal to about 0.019, Less than or equal to about 0.018, Less than or equal to about 0.017, Less than or equal to about 0.016, Less than or equal to about 0.015, Less than or equal to about 0.014, Less than or equal to about 0.013, Less than or equal to about 0.012, Less than or equal to about 0.011, or Less than or equal to about 0.01. For example, in the first semiconductor compound, the molar ratio of tellurium (Te) to zinc (Zn) may be less than or equal to about 0.02, less than or equal to about 0.019, less than or equal to about 0.018, less than or equal to about 0.017, less than or equal to about 0.016, less than or equal to about 0.015, less than or equal to about 0.014, less than or equal to about 0.013, less than or equal to about 0.012, less than or equal to about 0.011, or less than or equal to about 0.010.

[0134] The second semiconductor compound may include, for example, group II-VI semiconductor compounds, group III-V semiconductor compounds, group IV-VI semiconductor compounds, group IV semiconductors, group I-III-VI semiconductor compounds, group I-II-IV-VI semiconductor compounds, group II-III-V semiconductor compounds, or combinations thereof. Examples of the group II-VI semiconductor compounds, group III-V semiconductor compounds, group IV-VI semiconductor compounds, group IV semiconductors, group I-III-VI semiconductor compounds, group I-II-IV-VI semiconductor compounds, and group II-III-V semiconductor compounds are the same as those described above.

[0135] For example, the second semiconductor compound may include zinc (Zn), selenium (Se), and / or sulfur (S). For example, the shell may include ZnSeS, ZnSe, ZnS, or combinations thereof. For example, the shell may include at least one inner shell disposed near the core and an outermost shell disposed at the outermost edge of the quantum dot. The inner shell may include ZnSeS, ZnSe, or combinations thereof, and the outermost shell may include ZnS. For example, the shell may have a concentration gradient of components, and the amount of, for example, sulfur (S) may increase as it leaves the core.

[0136] For example, a quantum dot having a core-shell structure may include: a core comprising a third semiconductor compound comprising at least one of indium (In), zinc (Zn), and phosphorus (P); and a shell disposed on at least a portion of the core and comprising a fourth semiconductor compound having a composition different from that of the core.

[0137] In the In-Zn-P based third semiconductor compound, the molar ratio of zinc (Zn) to indium (In) can be greater than or equal to about 25. For example, in the In-Zn-P based third semiconductor compound, the molar ratio of zinc (Zn) to indium (In) can be greater than or equal to about 28, greater than or equal to about 29, or greater than or equal to about 30. For example, in the In-Zn-P based third semiconductor compound, the molar ratio of zinc (Zn) to indium (In) can be less than or equal to about 55, for example, less than or equal to about 50, less than or equal to about 45, less than or equal to about 40, less than or equal to about 35, less than or equal to about 34, less than or equal to about 33, or less than or equal to about 32.

[0138] The fourth semiconductor compound may include, for example, group II-VI semiconductor compounds, group III-V semiconductor compounds, group IV-VI semiconductor compounds, group IV semiconductors, group I-III-VI semiconductor compounds, group I-II-IV-VI semiconductor compounds, group II-III-V semiconductor compounds, or combinations thereof. Examples of the group II-VI semiconductor compounds, group III-V semiconductor compounds, group IV-VI semiconductor compounds, group IV semiconductors, group I-III-VI semiconductor compounds, group I-II-IV-VI semiconductor compounds, and group II-III-V semiconductor compounds are the same as those described above.

[0139] For example, the fourth semiconductor compound may include zinc (Zn) and sulfur (S), and optionally selenium (Se). For example, the shell may include ZnSeS, ZnSe, ZnS, or combinations thereof. For example, the shell may include at least one inner shell disposed near the core and an outermost shell disposed at the outermost edge of the quantum dot. At least one of the inner shell and the outermost shell may include the fourth semiconductor compound ZnS, ZnSe, or ZnSeS.

[0140] The light-emitting layer may have a thickness of, for example, from about 5 nm to about 200 nm, within the range of, for example, from about 10 nm to about 150 nm, from about 10 nm to about 100 nm, or from about 10 nm to about 50 nm. The quantum dots contained in the light-emitting layer may be laminated into one or more layers, for example, two layers. However, embodiments of the present disclosure are not limited thereto, and the quantum dots may be laminated into one to ten layers. Depending on the type (or kind) of quantum dots used and the desired emission wavelength of the light, the quantum dots may be laminated into any suitable number of layers.

[0141] Quantum dot bulks can have relatively deep HOMO levels, for example, HOMO levels greater than or equal to about 5.4 eV, and within the range, for example greater than or equal to about 5.5 eV, for example greater than or equal to about 5.6 eV, for example greater than or equal to about 5.7 eV, for example greater than or equal to about 5.8 eV, for example greater than or equal to about 5.9 eV, for example greater than or equal to about 6.0 eV. Within the stated range, the HOMO energy levels of the quantum dot layer 13 can be, for example, about 5.4 eV to about 7.0 eV, for example, about 5.4 eV to about 6.8 eV, for example, about 5.4 eV to about 6.7 eV, for example, about 5.4 eV to about 6.5 eV, for example, about 5.4 eV to about 6.3 eV, for example, about 5.4 eV to about 6.2 eV, for example, about 5.4 eV to about 6.1 eV, and within the stated range, for example, about 5.5 eV to about 7.0 eV, for example, about 5.5 eV to about 6.8 eV, for example, about 5.5 eV to about 6.7 eV, for example, about 5.5 eV to about 6.5 eV, for example, about 5.5 eV to about 6.3 eV, for example, about 5.5 eV to about 6.2 eV, for example, about 5.5 eV to about 6.1 eV, for example, about 5.5 eV to about 7.0 eV, for example, about 5.6 eV to about 6.8 eV, for example, about 5.6 eV to about 6.7 eV, for example, about 5.6 eV to about 6.5 eV, for example, about 5.6 eV to about 6.3 eV, for example, about 5.6 eV to about 6.2 eV, for example, about 5 From 0.6 eV to about 6.1 eV, within the range of, for example, from about 5.7 eV to about 7.0 eV, for example, from about 5.7 eV to about 6.8 eV, for example, from about 5.7 eV to about 6.7 eV, for example, from about 5.7 eV to about 6.5 eV, for example, from about 5.7 eV to about 6.3 eV, for example, from about 5.7 eV to about 6.2 eV, for example, from about 5.7 eV to about 6.1 eV, within the range of, for example, from about 5.8 eV to about 7.0 eV, for example, from about 5.8 eV to about 6.8 eV, for example, from about 5.8 eV. eV to 6.7 eV, for example, about 5.8 eV to 6.5 eV, for example, about 5.8 eV to 6.3 eV, for example, about 5.8 eV to 6.2 eV, for example, about 5.8 eV to 6.1 eV, within the range of, for example, about 6.0 eV to 7.0 eV, for example, about 6.0 eV to 6.8 eV, for example, about 6.0 eV to 6.7 eV, for example, about 6.0 eV to 6.5 eV, for example, about 6.0 eV to 6.3 eV, for example, about 6.0 eV to 6.2 eV.

[0142] The quantum dot bulk may have relatively shallow LUMO energy levels, for example, less than or equal to about 3.7 eV, and within the range of, for example, less than or equal to about 3.6 eV, less than or equal to about 3.5 eV, less than or equal to about 3.4 eV, less than or equal to about 3.3 eV, less than or equal to about 3.2 eV, or less than or equal to about 3.0 eV. Within the range of, the LUMO energy levels of the quantum dot layer 13 may be about 2.5 eV to about 3.7 eV, about 2.5 eV to about 3.6 eV, about 2.5 eV to about 3.5 eV, about 2.5 eV to about 3.4 eV, about 2.5 eV to about 3.3 eV, about 2.5 eV to about 3.2 eV, about 2.5 eV to about 3.1 eV, about 2.5 eV to about 3.0 eV, or about 2. 8 eV to about 3.7 eV, about 2.8 eV to about 3.6 eV, about 2.8 eV to about 3.5 eV, about 2.8 eV to about 3.4 eV, about 2.8 eV to about 3.3 eV, about 2.8 eV to about 3.2 eV, about 3.0 eV to about 3.7 eV, about 3.0 eV to about 3.6 eV, about 3.0 eV to about 3.5 eV, or about 3.0 eV to about 3.4 eV.

[0143] The quantum dot body may have a band gap of about 1.7 eV to about 2.3 eV or about 2.4 eV to about 2.9 eV. Within these ranges, for example, the quantum dot layer 13 may have a band gap of about 1.8 eV to about 2.2 eV or about 2.4 eV to about 2.8 eV, and within these ranges, for example, about 1.9 eV to about 2.1 eV or about 2.4 eV to about 2.7 eV.

[0144] The light emission method of the light-emitting device provided in the embodiments of this disclosure can be bottom light emission or top light emission.

[0145] In some embodiments, the light-emitting device provided in this disclosure may also include other functional film layers well known to those skilled in the art, which will not be described in detail here.

[0146] Based on the same inventive concept, this disclosure also provides a method for manufacturing a light-emitting device, used to manufacture the light-emitting device provided in this disclosure embodiment, as shown in FIG11, the manufacturing method includes:

[0147] S1101, A plurality of gate electrodes are formed at intervals on one side of a substrate;

[0148] S1102, Form a first insulating layer covering the surface of each gate electrode portion;

[0149] S1103. A first electrode is formed between the first insulating layers between each gate electrode, the first electrode including a plurality of first through holes for embedding each gate electrode and the corresponding first insulating layer;

[0150] S1104. A first carrier transport layer is formed on the side of the first electrode away from the substrate, and the end of the gate electrode away from the substrate extends at least into the first carrier transport layer.

[0151] S1105, A light-emitting layer is formed on the side of the first carrier transport layer away from the substrate;

[0152] S1106. A second carrier transport layer is formed on the side of the light-emitting layer away from the substrate.

[0153] S1107. A second electrode is formed on the side of the second carrier transport layer away from the substrate.

[0154] The fabrication method of the light-emitting device provided in this embodiment can form a MOS capacitor structure composed of a gate electrode, a first insulating layer, and a first carrier transport layer within the first carrier transport layer. When the light-emitting device is working, the transverse electric field of the MOS capacitor structure can be used to induce free hole carriers in the first carrier transport layer (e.g., a hole transport layer), thereby improving the conductivity of the hole transport layer, or causing the electron carriers in the first carrier transport layer (e.g., an electron transport layer) to be in a depleted state, reducing the electron concentration, and making the electron-hole transport of the light-emitting device more balanced, thereby improving the efficiency of the light-emitting device.

[0155] The following describes in detail the fabrication method of the light-emitting device provided in this embodiment of the present disclosure, using Figure 1 as an example. The method specifically includes the following steps:

[0156] (1) As shown in Figure 12A, a conductive connection layer 11 is formed on one side of the substrate 1 by processes such as evaporation / sputtering. The material of the conductive connection layer 11 can be Ni, Al, Mo, etc.

[0157] (2) As shown in Figure 12B, a buffer layer 10 is formed on the side of the conductive connection layer 11 away from the substrate 1. The buffer layer 10 includes a second via H2. Specifically, a buffer material film can be deposited on the side of the conductive connection layer 11 away from the substrate 1, and a plurality of second vias H2 penetrating the buffer material film can be formed by photolithography etching process.

[0158] (3) As shown in Figure 12C, a gate electrode material thin film 7' is formed on the side of the buffer layer 10 away from the substrate 1. Specifically, the gate electrode material can be a transparent conductive material such as heavily doped polycrystalline silicon, ITO or AZO, or it can be gold, aluminum, molybdenum, nickel, tungsten, titanium, etc.

[0159] (4) As shown in Figure 12D, the gate electrode material thin film 7' is patterned by photolithography etching process to form gate electrodes 7 located in each second through hole H2. The height of the gate electrode 7 is greater than the height of the buffer layer 10. That is, multiple gate electrodes 7 are formed on one side of the substrate 1 at intervals. The end of each gate electrode 7 facing the substrate 1 is electrically connected to the conductive connection layer 11.

[0160] (5) As shown in Figure 12E, a first insulating layer 81 and a second insulating layer 82 are formed on the side of the gate electrode 7 away from the substrate 1 by sputtering or vapor deposition. The first insulating layer 81 covers part of the surface of each gate electrode 7, and the second insulating layer 82 is located between the buffer layer 10 and the subsequently formed first electrode 2. Specifically, the material of the first insulating layer 81 can be an insulating material with a high dielectric constant such as silicon oxide, silicon nitride, or hafnium oxide.

[0161] (6) As shown in FIG12F, a photoresist layer 20 is formed on the side of the first insulating layer 81 and the second insulating layer 82 away from the substrate 1.

[0162] (7) As shown in Figure 12G, the photoresist layer 20 is patterned by photolithography etching process to form a photoresist pattern 20' on the top surface and part of the side surface of the overall structure of the gate electrode 7 and the first insulating layer 81.

[0163] (8) As shown in Figure 12H, a first conductive material thin film 2' is formed on the side of the photoresist pattern 20' away from the substrate 1 by sputtering or other methods.

[0164] (9) As shown in Figure 12I, the photoresist pattern 20' is stripped off, that is, a first electrode 2 is formed on the side of the second insulating layer 82 away from the substrate 1. The first electrode 2 includes a plurality of first through holes H1 spaced apart, and the first through holes H1 correspond one-to-one with the second through holes H2.

[0165] (10) As shown in Figure 12J, a hole injection layer 9 and a first carrier transport layer 3 (hole transport layer) are formed on the side of the first electrode 2 away from the substrate 1, and the end of the gate electrode 7 away from the substrate 1 extends into the first carrier transport layer 3 (hole transport layer).

[0166] (11) As shown in Figure 12K, a light-emitting layer 4 is formed on the side of the first carrier transport layer 3 (hole transport layer) away from the substrate 1.

[0167] (12) As shown in Figure 12L, a second carrier transport layer 5 (electron transport layer) is formed on the side of the light-emitting layer 4 away from the substrate 1.

[0168] (13) As shown in Figure 1, a second electrode 6 is formed on the side of the second carrier transport layer 5 (electron transport layer) away from the substrate 1.

[0169] Next, the device is packaged and cut to complete the fabrication of the entire light-emitting device.

[0170] Based on the same inventive concept, this disclosure also provides a display device, including the light-emitting device described above. Since the principle by which this display device solves the problem is similar to that of the light-emitting device, the implementation of the display device provided in this disclosure can refer to the implementation of the light-emitting device, and repeated details will not be described again.

[0171] In specific implementation, the display device provided in the embodiments of this disclosure can be an organic light-emitting display device.

[0172] In specific implementation, the display device provided in the embodiments of this disclosure may be a full-screen display device or a flexible display device, etc., and is not limited thereto.

[0173] In specific implementations, the display device provided in this disclosure embodiment can be a full-screen mobile phone as shown in FIG13. Of course, the display device provided in this disclosure embodiment can also be any product or component with display function, such as a tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure. This display device includes, but is not limited to, components such as: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in this disclosure embodiment. In other words, the display device provided in this disclosure embodiment can include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0174] This disclosure provides a light-emitting device and its fabrication method, as well as a display device. By embedding a gate electrode and a first insulating layer within at least a first carrier transport layer, the gate electrode, the first insulating layer, and the first carrier transport layer form a MOS (metal-oxide-semiconductor field-effect transistor) capacitor structure perpendicular to the surface of the first electrode. This MOS capacitor structure allows for control of the charge distribution in the semiconductor base (i.e., the first carrier transport layer) by changing the gate electrode voltage, thereby achieving current control. Since the preset voltage applied to the gate electrode during operation is less than the voltage applied to the first electrode and less than the voltage applied to the second electrode, the lateral electric field of the MOS capacitor structure can be used to induce free hole carriers within the first carrier transport layer (e.g., a hole transport layer), improving the conductivity of the hole transport layer, or depleting the electron carriers within the first carrier transport layer (e.g., an electron transport layer), reducing the electron concentration, and making the electron-hole transport of the light-emitting device more balanced, thereby improving the efficiency of the light-emitting device.

[0175] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0176] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A light-emitting device, wherein, include: A substrate, and a first electrode, a first carrier transport layer, a light-emitting layer, a second carrier transport layer, and a second electrode stacked on the substrate; The first electrode includes a plurality of spaced-apart first through holes; It also includes: a gate electrode located within the first via and extending at least one end into the first carrier transport layer, and a first insulating layer located between at least a portion of the sidewall of the gate electrode and the sidewall of the first via and covering the surface of each portion of the gate electrode; wherein the first insulating layer is configured to insulate the gate electrode from the first electrode, and the first insulating layer is further configured to insulate at least the gate electrode from the first carrier transport layer, and the gate electrode is configured to be loaded with a preset voltage when the light-emitting device is operating, the preset voltage being less than the voltage loaded on the first electrode and less than the voltage loaded on the second electrode.

2. The light-emitting device as described in claim 1, wherein, The first insulating layer conformally covers at least a portion of the surface of the gate electrode.

3. The light-emitting device as described in claim 2, wherein, It also includes a second insulating layer located between the first electrode and the substrate, wherein the first insulating layer and the second insulating layer are an integral structure.

4. The light-emitting device as described in claim 3, wherein, One end of the gate electrode extends into the first carrier transport layer.

5. The light-emitting device as described in claim 4, wherein, The overall structure of the gate electrode and the first insulating layer is the first structure, and the thickness of the first structure within the first carrier transport layer is less than the thickness of the first carrier transport layer.

6. The light-emitting device as described in claim 5, wherein, The thickness of the first structure within the first carrier transport layer is greater than half the thickness of the first carrier transport layer.

7. The light-emitting device as described in claim 3, wherein, One end of the gate electrode extends into the second carrier transport layer.

8. The light-emitting device as claimed in claim 7, wherein, The overall structure of the gate electrode and the first insulating layer is the first structure, and the thickness of the first structure within the second carrier transport layer is less than the thickness of the second carrier transport layer.

9. The light-emitting device as claimed in claim 8, wherein, The thickness of the first structure within the second carrier transport layer is greater than half the thickness of the second carrier transport layer.

10. The light-emitting device according to any one of claims 3-9, wherein, It also includes: a buffer layer located between the substrate and the second insulating layer, and a conductive connection layer located between the substrate and the buffer layer; The buffer layer includes second through holes that correspond one-to-one with the first through holes, and the other end of each gate electrode extends through the second through hole to be electrically connected to the conductive connection layer.

11. The light-emitting device as claimed in claim 10, wherein, The orthographic projection shape of the second through hole on the substrate is the same as the orthographic projection shape of the first through hole on the substrate.

12. The light-emitting device according to any one of claims 1-11, wherein, The orthographic projection of the first through hole onto the substrate is circular or square.

13. The light-emitting device as claimed in claim 12, wherein, Multiple first through holes are arranged in an array.

14. The light-emitting device according to any one of claims 1-11, wherein, The first through-hole has a strip-shaped orthographic projection on the substrate.

15. The light-emitting device as claimed in claim 14, wherein, The first through hole extends in a first direction, and a plurality of the first through holes are arranged at equal intervals along a second direction, the second direction being perpendicular to the first direction.

16. The light-emitting device according to any one of claims 1-15, wherein, The first electrode is the anode, the second electrode is the cathode, the first carrier transport layer is the hole transport layer, and the second carrier transport layer is the electron transport layer; The light-emitting device further includes a hole injection layer located between the first electrode and the first carrier transport layer, wherein the orthographic projection of the hole injection layer on the substrate does not overlap with the orthographic projection of the first via on the substrate.

17. The light-emitting device according to any one of claims 1-16, wherein, The first electrode is a cathode, the second electrode is an anode, the first carrier transport layer is an electron transport layer, and the second carrier transport layer is a hole transport layer; The light-emitting device further includes a hole injection layer located between the second electrode and the second carrier transport layer.

18. The light-emitting device as claimed in claim 16 or 17, wherein, The material of the hole transport layer includes a cross-linked network structure.

19. A display device, wherein, Including the light-emitting device as described in any one of claims 1-18.

20. A method for manufacturing a light-emitting device, used to manufacture the light-emitting device as described in any one of claims 1-18, wherein, The manufacturing method includes: Multiple gate electrodes are formed at intervals on one side of the substrate. A first insulating layer is formed covering the surface of each of the gate electrode portions; A first electrode is formed between the first insulating layers between each of the gate electrodes, the first electrode including a plurality of first through holes for embedding each of the gate electrodes and the corresponding first insulating layers; A first carrier transport layer is formed on the side of the first electrode away from the substrate, and the end of the gate electrode away from the substrate extends at least into the first carrier transport layer. A light-emitting layer is formed on the side of the first carrier transport layer away from the substrate. A second carrier transport layer is formed on the side of the light-emitting layer opposite to the substrate. A second electrode is formed on the side of the second carrier transport layer opposite to the substrate.

21. The manufacturing method as described in claim 20, wherein, Multiple gate electrodes are formed at intervals on one side of the substrate, specifically including: A buffer layer is formed on one side of the substrate, the buffer layer including second through holes that correspond one-to-one with the first through holes; A thin film of gate electrode material is formed on the side of the buffer layer opposite to the substrate. The gate electrode material film is patterned to form a gate electrode located in each of the second vias, the height of which is greater than the height of the buffer layer.

22. The manufacturing method as described in claim 21, wherein, Before forming the buffer layer, the following is also included: A conductive connection layer is formed on one side of the substrate, and the end of each gate electrode facing the substrate is electrically connected to the conductive connection layer.

23. The manufacturing method according to any one of claims 20-22, wherein, When forming the first insulating layer covering the surface of each of the gate electrode portions, the method further includes forming a second insulating layer located between the first electrode and the substrate and integrally formed with the first insulating layer.

24. The manufacturing method as described in claim 23, wherein, A first electrode is formed between the first insulating layers between each of the gate electrodes, specifically including: A photoresist layer is formed on the side of the first insulating layer and the second insulating layer away from the substrate. The photoresist layer is patterned to form a photoresist pattern covering the top surface and part of the side surfaces of the overall structure of the gate electrode and the first insulating layer. A first conductive material thin film is formed on the side of the photoresist pattern facing away from the substrate. The photoresist pattern is peeled off to form the first electrode.

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