Array substrate, display panel, and display device

Abstract

The present application discloses an array substrate, a display panel, and a display device. The array substrate comprises a first area and a second area, and comprises a driving circuit layer, a first sub-passivation layer, and a second sub-passivation layer that are stacked. The first sub-passivation layer is located in the first area and the second area, and the second sub-passivation layer is located in the second area. The first sub-passivation layer has a stronger hydrogen blocking capability than the second sub-passivation layer, and the second sub-passivation layer has a stronger water blocking capability than the first sub-passivation layer.

Description

Array substrate, display panel and display device Technical Field

[0001] This application belongs to the field of display technology, specifically relating to an array substrate, a display panel, and a display device. Background Technology

[0002] In recent years, organic light-emitting diodes (OLEDs) have been favored by more and more manufacturers due to their advantages such as high contrast, high brightness, high response speed, and low power consumption, which has also promoted the development of OLEDs in the display field.

[0003] Currently, the main backplane technologies for small-sized OLED displays are Low Temperature Poly-Silicon (LTPS) thin-film transistor (TFT) backplane technology and oxide TFT backplane technology. However, due to the high carrier mobility of LTPS leading to high leakage current, and the difficulty in controlling the front-side uniformity of oxide, Low Temperature Polycrystalline Oxide (LTPO) technology has emerged. LTPO technology combines the advantages of both LTPS and oxides (such as indium gallium zinc oxide, IGZO), forming a fast response speed and lower power consumption LTPO solution.

[0004] However, compared to LTPS products, IGZO thin-film transistors in LTPO products are more sensitive to the surrounding atmosphere (such as hydrogen, water, etc.). Therefore, it is necessary to provide a new LTPO structure to reduce the reliability risk of LTPO products. Invention Overview

[0005] This application provides an array substrate, a display panel, and a display device, which can avoid or reduce the negative impact of hydrogen on the electrical properties of the first thin-film transistor, and can also effectively block the intrusion of water vapor, thereby effectively reducing the reliability risk of the display product.

[0006] In a first aspect, this application provides an array substrate having a first region and a second region disposed adjacent to each other; the array substrate includes:

[0007] A substrate layer located in the first region and the second region;

[0008] A driving circuit layer is located on one side of the substrate layer and includes a first thin-film transistor located in the first region; the first thin-film transistor includes a first active layer and a first source / drain electrode that are electrically connected to each other, the first source / drain electrode being located on the side of the first active layer away from the substrate layer, and the material of the first active layer is an oxide.

[0009] A passivation layer is located in the first region and the second region, and is located on the side of the driving circuit layer opposite to the substrate layer; the passivation layer includes a first sub-passivation layer and a second sub-passivation layer; the first sub-passivation layer covers at least the first source / drain electrode and extends from the first region to the second region; the second sub-passivation layer covers the first sub-passivation layer located in the second region;

[0010] Wherein, the hydrogen atom content in the material of the first sub-passivation layer is less than the hydrogen atom content in the second sub-passivation layer, and the water permeability in the second sub-passivation layer is less than the water permeability in the first sub-passivation layer.

[0011] Secondly, this application also provides a display panel, the display panel including the array substrate described above, the display panel further including a light-emitting layer and an encapsulation layer stacked on the array substrate;

[0012] The light-emitting layer is located in the first region and is electrically connected to the driving circuit layer; the encapsulation layer covers the light-emitting layer and extends from the first region to cover at least part of the array substrate located in the second region.

[0013] Thirdly, this application also provides a display device, the display device comprising the array substrate described above, or the display device comprising the display panel described above. Attached Figure Description

[0014] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0015] Figure 1 is a schematic cross-sectional view of an exemplary display panel provided in an embodiment of this application;

[0016] Figure 2 is a schematic cross-sectional view of an array substrate provided in an embodiment of this application;

[0017] Figure 3 is a schematic flowchart of the fabrication method of the array substrate shown in Figure 2;

[0018] Figures 4 to 10 are schematic diagrams of a method for fabricating an array substrate according to an embodiment of this application;

[0019] Figure 11 is a schematic cross-sectional view of a display panel provided in an embodiment of this application. Embodiments of the present invention

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] As shown in Figure 1, an exemplary display panel 1 has a display area AA and a non-display area NAA. The display panel 1 includes an array substrate 2, a light-emitting layer 3, an encapsulation layer 4 and a touch layer 5 from bottom to top. The array substrate 2 is located in the display area AA and the non-display area NAA, the light-emitting layer 3 is located in the display area AA, the encapsulation layer 4 is located in the display area AA and part of the non-display area NAA, and the touch layer 5 is located in the display area AA and the non-display area NAA.

[0022] The display panel 1 is manufactured based on LTPO backplane technology. The array substrate 2 includes a substrate layer 38, a first barrier layer 6, a light-shielding layer 7, a second barrier layer 8, a buffer layer 9, a first active layer 10, a first gate insulating layer 11, a first metal layer 12, a second gate insulating layer 13, a second metal layer 14, a first interlayer insulating layer 15, a second active layer 16, a third gate insulating layer 17, a third metal layer 18, a second interlayer insulating layer 19, a fourth metal layer 20, a passivation layer 21, a first planarization layer 22, a fifth metal layer 23, and a second planarization layer 24. The first metal layer 12 includes a first gate GE1 located in the display area AA and aligned with the first active layer 10; the second metal layer 14 includes a second gate GE2 aligned with the first gate GE1, a third gate GE3 located in the display area AA and spaced apart from the second gate GE2, and a first conductor portion 25 located in the non-display area NAA, with the third gate GE3 aligned with the second active layer 16; the third metal layer 18 includes a fourth gate GE4 aligned with the second active layer 16; the fourth metal layer 20 includes a first source / drain electrode SD1 located in the display area AA and electrically connected to the first active layer 10, a second source / drain electrode SD2 located in the display area AA and electrically connected to the second active layer 16, and a first transfer electrode 26 located in the non-display area NAA and electrically connected to the first conductor portion 25; the fifth metal layer 23 includes a second conductor portion 27 located in the display area AA and electrically connected to the first source / drain electrode SD1, and a second transfer electrode 28 located in the non-display area NAA and electrically connected to the first transfer electrode 26.

[0023] The first active layer 10 is made of polysilicon, and the second active layer 16 is made of indium gallium zinc oxide (IGZO). The first active layer 10, the first gate GE1, the second gate GE2, and the first source / drain electrode SD1 constitute the LTPS thin-film transistor T1. The third gate GE3, the second active layer 16, the fourth gate GE4, and the second source / drain electrode SD2 constitute the IGZO thin-film transistor T2. A passivation layer 21 covers the second interlayer insulating layer 19, the first source / drain electrode SD1, and the second source / drain electrode SD2. A light-shielding layer 7 is provided corresponding to the LTPS thin-film transistor T1.

[0024] The light-emitting layer 3 includes an anode layer 29 and a pixel definition layer 30 located on the second planarization layer 24, and a light-emitting functional layer 31 and a cathode layer 32 located on the anode layer 29. The pixel definition layer 30 has a pixel opening that exposes the anode layer 29, and the light-emitting functional layer 31 is located in the pixel opening. The encapsulation layer 4 covers the light-emitting layer 3 and part of the array substrate 2. The touch layer 5 includes a first touch insulating layer 33, a first touch electrode layer 34, a second touch insulating layer 35, a second touch electrode layer 36, and a protective layer 37 stacked sequentially on the encapsulation layer 4. The first touch insulating layer 33 and the second touch insulating layer 35 extend from the display area AA to the non-display area NAA and are stacked on the passivation layer 21 located in the non-display area NAA. The array substrate 2 also includes a third transition electrode 39 located in the non-display area NAA and disposed on the same layer as the second touch electrode layer 36. The third transition electrode 39 covers the second transition electrode 28 and the second touch insulating layer 35.

[0025] Since the active layer in the IGZO thin-film transistor T2 is made of IGZO, and IGZO is sensitive to hydrogen (H), the passivation layer 21 above the IGZO active layer can only be made of silicon oxide (SiO2). x It is made of SiO2. However, the inventors discovered through research that the contact interface between the passivation layer 21 and the first touch insulating layer 33 in the non-display area NAA is a weak area for moisture intrusion. The moisture intrusion route is shown in the schematic diagram of area A in Figure 1. When there are micro-cracks in the non-display area NAA, moisture will enter the contact interface between the first touch insulating layer 33 and the array substrate 2 (i.e., the contact interface between the first touch insulating layer 33 and the passivation layer 21) along the cracks. Furthermore, due to SiO2... x The relatively loose texture of the film layer leads to SiO x The membrane layer has a weak inhibitory effect on water vapor intrusion. If SiO2 is used... x If the film layer is used as a passivation layer 21, a channel for moisture intrusion will be formed in the passivation layer 21, which will cause the reliability of the display panel 1 to fail.

[0026] To address the aforementioned technical problems, embodiments of this application provide an array substrate, a display panel, and a display device. By layering and partitioning the passivation layer in the array substrate, the non-display area utilizes SiO2. x -SiN x The stacked structure is used as the passivation layer, and the display area uses SiO2. x A single-layer structure is used as the passivation layer, and the SiO₂ in the display area and the non-display area are... x The film layers are disposed in the same layer; at this time, the passivation layer near the IGZO thin film transistor extends from the display area to the non-display area, and its material is silicon oxide (SiO2). x This can effectively avoid SiN x Hydrogen diffuses into the channel of the IGZO active layer, causing the IGZO to become conductive, thus avoiding the negative electrical effects of hydrogen on the IGZO thin-film transistor. Furthermore, the passivation layer on the side furthest from the IGZO thin-film transistor is located in the non-display area, and its material is silicon nitride (SiN). x ), due to SiN x The film layer has a denser texture, providing stronger inhibition against moisture intrusion and effectively blocking moisture penetration, thereby significantly reducing the reliability risk of the display panel. Please refer to the following description of the embodiments for details.

[0027] As shown in Figure 2, this embodiment of the application provides an array substrate 40, which has a first region 41 and a second region 42 disposed adjacent to each other. The array substrate 40 includes a substrate layer 43 and a driving circuit layer 44 and a passivation layer 45 stacked on the substrate layer 43. The substrate layer 43 is located in the first region 41 and the second region 42; the driving circuit layer 44 is located on one side of the substrate layer 43 and includes a first thin-film transistor 46 located in the first region 41. The first thin-film transistor 46 includes a first active layer 47 and a first source / drain electrode 48 electrically connected to each other. The first source / drain electrode 48 is located on the side of the first active layer 47 facing away from the substrate layer 43, and the material of the first active layer 47 is oxide. The passivation layer 45 is located in the first region 41 and the second region 42, and is located on the side of the driving circuit layer 44 facing away from the substrate layer 43. The passivation layer 45 includes a first sub-passivation layer 45a and a second sub-passivation layer 45b; the first sub-passivation layer 45a covers at least the first source / drain electrode 48 and extends from the first region 41 to the second region 42; the second sub-passivation layer 45b covers the first sub-passivation layer 45a located in the second region 42.

[0028] The hydrogen atom content in the material of the first sub-passivation layer 45a is less than the hydrogen atom content in the second sub-passivation layer 45b, and the water permeability in the second sub-passivation layer 45b is less than the water permeability in the first sub-passivation layer 45a.

[0029] It should be noted that in this embodiment, the first area 41 corresponds to the effective display area (AA area) of the display panel 80, and the second area 42 corresponds to the non-display area (NAA area) of the display panel 80.

[0030] In some embodiments, the second region 42 is a bonding region used to establish electrical connections between the driver IC and the traces in the driver circuit layer. Because pressure is applied to the second region 42 of the array substrate 40 during the bonding process, this process may cause micro-cracks to form in the second region 42, leading to moisture intrusion.

[0031] Since the material of the first active layer 47 is oxide, the first thin-film transistor 46 is an oxide thin-film transistor, which is sensitive to the surrounding atmosphere (such as hydrogen and water). If hydrogen diffuses into the channel of the first active layer 47, it will cause the first active layer 47 to become conductive, thereby affecting the electrical properties of the first thin-film transistor 46. If water vapor intrudes, it will cause the threshold voltage of the first thin-film transistor 46 to shift, resulting in the failure of the first thin-film transistor 46.

[0032] Since the hydrogen atom content in the material of the first sub-passivation layer 45a is less than that in the second sub-passivation layer 45b, and the first sub-passivation layer 45a is located on the side of the second sub-passivation layer 45b closer to the first thin-film transistor 46, hydrogen release from the first sub-passivation layer 45a can be avoided or reduced during high-temperature processing. Furthermore, the first sub-passivation layer 45a can block the diffusion of hydrogen released from the second sub-passivation layer 45b towards the first thin-film transistor 46, thereby avoiding or reducing the negative impact of hydrogen on the electrical properties of the first thin-film transistor 46. Simultaneously, since the water penetration rate in the second sub-passivation layer 45b is less than that in the first sub-passivation layer 45a, and the second sub-passivation layer 45b is located in the second region 42 and on the side of the first sub-passivation layer 45a away from the first thin-film transistor 46, when micro-cracks occur in the second region 42, the second sub-passivation layer 45b, located on the outer layer of the second region 42, can effectively block the intrusion of water vapor, preventing water vapor from affecting the threshold voltage of the first thin-film transistor 46.

[0033] Therefore, the combination of the first sub-passivation layer 45a and the second sub-passivation layer 45b can both avoid or reduce the negative impact of hydrogen on the electrical properties of the first thin-film transistor 46 and effectively block the intrusion of moisture, thereby effectively reducing the reliability risk of the display substrate. Furthermore, by providing the first sub-passivation layer 45a in the second region 42, it can also prevent over-etching of the insulating layer in the underlying driving circuit layer 44 during the etching of the second sub-passivation layer 45b, thus improving the electrical insulation performance of the lower insulating layer.

[0034] In some embodiments, the material of the first sub-passivation layer 45a is a silicon oxide compound, such as silicon oxide, but not limited thereto; the material of the second sub-passivation layer 45b is a silicon nitride compound, such as silicon nitride, but not limited thereto.

[0035] Since the hydrogen atom content in silicon oxide compounds is less than that in silicon nitride compounds, the first sub-passivation layer 45a made of silicon oxide compound is disposed in the first region 41 and the second region 42. This effectively blocks hydrogen and prevents hydrogen in the silicon nitride compound from negatively affecting the electrical properties of the first thin-film transistor 46. Furthermore, since silicon nitride compounds have a denser texture than silicon oxide compounds, the second sub-passivation layer 45b made of silicon nitride compound is disposed in the second region 42, which is prone to cracking, and is located away from the first thin-film transistor 46. This effectively blocks moisture intrusion at the initiation point of moisture intrusion and prevents moisture from negatively affecting the threshold voltage of the first thin-film transistor 46.

[0036] In some embodiments, the substrate 43 can be a flexible substrate or a rigid substrate, and no limitation is made here.

[0037] In one specific embodiment, the substrate layer 43 is a flexible substrate layer. In this case, the substrate layer 43 can be a single-layer flexible substrate layer or a double-layer flexible substrate layer. The material of the flexible substrate layer includes polyimide (PI), but is not limited to this.

[0038] In some embodiments, the driving circuit layer 44 further includes a stacked structure 49 located on the substrate layer 43, and the stacked structure 49 is located in the first region 41 and the second region 42. A first source / drain electrode 48 is located on the side of the stacked structure 49 facing away from the substrate layer 43, and a first sub-passivation layer 45a covers the stacked structure 49 and the first source / drain electrode 48. The stacked structure 49 includes multiple layers of insulating layers stacked together, and a first active layer 47 is located between two adjacent insulating layers; the material of the insulating layer adjacent to the first active layer 47 includes a silicon oxide compound.

[0039] Since the first active layer 47 is sensitive to hydrogen, when the insulating layer adjacent to the first active layer 47 is made of silicon oxide, it can more effectively block hydrogen while providing electrical insulation, thereby further preventing hydrogen from affecting the electrical properties of the first thin-film transistor 46.

[0040] In some embodiments, the insulating layer adjacent to the first sub-passivation layer 45a is made of a silicon oxide compound. Typically, the insulating layer adjacent to the first sub-passivation layer 45a is an interlayer insulating layer, and the first drain electrode is disposed on the interlayer insulating layer. The interlayer insulating layer provides electrical insulation to the first source / drain electrode 48 and the gate of the first thin-film transistor 46. When the insulating layer adjacent to the first sub-passivation layer 45a is made of a silicon oxide compound, it can further effectively block hydrogen in addition to providing electrical insulation to the first source / drain electrode and the gate of the first thin-film transistor 46, thereby further preventing hydrogen from affecting the electrical properties of the first thin-film transistor 46.

[0041] In some embodiments, the first thin-film transistor 46 further includes a first gate 50 and a second gate 51 spaced apart from and aligned with the first active layer 47; the first gate 50 is located on the side of the first active layer 47 close to the substrate layer 43, and the second gate 51 is located on the side of the first active layer 47 away from the substrate layer 43; at least one insulating layer in the stacked structure 49 is located on the side of the second gate 51 away from the first active layer 47, and the material of the insulating layer on the side of the second gate 51 away from the first active layer 47 includes any one or more combinations of silicon nitride compounds, silicon oxide compounds, and silicon nitride compounds.

[0042] Understandably, when a second gate 51 is provided above the first active layer 47, the second gate 51 protects the first active layer 47 and can prevent hydrogen from diffusing into the channel of the first active layer 47. At this time, the material of the insulating layer located on the side of the second gate 51 away from the first active layer 47 is more selective. For example, the material of the insulating layer can be a silicon nitride compound, a silicon oxide compound, a silicon nitride compound or a combination thereof.

[0043] In some embodiments, the driving circuit layer 44 further includes a first conductor portion 52 located in the second region 42, the first conductor portion 52 being located between two adjacent insulating layers in the stacked structure 49; the stacked structure 49 has a first opening 53 on the side facing away from the substrate layer 43, and the first conductor portion 52 is at least partially exposed in the first opening 53. The driving circuit layer 44 also includes a first transition electrode 54, the first transition electrode 54 being located on the sidewall of the first opening 53 and on the first conductor portion 52 exposed in the first opening 53, and extending from the sidewall of the first opening 53 to the side of the stacked structure 49 facing away from the substrate layer 43; the first transition electrode 54 and the first source / drain electrode 48 are disposed in the same layer; a first sub-passivation layer 45a and a second sub-passivation layer 45b are also sequentially stacked on the first transition electrode 54 located on the side of the stacked structure 49 facing away from the substrate layer 43.

[0044] Understandably, the first transfer electrode 54 is used to transmit electrical signals from the drive circuit located in the first region 41 through the first conductor portion 52, or the first transfer electrode 54 is used to input electrical signals to the drive circuit located in the first region 41 through the first conductor portion 52.

[0045] Because the stacked structure 49 in the second region 42 has a first opening 53, the risk of cracks forming in the second region 42 is increased, thereby increasing the risk of moisture intrusion. In this embodiment, the first sub-passivation layer 45a and the second sub-passivation layer 45b located in the second region 42 are stacked on the first transition electrode 54 located on the side of the stacked structure 49 away from the substrate layer 43. This increases the path for moisture intrusion, which helps to enhance the barrier effect of the passivation layer 45 on moisture, thereby reducing the risk of moisture intrusion.

[0046] In some embodiments, the first transition electrode 54 forms a second opening 55 in the first opening 53, and a first sub-passivation layer 45a and a second sub-passivation layer 45b located in the second region 42 are disposed around the second opening 55. The drive circuit layer 44 further includes a second transition electrode 56 located on the first transition electrode 54 exposed by the second opening 55, and extending from the sidewall of the second opening 55 to the side of the second sub-passivation layer 45b opposite to the substrate layer 43.

[0047] Understandably, the second transfer electrode 56 is electrically connected to the first transfer electrode 54, and the second transfer electrode 56 covers the edge of the second sub-passivation layer 45b surrounding the second opening 55. This design allows the edges of the first sub-passivation layer 45a and the second sub-passivation layer 45b to be sandwiched between the first transfer electrode 54 and the second transfer electrode 56, thereby preventing the edges of the first sub-passivation layer 45a and the second sub-passivation layer 45b near the second opening 55 from being exposed, and further extending the path of moisture intrusion, which is beneficial to further enhance the moisture barrier effect.

[0048] In some embodiments, the array substrate 40 further includes a first planarization layer 57, a second conductor portion 58, and a second planarization layer 59 located in the first region 41 and stacked on the side of the passivation layer 45 facing away from the substrate layer 43. The first planarization layer 57 covers the first source / drain electrode 48 and the first sub-passivation layer 45a, and extends from the first region 41 to cover a portion of the second sub-passivation layer 45b. The second conductor portion 58 is located on the first planarization layer 57 and is electrically connected to the drive circuit layer 44; the second planarization layer 59 covers the second conductor portion 58 and the first planarization layer 57; the second transition electrode 56 and the second conductor portion 58 are disposed in the same layer.

[0049] Understandably, the first planarization layer 57 covers the side of the second sub-passivation layer 45b near the first region 41, which can prevent moisture from intruding from the side of the second sub-passivation layer 45b near the first region 41.

[0050] The array substrate 40 also includes a third region 60 disposed adjacent to the first region 41 and a third opening 61 located in the third region 60; the third opening 61 penetrates at least the stacked structure 49 and the first sub-passivation layer 45a; the first planarization layer 57 extends from the first region 41 to the third region 60 and fills the third opening 61; the second planarization layer 59 extends from the first region 41 to the third region 60.

[0051] Specifically, the third region 60 can be a foldable region. For example, the third region 60 can be a bending region in a non-display area, but it is not limited to this. When the third region 60 is a foldable region, the material of the first planarization layer 57 is a flexible material, such as an organic planarization material. Filling the third opening 61 with the first planarization layer 57 can improve the bending performance of the third region 60.

[0052] Of course, the third region 60 can also be a non-bending region in the effective display area, and the third region 60 is located between two adjacent second regions 42. In order to improve the light transmittance of the third region 60, a material with high light transmittance can be selected as the material of the first planarization layer 57.

[0053] It is understood that the third region 60 may be located within the effective display area or within the non-display area, and this application does not limit this; furthermore, the embodiments of this application do not specifically limit the function of the third region 60 and the material of the first planarization layer 57, and those skilled in the art can select appropriate materials as the material of the first planarization layer 57 according to actual needs.

[0054] In some embodiments, the bottom of the third opening 61 may also extend toward the interior of the substrate layer 43.

[0055] In some embodiments, as shown in FIG2, the driving circuit layer 44 further includes a second thin-film transistor 62 located in the first region 41, the second thin-film transistor 62 and the first thin-film transistor 46 being disposed at intervals; the second thin-film transistor 62 includes a second active layer 63 and a second source / drain electrode 64, the second source / drain electrode 64 and the first source / drain electrode 48 being disposed in the same layer and electrically connected to the second active layer 63, the material of the second active layer 63 including polysilicon; the first sub-passivation layer 45a also covers the second source / drain electrode 64.

[0056] It is understandable that the second thin-film transistor 62 can be an LTPS thin-film transistor, that is, the array substrate 40 in the embodiments of this application is an LTPO type array substrate.

[0057] In some embodiments, the second thin-film transistor 62 further includes a third gate 65 and a fourth gate 66 spaced apart from and aligned with the second active layer 63. The third gate 65 is located on the side of the second active layer 63 closer to the substrate layer 43, and the fourth gate 66 is located on the side of the third gate 65 away from the substrate layer 43. The first thin-film transistor 46 includes a gate disposed on the same layer as the third gate 65 or the fourth gate 66. This design can save a metal layer, which helps to simplify the fabrication process of the array substrate 40 and saves fabrication costs.

[0058] In one specific embodiment, the stacked structure 49 includes a first barrier layer 67, a second barrier layer 68, a buffer layer 69, a first gate insulating layer 70, a second gate insulating layer 71, a first interlayer insulating layer 72, a third gate insulating layer 73, and a second interlayer insulating layer 74 stacked on the substrate layer 43.

[0059] Specifically, the second active layer 63 is located between the buffer layer 69 and the first gate insulating layer 70, the third gate 65 is located between the first gate insulating layer 70 and the second gate insulating layer 71, the first gate 50, the fourth gate 66 and the first conductor portion 52 are located between the second gate insulating layer 71 and the first interlayer insulating layer 72, the first active layer 47 is located between the first interlayer insulating layer 72 and the third gate insulating layer 73, the second gate 51 is located between the third gate insulating layer 73 and the second interlayer insulating layer 74, and the first source / drain electrode 48 and the second source / drain electrode 64 are located between the second interlayer insulating layer 74 and the first sub-passivation layer 45a.

[0060] Specifically, the first opening 53 penetrates the first interlayer insulating layer 72, the third gate insulating layer 73, and the second interlayer insulating layer 74, and exposes at least a portion of the first conductor portion 52.

[0061] In some embodiments, the driving circuit layer 44 further includes a light-shielding layer 75 located between the first barrier layer 67 and the second barrier layer 68 and corresponding to the second thin-film transistor 62. The light-shielding layer 75 is used to block external light from entering the second thin-film transistor 62 from the bottom. The material of the light-shielding layer 75 can be a black light-shielding material, such as black light-shielding metal or black organic material.

[0062] In some embodiments, the first active layer 47 includes a first channel portion and first ohmic contact portions located on opposite sides of the first channel portion and disposed in the same layer. The source and drain electrodes of the first source-drain electrodes are electrically connected to the first ohmic contact portions located on opposite sides of the first channel portion, respectively. The second active layer 63 includes a second channel portion and second ohmic contact portions located on opposite sides of the second channel portion and disposed in the same layer. The source and drain electrodes of the second source-drain electrodes are electrically connected to the second ohmic contact portions located on opposite sides of the second channel portion, respectively.

[0063] In some embodiments, the materials of the first interlayer insulating layer 72 and the third gate insulating layer 73 are silicon oxide compounds, which can effectively prevent hydrogen diffusion to the first active layer 47.

[0064] In some embodiments, the material of the second interlayer insulating layer 74 is a silicon oxide compound, which can enhance the barrier effect against hydrogen.

[0065] In some embodiments, the materials of the first barrier layer 67, the second barrier layer 68, the buffer layer 69, the first gate insulating layer 70, and the second gate insulating layer 71 may be silicon nitride compounds, silicon oxide compounds, silicon nitride compounds, or combinations thereof, but are not limited thereto.

[0066] In one specific embodiment, the buffer layer 69 and the first gate insulating layer 70, which are disposed adjacent to the second active layer 63, can be made of silicon nitride compound. Since silicon nitride compounds have a high hydrogen content, they can release hydrogen gas at high temperatures, thereby replenishing hydrogen to the second active layer 63 prepared using low-temperature polycrystalline silicon technology, thus meeting the requirements of low-temperature polycrystalline silicon technology and ensuring the performance of the second active layer 63. Simultaneously, since a first gate 50 and a second gate insulating layer 71 made of silicon oxide compound are also provided between the first active layer 47 and the first gate insulating layer 70, using silicon nitride compound as the material for the first gate insulating layer 70 will not have a negative impact on the first active layer 47.

[0067] In some embodiments, the materials of the first gate 50, the second gate 51, the third gate 65 and the fourth gate 66 may be molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., or alloys of at least two or more metals, or multilayer thin film structures composed of at least two or more metals.

[0068] In some embodiments, the materials of the first source / drain electrode and the second source / drain electrode may be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium trilayer metal, but are not limited thereto.

[0069] In this embodiment, the passivation layer 45 on the driving circuit layer 44 is divided into two layers, such that the passivation layer 45 includes a first sub-passivation layer 45a near the driving circuit layer 44 and a second sub-passivation layer 45b away from the driving circuit layer 44. Since the first sub-passivation layer 45a is disposed in the first region 41 and the second region 42, and the material of the first sub-passivation layer 45a has a low hydrogen content, hydrogen release from the first sub-passivation layer 45a can be avoided or reduced during high-temperature processes, and the first sub-passivation layer 45a can block hydrogen release from the second sub-passivation layer 45b. The released hydrogen diffuses towards the first thin-film transistor 46, thereby avoiding or reducing the negative impact of hydrogen on the electrical properties of the first thin-film transistor 46. Simultaneously, since the second sub-passivation layer 45b is disposed in the second region 42, and the permeability of water in the second sub-passivation layer 45b is less than that in the first sub-passivation layer 45a, when a micro-crack occurs in the second region 42, the second sub-passivation layer 45b located on the outer layer of the second region 42 can effectively block the intrusion of water vapor, preventing water vapor from affecting the threshold voltage of the first thin-film transistor 46. Therefore, the combination of the first sub-passivation layer 45a and the second sub-passivation layer 45b provided in this embodiment can both avoid or reduce the negative impact of hydrogen on the electrical properties of the first thin-film transistor 46 and effectively block the intrusion of water vapor, thereby effectively reducing the reliability risk of the display substrate.

[0070] As shown in Figure 3, this application embodiment also provides a method for fabricating the array substrate 40 described in the foregoing embodiment, the fabrication method including steps S301 to S307.

[0071] S301: A driving circuit layer is formed on a substrate layer; wherein the substrate layer includes a first region and a second region disposed adjacent to each other, the driving circuit layer includes a first thin film transistor and a second thin film transistor located in the first region, and a first conductor portion, a first opening and a first transfer electrode located in the second region, the first conductor portion being exposed in the first opening, and the first transfer electrode being located at least on the sidewall and bottom of the first opening and electrically connected to the first conductor portion.

[0072] As shown in FIG4, the substrate layer 43 includes a first region 41 and a second region 42 disposed adjacent to each other. The driving circuit layer 44 includes a first thin film transistor 46 and a second thin film transistor 62 located in the first region 41, and a first conductor portion 52, a first opening 53 and a first transition electrode 54 located in the second region 42. The first conductor portion 52 is exposed in the first opening 53. The first transition electrode 54 is located at least on the sidewall and bottom of the first opening 53 and is electrically connected to the first conductor portion 52.

[0073] The driving circuit layer 44 also includes a stacked structure 49 located in the first region 41 and the second region 42. The source and drain electrodes of the first thin-film transistor 46 and the second thin-film transistor 62 are located on the stacked structure 49, and a first opening 53 is formed on the side of the stacked structure 49 away from the substrate layer 43. The first transition electrode 54 is disposed in the same layer as the source and drain electrodes of the first thin-film transistor 46 and the second thin-film transistor 62.

[0074] The specific structure of the driving circuit layer 44 can be found in the description of the foregoing embodiments, and will not be repeated here.

[0075] S302: A first sub-passivation layer and a second sub-passivation layer are formed on the entire surface of the driving circuit layer; the first sub-passivation layer continuously covers the first thin film transistor, the second thin film transistor and the first transition electrode, and the second sub-passivation layer completely covers the first sub-passivation layer; the material of the first sub-passivation layer is a silicon oxide compound and the material of the second sub-passivation layer is a silicon nitride compound.

[0076] As shown in Figure 5, the first sub-passivation layer 45a and the second sub-passivation layer 45b sequentially cover the entire surface of the driving circuit layer 44 shown in Figure 4.

[0077] S303: A photoresist layer is formed on the surface of the second sub-passivation layer using a halftone mask; the photoresist layer includes a fourth opening corresponding to the first opening, and the thickness of the photoresist layer in the first region is less than the thickness of the photoresist layer in the second region.

[0078] As shown in Figure 6, the photoresist layer 76 is located on the second sub-passivation layer 45b. The photoresist layer 76 includes a fourth opening 77 corresponding to the first opening 53, and the thickness of the photoresist layer 76 located in the first region 41 is less than the thickness of the photoresist layer 76 located in the second region 42.

[0079] S304: Etch the second sub-passivation layer located in the first opening to remove the second sub-passivation layer located in the first opening.

[0080] As shown in Figure 7, the second sub-passivation layer 45b located in the first opening 53 is etched away through the first etching process, exposing the first sub-passivation layer 45a.

[0081] S305: Ash the photoresist layer and remove the photoresist layer located in the first region.

[0082] As shown in Figure 8, during the ashing process of the photoresist layer 76, the overall thickness of the photoresist layer 76 is reduced until the photoresist layer 76 located in the first region 41 is completely removed, leaving only the photoresist layer 76 located in the second region 42.

[0083] S306: Simultaneously etch the first sub-passivation layer located in the first opening and the second sub-passivation layer located in the first region to remove the first sub-passivation layer located in the first opening and the second sub-passivation layer located in the second region.

[0084] As shown in Figure 9, through the second etching process, the first sub-passivation layer 45a located in the first opening 53 and the second sub-passivation layer 45b located in the second region 42 are removed, exposing the first transfer electrode 54 located in the first opening 53 and the first sub-passivation layer 45a located in the first region 41.

[0085] S307: Remove the photoresist layer located in the second region to form a first sub-passivation layer located in the first region and the second region, and a second sub-passivation layer located in the second region.

[0086] As shown in Figure 10, after removing the photoresist layer 76, a first sub-passivation layer 45a located in the first region 41 and the second region 42 and a second sub-passivation layer 45b located in the second region 42 are formed, and the first sub-passivation layer 45a and the second sub-passivation layer 45b constitute the passivation layer 45.

[0087] As shown in Figure 2, after step S307, the preparation method further includes the following steps:

[0088] The driving circuit layer 44 and the passivation layer 45 are patterned, and the stacked structure 49 and the first sub-passivation layer 45a in the preset area (corresponding to the third area) are removed to form the third opening 61.

[0089] The first leveling layer 57 is laid on the entire surface, and the first leveling layer 57 fills the third opening 61;

[0090] The first planarization layer 57 is patterned, and a portion of the first planarization layer 57 located in the second region 42 is removed, so that the first planarization layer 57 covers the edge of the second sub-passivation layer 45b in the second region 42.

[0091] A second conductor portion 58 is formed on the first planarization layer 57 and a second transfer electrode 56 is formed in the second opening 55; and

[0092] A patterned second planarization layer 59 is formed, such that the second planarization layer 59 covers the first planarization layer 57; the resulting array substrate 40 is shown in Figure 2.

[0093] In this embodiment, the use of halftone masking to fabricate the passivation layer 45 of the array substrate 40 with a double-layer structure can save one photomask process, which helps to simplify the fabrication process of the array substrate 40.

[0094] As shown in FIG11, an embodiment of this application also provides a display panel 80, which includes an array substrate 40 as described in the foregoing embodiment, and a light-emitting layer 78 and an encapsulation layer 79 stacked on the array substrate 40; wherein, the light-emitting layer 78 is located in a first region 41 and is electrically connected to a driving circuit layer 44; the encapsulation layer 79 covers the light-emitting layer 78 and extends from the first region 41 to cover at least part of the array substrate 40 located in a second region 42.

[0095] Specifically, the display panel 80 includes a display area and a non-display area. The display area covers at least the first area 41, and the non-display area covers at least the second area 42. That is, the second area 42 can be a part of the non-display area or the entire non-display area.

[0096] In some embodiments, the light-emitting layer 78 includes an anode layer 81 and a pixel definition layer 82 located on the array substrate 40, a light-emitting functional layer 83 located on the anode layer 81, and a cathode layer 84.

[0097] In some embodiments, the anode layer 81, the light-emitting functional layer 83, and the cathode layer 84 in the light-emitting functional layer 83 constitute a plurality of light-emitting devices, including OLED devices, but not limited thereto.

[0098] Specifically, the pixel definition layer 82 has multiple pixel openings, and the light-emitting functional layer 83 and the cathode layer 84 are stacked on the anode layer 81 in the pixel openings.

[0099] In some embodiments, a support layer is provided on the pixel definition layer 82. The support layer can be formed in the same process as the pixel definition layer 82, for example, the pixel definition layer 82 and the support layer can be made using a halftone mask.

[0100] In some embodiments, the pixel definition layer 82 and the anode layer 81 are disposed on the side of the second planarization layer 59 away from the first planarization layer 57, and the anode layer 81 is electrically connected to the second conductor portion 58 through a via penetrating the second planarization layer 59, thereby realizing electrical connection with the second source / drain electrode 64 of the second thin film transistor 62.

[0101] In some embodiments, the encapsulation layer 79 covers the second planarization layer 59 and the light-emitting layer 78, and the encapsulation layer 79 is located in the first region 41 and extends from the first region 41 to the second region 42.

[0102] In some embodiments, the encapsulation layer 79 includes a thin film encapsulation (TFE) layer, but is not limited thereto.

[0103] In some embodiments, the first planarization layer 57 and the second planarization layer 59 are aligned at their edges in the second region 42, and the edge of the encapsulation layer 79 in the second region 42 is also aligned with the edge of the second planarization layer 59. This design allows the patterning of the first planarization layer 57, the second planarization layer 59, and the encapsulation layer 79 to be completed in the same process.

[0104] In some embodiments, the display panel 80 further includes a touch layer 85 located on the side of the encapsulation layer 79 opposite to the light-emitting layer 78; the touch layer 85 includes at least one touch insulating layer located on the side of the encapsulation layer 79 opposite to the light-emitting layer 78, the touch insulating layer extending from the first region 41 to cover the second sub-passivation layer 45b located in the second region 42; the material of the touch insulating layer is the same as the material of the second sub-passivation layer 45b.

[0105] In one specific embodiment, the touch layer 85 includes a first touch insulating layer 86, a first touch electrode layer 87, a second touch insulating layer 88, a second touch electrode layer 89, and a protective layer 90 stacked on the encapsulation layer 79; wherein the first touch insulating layer 86 and the second touch insulating layer 88 extend from the first region 41 to the second region 42 and are stacked and cover the second sub-passivation layer 45b located in the second region 42; the first touch electrode layer 87 and the second touch electrode layer 89 are located in the first region 41, and the second touch electrode layer 89 is electrically connected to the first touch electrode layer 87 through a via penetrating the second touch insulating layer 88.

[0106] It is understood that the embodiments of this application do not limit the type of touch control, and the above description of the structure of the touch electrode is only an illustrative example.

[0107] In some embodiments, the first touch insulating layer 86 and the second touch insulating layer 88 are made of silicon nitride compound. Since the first touch insulating layer 86 and the second touch insulating layer 88 are located above the passivation layer 45 in the second region 42, and the first touch insulating layer 86 and the second touch insulating layer 88 are made of silicon nitride compound, which has better water-repellent properties, this design can more effectively prevent moisture intrusion.

[0108] In some embodiments, the display panel 80 further includes a third transfer electrode 91 located in the second region 42. The third transfer electrode 91 covers the second transfer electrode 56 and a portion of the second touch insulating layer 88. The third transfer electrode 91 is disposed in the same layer as either the first touch electrode layer 87 or the second touch electrode layer 89. This design allows the edges of the first touch insulating layer 86 and the second touch insulating layer 88 near the second opening 55 to be covered by the third transfer electrode 91, and the edges of the first touch insulating layer 86 and the second touch insulating layer 88 near the second opening 55 are sandwiched between the second transfer electrode 56 and the third transfer electrode 91, further extending the moisture intrusion path and helping to further block moisture intrusion.

[0109] In this embodiment, the first touch insulating layer 86 and the second touch insulating layer 88 of the second region 42 (i.e., the non-display area) of the display panel 80 are sequentially stacked on the second sub-passivation layer 45b. Furthermore, the first touch insulating layer 86, the second touch insulating layer 88, and the second sub-passivation layer 45b are made of the same material, all of which are highly water-resistant materials. This effectively prevents moisture from entering the driving circuit layer 44, avoiding negative impacts on the reliability of the oxide thin-film transistors. Additionally, the first sub-passivation layer 45a is located on the side of the second sub-passivation layer 45b closest to the driving circuit layer 44, and the material of the first sub-passivation layer 45a is a hydrogen-resistant material, effectively preventing negative impacts of hydrogen on the electrical properties of the oxide thin-film transistors. Therefore, the electrical stability of the oxide thin-film transistors in the display panel 80 provided in this embodiment can be greatly improved, and the reliability risk of the panel can be greatly reduced.

[0110] This application also provides a display device, which includes the array substrate 40 described in the above embodiments, or the display device includes the display panel 80 described in the above embodiments.

[0111] In some embodiments, the display device further includes a housing, which is located at least on the side of the substrate layer 43 of the array substrate 40 away from the driving circuit layer 44, or the housing is located at least on the side of the substrate layer 43 of the display panel 80 away from the driving circuit.

[0112] In this embodiment, since the array substrate 40 and display panel 80 provided in the aforementioned embodiments have strong blocking capabilities against hydrogen and water vapor, the performance and reliability of the display device can be effectively improved.

[0113] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0114] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0115] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0116] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, the array substrate having a first region and a second region disposed adjacent to each other; the array substrate comprising: A substrate layer located in the first region and the second region; A driving circuit layer is located on one side of the substrate layer and includes a first thin-film transistor located in the first region; The first thin-film transistor includes a first active layer and a first source / drain electrode that are electrically connected to each other. The first source / drain electrode is located on the side of the first active layer away from the substrate layer. The material of the first active layer is an oxide. A passivation layer is located in the first region and the second region, and is located on the side of the driving circuit layer opposite to the substrate layer; The passivation layer includes a first sub-passivation layer and a second sub-passivation layer; the first sub-passivation layer covers at least the first source / drain electrode and extends from the first region to the second region; the second sub-passivation layer covers the first sub-passivation layer located in the second region; Wherein, the hydrogen atom content in the material of the first sub-passivation layer is less than the hydrogen atom content in the second sub-passivation layer, and the water permeability in the second sub-passivation layer is less than the water permeability in the first sub-passivation layer.

2. The array substrate according to claim 1, wherein, The material of the first sub-passivation layer includes a silicon oxide compound, and the material of the second sub-passivation layer includes a silicon nitride compound.

3. The array substrate according to claim 1, wherein, The driving circuit layer further includes a stacked structure located on the substrate layer, the stacked structure being located in the first region and the second region; the first source / drain electrode is located on the side of the stacked structure facing away from the substrate layer, and the first sub-passivation layer covers the stacked structure and the first source / drain electrode; The stacked structure includes multiple layers of stacked insulating layers, with the first active layer located between two adjacent insulating layers. The insulating layer disposed adjacent to the first active layer is made of a silicon oxide compound.

4. The array substrate according to claim 3, wherein, The insulating layer disposed adjacent to the first sub-passivation layer is made of a silicon oxide compound.

5. The array substrate according to claim 3, wherein, The first thin-film transistor further includes a first gate and a second gate spaced apart from and aligned with the first active layer; the first gate is located on the side of the first active layer close to the substrate layer, and the second gate is located on the side of the first active layer away from the substrate layer. In the stacked structure, at least one insulating layer is located on the side of the second gate away from the first active layer, and the material of the insulating layer located on the side of the second gate away from the first active layer includes any one or more combinations of silicon nitride, silicon oxide, and silicon nitride.

6. The array substrate according to claim 3, wherein, The driving circuit layer further includes a first conductor portion located in the second region, the first conductor portion being located between two adjacent insulating layers in the stacked structure; the stacked structure has a first opening on the side facing away from the substrate layer, and the first conductor portion is at least partially exposed in the first opening; The driving circuit layer further includes a first transition electrode, which is located on the sidewall of the first opening and on the first conductor portion exposed in the first opening, and extends from the sidewall of the first opening to the side of the stacked structure opposite to the substrate layer. The first transfer electrode and the first source / drain electrode are disposed in the same layer; The first sub-passivation layer and the second sub-passivation layer are also stacked sequentially on the first transition electrode located on the side of the stacked structure opposite to the substrate layer.

7. The array substrate according to claim 6, wherein, The first transition electrode forms a second opening in the first opening, and the first sub-passivation layer and the second sub-passivation layer located in the second region are disposed around the second opening; the driving circuit layer further includes a second transition electrode, which is located on the first transition electrode exposed by the second opening, and extends from the sidewall of the second opening to the side of the second sub-passivation layer opposite to the substrate layer.

8. The array substrate according to claim 7, wherein, The array substrate further includes a first planarization layer, a second conductor portion, and a second planarization layer located in the first region and stacked on the side of the passivation layer opposite to the substrate layer; the first planarization layer covers the first source / drain electrode and the first sub-passivation layer, and extends from the first region to cover a portion of the second sub-passivation layer; the second conductor portion is located on the first planarization layer and is electrically connected to the driving circuit layer; the second planarization layer covers the second conductor portion and the first planarization layer; the second transition electrode and the second conductor portion are disposed in the same layer; The array substrate further includes a third region disposed adjacent to the first region and a third opening located in the third region; the third opening at least penetrates the stacked structure and the first sub-passivation layer; the first planarization layer further extends from the first region to the third region and fills the third opening; the second planarization layer further extends from the first region to the third region.

9. The array substrate according to any one of claims 1 to 8, wherein, The driving circuit layer further includes a second thin-film transistor located in the first region, the second thin-film transistor and the first thin-film transistor being disposed at intervals; the second thin-film transistor includes a second active layer and a second source / drain electrode, the second source / drain electrode and the first source / drain electrode being disposed in the same layer and electrically connected to the second active layer, the material of the second active layer including polycrystalline silicon; the first sub-passivation layer also covers the second source / drain electrode.

10. The array substrate according to claim 9, wherein, The second thin-film transistor further includes a third gate and a fourth gate spaced apart from and aligned with the second active layer, wherein the third gate is located on the side of the second active layer closer to the substrate layer, and the fourth gate is located on the side of the third gate away from the substrate layer. The first thin-film transistor includes a gate disposed in the same layer as the third gate or the fourth gate.

11. The array substrate according to claim 10, wherein, The stacked structure includes a first barrier layer, a second barrier layer, a buffer layer, a first gate insulating layer, a second gate insulating layer, a first interlayer insulating layer, a third gate insulating layer, and a second interlayer insulating layer stacked on the substrate layer. The second active layer is located between the buffer layer and the first gate insulating layer, the third gate is located between the first gate insulating layer and the second gate insulating layer, the fourth gate is located between the second gate insulating layer and the first interlayer insulating layer, the first active layer is located between the first interlayer insulating layer and the third gate insulating layer, and the first source / drain electrode and the second source / drain electrode are located between the second interlayer insulating layer and the first sub-passivation layer.

12. The array substrate according to claim 11, wherein, The driving circuit layer further includes a light-shielding layer located between the first barrier layer and the second barrier layer and disposed corresponding to the second thin-film transistor.

13. The array substrate according to claim 11, wherein, The materials of the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer are silicon oxide compounds.

14. The array substrate according to claim 11, wherein, The materials of the first barrier layer, the second barrier layer, the buffer layer, the first gate insulating layer, and the second gate insulating layer are selected from at least one of silicon nitride, silicon oxide, and silicon nitride.

15. The array substrate according to claim 14, wherein, The buffer layer and the first gate insulating layer, which are disposed adjacent to the second active layer, are made of silicon nitrogen compound.

16. A display panel comprising the array substrate of claim 1, wherein the display panel further comprises a light-emitting layer and an encapsulation layer stacked on the array substrate; The light-emitting layer is located in the first region and is electrically connected to the driving circuit layer; the encapsulation layer covers the light-emitting layer and extends from the first region to cover at least part of the array substrate located in the second region.

17. The display panel according to claim 16, wherein, The display panel further includes a touch layer located on the side of the encapsulation layer opposite to the light-emitting layer; the touch layer includes at least one touch insulating layer located on the side of the encapsulation layer opposite to the light-emitting layer, the touch insulating layer extending from the first region to cover the second sub-passivation layer located in the second region; the material of the touch insulating layer is the same as the material of the second sub-passivation layer.

18. The display panel according to claim 17, wherein, The touch layer includes a first touch insulating layer, a first touch electrode layer, a second touch insulating layer, a second touch electrode layer, and a protective layer stacked on the encapsulation layer; The first touch insulating layer and the second touch insulating layer extend from the first region to the second region and are stacked on the second sub-passivation layer located in the second region; the first touch electrode layer and the second touch electrode layer are located in the first region, and the second touch electrode layer is electrically connected to the first touch electrode layer through a via penetrating the second touch insulating layer.

19. The display panel according to claim 16, wherein, The material of the first sub-passivation layer includes a silicon oxide compound, and the material of the second sub-passivation layer includes a silicon nitride compound.

20. A display device comprising the display panel of claim 16.

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