PCB layout open circuit and short circuit positioning method

Abstract

A PCB layout open circuit and short circuit positioning method, comprising: acquiring files of a PCB layout to be inspected; and acquiring original CAD data as a comparison PCB layout file (S1); by comparing the files of the PCB layout to be inspected with the comparison PCB layout file, using image pixel continuity to search for a difference position (S3); and on the basis of the difference position, determining an open circuit position and a short circuit position in the PCB layout to be inspected (S4). According to the method, an image of the difference position can be used to determine image continuity on the comparison PCB layout file so as to obtain the open circuit position, and determine image continuity on the files of the PCB layout to be inspected so as to obtain the short circuit position, thereby accurately obtaining specific positions of the open and short circuits. Compared with manual inspection, the method is free from errors and omissions inherent in manual detection, has high accuracy and short processing time, improves inspection efficiency, can avoid unnecessary rework and loss during PCB manufacturing, significantly shortens PCB manufacturing time, and reduces cost investment.

Description

A method for locating open and short circuits in PCB layout Technical Field

[0001] This invention belongs to the field of printed circuit board technology, specifically relating to a method for locating open and short circuits in a PCB layout. Background Technology

[0002] With the continuous development of technology and the improvement of manufacturing processes, electronic products are trending towards lighter, thinner, and smaller sizes. Printed Circuit Boards (PCBs) are evolving towards higher density, smaller components, finer pitch, and more layers, making PCB quality inspection increasingly challenging. Before PCB manufacturing, customers need to provide PCB design files or Gerber files for production use. However, when PCB design files are converted to different Gerber file formats, or when the PCB manufacturer processes the Gerber files to meet design requirements, errors can easily occur in the converted or processed Gerber files, leading to open or short circuits in the PCB circuitry. Currently, this is addressed manually by comparing the Gerber files with the original PCB design files. When there are many components on the PCB, locating open or short circuits becomes more complex and tedious, time-consuming, and inefficient. While some software on the market can identify network cells with open or short circuits in Gerber files through network connections, it cannot pinpoint the exact location of the open or short circuit, still requiring manual intervention. Therefore, the ability to quickly and accurately locate open and short circuits in PCB engineering data is crucial for PCB manufacturing.

[0003] Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a method for locating open and short circuits in a PCB layout. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a method for locating open circuits in a PCB layout, the method comprising:

[0006] Obtain the Gerber file, drill file, and IPC netlist file of the PCB layout to be inspected as the PCB layout file to be inspected; obtain the original CAD data of the PCB layout to be inspected as the comparison PCB layout file.

[0007] The signal network group with open circuits in the PCB layout file to be checked is selected as the target signal network group to be checked; the signal network at the same position in the comparison PCB layout file corresponding to the target signal network group to be checked is selected as the comparison target signal network.

[0008] Acquire the target signal network group image and the comparison target signal network image, and obtain the difference positions between the target signal network group image and the comparison target signal network image based on the continuity of image pixels;

[0009] The location of the open circuit in the PCB layout to be inspected is determined based on the location of the difference.

[0010] In one embodiment of the present invention, determining the open circuit location in the PCB layout to be inspected based on the difference location includes:

[0011] For any discrepancy location, the image of the discrepancy location is removed from the comparison target signal network image. When the discrepancy location is connected to two or more target signal networks, the open circuit location in the PCB layout to be inspected is determined by judging the signal connectivity between the obtained target signal networks.

[0012] In one embodiment of the present invention, for any difference location, the image of the difference location is removed from the comparison target signal network image. When the difference location is connected to two or more target signal networks, the open circuit location in the PCB layout to be inspected is determined by judging the signal connectivity between the obtained target signal networks, including:

[0013] In the comparison PCB layout file, determine the PCB layer where the difference location is located. In the PCB layer where the difference location is located, remove the image of the difference location from the comparison target signal network image to obtain the images of each target signal network originally connected to the difference location.

[0014] The PCB layer from the location of the difference to the last PCB layer of the signal network where the difference is located are sequentially used as the current layer for the judgment step. The judgment step includes determining whether each target signal network satisfies the requirement of having signal connection in the current layer based on the pixel continuity of the image of each target signal network.

[0015] If the condition is met, it is determined that the location of the difference is not an open circuit location in the PCB layout to be inspected;

[0016] If the condition is not met, two target signal networks that do not have signal connections in the current layer are identified as target signal network pairs. Based on the difference in position between the target signal network pairs, the open circuit position of the PCB layout to be inspected is determined.

[0017] In one embodiment of the present invention, when the image of the difference location is removed from the comparison target signal network image, and the difference location is connected to only two target signal networks, determining the open circuit location in the PCB layout to be inspected based on the difference location includes:

[0018] Locate the undetermined open circuit location in the PCB layout file to be checked within the difference location;

[0019] Measure the distance between any endpoint of the undetermined open-circuit location and other endpoints in the open-circuit signal network group of the layer in which it is located;

[0020] Determine the minimum value among all distances, and identify the two endpoints corresponding to the minimum value as the open path positions.

[0021] This invention also provides a PCB layout open circuit positioning device, the PCB layout open circuit positioning device comprising:

[0022] The file acquisition module is used to acquire the Gerber file, drill file, and IPC netlist file of the PCB layout to be inspected, as the PCB layout file to be inspected; and to acquire the original CAD data of the PCB layout to be inspected, as the comparison PCB layout file.

[0023] The module for acquiring the target signal network group to be checked and the module for acquiring the target signal network to be compared are used to acquire the signal network group with open circuits in the PCB layout file to be checked, as the target signal network group to be checked; and to acquire the signal network at the same position in the PCB layout file to be compared, which corresponds to the target signal network group to be checked, as the target signal network to be compared.

[0024] The difference location acquisition module is used to acquire the image of the target signal network group to be investigated and the image of the comparison target signal network, and to obtain the difference location between the image of the target signal network group to be investigated and the image of the comparison target signal network based on the continuity of the image pixels;

[0025] An open circuit location module is used to determine the open circuit location in the PCB layout to be inspected based on the difference location.

[0026] This invention also provides a PCB layout short circuit location method, the PCB layout short circuit location method comprising:

[0027] Obtain the Gerber file, drill file, and IPC netlist file of the PCB layout to be inspected as the PCB layout file to be inspected; obtain the original CAD data of the PCB layout to be inspected as the comparison PCB layout file.

[0028] The signal network with a short circuit in the PCB layout file to be checked is obtained as the target signal network to be checked; the signal network group corresponding to the target signal network to be checked at the same position in the comparison PCB layout file is obtained as the comparison target signal network group.

[0029] Acquire the target signal network image to be investigated and the comparison target signal network group image, and obtain the difference positions between the target signal network image to be investigated and the comparison target signal network group image based on the continuity of image pixels;

[0030] The location of the short circuit in the PCB layout to be inspected is determined based on the location of the difference.

[0031] In one embodiment of the present invention, determining the short circuit location in the PCB layout to be inspected based on the difference location includes:

[0032] For any discrepancy location, the image at that discrepancy location is removed from the image of the target signal network to be inspected. When the discrepancy location is connected to two or more target signal networks, the short circuit location in the PCB layout to be inspected is determined by judging the signal connectivity between the obtained target signal networks.

[0033] In one embodiment of the present invention, for any discrepancy location, the image at that discrepancy location is removed from the image of the target signal network to be inspected. When the discrepancy location is connected to two or more target signal networks, the short circuit location in the PCB layout to be inspected is determined by judging the signal connectivity between the obtained target signal networks, including:

[0034] In the PCB layout file to be checked, determine the PCB layer where the difference is located. In the PCB layer where the difference is located, remove the image of the difference location from the image of the target signal network to be checked to obtain the images of each target signal network originally connected to the difference location.

[0035] The PCB layer from the location of the difference to the last PCB layer of the signal network where the difference is located are sequentially used as the current layer for the judgment step. The judgment step includes determining whether each target signal network satisfies the requirement of having signal connection in the current layer based on the pixel continuity of the image of each target signal network.

[0036] If the condition is met, it is determined that the location of the difference is not a short circuit location in the PCB layout to be inspected;

[0037] If the condition is not met, two target signal networks that do not have signal connections in the current layer are identified as target signal network pairs. Based on the difference in position between the target signal network pairs, the short circuit location of the PCB layout to be inspected is determined.

[0038] This invention also provides a PCB layout short-circuit locating device, the PCB layout short-circuit locating device comprising:

[0039] The file acquisition module is used to acquire the Gerber file, drill file, and IPC netlist file of the PCB layout to be inspected, as the PCB layout file to be inspected; and to acquire the original CAD data of the PCB layout to be inspected, as the comparison PCB layout file.

[0040] The module for acquiring the target signal network to be checked and the comparison target signal network group is used to acquire the signal network with a short circuit in the PCB layout file to be checked as the target signal network to be checked; and to acquire the signal network group at the same position in the comparison PCB layout file corresponding to the target signal network to be checked as the comparison target signal network group.

[0041] The difference location acquisition module is used to acquire the target signal network image to be investigated and the comparison target signal network group image, and to obtain the difference location between the target signal network image to be investigated and the comparison target signal network group image based on the continuity of image pixels;

[0042] A short-circuit location module is used to determine the short-circuit location in the PCB layout to be inspected based on the difference location.

[0043] This invention also provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0044] The memory is used to store computer programs;

[0045] When the processor executes the program stored in the memory, it implements the steps of the PCB layout open circuit positioning method or the PCB layout short circuit positioning method provided in the embodiments of the present invention.

[0046] This invention also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the steps of the PCB layout open circuit positioning method or the PCB layout short circuit positioning method provided in this invention.

[0047] The beneficial effects of this invention are:

[0048] In the solution provided by the embodiments of the present invention, the Gerber file, drill file and IPC netlist file of the PCB layout to be inspected are first obtained as the PCB layout file to be inspected; the original CAD data of the PCB layout to be inspected is obtained as the comparison PCB layout file.

[0049] For open circuit location, the signal network group containing an open circuit in the PCB layout file to be inspected is obtained as the target signal network group to be inspected; the signal network at the same position in the comparison PCB layout file corresponding to the target signal network group to be inspected is obtained as the comparison target signal network; then, the image of the target signal network group to be inspected and the image of the comparison target signal network are obtained, and the difference position between the image of the target signal network group to be inspected and the image of the comparison target signal network are obtained according to the continuity of the image pixels; finally, the open circuit position in the PCB layout to be inspected is determined based on the difference position.

[0050] For short circuit location, the signal network with a short circuit in the PCB layout file to be inspected is obtained as the target signal network to be inspected; the signal network group at the same position in the comparison PCB layout file corresponding to the target signal network to be inspected is obtained as the comparison target signal network group; then, the image of the target signal network to be inspected and the image of the comparison target signal network group are obtained, and the difference position between the image of the target signal network to be inspected and the image of the comparison target signal network group are obtained according to the continuity of the image pixels; finally, the short circuit position in the PCB layout to be inspected is determined based on the difference position.

[0051] This invention compares a PCB layout file to be inspected with a comparison PCB layout file, using the continuity of image pixels to find differences, and then determines the locations of open and short circuits in the PCB layout to be inspected based on these differences. This invention can use the images at the differences to determine the location of open circuits by judging image continuity in the comparison PCB layout file, and to determine the location of short circuits by judging image continuity in the PCB layout file to be inspected, thus accurately determining the specific locations of open and short circuits.

[0052] Gerber files can be effectively checked before PCB manufacturing. Compared with manual inspection, the solution proposed in this application can greatly improve the accuracy, shorten the inspection time, improve the inspection efficiency, avoid unnecessary rework and loss in the PCB manufacturing process, effectively reduce the workload of PCB quality inspection and analysis, greatly reduce the scrap rate of PCB finished products, improve production efficiency, and reduce cost input. Attached Figure Description

[0053] Figure 1 is a flowchart illustrating a PCB layout open-circuit positioning method provided in an embodiment of the present invention;

[0054] Figures 2a and 2b are schematic diagrams showing the connection between the difference location and two or more target signal networks in the open-circuit positioning of the present invention.

[0055] Figure 3 is a schematic diagram showing the continuity of the images in the current layer in the first target signal network image and the second target signal network image during open-circuit localization in an embodiment of the present invention.

[0056] Figure 4 is a schematic diagram showing the continuity of the next layer image in open-circuit positioning according to an embodiment of the present invention, when there are vias at both ends of the first target signal network image and the second target signal network image.

[0057] Figure 5 is a schematic diagram of the difference location and its image when the difference location is connected to more than two target signal networks in the open-circuit positioning of an embodiment of the present invention.

[0058] Figure 6 is a schematic diagram of open-circuit positioning achieved by measuring distance in an embodiment of the present invention;

[0059] Figure 7 is a schematic diagram of how open-circuit localization is achieved by placing images of the differences in the target signal network image into the undetermined open-circuit position in an embodiment of the present invention;

[0060] Figure 8 is a flowchart illustrating a PCB layout short-circuit location method provided in an embodiment of the present invention;

[0061] Figure 9 is a schematic diagram showing the continuity of the images in the current layer in the third target signal network image and the fourth target signal network image during short-circuit localization in an embodiment of the present invention;

[0062] Figure 10 is a schematic diagram showing the continuity of the next layer image when there are vias at both ends of the third target signal network image and the fourth target signal network image in the short-circuit localization of the present invention.

[0063] Figure 11 is a schematic diagram of the difference location and its image when the difference location is connected to more than two target signal networks in the short-circuit localization of an embodiment of the present invention. Detailed Implementation

[0064] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0065] To quickly and accurately locate open and short circuits in a PCB layout and improve inspection efficiency, this invention provides a PCB layout open circuit location method, a PCB layout open circuit location device, a PCB layout short circuit location method, a PCB layout short circuit location device, as well as an electronic device and a computer-readable storage medium for implementing the PCB layout open circuit location method or the PCB layout short circuit location method.

[0066] In a first aspect, embodiments of the present invention provide a PCB layout open circuit positioning method, as shown in FIG1, which may include the following steps:

[0067] S1. Obtain the Gerber file, drill file, and IPC netlist file of the PCB layout to be inspected, as the PCB layout file to be inspected; obtain the original CAD data of the PCB layout to be inspected, as the comparison PCB layout file.

[0068] As will be understood by those skilled in the art, a Gerber file, or photoplotting file, is the output of the circuit design process, including the physical properties of the PCB layers and the PCB layers themselves. A drill file, or drill hole file, contains drill hole information on the PCB, used to identify the size and location of drill holes. An IPC (Institute of Printed Circuits) netlist file is a collection of nets that records the logical relationships between various parts of the design file. It can be used to display individual signal nets and to check for open circuits, short circuits, and issues with trace spacing on the PCB.

[0069] In this embodiment of the invention, the PCB layout file to be compared is the original design data of the PCB layout file to be checked, i.e., the original design CAD file, which is usually provided by the PCB designer. The PCB layout file to be checked is a file of a different format than the PCB layout file to be compared. Due to the different file formats, some errors may occur in the PCB design data output from the PCB routing software, resulting in the designed layout being different from the original netlist connectivity, forming open circuits or short circuits. Moreover, based on the manufacturing process of bare PCBs, bare PCB manufacturers will make appropriate modifications to the PCB design data (e.g., Gerber files) before bare PCB manufacturing so that the actual manufactured bare PCB can meet the design functions. However, the modification process may cause open circuits or short circuits. Therefore, before using the PCB layout file to be checked for board fabrication, it is necessary to use the PCB layout file to be compared as a reference for inspection.

[0070] To ensure the accuracy and consistency of the obtained PCB layout files for comparison, the number of PCB layers can be used for verification. If the number of layers is the same as that of the PCB layout file to be checked, it indicates that the obtained comparison PCB layout file is consistent with the PCB file to be checked, meaning that the exported file of the comparison PCB layout file is the PCB file to be checked. Of course, file identification information can also be used for auxiliary verification, such as file name, number, etc.

[0071] S2, obtain the signal network group with open circuits in the PCB layout file to be checked, as the target signal network group to be checked; obtain the signal network in the same position in the comparison PCB layout file corresponding to the target signal network group to be checked, as the comparison target signal network;

[0072] This invention can employ existing PCB layout open-circuit checking methods to obtain all signal network groups with open circuits in the PCB layout file to be checked, which are denoted as the target signal network groups to be checked. One optional method can be implemented with reference to patent CN201811407159.X, where the netlist network groups with open circuit problems identified by that patent are the target signal network groups to be checked in this invention. Each target signal network group to be checked contains at least two signal networks due to the presence of open circuits. In this invention, a signal network refers to a network where the signal transmission line has connectivity and does not contain any components.

[0073] For each target signal network group to be investigated, the signal network at the same position in the comparison PCB layout file corresponding to the target signal network group to be investigated can be obtained through location information. This network is then used as the comparison target signal network for that target signal network group. Since the comparison target signal network does not have any open circuits, it is a complete signal network. In this embodiment of the invention, each target signal network group to be investigated is processed separately. S2 to S4 are described using any one target signal network group to be investigated.

[0074] S3, acquire the image of the target signal network group to be investigated and the image of the target signal network to be compared, and obtain the difference position between the image of the target signal network group to be investigated and the image of the target signal network to be compared based on the continuity of image pixels;

[0075] The image of the target signal network group to be investigated refers to the image corresponding to the target signal network group to be investigated. The image of the target signal network to be compared refers to the image corresponding to the target signal network to be compared. The difference location is the suspected location of an open circuit in the same layer of the PCB conductor.

[0076] Among them, the image of the target signal network group to be investigated and the image of the target signal network to be compared may have multiple differences, and the differences are determined by the coordinates of each endpoint and the PCB layer in which they are located.

[0077] In this embodiment of the invention, the difference location is only found in the case of an open circuit in the middle of the same layer of conductors, and does not involve an open circuit between the endpoint and the next layer.

[0078] S4, determine the open circuit location in the PCB layout to be inspected based on the difference location.

[0079] In one optional implementation, S4 may include the following steps:

[0080] S41, for any difference location, remove the image of the difference location from the comparison target signal network image. When the difference location is connected to two or more target signal networks, determine the open circuit location in the PCB layout to be inspected by judging the signal connectivity between the obtained target signal networks.

[0081] In this embodiment of the invention, for any discrepancy location, the image of the discrepancy location is first removed from the comparison target signal network image. This results in the original signal network in the comparison target signal network image being split into several target signal networks after the image of the discrepancy location is removed. When the discrepancy location is connected to two or more target signal networks, the open circuit location in the PCB layout to be inspected is determined by judging the signal connectivity between the obtained target signal networks. For an understanding of the discrepancy location being connected to two or more target signal networks, please refer to Figures 2a and 2b. Figures 2a and 2b use long rectangular bars to represent signal traces in the signal network and do not show components. Figure 2a shows the discrepancy location connected to two target signal networks (each of the long rectangular bars on the left and right sides represents one target signal network), and Figure 2b shows the discrepancy location connected to more than two target signal networks. Figure 2b uses the discrepancy location connected to three target signal networks as an example (each of the long rectangular bars on the left, right, and bottom sides represents one target signal network).

[0082] In this embodiment of the invention, the image of the difference location is a wire or a via with an electrical connection, and S4 is executed sequentially for each difference location.

[0083] In one optional implementation, S41 may include the following steps:

[0084] S411, determine the PCB layer where the difference location is located in the comparison PCB layout file, and remove the image of the difference location in the comparison target signal network image in the PCB layer where the difference location is located, to obtain the images of each target signal network originally connected to the difference location;

[0085] In this embodiment of the invention, steps S411 to S414 are performed in the comparison PCB layout file. Regarding S411, it can be understood that after removing the difference location, the original comparison target signal network is split into two or more target signal networks, and images of each target signal network can be obtained.

[0086] In S411, based on the endpoint coordinates and the PCB layer in which they are located, the PCB layer in which the difference is located can be determined in the comparison PCB layout file.

[0087] S412, the PCB layer where the difference location is located to the last PCB layer of the signal network where the difference location is located are sequentially used as the current layer for the judgment step. The judgment step includes determining whether each target signal network satisfies the requirement of having signal connection in the current layer based on the pixel continuity of the image of each target signal network.

[0088] Since signal networks can be connected on different PCB layers, the judgment steps need to be performed layer by layer.

[0089] Each target signal network satisfies the requirement of having signal connections at the current layer, including:

[0090] In the images of each target signal network, the images in the current layer are all consecutive.

[0091] Specifically, in the images of each target signal network, the fact that the images in the current layer are consecutive in pairs is used as a direct condition to determine that the current layer has signal connections.

[0092] If there are only two target signal networks, the above condition is that the images of these two target signal networks in the current layer are continuous; if there are more than two target signal networks, the above condition is that the images of every two target signal networks in the current layer are continuous.

[0093] In the above conditions, the continuity of two images in the current layer is determined by the continuity of image pixels. When they belong to the same signal network, the colors of the signal wiring are the same. If the two images to be judged are in the current layer and are connected by other signal lines except for the difference position, then it can be directly determined that the two images to be judged are continuous in the current layer.

[0094] If the above conditions are not met, it is necessary to further use the vias in the image to determine whether each target signal network may have a signal connection in the next layer. If it is possible that there is a signal connection in the next layer, the next layer is used as the current layer and the judgment step is executed again until the last PCB layer of the signal network where the difference is located is judged.

[0095] S413, if satisfied, determine that the difference location is not an open circuit location of the PCB layout to be inspected;

[0096] If the above conditions are met, it can be directly determined that each target signal network has a signal connection in the current layer, and the difference location is not an open circuit location of the PCB layout to be inspected.

[0097] S414, if not satisfied, determine the two target signal networks that do not have signal connections in the current layer as target signal network pairs, and determine the open circuit position of the PCB layout to be inspected based on the difference position between the target signal network pairs.

[0098] Specifically, S414 may include the following steps:

[0099] Step 1), identify two target signal networks that do not have signal connections in the current layer as target signal network pairs;

[0100] In the images of each target signal network, if there are two discontinuous target signal networks in the current layer, they are identified as a target signal network pair.

[0101] Step 2), determine whether there are vias at both ends of the image in the current layer of the target signal network;

[0102] Here, the via refers to a via that has an electrical connection;

[0103] Step 3): If the target signal network pair has no vias at either end of the image in the current layer, or has a via at only one end of any image, the difference position between the target signal network pairs is determined as the open circuit position.

[0104] If the target signal network pair has no vias at either end of the image in the current layer, or has a via at only one end of the image, it indicates that the target signal network pair definitely does not have a signal connection, and the difference position between the target signal network pairs is determined as the open circuit position.

[0105] Step 4): If the target signal network has vias at both ends of the image in the current layer, the next layer after the current layer is recorded as the current layer, and the process returns to the judgment step.

[0106] If the target signal network pair has vias at both ends of the image in the current layer, it indicates that the target signal network pair may have signal connections in the next layer, so it needs to be judged again.

[0107] After the judgment is completed, the open circuit positions of the PCB layout file to be checked are determined by the difference positions between all target signal network pairs.

[0108] For ease of understanding, the process of S41 will be described below with the difference location connected to only two target signal networks. This process may include the following steps:

[0109] Step a1: Determine the PCB layer where the difference is located in the compared PCB layout file, and use it as the current layer;

[0110] Step a2: Remove the image at the difference position in the comparison target signal network image to obtain the images of the first target signal network and the second target signal network that were originally connected to the difference position, and use them as the first target signal network image and the second target signal network image, respectively.

[0111] Step a3: Determine whether the images in the current layer of the first target signal network image and the second target signal network image are continuous based on the continuity of image pixels;

[0112] The first target signal network image and the second target signal network image are continuous in the current layer, as can be understood with reference to Figure 3. In Figure 3, PCB1 is the PCB layout file to be checked, and PCB2 is the PCB layout file to be compared. Figure 3 shows signal networks but does not contain components. It can be seen that PCB1 has an open circuit, which is the difference position in PCB2. After removing this difference position in the comparison target signal network image of PCB2, the target signal network images on the left and right sides can still be connected through a signal line located above the difference position in Figure 3. These two target signal network images are still continuous in the current layer, therefore, these two target signal networks have a signal connection in the current layer.

[0113] Step a4: If the images of the first target signal network image and the second target signal network image are continuous in the current layer, it indicates that the first target signal network and the second target signal network have signal connection in the current layer. Then, it is determined that the difference position is not the open circuit position of the PCB layout to be inspected.

[0114] Step a5: If the images in the current layer of the first target signal network image and the second target signal network image are discontinuous, determine whether there are vias at both ends of the first target signal network image and the second target signal network image;

[0115] Step a6: If neither the first target signal network image nor the second target signal network image has a via, or if only one end of either the first target signal network image or the second target signal network image has a unique via, then the difference location is determined to be the open circuit location of the PCB layout to be inspected.

[0116] Step a7: If there are vias at both ends of the first target signal network image and the second target signal network image, take the next layer of the current layer as the current layer, return to step a3, and continue until the last PCB layer of the signal network where the difference is located is determined.

[0117] When both ends of the first target signal network image and the second target signal network image have vias, please refer to Figure 4 for understanding the continuity of the next layer image. As can be seen from Figure 4, PCB2 achieves image continuity in the (n-1)th layer.

[0118] When the location of the difference is connected to more than two target signal networks, the process in S41 is similar to the process described above, and this process may include the following steps:

[0119] Step b1: Determine the PCB layer where the difference is located in the comparison PCB layout file, and use it as the current layer;

[0120] Step b2: Remove the image at the difference location from the image of the target signal network to obtain the images of the multiple target signal networks that were originally connected to the difference location.

[0121] Please refer to Figure 5 to understand the difference location and its image. Figure 5 shows an example of the difference location connected to a network of three target signals.

[0122] Step b3: Based on the continuity of image pixels, determine whether the images in the current layer of each of the multiple target signal networks are all consecutive in pairs;

[0123] Pairwise continuity means that the images of each pair of target signal networks are continuous in the current layer.

[0124] Step b4: If the images of the multiple target signal networks in the current layer are all consecutive in pairs, it means that the multiple target signal networks have signal connections in the current layer. Then, it is determined that the difference position is not the open circuit position of the PCB layout to be inspected.

[0125] Step b5: If there are two discontinuous target signal networks in the current layer of the image of each of the multiple target signal networks, the two discontinuous target signal networks are taken as a target signal network pair, and it is determined whether there are vias at both ends of the target signal network pair in the current layer image.

[0126] Step b6: If there are no vias at either end of the image of the target signal network pair, or only one via exists at one end of any image, determine the difference location as the open circuit location of the PCB layout to be inspected.

[0127] Step b7: If there are vias at both ends of the image of the target signal network pair, take the next layer of the current layer as the current layer, return to step b3, and continue until the last PCB of the signal network where the difference is located is determined.

[0128] In the above embodiments, for any discrepancy location, processing is performed in the comparison PCB layout file. The image of the discrepancy location is removed from the comparison target signal network image. When the discrepancy location is connected to two or more target signal networks, the open circuit location in the PCB layout to be inspected is determined by judging the signal connectivity between the obtained target signal networks. This embodiment compares the PCB layout file to be inspected with the comparison PCB layout file, which serves as the original CAD data, to find discrepancies. The open circuit location is obtained by judging the image continuity in the comparison PCB layout file. This can accurately obtain the specific location of open and short circuits. Compared with manual inspection, there are no errors or omissions that exist in manual inspection. The accuracy rate is high and the time is short, which improves the efficiency of inspection, avoids unnecessary rework and losses in the PCB manufacturing process, greatly shortens the PCB manufacturing time, reduces cost investment, and effectively realizes the automated detection of open circuit locations.

[0129] In one optional implementation, for S4, when, after removing the image at the difference location from the comparison target signal network image, the difference location is connected to only two target signal networks, determining the open circuit location in the PCB layout to be inspected based on the difference location may include:

[0130] S421, Locate the undetermined open circuit location in the PCB layout file to be checked in the difference location;

[0131] The principles for determining the locations of potential openings can be established by designers based on their experience. Generally speaking, when faced with multiple differing locations, designers, combining their own experience, can identify some of the more likely opening locations as potential locations.

[0132] S422, Measure the distance between any endpoint of the undetermined open-circuit position and other endpoints in the open-circuit signal network group of the layer in which it is located;

[0133] S423, determine the minimum value among all distances, and identify the two endpoints corresponding to the minimum value as open-path positions.

[0134] Please refer to Figure 6 for understanding. Figure 6 is a schematic diagram of open circuit positioning achieved by measuring distance in an embodiment of the present invention. In Figure 6, the area between A and B is the undetermined open circuit position, and A and B are its two endpoints. The lines where C and D are located are the remaining signal networks in the open circuit signal network group of the layer where the undetermined open circuit position is located. For ease of understanding, the position of the device is illustrated by a diode in this figure, and CD are the endpoints at both ends of the device. In this embodiment of the present invention, the distance between any endpoint of the undetermined open circuit position and other endpoints in the open circuit signal network group of the layer is measured. The other endpoints referred to are the two endpoints of the device on the signal wiring in the open circuit signal network group of the layer where the undetermined open circuit position is located, such as the endpoints C and D mentioned above. Taking A as an example, this embodiment of the present invention can calculate the distance between A and B, the distance between A and C, and the distance between A and D. Generally, the open circuit position is very short. Therefore, the shortest of the three calculated distances should be the open circuit position. The two endpoints AB corresponding to the minimum distance are determined as the open circuit position.

[0135] This implementation method can also accurately achieve automated detection of open-circuit locations by calculating distances.

[0136] In one optional implementation, S4 may include the following steps:

[0137] S431, Locate the undetermined open circuit location in the PCB layout file to be checked in the difference location;

[0138] S432, the image of the difference position in the comparison target signal network image is placed at the undetermined open circuit position. If the image of the difference position is connected to the surrounding signal network of the undetermined open circuit position, and the image of the difference position and the surrounding signal network of the undetermined open circuit position form the same signal network as the comparison target signal network image in the PCB layout file to be checked, then the undetermined open circuit position is determined to be an open circuit position.

[0139] This implementation achieves open circuit location by placing the image of the difference position in the comparison target signal network image at the undetermined open circuit position. As can be understood from Figure 7, the image of the difference position in PCB2 is placed at the undetermined open circuit position in PCB1. If the signal network around the undetermined open circuit position on PCB1 can be connected by the image of the difference position, and the signal network formed after the connection is the same as the signal network in PCB2, then it indicates that the undetermined open circuit position is indeed an open circuit position.

[0140] Similarly, in an alternative implementation, S4 may include the following steps:

[0141] S441, Locate the undetermined open circuit location in the PCB layout file to be checked in the difference location;

[0142] S442, connect the two endpoints of the undetermined open circuit position to connect the different signal networks around the undetermined open circuit position. If the connection forms the same signal network in the PCB layout file to be checked as in the comparison PCB layout file, then the undetermined open circuit position is determined to be an open circuit position.

[0143] This implementation method is similar to the previous one. It connects the two endpoints of the undetermined open circuit position on PCB1, so that different signal networks around the undetermined open circuit position are connected. It is then determined whether the connected signal network is the same as the signal network in PCB2. If they are the same, it means that the undetermined open circuit position is indeed an open circuit position.

[0144] Compared to the previous implementation methods, the two implementation methods are similar and can also accurately achieve automated detection of open circuit locations.

[0145] Secondly, embodiments of the present invention also provide a PCB layout short-circuit location method, as shown in Figure 8, which includes the following steps s1 to s4. To distinguish it from the steps of the PCB layout open-circuit location method, the step numbers of the PCB layout short-circuit location method are in lowercase. Specifically:

[0146] s1. Obtain the Gerber file, drill file, and IPC netlist file of the PCB layout to be inspected, as the PCB layout file to be inspected; Obtain the original CAD data of the PCB layout to be inspected, as the comparison PCB layout file.

[0147] Please refer to step S1 in the first aspect for a better understanding of this step, which will not be repeated here.

[0148] s2, obtain the signal network with short circuit in the PCB layout file to be checked, as the target signal network to be checked; obtain the signal network group at the same position in the comparison PCB layout file corresponding to the target signal network to be checked, as the comparison target signal network group;

[0149] This invention can employ existing PCB layout short-circuit checking methods to obtain all signal networks with short circuits in the PCB layout file to be checked, which are all recorded as the target signal networks to be checked. One optional method can be implemented with reference to patent CN201811407159.X, in which the netlist networks with short-circuit problems identified by this patent are the target signal networks to be checked in this invention. The short circuit in the target signal network is caused by short-circuiting two or more target signal networks that should not be connected.

[0150] For each target signal network to be investigated, the signal network group corresponding to the same position in the comparison PCB layout file can be obtained through location information, and this group is used as the comparison target signal network group for that target signal network. Since there is no short circuit in the comparison target signal network group, it contains two or more signal networks. In this embodiment of the invention, each target signal network to be investigated is processed separately, and s2 to s4 are described using any one of the target signal networks to be investigated.

[0151] s3, acquire the target signal network image to be investigated and the comparison target signal network group image, and obtain the difference position between the target signal network image to be investigated and the comparison target signal network group image based on the continuity of image pixels. The difference position is the suspected location of short circuit in the conductor of the same layer of PCB.

[0152] The image of the target signal network to be investigated refers to the image corresponding to the target signal network to be investigated. The image of the comparison target signal network group refers to the image corresponding to the comparison target signal network group.

[0153] Among them, the target signal network image to be investigated and the comparison target signal network group image may have multiple differences, and the differences are determined by the coordinates of each endpoint and the PCB layer in which they are located.

[0154] The difference location is the suspected location of a short circuit in the same layer of the PCB conductor; in this embodiment of the invention, the difference location is only the case of a short circuit in the middle of the same layer conductor.

[0155] s4, determine the short circuit location in the PCB layout to be inspected based on the difference location.

[0156] In one alternative implementation, s4 may include the following steps:

[0157] s41, for any difference location, remove the image of the difference location from the image of the target signal network to be inspected. When the difference location is connected to two or more target signal networks, determine the short circuit location in the PCB layout to be inspected by judging the signal connectivity between the obtained target signal networks.

[0158] In this embodiment of the invention, the image of the difference location is a wire or a via with an electrical connection, and s4 is executed sequentially for each difference location.

[0159] In one optional implementation, s41 may include the following steps:

[0160] s411, determine the PCB layer where the difference location is located in the PCB layout file to be checked, and remove the image of the difference location in the image of the target signal network to be checked in the PCB layer where the difference location is located, to obtain the images of each target signal network originally connected to the difference location;

[0161] In this embodiment of the invention, steps s411 to s414 are performed in the PCB layout file to be inspected. Regarding s411, it can be understood that after removing the difference location, the original target signal network to be inspected is split into two or more target signal networks, and images of each target signal network can be obtained.

[0162] In s411, based on the endpoint coordinates and the PCB layer they are located on, the PCB layer where the difference is located can be determined in the PCB layout file to be checked.

[0163] s412, the PCB layer where the difference location is located to the last PCB layer of the signal network where the difference location is located are sequentially used as the current layer to perform the judgment step. The judgment step includes determining whether each target signal network satisfies the requirement of having signal connection in the current layer based on the pixel continuity of the image of each target signal network.

[0164] Since signal networks can be connected on different PCB layers, the judgment steps need to be performed layer by layer.

[0165] Each target signal network satisfies the requirement of having signal connections at the current layer, including:

[0166] In the images of each target signal network, the images in the current layer are all consecutive.

[0167] Specifically, in the images of each target signal network, the fact that the images in the current layer are consecutive in pairs is used as a direct condition to determine that the current layer has signal connections.

[0168] If there are only two target signal networks, the above condition is that the images of these two target signal networks in the current layer are continuous; if there are more than two target signal networks, the above condition is that the images of every two target signal networks in the current layer are continuous.

[0169] In the above conditions, the continuity of two images in the current layer is determined by the continuity of image pixels. When they belong to the same signal network, the colors of the signal wiring are the same. If the two images to be judged are in the current layer and are connected by other signal lines except for the difference position, then it can be directly determined that the two images to be judged are continuous in the current layer.

[0170] If the above conditions are not met, it is necessary to further use the vias in the image to determine whether each target signal network may have a signal connection in the next layer. If it is possible that there is a signal connection in the next layer, the next layer is used as the current layer and the judgment step is executed again until the last PCB layer of the signal network where the difference is located is judged.

[0171] If s413 is satisfied, it is determined that the difference location is not a short circuit location of the PCB layout to be inspected;

[0172] If the above conditions are met, it can be directly determined that each target signal network has a signal connection in the current layer, and the difference location is not the short circuit location of the PCB layout to be inspected.

[0173] If s414 is not satisfied, determine the two target signal networks that do not have signal connections in the current layer as target signal network pairs, and determine the short circuit location of the PCB layout to be inspected based on the difference position between the target signal network pairs.

[0174] Specifically, s414 may include the following steps:

[0175] Step 1), identify two target signal networks that do not have signal connections in the current layer as target signal network pairs;

[0176] In the images of each target signal network, if there are two discontinuous target signal networks in the current layer, they are identified as a target signal network pair.

[0177] Step 2), determine whether there are vias at both ends of the image in the current layer of the target signal network;

[0178] Here, the via refers to a via that has an electrical connection;

[0179] Step 3): If the target signal network pair has no vias at either end of the image in the current layer, or has a via at only one end of any image, the difference position between the target signal network pairs is determined as the short-circuit position.

[0180] If the target signal network pair has no vias at either end of the image in the current layer, or has a via at only one end of the image, it indicates that the target signal network pair definitely does not have a signal connection, and the difference position between the target signal network pairs is determined as a short circuit position.

[0181] Step 4): If the target signal network has vias at both ends of the image in the current layer, the next layer after the current layer is recorded as the current layer, and the process returns to the judgment step.

[0182] If the target signal network pair has vias at both ends of the image in the current layer, it indicates that the target signal network pair may have signal connections in the next layer, so it needs to be judged again.

[0183] After the judgment is completed, the difference positions between all target signal network pairs constitute the short circuit positions of the PCB layout file to be checked.

[0184] For ease of understanding, the process of s41 will be described below with the difference location connected to only two target signal networks. This process may include the following steps:

[0185] Step c1: Determine the PCB layer where the difference is located in the PCB layout file to be checked, and use it as the current layer;

[0186] Step c2: Remove the image at the difference position in the target signal network image to be investigated, and obtain the images of the third target signal network and the fourth target signal network that were originally connected to the difference position, respectively, as the third target signal network image and the fourth target signal network image;

[0187] Step c3: Determine whether the images in the current layer of the third target signal network image and the fourth target signal network image are continuous based on the continuity of image pixels;

[0188] The third and fourth target signal network images are continuous in the current layer, as can be understood with reference to Figure 9. In Figure 9, PCB1 is the PCB layout file to be checked, and PCB2 is the PCB layout file to be compared. Figure 9 shows signal networks but does not contain components. It can be seen that PCB1 has a short circuit, and this short open circuit position is the difference position in PCB1. After removing this difference position in the target signal network image to be checked in PCB1, the target signal network images on the left and right sides can still be connected through a signal line located above the difference position in Figure 9. These two target signal network images are still continuous in the current layer, therefore, these two target signal networks have a signal connection in the current layer.

[0189] Step c4: If the images of the third target signal network image and the fourth target signal network image are continuous in the current layer, it indicates that the third target signal network and the fourth target signal network have signal connection in the current layer. Then, it is determined that the difference position is not the short circuit position of the PCB layout to be inspected.

[0190] Step c5: If the images in the current layer of the third target signal network image and the fourth target signal network image are discontinuous, determine whether there are vias at both ends of the third target signal network image and the fourth target signal network image;

[0191] Step c6: If neither the third target signal network image nor the fourth target signal network image has a via, or if only one end of either the third target signal network image or the fourth target signal network image has a unique via, then the difference location is determined to be the short circuit location of the PCB layout to be inspected.

[0192] Step c7: If both ends of the third target signal network image and the fourth target signal network image have vias, take the next layer of the current layer as the current layer, return to step c3, and continue until the last PCB layer of the signal network where the difference is located is determined.

[0193] When both ends of the third and fourth target signal network images have vias, the continuity of the next layer image is understood by referring to Figure 10. As can be seen from Figure 10, PCB1 achieves image continuity in the (n-1)th layer.

[0194] When the location of the difference is connected to more than two target signal networks, the process of s41 is similar to the process described above, and this process may include the following steps:

[0195] Step d1: Determine the PCB layer where the difference is located in the PCB layout file to be checked, and use it as the current layer;

[0196] Step d2: Remove the image at the difference location from the image of the target signal network to be investigated, and obtain the images of the multiple target signal networks that were originally connected to the difference location.

[0197] Please refer to Figure 11 to understand the difference location and the image of the difference location. Figure 11 shows the difference location connected to the three target signal networks as an example.

[0198] Step d3: Based on the continuity of image pixels, determine whether the images in the current layer of each of the multiple target signal networks are all consecutive in pairs;

[0199] Pairwise continuity means that the images of each pair of target signal networks are continuous in the current layer.

[0200] Step d4: If the images of the multiple target signal networks in the current layer are all consecutive in pairs, it means that the multiple target signal networks have signal connections in the current layer. Then, it is determined that the difference position is not the short circuit position of the PCB layout to be inspected.

[0201] Step d5: If there are two discontinuous target signal networks in the current layer of the image of each of the multiple target signal networks, the two discontinuous target signal networks are taken as a target signal network pair, and it is determined whether there are vias at both ends of the target signal network pair in the current layer image.

[0202] Step d6: If there are no vias at either end of the image of the target signal network pair, or only one via exists at one end of any image, the difference location is determined to be the short circuit location of the PCB layout to be inspected.

[0203] Step d7: If there are vias at both ends of the image of the target signal network pair, take the next layer of the current layer as the current layer, return to step d3, and continue until the last PCB of the signal network where the difference is located is determined.

[0204] In the above embodiments, for any discrepancy location, processing is performed on the PCB layout file to be inspected. The image of the discrepancy location is removed from the image of the target signal network to be inspected. When the discrepancy location is connected to two or more target signal networks, the short circuit location in the PCB layout to be inspected is determined by judging the signal connectivity between the obtained target signal networks. This embodiment compares the PCB layout file to be inspected with a comparison PCB layout file that serves as the original CAD data to find discrepancies. The short circuit location is obtained by judging the image continuity on the PCB layout file to be inspected. This can accurately obtain the specific location of the short circuit. Compared with manual inspection, there are no errors or omissions that exist in manual inspection. It has a high accuracy rate and is quick, improving inspection efficiency, avoiding unnecessary rework and losses in the PCB manufacturing process, greatly shortening PCB manufacturing time, reducing cost investment, and effectively realizing automated detection of short circuit locations.

[0205] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0206] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0207] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for locating open circuits in a PCB layout, characterized in that, include: Obtain the Gerber file, drill file, and IPC netlist file of the PCB layout to be inspected, and use them as the PCB layout files to be inspected; Obtain the original CAD data of the PCB layout to be inspected, as a comparison PCB layout file; The signal network group containing an open circuit in the PCB layout file to be checked is selected as the target signal network group to be checked. The signal network at the same position in the comparison PCB layout file corresponding to the target signal network group to be investigated is obtained as the comparison target signal network; Acquire the target signal network group image and the comparison target signal network image, and obtain the difference positions between the target signal network group image and the comparison target signal network image based on the continuity of image pixels; The location of the open circuit in the PCB layout to be inspected is determined based on the location of the difference.

2. The PCB layout open-circuit positioning method according to claim 1, characterized in that, Determining the open circuit location in the PCB layout to be inspected based on the difference location includes: For any discrepancy location, the image of the discrepancy location is removed from the comparison target signal network image. When the discrepancy location is connected to two or more target signal networks, the open circuit location in the PCB layout to be inspected is determined by judging the signal connectivity between the obtained target signal networks.

3. The PCB layout open-circuit positioning method according to claim 2, characterized in that, For any discrepancy location, the image at that discrepancy location is removed from the comparison target signal network image. When the discrepancy location is connected to two or more target signal networks, the open circuit location in the PCB layout to be inspected is determined by judging the signal connectivity between the obtained target signal networks, including: In the comparison PCB layout file, determine the PCB layer where the difference location is located. In the PCB layer where the difference location is located, remove the image of the difference location from the comparison target signal network image to obtain the images of each target signal network originally connected to the difference location. From the PCB layer where the difference is located to the last PCB of the signal network where the difference is located. Each layer is used as the current layer to perform a judgment step, which includes determining whether each target signal network satisfies the requirement of having signal connections in the current layer based on the pixel continuity of the image of each target signal network. If the condition is met, it is determined that the location of the difference is not an open circuit location in the PCB layout to be inspected; If the condition is not met, two target signal networks that do not have signal connections in the current layer are identified as target signal network pairs. Based on the difference in position between the target signal network pairs, the open circuit position of the PCB layout to be inspected is determined.

4. The PCB layout open-circuit positioning method according to claim 1, characterized in that, In the comparison target signal network image, after removing the image at the difference location, when the difference location is connected to only two target signal networks, the open circuit location in the PCB layout to be inspected is determined based on the difference location, including: Locate the undetermined open circuit location in the PCB layout file to be checked within the difference location; Measure the distance between any endpoint of the undetermined open-circuit location and other endpoints in the open-circuit signal network group of the layer in which it is located; Determine the minimum value among all distances, and identify the two endpoints corresponding to the minimum value as the open path positions.

5. A PCB layout open-circuit positioning device, characterized in that, include: The file acquisition module is used to acquire the Gerber file, drill file, and IPC netlist file of the PCB layout to be inspected, as the PCB layout file to be inspected. Obtain the original CAD data of the PCB layout to be inspected, as a comparison PCB layout file; The module for acquiring the target signal network group to be checked and the module for acquiring the target signal network to be compared are used to acquire the signal network group with open circuits in the PCB layout file to be checked, as the target signal network group to be checked; and to acquire the signal network at the same position in the PCB layout file to be compared, which corresponds to the target signal network group to be checked, as the target signal network to be compared. The difference location acquisition module is used to acquire the image of the target signal network group to be investigated and the image of the comparison target signal network, and to obtain the difference location between the image of the target signal network group to be investigated and the image of the comparison target signal network based on the continuity of the image pixels; An open circuit location module is used to determine the open circuit location in the PCB layout to be inspected based on the difference location.

6. A method for locating short circuits in a PCB layout, characterized in that, include: Obtain the Gerber file, drill file, and IPC netlist file of the PCB layout to be inspected, and use them as the PCB layout files to be inspected; Obtain the original CAD data of the PCB layout to be inspected, as a comparison PCB layout file; The signal network with a short circuit in the PCB layout file to be checked is obtained as the target signal network to be checked; the signal network group corresponding to the target signal network to be checked at the same position in the comparison PCB layout file is obtained as the comparison target signal network group. Acquire the target signal network image to be investigated and the comparison target signal network group image, and obtain the difference positions between the target signal network image to be investigated and the comparison target signal network group image based on the continuity of image pixels; The location of the short circuit in the PCB layout to be inspected is determined based on the location of the difference.

7. The PCB layout short-circuit location method according to claim 6, characterized in that, Determining the short circuit location in the PCB layout to be inspected based on the difference location includes: For any discrepancy location, the image at that discrepancy location is removed from the image of the target signal network to be inspected. When the discrepancy location is connected to two or more target signal networks, the short circuit location in the PCB layout to be inspected is determined by judging the signal connectivity between the obtained target signal networks.

8. The PCB layout short-circuit location method according to claim 7, characterized in that, For any discrepancy location, the image at that discrepancy location is removed from the target signal network image to be inspected. When the discrepancy location is connected to two or more target signal networks, the short circuit location in the PCB layout to be inspected is determined by judging the signal connectivity between the obtained target signal networks, including: In the PCB layout file to be checked, determine the PCB layer where the difference is located. In the PCB layer where the difference is located, remove the image of the difference location from the image of the target signal network to be checked to obtain the images of each target signal network originally connected to the difference location. The PCB layer from the location of the difference to the last PCB layer of the signal network where the difference is located are sequentially used as the current layer for the judgment step. The judgment step includes determining whether each target signal network satisfies the requirement of having signal connection in the current layer based on the pixel continuity of the image of each target signal network. If the condition is met, it is determined that the location of the difference is not a short circuit location in the PCB layout to be inspected; If the condition is not met, two target signal networks that do not have signal connections in the current layer are identified as target signal network pairs. Based on the difference in position between the target signal network pairs, the short circuit location of the PCB layout to be inspected is determined.

9. A PCB layout short-circuit positioning device, characterized in that, include: The file acquisition module is used to acquire the Gerber file, drill file, and IPC netlist file of the PCB layout to be inspected, as the PCB layout file to be inspected. Obtain the original CAD data of the PCB layout to be inspected, as a comparison PCB layout file; The module for acquiring the target signal network to be checked and the comparison target signal network group is used to acquire the signal network with a short circuit in the PCB layout file to be checked as the target signal network to be checked; and to acquire the signal network group at the same position in the comparison PCB layout file corresponding to the target signal network to be checked as the comparison target signal network group. The difference location acquisition module is used to acquire the target signal network image to be investigated and the comparison target signal network group image, and to obtain the difference location between the target signal network image to be investigated and the comparison target signal network group image based on the continuity of image pixels; A short-circuit location module is used to determine the short-circuit location in the PCB layout to be inspected based on the difference location.

10. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; The memory is used to store computer programs; When the processor executes the program stored in the memory, it implements claims 1-4. The steps of any of the PCB layout open circuit positioning methods, or the steps of implementing any of the PCB layout short circuit positioning methods according to claims 6-8.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the PCB layout open-circuit positioning method according to any one of claims 1-4, or the steps of the PCB layout short-circuit positioning method according to any one of claims 6-8.

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