Display panel and display apparatus

Abstract

A display panel, which includes a display area (AA) and a non-display area (NA), wherein a first active layer (123) of the display area (AA) includes low-temperature polysilicon transistors, and a second active layer (127) thereof includes metal oxide transistors; and each of gate driving units (200a) of the non-display area (NA) includes a plurality of gate transistors and a storage capacitor (Cst1) connected to the gate transistors, active parts of the gate transistors and one electrode plate of the storage capacitor (Cst1) being located in mutually different ones of the first active layer (123) and the second active layer (127).

Description

Display panel and display device Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Current Organic Light-Emitting Diode (OLED) display devices face increasingly stringent requirements for power consumption and screen-to-body ratio. To reduce power consumption and increase screen-to-body ratio, Low Temperature Polysilicon Oxide (LTPO) technology is employed. LTPO technology refers to the simultaneous use of low-temperature polysilicon thin-film transistors (LTPTs) and oxide thin-film transistors (OSTs), allowing the driving circuit to combine the advantages of both LTPTs and OSTs, thereby reducing power consumption and leakage current.

[0003] Currently, display devices using LTPO technology have a large number of film layers, which in turn requires a large number of photomasks, resulting in a more complex process and higher costs. Invention Overview

[0004] This application provides a display panel and display device to solve the technical problem of complex manufacturing processes in existing display devices using LTPO technology.

[0005] To address the above issues, the technical solution provided in this application is as follows:

[0006] This application discloses a display panel comprising:

[0007] The display area includes a pixel driving circuit with multiple pixel transistors. The multiple pixel transistors include low-temperature polysilicon transistors and metal oxide transistors. The active part of the low-temperature polysilicon transistor is located in a first active layer, and the active part of the metal oxide transistor is located in a second active layer.

[0008] A non-display area is located on one side of the display area. The non-display area is provided with a gate drive circuit of multiple cascaded gate drive units. Each gate drive unit includes multiple gate transistors and a storage capacitor connected to the gate transistors.

[0009] The active portion of the gate transistor is located in one of the first active layer or the second active layer, and one plate of the storage capacitor is located in the other of the first active layer or the second active layer. Attached Figure Description

[0010] Figure 1 is a simplified diagram of the first structure of the display panel of this application;

[0011] Figure 2 is an equivalent circuit diagram of the pixel driving circuit in the display panel of this application;

[0012] Figure 3 is a simplified diagram of the second structure of the display panel of this application;

[0013] Figure 4 is a simplified diagram of the third structure of the display panel of this application;

[0014] Figure 5 is an equivalent circuit diagram of the gate driving circuit in the display panel of this application;

[0015] Figure 6 is a schematic diagram of the film layer in the display panel of this application;

[0016] Figure 7 is a film layer diagram of the first gate layer in the display panel of this application.

[0017] Figure 8 is a film layer diagram of the first active layer in the display panel of this application.

[0018] Figure 9 is a stacked diagram of the first active layer and the first gate layer in the display panel of this application.

[0019] Figure 10 is a film diagram of the second active layer in the display panel of this application.

[0020] Figure 11 is a stacked diagram of the first active layer, the second active layer, and the first gate layer in the display panel of this application.

[0021] Figure 12 is a film layer diagram of the second gate layer in the display panel of this application.

[0022] Figure 13 is a stacked diagram of the first active layer, the second active layer, the first gate layer and the second gate layer in the display panel of this application.

[0023] Figure 14 is a film diagram of the first source and drain layer in the display panel of this application.

[0024] Figure 15 is a stacked diagram of the first active layer, second active layer, first gate layer, second gate layer 129 and first source / drain layer in the display panel of this application.

[0025] Figure 16 is a film diagram of the second source / drain layer in the display panel of this application.

[0026] Figure 17 is a stacked diagram of the first active layer, second active layer, first gate layer, second gate layer, first source-drain layer and second source-drain layer in the display panel of this application. Embodiments of the present invention

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application.

[0028] In the description of this application, it should be understood that the terms "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, and "at least one" can mean one, two, or more, unless otherwise explicitly specified.

[0030] Please refer to Figures 1 to 17. This application provides a display panel 100, which includes a display area AA and a non-display area NA disposed on one side of the display area AA.

[0031] In this embodiment, the display area AA includes a pixel driving circuit 300 having multiple pixel transistors. The multiple pixel transistors include low-temperature polysilicon transistors and metal oxide transistors. The active portion of the low-temperature polysilicon transistor is located in the first active layer 123, and the active portion of the metal oxide transistor is located in the second active layer 127.

[0032] In this embodiment, the non-display area NA is located on one side of the display area AA. The non-display area NA includes a gate drive circuit 200 having multiple cascaded gate drive units 200a. Each gate drive unit 200a includes multiple gate transistors and a storage capacitor Cst1 connected to the gate transistors.

[0033] In this embodiment, the active portion of the gate transistor is located in one of the first active layer 123 or the second active layer 127, and one plate of the storage capacitor Cst1 is located in the other of the first active layer 123 or the second active layer 127.

[0034] In some embodiments of this application, the storage capacitor Cst1 of the gate driving unit 200a is typically composed of two layers of metal material, resulting in a large number of film layers in the display panel 100, which in turn increases the number of photomasks, leading to a more complex process and higher cost. However, this application utilizes the material of one of the first active layer 123 and the second active layer 127 to form the active portion of the gate transistor, and the material of the other to form one electrode of the storage capacitor Cst1. This replaces the metal material of the one electrode of the storage capacitor Cst1 with the active layer material, eliminating the metal layer originally used to prepare the one electrode of the storage capacitor Cst1, reducing the number of film layers in the display panel 100, and simplifying the manufacturing process of the display panel 100.

[0035] It should be noted that the low-temperature polysilicon transistor in this application is a P-type transistor, and the metal-oxide transistor is an N-type transistor.

[0036] It should be noted that the pixel transistor in this application is the transistor constituting the pixel driving circuit 300, and the gate transistor is the transistor constituting the gate driving circuit 200.

[0037] The technical solution of this application will now be described in conjunction with specific embodiments.

[0038] Referring to Figure 1, the display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA is located within the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is enclosed by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that perform these functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in performing their display functions.

[0039] Please refer to Figure 1. A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit. The bonding terminal 400 transmits the signals input from the external circuit to the data traces, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0040] In this embodiment, multiple light-emitting devices (LEDs) and pixel driving circuits 300 for driving the LEDs can be arrayed in the display area AA. The pixel driving circuit 300 can be a 7T1C, 7T2C, 8T2C, 8T3C, 8T4C, etc. This application does not impose specific limitations. The following description uses an 8T2C pixel driving circuit 300 as an example.

[0041] Referring to Figure 2, the pixel driving circuit 300 may include a switching transistor T2A, a driving transistor T1A, a compensation transistor T3A, a first reset transistor T4A, a second reset transistor T7A, a third reset transistor T8A, a first light-emitting transistor T5A, a second light-emitting transistor T6A, a boost capacitor Cboost, and a control capacitor Cst2.

[0042] Referring to Figure 2, the first electrode of switching transistor T2A is connected to the data signal line Data, the second electrode of switching transistor T2A is connected to control node A1, and the gate of switching transistor T2A receives the switching control signal Pscan1; the first electrode of driving transistor T1A is connected to control node A1, the second electrode of driving transistor T1A is connected to control node B1, and the gate of driving transistor T1A is connected to control node Q1; the first electrode of compensation transistor T3A is connected to control node Q1, the second electrode of compensation transistor T3A is connected to control node B1, and the gate of compensation transistor T3A receives the compensation control signal Nscan1; the first electrode of the first reset transistor T4A receives the first reset signal Vi1, the second electrode of the first reset transistor T4A is connected to control node Q1, and the gate of the first reset transistor T4A receives the first reset control signal Nscan2; the first electrode of the second reset transistor T7A is connected to the second reset signal Vi2, and the second electrode of the second reset transistor T7A is connected to the anode of the light-emitting device. The gate of transistor 7A receives the second reset control signal Pscan2; the first electrode of the third reset transistor T8A receives the third reset signal Vi3, the second electrode of the third reset transistor T8A is connected to control node A1, and the gate of the third reset transistor T8A receives the third reset control signal Vi3; the first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, the second electrode of the first light-emitting transistor T5A is connected to control node A1, and the gate of the first light-emitting transistor T5A receives the light-emitting control signal EM; the first electrode of the second light-emitting transistor T6A is connected to the second node B1, the second electrode of the second light-emitting transistor T6A is connected to the anode of the light-emitting device, and the gate of the second light-emitting transistor T6A receives the light-emitting control signal EM; one end of the boost capacitor Cboost is connected to control node Q1, and the other end of the boost capacitor Cboost is connected to the gate of the switching transistor T2A; one end of the control capacitor Cst2 is connected to control node Q1, and the other end of the control capacitor Cst2 is connected to the high-level source VDD; the cathode of the light-emitting device is connected to the low-level source VSS.

[0043] In this embodiment, the high-level source VDD is used to provide a constant high voltage to the pixel driving circuit 300, and the low-level source VSS is used to provide a constant low voltage to the pixel driving circuit 300.

[0044] In this embodiment, the switching transistor T2A, driving transistor T1A, second reset transistor T7A, third reset transistor T8A, first light-emitting transistor T5A, and second light-emitting transistor T6A can be either P-type transistors or N-type transistors, and the compensation transistor T3A and first reset transistor T4A can be either P-type transistors or N-type transistors. This application uses the example of switching transistor T2A, driving transistor T1A, second reset transistor T7A, third reset transistor T8A, first light-emitting transistor T5A, and second light-emitting transistor T6A being P-type transistors, and compensation transistor T3A and first reset transistor T4A being N-type transistors for illustration.

[0045] In this embodiment, the capacitance of the boost capacitor Cboost is smaller than that of the control capacitor Cst2. In this embodiment, the control capacitor Cst2 is mainly used to maintain the stability of the potential of the third node Q1; therefore, the capacitance of the control capacitor Cst2 is relatively large, for example, the capacitance value of the control capacitor Cst2 can range from 45fF to 55fF, and the capacitance value of the boost capacitor Cboost can range from 5fF to 15fF.

[0046] In this embodiment, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain.

[0047] Please refer to Figures 3 and 4. The gate driving circuit 200 is disposed in the non-display area NA, and the gate driving circuit 200 can be disposed on both sides of the display area AA. The gate driving circuit 200 can include N cascaded gate driving units 200a. The N gate driving units 200a can be arranged along the first direction X. The structure of the gate driving unit 200a can be various. For example, in the structure of Figure 3, the non-display area NA can include a plurality of first gate circuits 210 arranged and cascaded along the first direction X, a plurality of second gate circuits 220 arranged and cascaded along the first direction X, a plurality of third gate circuits 230 arranged and cascaded along the first direction X, a plurality of fourth gate circuits 240 arranged and cascaded along the first direction X, and a plurality of fifth gate circuits 250 arranged and cascaded along the first direction X.

[0048] In this embodiment, the second direction Y is parallel to the scan line of the display panel 100, and the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°. The scan line can be a gate signal transmission line, such as a compensation control line, a first reset control line, a switch control line, a second reset control line, or a light emission control line.

[0049] Please refer to Figures 3 and 4. The first gate circuit 210 is located on both sides of the display area AA. The first gate circuit 210 is used to transmit the compensation control signal Nscan1. The first gate circuit 210 is connected to two compensation control lines. That is, the first gate circuit 210 is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300. In other words, the two-row pixel driving circuit 300 requires a first gate circuit 210.

[0050] Please refer to Figures 3 and 4. The second gate circuit 220 is disposed on both sides of the display area AA. The second gate circuit 220 and the first gate circuit 210 are arranged along the second direction Y. The second gate circuit 220 is used to transmit the first reset control signal Nscan2. One second gate circuit 220 is connected to two first reset control lines. At the same time, the first-level second gate circuit 220 of this application is used to output the first reset control signal Nscan2 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level second gate circuit 220.

[0051] Please refer to Figures 3 and 4. The fifth gate circuit 250 is located on both sides of the display area AA, and between the display area AA and the first gate circuit 210, and between the display area AA and the second gate circuit 220. The fifth gate circuit 250 is used to transmit the switch control signal Pscan1. The fifth gate circuit 250 is connected to two switch control lines. At the same time, the first-level fifth gate circuit 250 of this application is used to output the switch control signal Pscan1 to the row pixel driving circuit 300, that is, the row pixel driving circuit 300 requires a first-level fifth gate circuit 250.

[0052] It should be noted that, as shown in Figures 3 and 4, each display area AA is provided with a first gate circuit 210, a second gate circuit 220 and a fifth gate circuit 250 on both sides, that is, the first gate circuit 210, the second gate circuit 220 and the fifth gate circuit 250 of this application are driven simultaneously on both sides.

[0053] Please refer to Figures 3 and 4. The third gate circuit 230 is located on the first side of the display area AA, and the third gate circuit 230 is located on the side of the first gate circuit 210 away from the display area AA. The third gate circuit 230 is used to transmit the second reset control signal Pscan2. The third gate circuit 230 is connected to two second reset control lines. At the same time, the first-level fourth gate circuit 240 of this application is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level third gate circuit 230.

[0054] Please refer to Figures 3 and 4. The fourth gate circuit 240 is located on the second side of the display area AA, and the fourth gate circuit 240 is located on the side of the first gate circuit 210 away from the display area AA. The fourth gate circuit 240 is used to transmit the light emission control signal EM. The fourth gate circuit 240 is connected to two light emission control lines. At the same time, the first-level fourth gate circuit 240 of this application is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level fourth gate circuit 240.

[0055] It should be noted that, in this application, only the third gate circuit 230 is provided on one side of the display area AA, and only the fourth gate circuit 240 is provided on the other side of the display area AA, that is, the third gate circuit 230 and the fourth gate circuit 240 are driven on one side only.

[0056] It should be noted that since the first reset signal Vi1, the second reset signal Vi2 and the third reset signal Vi3 are all constant voltages, they do not require the corresponding gate drive circuit 200 to control them, and can be directly connected to the corresponding constant voltage source.

[0057] In this embodiment, the first gate circuit 210, the second gate circuit 220, the third gate circuit 230, the fourth gate circuit 240, and the fifth gate circuit 250 of this application can be mTnC gate circuits. In the following embodiment, the structure of the gate driving unit 200a of this application will be described using 16T4C as an example of the first gate circuit 210 and the second gate circuit 220.

[0058] It should be noted that the difference between Figure 3 and Figure 4 is that the display panel in Figure 4 is equipped with an under-display camera area (CUP), while the display panel in Figure 3 is not equipped with an under-display camera area (CUP).

[0059] Referring to Figure 5, the gate drive unit 200a may include a receiving circuit 221 and an output circuit 222. The receiving circuit 221 and the output circuit 222 are arranged along the second direction Y. The receiving circuit 221 is used to receive the stage transmission signal generated by the upper gate drive circuit 200. The output circuit 222 is electrically connected to the receiving circuit 221 through the second node Q2 and the first node P2, and is used to output the control signal of this stage and the stage transmission signal of the next stage according to the signal of the second node Q2 and the signal of the first node P2.

[0060] Please refer to Figure 5. The output circuit 222 includes a second output transistor T10 and a first output transistor T9. The gate of the second output transistor T10 is electrically connected to the second node Q2, the source of the second output transistor T10 is electrically connected to the high potential line VGH, and the drain of the second output transistor T10 is electrically connected to the output terminal OUT in the gate drive circuit 200. The gate of the first output transistor T9 is electrically connected to the first node P2, the source of the first output transistor T9 is electrically connected to the low potential line VGL, and the drain of the first output transistor T9 is electrically connected to the output terminal OUT.

[0061] Please refer to Figure 5. The receiving circuit 221 includes a first node control module 221a and a second node control module 221b. The first output transistor T9 and the first node control module 221a are connected to the first node P2, and the second output transistor T10 and the second node control module 221b are connected to the second node Q2.

[0062] Please refer to Figure 5. The storage capacitors include a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The first capacitor C1 includes a first plate C1a and a second plate C1b, which are respectively connected to different internal nodes in the first node control module 221a. The second capacitor C2 includes a third plate C2a and a fourth plate C2b, which are respectively connected to different internal nodes in the second node control module 221b. The third capacitor C3 includes a fifth plate C3a and a sixth plate C3b, with the fifth plate C3a connected to the source of the first output transistor T9 and the sixth plate C3b connected to the first node P2. The fourth capacitor C4 includes a seventh plate C4a and an eighth plate C4b, with the seventh plate C4a connected to the source of the second output transistor T10 and the eighth plate C4b connected to the second node Q2.

[0063] Please refer to Figure 5. The receiving circuit 221 includes a third transistor T3. The gate of the third transistor T3 is loaded with the first clock signal line XCK. The source of the third transistor T3 is connected to the start signal line STV. The drain of the third transistor T3 is connected to the control node N3.

[0064] Please refer to Figure 5. The receiving circuit 221 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate of the fifth transistor T5 is electrically connected to the control node N3. The source of the fifth transistor T5 is loaded with the first clock signal line XCK. The gate of the fourth transistor T4 is loaded with the first clock signal line XCK. The source of the fourth transistor T4 is loaded with the low potential line VGL. The drain of the fourth transistor T4 is electrically connected to the control node N2. The drain of the fifth transistor T5 is electrically connected to the control node N2. The gate of the sixth transistor T6 is electrically connected to the control node N1. The drain of the sixth transistor T6 is electrically connected to the source of the seventh transistor T7. The source of the sixth transistor T6 and the gate of the seventh transistor T7 are both loaded with the second clock signal line CK. The drain of the seventh transistor T7 is electrically connected to the second node Q2.

[0065] Please refer to Figure 5. The receiving circuit 221 includes a thirteenth transistor T13, a first capacitor C1, a first transistor T1, and a second transistor T2. The gate of the thirteenth transistor T13 is electrically connected to the control line Control to load a control signal. The source of the thirteenth transistor T13 is loaded with a high potential line VGH. The drain of the thirteenth transistor T13 is electrically connected to the control node N3. The gate of the first transistor T1 is electrically connected to the control node N2. The source of the first transistor T1 is loaded with a high potential line VGH. The drain of the first transistor T1 is electrically connected to the source of the second transistor T2. The drain of the second transistor T2 is loaded with a second clock signal line CK. The gate of the second transistor T2 is electrically connected to the control node N4. The first capacitor C1 is electrically connected between the gate and drain of the second transistor T2.

[0066] Please refer to Figure 5. The receiving circuit 221 includes an eleventh transistor T11, a second capacitor C2, and a twelfth transistor T12. The output circuit 222 may also include a third capacitor C3 electrically connected between the gate and source of the tenth transistor T10. The gates of the eleventh transistor T11 and the twelfth transistor T12 can both be loaded with a low potential line VGL to maintain their on state. The source and drain of the eleventh transistor T11 are electrically connected to control node N2 and control node N1, respectively. The second capacitor C2 is electrically connected between the gate and drain of the sixth transistor T6. The source and drain of the twelfth transistor T12 are electrically connected to control node N3 and first node P2, respectively.

[0067] Please refer to Figure 5. The receiving circuit 221 includes an eighth transistor T8. The gate of the eighth transistor is connected to the control node N3, the drain of the eighth transistor T8 is connected to the high potential line VGH, and the source of the eighth transistor T8 is connected to the second node Q2.

[0068] Referring to Figure 5, the receiving circuit 221 includes a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16. The source of the fourteenth transistor T14 is connected to the start signal line STV, the gate of the fourteenth transistor T14 is loaded with the first clock signal line XCK, and the drain of the fourteenth transistor T14 is electrically connected to the source of the fifteenth transistor T15. The gate of the fifteenth transistor T15 is loaded with the low potential line VGL, and the drain of the fifteenth transistor T15 is electrically connected to the control node N4. The gate and source of the sixteenth transistor T16 are both electrically connected to the control node N4, and the drain of the sixteenth transistor T16 is electrically connected to the first node P2.

[0069] Please refer to Figure 5. The output circuit 222 also includes a fourth capacitor C4. The first plate of the fourth capacitor C4 is connected to the output terminal OUT, and the second plate of the fourth capacitor C4 is connected to the first node P2.

[0070] It should be noted that the source of the fourteenth transistor T14 and the source of the third transistor T3 are only connected to the start signal line STV in the first stage. In the gate drive circuit 200 after the second stage, the source of the fourteenth transistor T14 and the source of the third transistor T3 are electrically connected to the output terminal OUT of the previous stage gate drive circuit 200.

[0071] It should be noted that the source and drain in the transistors described above in this application are only different in name; as long as one is the input terminal and the other is the output terminal, it is acceptable.

[0072] It should be noted that all transistors in the gate drive circuit 200 of this application can be N-type transistors or P-type transistors. In this embodiment, all transistors in the gate drive circuit 200 are described using P-type transistors as an example.

[0073] It should be noted that the first node control module 221a of this application may include a first transistor T1 and a second transistor T2, and the second node control module 221b may include a sixth transistor T6 and a seventh transistor T7.

[0074] Alternatively, the first node control module 221a of this application may include a first transistor T1, a second transistor T2 and a sixteenth transistor T16, and the second node control module 221b may include a sixth transistor T6, a seventh transistor T7 and an eleventh transistor T11.

[0075] Referring to Figure 6, the display area AA and the non-display area NA of the display panel 100 may be provided with a substrate 110 and an array driving layer 120 disposed on the substrate 110. Within the display area AA, the display panel 100 may also be provided with a pixel definition layer (not shown) disposed on the array driving layer 120, a light-emitting device layer (not shown) disposed on the same layer as the pixel definition layer, and an encapsulation layer (not shown) disposed on the pixel definition layer. The following description mainly focuses on the film layer structure within the non-display area NA and the display area AA.

[0076] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate, as well as a transparent substrate, can be used.

[0077] In this embodiment, the substrate 110 is used to support the various film layers disposed on the substrate 110. The substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0078] In this embodiment, the substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 stacked together. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0079] In this embodiment, the first flexible substrate 111 is formed by coating a polymeric material onto a support substrate (not shown) and then curing the polymeric material. The second flexible substrate 113 is formed by coating the first flexible substrate 111 with the same material and then curing the material. The second flexible substrate 113 is formed by the same method as that used to form the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 may be formed to have a thickness of about 8 μm to about 12 μm. Furthermore, when the substrate 110 is formed from the first flexible substrate 111 and the second flexible substrate 113, pinholes, cracks, etc., formed during the manufacturing of the first flexible substrate 111 are covered by the second flexible substrate 113, thereby removing the aforementioned defects.

[0080] Please refer to Figure 6. The array driving layer 120 may include multiple thin-film transistors. The thin-film transistors may be etch-block type, back-channel etch type, or classified into bottom-gate thin-film transistors, top-gate thin-film transistors, etc., according to the position of the gate and the active layer, or classified into N-type thin-film transistors and P-type thin-film transistors according to their performance. For example, the gate transistor in the non-display area AA may be a P-type thin-film transistor, and the pixel transistor in the display area AA may be an N-type thin-film transistor or a P-type thin-film transistor. Secondly, the thin-film transistors in Figure 6 do not represent the structural diagram of any transistor in Figure 2, but are only schematic diagrams of each film layer of the display panel 100 of this application.

[0081] Referring to Figure 6, the array driving layer 120 may include a third barrier layer 135 disposed on the substrate 110, a light-shielding layer 121 embedded in the barrier layer 135, a buffer layer 122 disposed on the barrier layer 135, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first gate layer 125, and a third barrier layer 124 disposed on the second insulating layer 125. The second active layer 127 on the 6, the third insulating layer 128 disposed on the second active layer 127, the second gate layer 129 disposed on the third insulating layer 128, the fourth insulating layer 130 disposed on the second gate layer 129, the first source-drain layer 131 disposed on the fourth insulating layer 130, the first planarization layer 132 disposed on the first source-drain layer 131, the second source-drain layer 133 disposed on the first planarization layer 132, and the second planarization layer 134 disposed on the second source-drain layer 133.

[0082] Please refer to Figure 6. The light-shielding layer 121 is disposed on the second barrier layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be made of black light-shielding material, such as black light-shielding metal or black organic material. In this application, the light-shielding layer 121 can be disposed only in the display area AA.

[0083] Please refer to Figure 6. The buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may be composed of a compound consisting of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0084] Please refer to Figure 6. The first active layer 123 is disposed on the buffer layer 122, and the second active layer 127 is disposed on the second insulating layer 126. In this application, the material of the first active layer 123 can be low-temperature polycrystalline silicon, and the material of the second active layer 127 can be indium gallium zinc oxide semiconductor. Since the transistors in the gate driving unit 200a are all P-type transistors, no metal oxide semiconductor is disposed in the non-display area AA of this application. However, the pixel driving circuit 300 has N-type transistors and P-type transistors. Therefore, the display area AA of this application is provided with metal oxide semiconductor and low-temperature polycrystalline silicon semiconductor.

[0085] Please refer to Figure 6. The first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 are respectively disposed on the corresponding metal layer or semiconductor layer, and are disposed separately as different metal layers or semiconductor layers. The materials of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 can be inorganic materials composed of at least two elements in silicon oxynitride or organic materials with planarity.

[0086] Please refer to Figure 6. The first gate layer 125 and the second gate layer 129 are respectively disposed on the corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 129 can be copper, molybdenum, or molybdenum-titanium alloy, etc.

[0087] Please refer to Figure 6. The first source-drain layer 131 is disposed on the fourth insulating layer 130, and the second source-drain layer 133 is disposed on the first planarization layer 132. The materials of the first source-drain layer 131 and the second source-drain layer 133 can be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0088] Please refer to Figure 6. The first planarization layer 132 and the second planarization layer 134 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first planarization layer 132 and the second planarization layer 134 can be inorganic materials composed of silicon oxynitride or organic materials with flatness.

[0089] As shown in Figure 6, the two plates of the storage capacitor Cst1 in the non-display area AA of this application are respectively made of the material of the first gate layer 125 and the material of the second active layer 127. For example, the first plate C1a, the third plate C2a, the fifth plate C3a and the seventh plate C4a are located in the second active layer 127, and the second plate C1b, the fourth plate C2b, the sixth plate C3b and the eighth plate C4b are located in the first gate layer 125. The metal layer and an insulating layer between the original second active layer 127 and the first gate layer 125 are removed, which reduces the number of film layers in the display panel 100, simplifies the manufacturing process of the display panel 100, and reduces the cost of the display panel 100.

[0090] It should be noted that when all transistors in the gate drive circuit 200 of this embodiment are N-type transistors, the active portions of all transistors in the gate drive circuit 200 can be set using the second active layer 127, and the materials of the first active layer 123 and the first gate layer 125 can be used to form the two plates of the storage capacitor Cst1.

[0091] The structure of each film layer in the gate drive unit 200a is described below based on the stack-up diagram.

[0092] Please refer to Figure 7, which is a film layer diagram of the first gate layer 125 in the display panel 100 of this application.

[0093] In this embodiment, the first gate layer 125 includes a first gate T9G of the first output transistor T9 and a second gate T10G of the second output transistor T10, and the first gate T9G and the second gate T10G are arranged in the first direction X.

[0094] In this embodiment, the first gate T9G includes a first main gate T9Ga and a plurality of first branch gates T9Gb connected to the first main gate T9Ga. The first main gate T9Ga extends along a first direction X, and the plurality of first branch gates T9Gb extends along a second direction Y. The plurality of first branch gates T9Gb are spaced apart in the first direction X. The first main gate T9Ga and part of the first branch gates T9Gb are multiplexed as the sixth electrode plate C3b. For example, in the structure of FIG7, the first gate T9G includes one first main gate T9Ga and four first branch gates T9Gb. The first main gate T9Ga is located on the side of the first branch gates T9Gb away from the display area AA.

[0095] In this embodiment, the second gate T10G includes a second main gate T10Ga and a plurality of second branch gates T10Gb connected to the second main gate T10Ga. The second main gate T10Ga extends along a first direction X, and the plurality of second branch gates T10Gb extends along a second direction Y. The plurality of second branch gates T10Gb are spaced apart in the first direction X. The second main gate T10Ga and part of the second branch gates T10Gb are multiplexed as the eighth electrode plate C4b. For example, in the structure of FIG7, the second gate T10G includes one second main gate T10Ga and four second branch gates T10Gb. The second main gate T10Ga is located on the side of the second branch gates T10Gb away from the display area AA.

[0096] In this embodiment, the length and number of the strip-shaped branch gates in the second direction Y are positively correlated with the output load of the output transistor. Therefore, in order to improve the driving capability of the first output transistor T9 and the second output transistor T10, this application sets the first output transistor T9 and the second output transistor T10 as multiple separately arranged strip-shaped branch gates. Each strip-shaped branch gate bears the load of the corresponding transistor. The strip-shaped branch electrode corresponds to the channel of the active part in the corresponding transistor. The two adjacent strip-shaped branch gates correspond to the source and drain of the upper layer. The composite electric field formed by the multiple separately arranged strip-shaped branch gates can improve the driving capability of the transistor.

[0097] In this embodiment, in the first direction X, the spacing between two adjacent first branch gates T9Gb can be equal, and the spacing between two adjacent second branch gates T10Gb can be equal.

[0098] In this embodiment, in the first direction X, the spacing between two adjacent first branch gates T9Gb and the spacing between two adjacent second branch gates T10Gb can be equal.

[0099] In this embodiment, in the second direction Y, the linewidth of the first main gate T9Ga is smaller than the linewidth of the second main gate T10Ga.

[0100] Please refer to Figure 7. The first gate layer 125 also includes the second plate C1b of the first capacitor C1 and the fourth plate C2b of the second capacitor C2. The second plate C1b and the fourth plate C2b are arranged along the first direction X. The second plate C1b is disposed near the sixth plate C3b and the fourth plate C2b is disposed near the eighth plate C4b.

[0101] In this embodiment, the area of ​​the second electrode plate C1b can be larger than the area of ​​the fourth electrode plate C2b.

[0102] Referring to Figure 7, the first gate layer 125 also includes the gate T1G of the first transistor T1, the gate T2G of the second transistor T2, the gate T3G of the third transistor T3, the gate T4G of the fourth transistor T4, the gate T5G of the fifth transistor T5, the gate T6G of the sixth transistor T6, the gate T7G of the seventh transistor T7, the gate T8G of the eighth transistor T8, the gate T11G of the eleventh transistor T11, the gate T12G of the twelfth transistor T12, the gate T13G of the thirteenth transistor T13, the gate T14G of the fourteenth transistor T14, the gate T15G of the fifteenth transistor T15, and the gate T16G of the sixteenth transistor T16.

[0103] Please refer to Figure 7. The gates T2G of the second transistor T2, T6G of the sixth transistor T6, and T16G of the sixteenth transistor T16 all extend along the first direction X. The gates T1G of the first transistor T1, T3G of the third transistor T3, T4G of the fourth transistor T4, T8G of the eighth transistor T8, T12G of the twelfth transistor T12, T13G of the thirteenth transistor T13, T14G of the fourteenth transistor T14, T15G of the fifteenth transistor T15, and T11G of the eleventh transistor T11 extend along the second direction Y.

[0104] Please refer to Figure 7. The gate T2G of the second transistor T2 and the gate T16G of the sixteenth transistor T16 are both connected to the second plate C1b. The gate T2G of the second transistor T2 and the gate T6G of the sixth transistor T6 are located on the side of the fourth plate C2b away from the second plate C1b. The gate T6G of the sixth transistor T6 is connected to the fourth plate C2b, and the gate T6G of the sixth transistor T6 is located on the side of the fourth plate C2b closer to the second plate C1b.

[0105] Please refer to Figure 7. The gates T3G of the third transistor T3, T4G of the fourth transistor T4, and T14G of the fourteenth transistor T14 are connected. The gates T14G of the fourteenth transistor T14 and T4G of the fourth transistor T4 are connected through a vertical conductive structure. The gates T14G of the fourteenth transistor T14 and T3G of the third transistor T3 are both located on the same side of the gate T4G of the fourth transistor T4. The gates T3G of the third transistor T3, T4G of the fourth transistor T4, and T14G of the fourteenth transistor T14 are located on the side of the fourth plate C2b away from the second output transistor T10.

[0106] Please refer to Figure 7. The gate T15G of the fifteenth transistor T15 and the gate T11G of the eleventh transistor T11 are connected. The gate T4G of the fourth transistor T4, the gate T13G of the thirteenth transistor T13, the gate T15G of the fifteenth transistor T15, and the gate T11G of the eleventh transistor T11 are located between the second plate C1b and the fourth plate C2b. The gate T13G of the thirteenth transistor T13 is located close to the output circuit 222, and the gate T15G of the fifteenth transistor T15 is located away from the output circuit 222. The gate T4G of the fourth transistor T4 is located between the thirteenth transistor T13 and the eleventh transistor T11.

[0107] Please refer to Figure 7. The gate T7G of the seventh transistor T7 is located between the fourth plate C2b and the second output transistor T10. The gate T12G of the twelfth transistor T12 is located between the second plate C1b and the first output transistor T9. The gate T5G of the fifth transistor T5 and the gate T8G of the eighth transistor T8 are connected. Both the gate T5G of the fifth transistor T5 and the gate T8G of the eighth transistor T8 are located between the fourth plate C2b and the second plate C1b, and the gate T5G of the fifth transistor T5 and the gate T8G of the eighth transistor T8 are located close to the second plate C1b.

[0108] Please refer to Figures 8 and 9. Figure 8 is a film layer diagram of the first active layer 123 in the display panel 100 of this application, and Figure 9 is a film layer stack diagram of the first active layer 123 and the first gate layer 125 in the display panel 100 of this application.

[0109] In this embodiment, the first active layer 123 includes a first active portion T9A of the first output transistor T9 and a second active portion T10A of the second output transistor T10. Both the first active portion T9A and the second active portion T10A extend along the first direction X and are connected to each other. The first active portion T9A partially overlaps with multiple first branch gates T9Gb, and the second active portion T10A partially overlaps with multiple second branch gates T10Gb. The overlapping portion of the first active portion T9A and the multiple first branch gates T9Gb forms the channel of the first output transistor T9, and the overlapping portion of the second active portion T10A and the multiple second branch gates T10Gb forms the channel of the second output transistor T10.

[0110] Since the second output transistor T10 is used to control the low-level output to quickly turn off the pixel transistors in the display area AA, the second output transistor T10 needs to have a stronger output capability. Referring to Figures 8 and 9, in the second direction Y, the width of the first active part T9A is smaller than the width of the second active part T10A. The increase in the width of the second active part T10A improves the width of the second active part T10A, thereby improving the driving capability of the second output transistor T10.

[0111] In this embodiment, the first active layer 123 further includes the active portion T1A of the first transistor T1, the active portion T2A of the second transistor T2, the active portion T3A of the third transistor T3, the active portion T4A of the fourth transistor T4, the active portion T5A of the fifth transistor T5, the active portion T6A of the sixth transistor T6, the active portion T7A of the seventh transistor T7, the active portion T8A of the eighth transistor T8, the active portion T11A of the eleventh transistor T11, the active portion T12A of the twelfth transistor T12, the active portion T13A of the thirteenth transistor T13, the active portion T14A of the fourteenth transistor T14, the active portion T15A of the fifteenth transistor T15, and the active portion T16A of the sixteenth transistor T16. Furthermore, the active portions of the aforementioned transistors all overlap with the gate of the corresponding transistor, and this overlapping portion constitutes the channel of the corresponding transistor.

[0112] In this embodiment, the active portion T2A of the second transistor T2, the active portion T6A of the sixth transistor T6, and the active portion T16A of the sixteenth transistor T16 extend along the second direction Y, while the active portions of the remaining transistors all extend along the first direction X.

[0113] In this embodiment, the active portion T7A of the seventh transistor T7, the active portion T8A of the eighth transistor T8, the active portion T13A of the thirteenth transistor T13, the active portion T12A of the twelfth transistor T12, and the active portion T16A of the sixteenth transistor T16 are connected sequentially in the first direction X. The active portion T5A of the fifth transistor T5 and the active portion T11A of the eleventh transistor T11 are connected, and the active portions of the remaining transistors are separated from each other.

[0114] Please refer to Figures 10 and 11. Figure 10 is a film layer diagram of the second active layer 127 in the display panel 100 of this application, and Figure 11 is a film layer stack diagram of the first active layer 123, the second active layer 127 and the first gate layer 125 in the display panel 100 of this application.

[0115] In this embodiment, the second active layer 127 includes a first plate C1a of a first capacitor C1, a third plate C2a of a second capacitor C2, a fifth plate C3a of a third capacitor C3, and a seventh plate C4a of a fourth capacitor C4. The first plate C1a and the second plate C1b are at least partially overlapped, the third plate C2a and the fourth plate C2b are at least partially overlapped, the fifth plate C3a and the sixth plate C3b are at least partially overlapped, and the seventh plate C4a and the eighth plate C4b are at least partially overlapped.

[0116] Please refer to Figure 11. In order to increase the capacitance of the storage capacitor Cst1, this application makes the area of ​​the first plate C1a larger than the area of ​​the second plate C1b, the area of ​​the third plate C2a larger than the area of ​​the fourth plate C2b, the area of ​​the fifth plate C3a larger than the area of ​​the sixth plate C3b, and the area of ​​the seventh plate C4a larger than the area of ​​the eighth plate C4b. That is, the orthographic projection of the second plate C1b on the second active layer 127 is located within the first plate C1a, the orthographic projection of the fourth plate C2b on the second active layer 127 is located within the third plate C2a, the orthographic projection of the sixth plate C3b on the second active layer 127 is located within the fifth plate C3a, and the orthographic projection of the eighth plate C4b on the second active layer 127 is located within the seventh plate C4a.

[0117] It should be noted that, since the first electrode plate C1a needs to be connected to the sixteenth transistor T16, the first electrode plate C1a of this application is provided with a conductive structure connected to the sixteenth transistor T16, and this area does not overlap with the second electrode plate C1b.

[0118] Please refer to Figure 11. The fifth electrode plate C3a includes a first main electrode plate C3aa and a plurality of first branch electrodes C3ab connected to the first main electrode plate C3aa. The first main electrode plate C3aa extends along a first direction X, and the plurality of first branch electrodes C3ab extends along a second direction Y. The plurality of first branch electrodes C3ab are spaced apart in the first direction X. The first main electrode plate C3aa overlaps at least partially with the first main gate T9Ga, and the first branch electrodes C3ab overlaps at least partially with the corresponding first branch gate T9Gb. The length of the first branch electrode plate C3ab is less than the length of the first branch gate T9Gb.

[0119] Please refer to Figure 11. The seventh electrode C4a includes a second main electrode C4aa and a plurality of second branch electrodes C4ab connected to the second main electrode C4aa. The second main electrode C4aa extends along a first direction X, and the plurality of second branch electrodes C4ab extends along a second direction Y. The plurality of second branch electrodes C4ab are spaced apart in the first direction X. The second main electrode C4aa overlaps at least partially with the second main gate T10Ga, and the second branch electrodes C4ab overlaps at least partially with the corresponding second branch gate T10Gb. The length of the second branch electrode C4ab is less than the length of the second branch gate T10Gb.

[0120] In the structure shown in Figure 11, in order to increase the capacitance of the third capacitor C3 and the fourth capacitor C4, this application provides multiple branch plates in the fifth plate C3a and the seventh plate C4a. By having the branch plates overlap with the corresponding branch gates, the capacitance of the corresponding capacitors is further increased.

[0121] Referring to Figure 11, since the width of the first main gate T9Ga is smaller than the width of the second main gate T10Ga, the overlap area of ​​the first main gate T9Ga and the first main plate C3aa is smaller than the overlap area of ​​the second main gate T10Ga and the second main plate C4aa. In order to reduce the difference in capacitance between the third capacitor C3 and the fourth capacitor C4, this application can make the length of the first branch plate C3ab greater than the length of the second branch plate C4ab in the second direction Y, that is, the area of ​​the fifth plate C3a is greater than the area of ​​the seventh plate C4a, thereby reducing the difference in capacitance between the third capacitor C3 and the fourth capacitor C4.

[0122] In this embodiment, the overlapping area of ​​the fifth electrode plate C3a and the first gate T9G can be greater than or equal to the overlapping area of ​​the seventh electrode plate C4a and the second gate T10G.

[0123] Please refer to Figures 12 and 13. Figure 12 is a film layer diagram of the second gate layer 129 in the display panel 100 of this application, and Figure 13 is a film layer stack diagram of the first active layer 123, the second active layer 127, the first gate layer 125 and the second gate layer 129 in the display panel 100 of this application.

[0124] In this embodiment, the second gate layer 129 includes a first output segment 129a and a second output segment 129b. The first output segment 129a and the second output segment 129b extend along the second direction Y. The first output segment 129a is disposed close to the second output transistor T10 and extends away from the end of the second output transistor T10. The second output segment 129b is disposed on the side of the first electrode C1a away from the third electrode C2a.

[0125] In this embodiment, the first output segment 129a is connected to the drain of the first output transistor T9 and the second output transistor T10 to transmit the control signal output by the gate driving unit 200a to the in-plane; the second output segment 129b is connected to the gate driving unit 200a for outputting the light emission control signal EM, which means that the gate driving unit 200a for outputting the light emission control signal EM transmits the light emission control signal EM to the display area AA through the second output segment 129b and other output segments.

[0126] Please refer to Figures 14 and 15. Figure 14 is a film layer diagram of the first source-drain layer 131 in the display panel 100 of this application, and Figure 15 is a film layer stack diagram of the first active layer 123, the second active layer 127, the first gate layer 125, the second gate layer 129 and the first source-drain layer 131 in the display panel 100 of this application.

[0127] In this embodiment, the display panel 100 further includes a first source-drain layer 131 disposed on the side of the second active layer 127 away from the first active layer 123. The first source-drain layer 131 includes a first source T9S and a first drain T9D of the first output transistor T9, and a second source T10S and a second drain T10D of the second output transistor T10.

[0128] In this embodiment, the first drain T9D includes a first main drain T9Da and a plurality of first branch drains T9Db connected to the first main drain T9Da. The first main drain T9Da extends along a first direction X, and the plurality of first branch drains T9Db extend along a second direction Y. For example, in the structure of FIG14, the first drain T9D includes one first main drain T9Da and three first branch drains T9Db. The first main drain T9Da is located away from the display area AA.

[0129] In this embodiment, the first source T9S includes a first main source T9Sa and a plurality of first branch sources T9Sb connected to the first main source T9Sa. The first main source T9Sa extends along a first direction X, and the plurality of first branch sources T9Sb extend along a second direction Y. For example, in the structure of FIG14, the first source T9S includes one first main source T9Sa and two first branch sources T9Sb. The first main source T9Sa is located on the side of the first main drain T9Da close to the display area AA.

[0130] Please refer to Figure 14. Multiple first branch source electrodes T9Sb are spaced apart in the first direction X, multiple first branch source electrodes T9Sb and multiple first branch drain electrodes T9Db are spaced apart in the first direction X, and a first branch gate electrode T9Gb is disposed between adjacent first branch source electrodes T9Sb and first branch drain electrodes T9Db.

[0131] In this embodiment, the second drain T10D includes a second main drain T10Da and a plurality of second branch drains T10Db connected to the second main drain T10Da. The second main drain T10Da extends along a first direction X, and the plurality of second branch drains T10Db extend along a second direction Y. For example, in the structure of FIG14, the second drain T10D includes one second main drain T10Da and three second branch drains T10Db. The second main drain T10Da is located close to the display area AA.

[0132] In this embodiment, the second source T10S includes a second main source T10Sa and a plurality of second branch sources T10Sb connected to the second main source T10Sa. The second main source T10Sa extends along a first direction X, and the plurality of second branch sources T10Sb extends along a second direction Y. For example, in the structure of FIG14, the second source T10S includes one second main source T10Sa and two second branch sources T10Sb. The second main source T10Sa is located on the side of the second main drain T10Da away from the display area AA.

[0133] Please refer to Figure 14. Multiple second branch sources T10Sb are spaced apart in the first direction X, multiple second branch sources T10Sb and multiple second branch drains T10Db are spaced apart in the first direction X, and a second branch gate T10Gb is disposed between adjacent second branch sources T10Sb and second branch drains T10Db.

[0134] Please refer to Figure 15. The first main drain T9Da, the first main gate T9Ga, and the fifth plate C3a are all at least partially overlapped. The second main source T10Sa, the second main gate T10Ga, and the seventh plate C4a are all at least partially overlapped.

[0135] Please refer to Figure 15. The second branch drain T10Db, which is closer to the first output transistor T9, is shared with the first branch drain T9Db, which is closer to the second output transistor T10.

[0136] Please refer to Figures 15 and 16. The display panel 100 includes a plurality of first contact holes HL1 and a plurality of second contact holes HL2 disposed in the area where the first output transistor T9 is located. The first drain T9D passes through the plurality of first contact holes HL1 and is connected to the first active part T9A. The first source T9S passes through the plurality of second contact holes HL2 and is connected to the first active part T9A.

[0137] Please refer to Figures 15 and 16. The display panel 100 includes a plurality of third contact holes HL3 and a plurality of fourth contact holes HL4 located in the area where the second output transistor T10 is located. The second drain T10D passes through the plurality of third contact holes HL3 and is connected to the first active part T9A. The second source T10S passes through the plurality of fourth contact holes HL4 and is connected to the first active part T9A.

[0138] In this embodiment, the first contact hole HL1, the second contact hole HL2, the third contact hole HL3 and the fourth contact hole HL4 penetrate the second insulating layer 126, the third insulating layer 128, the fourth insulating layer 130 and a portion of the first insulating layer 124.

[0139] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a first connection segment 401. One end of the first connection segment 401 is connected to the second main source T10Sa, and the other end of the first connection segment 401 passes through a via and is connected to the active part T8A of the eighth transistor T8.

[0140] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a second connection segment 402. One end of the second connection segment 402 passes through a via and is connected to the second main gate T10Ga. The other end of the second connection segment 402 passes through a via and is connected to one end of the active portion T7A of the seventh transistor T7.

[0141] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a third connection segment 403. One end of the third connection segment 403 passes through a via and is connected to the first clock signal line XCK. The other end of the third connection segment 403 passes through a via and is connected to the gate T7G of the seventh transistor T7.

[0142] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a fourth connection segment 404. One end of the fourth connection segment 404 passes through a via and is connected to the other end of the active portion T7A of the seventh transistor T7. The other end of the fourth connection segment 404 passes through a via and is connected to one end of the active portion T6A of the sixth transistor T6. The middle section of the fourth connection segment 404 passes through a via and is connected to the third plate C2a of the second capacitor C2.

[0143] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a fifth connection segment 405. One end of the fifth connection segment 405 passes through a via and is connected to the other end of the gate T7G of the seventh transistor T7. The other end of the fifth connection segment 405 passes through a via and is connected to the other end of the active portion T6A of the sixth transistor T6.

[0144] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a sixth connection segment 406. One end of the sixth connection segment 406 passes through a via and is connected to one end of the active portion T3A of the third transistor T3. The other end of the sixth connection segment 406 passes through a via and is connected to one end of the active portion T14A of the fourteenth transistor T14.

[0145] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a seventh connection segment 407. One end of the seventh connection segment 407 passes through a via and is connected to the other end of the active portion T14A of the fourteenth transistor T14. The other end of the seventh connection segment 407 passes through a via and is connected to one end of the active portion T15A of the fifteenth transistor T15.

[0146] Please refer to Figures 15 and 16. The first source-drain layer 131 includes an eighth connection segment 408. One end of the eighth connection segment 408 passes through a via and is connected to the other end of the active portion T15A of the fifteenth transistor T15. The other end of the eighth connection segment 408 passes through a via and is connected to the second plate C1b of the first capacitor C1.

[0147] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a ninth connection segment 409. One end of the ninth connection segment 409 passes through a via and is connected to the first plate C1a of the first capacitor C1. The other end of the ninth connection segment 409 passes through a via and is connected to one end of the active portion T2A of the second transistor T2.

[0148] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a tenth connection segment 410. One end of the tenth connection segment 410 passes through a via and is connected to the other end of the active portion T2A of the second transistor T2. The other end of the tenth connection segment 410 passes through a via and is connected to the second clock signal line CK.

[0149] Please refer to Figures 15 and 16. The first source-drain layer 131 includes an eleventh connection segment 411. One end of the eleventh connection segment 411 passes through a via and is connected to the other end of the active portion T3A of the third transistor T3. The other end of the eleventh connection segment 411 passes through a via and is connected to one end of the gate T6G of the sixth transistor T6.

[0150] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a twelfth connection segment 412. One end of the twelfth connection segment 412 passes through a via and is connected to the other end of the gate T6G of the sixth transistor T6. The other end of the twelfth connection segment 412 passes through a via and is connected to the active portion T11A of the eleventh transistor T11.

[0151] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a thirteenth connection segment 413. One end of the thirteenth connection segment 413 passes through a via and is connected to the active portion T16A of the sixteenth transistor T16. The other end of the thirteenth connection segment 413 passes through a via and is connected to the second plate C1b of the first capacitor C1.

[0152] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a fourteenth connection segment 414. One end of the fourteenth connection segment 414 passes through a via and is connected to one end of the active portion T4A of the fourth transistor T4. The other end of the fourteenth connection segment 414 passes through a via and is connected to the gate T12G of the twelfth transistor T12. The first connection region in the middle of the fourteenth connection segment 414 passes through a via and is connected to the gate T15G of the fifteenth transistor T15. The second connection region in the middle of the fourteenth connection segment 414 passes through a via and is connected to the second low potential line VGL2.

[0153] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a fifteenth connection segment 415. One end of the fifteenth connection segment 415 passes through a via and is connected to the other end of the active portion T4A of the fourth transistor T4. The other end of the fifteenth connection segment 415 passes through a via and is connected to the gate T1G of the first transistor T1. The middle section of the fifteenth connection segment 415 passes through a via and is connected to one end of the active portion T11A of the eleventh transistor T11.

[0154] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a sixteenth connection segment 416. One end of the sixteenth connection segment 416 passes through a via and is connected to the gate T8G of the eighth transistor T8. The other end of the sixteenth connection segment 416 passes through a via and is connected to the active portion T12A of the twelfth transistor T12.

[0155] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a seventeenth connection segment 417. One end of the seventeenth connection segment 417 passes through a via and is connected to one end of the active portion T5A of the fifth transistor T5. The other end of the seventeenth connection segment 417 passes through a via and is connected to the first clock signal line XCK.

[0156] Please refer to Figures 15 and 16. The first source-drain layer 131 includes an eighteenth connection segment 418. One end of the eighteenth connection segment 418 passes through a via and is connected to the other end of the active portion T16A of the sixteenth transistor T16. The other end of the eighteenth connection segment 418 passes through a via and is connected to the first main gate T9Ga of the first output transistor T9.

[0157] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a nineteenth connection segment 419. One end of the nineteenth connection segment 419 passes through a via and is connected to the first plate C1a of the first capacitor C1. The other end of the nineteenth connection segment 419 passes through a via and is connected to one end of the first transistor T1.

[0158] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a twentieth connection segment 420. One end of the twentieth connection segment 420 passes through a via and is connected to the other end of the first transistor T1. The other end of the twentieth connection segment 420 passes through a via and is connected to the second high potential line VGH2.

[0159] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a twenty-first connection segment 421. One end of the twenty-first connection segment 421 passes through a via and is connected to the gate T13G of the thirteenth transistor T13. The other end of the twenty-first connection segment 421 is connected to the control line Control.

[0160] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a twenty-second connection segment 422. One end of the twenty-second connection segment 422 passes through a via and is connected to the second output segment 129b. The first output segment 129a passes through a via and is connected to the second main drain T10Da.

[0161] Please refer to Figures 15 and 16. The first source-drain layer 131 includes a twenty-third connection segment 423. One end of the twenty-second connection segment 422 is connected to the first main drain T9Da, and the other end of the twenty-third connection segment 423 is connected to the sixth connection segment 406 of the next-stage gate drive unit 200a, so as to transmit the control signal of this stage to the fourth transistor T4 and the fourteenth transistor T14 of the next stage.

[0162] Please refer to Figures 16 and 17. Figure 16 is a film layer diagram of the second source / drain layer 133 in the display panel 100 of this application, and Figure 17 is a film layer stack diagram of the first active layer 123, the second active layer 127, the first gate layer 125, the second gate layer 129, the first source / drain layer 131, and the second source / drain layer 133 in the display panel 100 of this application.

[0163] In this embodiment, the display panel 100 further includes a second source-drain layer 133 disposed on the side of the first source-drain layer 131 away from the second active layer 127. The second source-drain layer 133 includes a first high potential line VGH1 and a first low potential line VGL1. The first high potential line VGH1 and the first low potential line VGL1 extend along a first direction X. The first high potential line VGH1 is electrically connected to at least one second branch drain T10Db, and the first low potential line VGL1 is electrically connected to at least one first branch drain T9Db.

[0164] In the structure of Figure 16, the second source-drain layer 133 includes two first high potential lines VGH1 and one first low potential line VGL1. The first low potential line VGL1 is connected to the first branch source T9Sb of the first transistor T1, and the two first high potential lines VGH1 are both connected to the second branch source T10Sb of the second transistor T2.

[0165] In this embodiment, the first high potential line VGH1 and the first low potential line VGL1 both extend along the first direction X and are arranged along the second direction Y. The first low potential line VGL1 is set close to the display area AA, and the two first high potential lines VGH1 are set away from the display area AA. The width of the first low potential line VGL1 is greater than the width of any one of the first high potential lines VGH1.

[0166] In this embodiment, the second source-drain layer 133 further includes a second low potential line VGL2, an initial signal line STV, a first clock signal line XCK, a second clock signal line CK, a second high potential line VGH2, and a control line Control, which are arranged sequentially at intervals along the first direction X and along the second direction Y. The control line Control is disposed adjacent to the first high potential line VGH1.

[0167] It should be noted that the initial signal line STV is only connected to the sixth connection segment 406 in the first-stage gate drive unit 200a, and the sixth connection segment 406 in the second-stage and above gate drive units 200a is connected to the output terminal of the output circuit 222 of the previous stage gate drive unit 200a.

[0168] It should be noted that, in order to improve the wiring space of this application, the conductor portions located in the first active layer 123 and on both sides of the channel in some transistors of this application are reused as the source or drain of the corresponding transistor, and it is not necessary to separately set the source or drain of the corresponding transistor in the first source-drain layer 131.

[0169] This application also provides a display device, which includes the aforementioned display panel. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0170] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0171] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions in the embodiments of this application.

Claims

1. A display panel comprising: The display area includes a pixel driving circuit with multiple pixel transistors. The multiple pixel transistors include low-temperature polysilicon transistors and metal oxide transistors. The active part of the low-temperature polysilicon transistor is located in a first active layer, and the active part of the metal oxide transistor is located in a second active layer. A non-display area is located on one side of the display area. The non-display area is provided with a gate drive circuit of multiple cascaded gate drive units. Each gate drive unit includes multiple gate transistors and a storage capacitor connected to the gate transistors. The active portion of the gate transistor is located in one of the first active layer or the second active layer, and one plate of the storage capacitor is located in the other of the first active layer or the second active layer.

2. The display panel according to claim 1, wherein, The display panel further includes a first gate layer disposed between the first active layer and the second active layer, the first gate layer including the gates of a plurality of gate transistors and the other plate of the storage capacitor.

3. The display panel according to claim 2, wherein, The plurality of gate driving units are arranged along a first direction, and each gate driving unit includes: The output circuit includes a first output transistor and a second output transistor arranged along the first direction; A receiving circuit, arranged along the second direction with the output circuit, the receiving circuit includes a first node control module and a second node control module, the first output transistor and the first node control module are connected to the first node, and the second output transistor and the second node control module are connected to the second node; The storage capacitor includes a first capacitor and a second capacitor. The first capacitor includes a first electrode and a second electrode, which are respectively connected to different internal nodes in the first node control module. The second capacitor includes a third electrode and a fourth electrode, which are respectively connected to different internal nodes in the second node control module. The first electrode and the third electrode are located in the second active layer, and the second electrode and the fourth electrode are located in the first gate layer. The second direction is parallel to the scan line of the display panel, and the angle between the first direction and the second direction is greater than 0° and less than or equal to 90°.

4. The display panel according to claim 3, wherein, The storage capacitor also includes: The third capacitor includes a fifth plate and a sixth plate, wherein the fifth plate is connected to the source of the first output transistor and the sixth plate is connected to the first node; The fourth capacitor includes a seventh plate and an eighth plate, wherein the seventh plate is connected to the source of the second output transistor and the eighth plate is connected to the second node; The fifth and seventh electrode plates are located in the second active layer, and the sixth and eighth electrode plates are located in the first gate layer.

5. The display panel according to claim 4, wherein, The first gate layer includes a first gate of the first output transistor and a second gate of the second output transistor, wherein the first gate and the second gate are arranged in the first direction; The first gate includes a first main gate and a plurality of first branch gates connected to the first main gate. The first main gate extends along the first direction, and the plurality of first branch gates extend along the second direction. The plurality of first branch gates are spaced apart in the first direction. The first main gate and a portion of the first branch gates are multiplexed as the sixth electrode plate. The second gate includes a second main gate and a plurality of second branch gates connected to the second main gate. The second main gate extends along the first direction, and the plurality of second branch gates extend along the second direction. The plurality of second branch gates are spaced apart in the first direction. The second main gate and a portion of the second branch gates are multiplexed as the eighth electrode plate.

6. The display panel according to claim 5, wherein, In the second direction, the linewidth of the first main gate is smaller than the linewidth of the second main gate.

7. The display panel according to claim 5, wherein, The first gate layer further includes a second plate of the first capacitor and a fourth plate of the second capacitor. The second plate and the fourth plate are arranged along the first direction. The second plate is disposed close to the sixth plate, and the fourth plate is disposed close to the eighth plate. The area of ​​the second electrode plate is larger than the area of ​​the fourth electrode plate.

8. The display panel according to claim 5, wherein, The first active layer includes a first active portion of the first output transistor and a second active portion of the second output transistor. Both the first active portion and the second active portion extend along the first direction and are connected to each other. The first active portion overlaps with multiple first branch gates, and the second active portion overlaps with multiple second branch gates.

9. The display panel according to claim 8, wherein, In the second direction, the width of the first active part is smaller than the width of the second active part.

10. The display panel according to claim 8, wherein, The second active layer includes the first plate of the first capacitor, the third plate of the second capacitor, the fifth plate of the third capacitor, and the seventh plate of the fourth capacitor; Wherein, the first electrode plate and the second electrode plate are at least partially overlapped, the third electrode plate and the fourth electrode plate are at least partially overlapped, the fifth electrode plate and the sixth electrode plate are at least partially overlapped, and the seventh electrode plate and the eighth electrode plate are at least partially overlapped. The area of ​​the first electrode plate is greater than the area of ​​the second electrode plate, the area of ​​the third electrode plate is greater than the area of ​​the fourth electrode plate, the area of ​​the fifth electrode plate is greater than the area of ​​the sixth electrode plate, and the area of ​​the seventh electrode plate is greater than the area of ​​the eighth electrode plate.

11. The display panel according to claim 10, wherein, The fifth electrode plate includes a first main electrode plate and a plurality of first branch electrode plates connected to the first main electrode plate. The first main electrode plate extends along the first direction, and the plurality of first branch electrode plates extend along the second direction. The plurality of first branch electrode plates are spaced apart in the first direction. The first main electrode plate at least partially overlaps with the first main gate, and the first branch electrode plate at least partially overlaps with the corresponding first branch gate. The length of the first branch electrode plate is less than the length of the first branch gate.

12. The display panel according to claim 11, wherein, The seventh electrode plate includes a second main electrode plate and a plurality of second branch electrode plates connected to the second main electrode plate. The second main electrode plate extends along the first direction, and the plurality of second branch electrode plates extend along the second direction. The plurality of second branch electrode plates are spaced apart in the first direction. The second main electrode plate at least partially overlaps with the second main gate, and the second branch electrode plate at least partially overlaps with the corresponding second branch gate. The length of the second branch electrode plate is less than the length of the second branch gate.

13. The display panel according to claim 12, wherein, In the second direction, the length of the first branch plate is greater than the length of the second branch plate.

14. The display panel according to claim 12, wherein, In the second direction, the area of ​​the fifth electrode plate is larger than the area of ​​the seventh electrode plate.

15. The display panel according to claim 12, wherein, The overlapping area of ​​the fifth electrode plate and the first gate is greater than or equal to the overlapping area of ​​the seventh electrode plate and the second gate.

16. The display panel according to claim 10, wherein, The display panel further includes a first source-drain layer disposed on the side of the second active layer away from the first active layer, the first source-drain layer including the first source and the first drain of the first output transistor; The first drain includes a first main drain and a plurality of first branch drains connected to the first main drain. The first main drain extends along the first direction, and the plurality of first branch drains extend along the second direction. The first source includes a first main source and a plurality of first branch sources connected to the first main source. The first main source extends along the first direction, and the plurality of first branch sources extend along the second direction. The plurality of first branch sources are spaced apart in the first direction. The plurality of first branch sources and the plurality of first branch drains are spaced apart in the first direction, and a first branch gate is disposed between adjacent first branch sources and first branch drains.

17. The display panel according to claim 16, wherein, The first source-drain layer includes the second source and the second drain of the second output transistor; The second drain includes a second main drain and a plurality of second branch drains connected to the second main drain. The second main drain extends along the first direction, and the plurality of second branch drains extend along the second direction. The second source includes a second main source and a plurality of second branch sources connected to the second main source. The second main source extends along the first direction, and the plurality of second branch sources extend along the second direction. The plurality of second branch sources are spaced apart in the first direction. The plurality of second branch sources and the plurality of second branch drains are spaced apart in the first direction, and a second branch gate is disposed between adjacent second branch sources and second branch drains.

18. The display panel according to claim 17, wherein, The drain of the second branch closest to the first output transistor among the plurality of second branch drains is shared with the drain of the first branch closest to the second output transistor among the plurality of first branch drains.

19. The display panel according to claim 17, wherein, The display panel further includes a second source-drain layer disposed on the side of the first source-drain layer away from the second active layer, the second source-drain layer including a first high potential line and a first low potential line; The first high-potential line and the first low-potential line extend along the first direction. The first high-potential line is electrically connected to at least one drain of the second branch, and the first low-potential line is electrically connected to at least one drain of the first branch.

20. A display device, wherein, The display device includes a display panel as described in any one of claims 1 to 19.

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