Memory chip, memory system and electronic device

Abstract

The embodiments disclosed in the present application belong to the technical field of memories, and in particular, relate to a memory chip, a memory system and an electronic device. A memory cell of the memory chip includes a memory layer, a first metal layer, a first electrode layer and a second electrode layer that are stacked, wherein the memory layer and the first metal layer are located between the first electrode layer and the second electrode layer. When the memory layer is in a high-impedance state, a semiconductor material forming the memory layer and a metal material forming the first metal layer meet the condition for generating a Schottky barrier, and the barrier voltage of the generated Schottky barrier is opposite in direction to the operating voltage applied to the memory cell. When the memory layer is in a low-impedance state, the semiconductor material forming the memory layer and the metal material forming the first metal layer do not meet the condition for generating the Schottky barrier. By means of the present application, a voltage operating window corresponding to a memory cell can be increased, and the stability of storing data by the memory cell can be improved.

Description

Memory chips, storage systems and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411207711.6, filed on August 29, 2024, entitled "Memory Chip, Memory System and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of storage technology, and in particular to a storage chip, storage system and electronic device. Background Technology

[0003] The voltage operating window is an important parameter for measuring the stability of data storage in a memory cell. Its value is equal to the difference between the threshold voltage corresponding to the high-resistance state and the low-resistance state of the memory cell. Generally, the larger the voltage operating window of a memory cell, the easier it is to distinguish the storage state of the memory cell by the read voltage, and the higher the stability of the data stored in the memory cell.

[0004] In practical applications, storage cells are easily affected by factors such as threshold voltage drift and read / write interference, which can cause changes in the threshold voltage of the storage cell, thereby reducing the voltage operating window of the storage cell and reducing the stability of the stored data. Summary of the Invention

[0005] This application provides a memory chip, a memory system, and an electronic device, which can increase the voltage operating window of the memory cell and improve the stability of data stored in the memory cell. The corresponding technical solutions include:

[0006] In a first aspect, a memory chip is provided, comprising multiple memory cells. Each memory cell includes a stacked memory layer, a first metal layer, a first electrode layer, and a second electrode layer, wherein the memory layer and the first metal layer are located between the first electrode layer and the second electrode layer. The materials of the memory layer and the first metal layer satisfy the following conditions: when the memory layer is in a high-resistivity state, a potential barrier can be generated at the interface between the memory layer and the first metal layer, and the barrier voltage is opposite in direction to the voltage corresponding to the operating voltage applied to the memory cell. When the memory layer is in a low-resistivity state, no potential barrier is generated at the interface between the memory layer and the first metal layer.

[0007] Here, the interface refers to the contact surface between the storage layer and the first metal layer. The potential barrier generated at the interface can be a Schottky barrier.

[0008] In the solution shown in this application, a first metal layer adjacent to the storage layer is added to the storage cell. When the storage layer is in a high-resistivity state, it forms a Schottky barrier with the first metal layer, which impedes the operating voltage. This effectively increases the threshold voltage of the storage cell in the high-resistivity state. Since no Schottky barrier is formed between the storage layer and the first metal layer when the storage layer is in a low-resistivity state, the threshold voltage of the storage cell remains unchanged. Therefore, the solution shown in this application can increase the threshold voltage of the storage cell in the high-resistivity state, thereby increasing the voltage operating window of the storage cell and improving the stability of the stored data.

[0009] In one feasible implementation, the operating voltage is directed from the first electrode layer to the second electrode layer, the memory layer is a P-type semiconductor, and the first metal layer is adjacent to the first electrode layer. When the memory layer is in a high-resistivity state, the work function of the memory layer is greater than the work function of the first metal layer, thereby creating a Schottky barrier at the interface between the memory layer and the first metal layer. When the memory layer is in a low-resistivity state, the work function of the memory layer is less than the work function of the first metal layer, thereby avoiding the creation of a Schottky barrier at the interface between the memory layer and the first metal layer.

[0010] In one feasible implementation, the operating voltage is directed from the first electrode layer to the second electrode layer, the memory layer is an N-type semiconductor, and the first metal layer is adjacent to the second electrode layer. When the memory layer is in a high-resistivity state, the work function of the memory layer is less than the work function of the first metal layer, thereby creating a Schottky barrier at the interface between the memory layer and the first metal layer. When the memory layer is in a low-resistivity state, the work function of the memory layer is greater than the work function of the first metal layer, thereby avoiding the creation of a Schottky barrier at the interface between the memory layer and the first metal layer.

[0011] In the scheme shown in this application, the design of the memory cell can be completed according to the direction of the set operating voltage, the type of storage material corresponding to the storage layer, the relative position of the first metal layer in the memory cell, the work function of the storage layer when it is in different resistive states, and the work function of the first metal layer. This enables the storage layer to generate a Schottky barrier that hinders the operating voltage when it is in a high-resistivity state, and the first metal layer to increase the voltage operating window of the memory cell, thereby improving the stability of the data stored in the memory cell.

[0012] In one feasible implementation, when the memory layer is a P-type semiconductor, under high-resistivity conditions, the work function of the memory layer is greater than the sum of the work function of the first metal layer and a first compensation value, where the first compensation value is positive. When the memory layer is an N-type semiconductor, under high-resistivity conditions, the work function of the memory layer is less than the difference between the work function of the first metal layer and a second compensation value, where the second compensation value is positive.

[0013] In the scheme shown in this application, different compensation values ​​can be set for the storage material type of the storage layer, so that when the storage layer is in a high-resistivity state, the Schottky barrier can be guaranteed to impede the operating voltage, thereby increasing the threshold voltage of the storage cell in a high-resistivity state.

[0014] In one possible implementation, the memory cell further includes a second metal layer. The memory layer is located between the first and second metal layers, and the memory layer, the first metal layer, and the second metal layer are located between the first and second electrode layers. The second metal layer does not create a Schottky barrier with the memory layer, thus preventing the second metal layer from affecting the Schottky barrier created between the first metal layer and the memory layer on the operating voltage, and also preventing material diffusion between the memory layer and other electrode layers.

[0015] In one feasible approach, the thickness of the first metal layer is between 2 and 20 nm, which facilitates fabrication and also facilitates the creation of a potential barrier at the interface between the first metal layer and the memory layer.

[0016] In one feasible approach, the material forming the storage layer is a phase change material, a ferroelectric material, or a resistive switching material.

[0017] In a second aspect, a storage system is provided, comprising a storage chip as described in the first aspect above, and a storage controller connected to the storage chip.

[0018] Thirdly, an electronic device is provided, comprising a processor and a storage system as described in the second aspect above. The processor is used to send read / write instructions to the storage system to enable the storage system to perform read / write operations. Attached Figure Description

[0019] Figure 1 is a schematic diagram of a threshold voltage distribution provided in an embodiment of this application;

[0020] Figure 2 is a schematic diagram of the structure of a storage unit provided in an embodiment of this application;

[0021] Figure 3 is a schematic diagram of a threshold voltage distribution provided in an embodiment of this application;

[0022] Figure 4 is a schematic diagram of the structure of a 1S1R storage unit provided in an embodiment of this application;

[0023] Figure 5 is a schematic diagram of forming a Schottky barrier according to an embodiment of this application;

[0024] Figure 6 is a schematic diagram of forming a Schottky barrier according to an embodiment of this application;

[0025] Figure 7 is a schematic diagram of forming a Schottky barrier according to an embodiment of this application;

[0026] Figure 8 is a schematic diagram of forming a Schottky barrier according to an embodiment of this application;

[0027] Figure 9 is a schematic diagram of the structure of a storage unit provided in an embodiment of this application;

[0028] Figure 10 is a schematic diagram of the structure of a memory chip provided in an embodiment of this application;

[0029] Figure 11 is a schematic diagram of a storage system provided in an embodiment of this application;

[0030] Figure 12 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0031] Illustration: 11, Storage layer; 12, First metal layer; 13, First electrode layer; 14, Second electrode layer; 15, Second metal layer; 21, OTS layer; 22, Third electrode layer. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0033] Resistive memory: It uses changes in resistance to store or retrieve data. For example, a resistive memory can store "0" in a high resistance state and "1" in a low resistance state.

[0034] Phase Change Memory (PCM): A novel non-volatile semiconductor memory based on chalcogenide compounds, belonging to the resistive memory category. It utilizes the difference in resistance between the crystalline and amorphous states of the phase change material that makes up the PCM to store "0" and "1". Specifically, when the phase change material is in an amorphous state, it is in a high-resistance state, defined as the RESET(0) state; when the phase change material is in a crystalline state, it is in a low-resistance state, defined as the SET(1) state.

[0035] Ovonic Threshold Switch (OTS): A novel bidirectional gating device based on chalcogenide compounds. When an electrical pulse of arbitrary direction (either positive or negative) below the corresponding threshold voltage is applied to the OTS, the response current is small, exhibiting a high-resistance non-conducting state. When an electrical pulse of arbitrary direction (either positive or negative) above the corresponding threshold voltage is applied to the OTS, the response current is large, exhibiting a low-resistance conducting state.

[0036] 1S1R memory cell: A memory cell consisting of an OTS and a PCM. In one implementation, when the PCM in the 1S1R memory cell is in the RESET(0) state, the 1S1R memory cell stores "0", and at this time, the 1S1R memory cell has a higher threshold voltage Vthr. When the PCM in the 1S1R memory cell is in the SET(1) state, the 1S1R memory cell stores "1", and at this time, the 1S1R memory cell has a lower threshold voltage Vths.

[0037] Based on the above characteristics, it can be seen that when the 1S1R memory cell stores "0", the 1S1R device cell has a small response current under a specific read voltage Vread (greater than Vths, less than Vthr); when the 1S1R memory cell stores "1", the 1S1R device cell has a larger response current under the specific read voltage Vread. Therefore, data stored in the 1S1R memory cell can be read by applying the read voltage Vread.

[0038] Word line: The signal line required to select a 1S1R memory cell in a memory array. It works together with the bit line to complete the selection of a 1S1R memory cell.

[0039] Bit lines: Signal lines used to select a specific column in a memory array. Working together with word lines, they enable the selection of a 1S1R memory cell. By applying corresponding electrical pulses to the word lines and bit lines, the aforementioned write and read operations can be performed on the selected 1S1R memory cell.

[0040] Threshold voltage drift of OTS: The characteristic of OTS devices to have a shift in threshold voltage due to long-term operation or the influence of factors such as ambient temperature is called threshold voltage drift of OTS.

[0041] The work function, also known as the work function or work function, is the minimum energy required to move an electron from the interior of a solid to the surface of that object.

[0042] A Schottky barrier is a potential barrier formed at the interface between a metal and a semiconductor due to the difference in their work functions. Like a diode, a Schottky barrier exhibits rectifying characteristics, allowing current to flow more easily in one direction while impeding it in the other.

[0043] Figure 1 is a schematic diagram of a threshold voltage distribution provided in an embodiment of this application. In Figure 1, the horizontal axis (Vt) represents the magnitude of the threshold voltage, and the vertical axis (count) represents the number of memory cells. As can be seen from Figure 1, the threshold voltage of a memory cell storing "1" is less than the threshold voltage of a memory cell storing "0". The interval between the threshold voltage distribution curve corresponding to the memory cell storing "1" and the threshold voltage distribution curve corresponding to the memory cell storing "0" is the voltage operation window, the size of which is equal to the difference between the maximum threshold voltage corresponding to the memory cell storing "1" and the minimum threshold voltage corresponding to the memory cell storing "0".

[0044] The voltage operating window is a critical parameter of a memory cell, within which the read voltage set for the cell falls. In practical applications, memory cells are easily affected by factors such as manufacturing processes, threshold voltage drift, and read / write interference, leading to a smaller voltage operating window. For example, because memory cells may experience threshold voltage drift, and the degree of drift differs between low-resistance and high-resistance states, the voltage operating window may shift and decrease. In severe cases, this can cause the voltage operating window to disappear, resulting in the failure of some memory cells.

[0045] This application provides a memory chip in which the memory cells can utilize the Schottky barrier to increase the threshold voltage of the memory cells in the high-resistivity state, thereby increasing the voltage operating window and improving the stability of data stored in the memory cells.

[0046] Figure 2 is a schematic diagram of the structure of a memory cell included in a memory chip provided in an embodiment of this application. As shown in Figure 2, the memory cell includes a stacked memory layer 11, a first metal layer 12, a first electrode layer 13, and a second electrode layer 14. The memory layer 11 and the first metal layer 12 are located between the first electrode layer 13 and the second electrode layer 14.

[0047] The memory layer 11 is composed of a semiconductor material and has two states: a high-resistivity state and a low-resistivity state. The semiconductor material constituting the memory layer 11 can be a phase-change material with phase-change characteristics. For example, it can be a PCM material, or further, an alloy based on chalcogenide compounds, such as a Ge-Sb-Te alloy. When the phase-change material constituting the memory layer 11 is in a crystalline state, the memory layer 11 is in a low-resistivity state; when the phase-change material constituting the memory layer 11 is in an amorphous state, the memory layer 11 is in a high-resistivity state. The memory layer 11 has different work functions in different resistance states.

[0048] Alternatively, the semiconductor material of the storage layer 11 can also be a resistive switching material with resistance change characteristics, such as a transition metal oxide, or a ferroelectric material with polarization direction change characteristics, such as zirconium ferrite, titanium ferrite, potassium niobium ferrite, etc.

[0049] The first metal layer 12 is made of a metallic material and is bonded to the storage layer 11. The materials used for the storage layer 11 and the first metal layer 12 can meet the following requirements:

[0050] When the memory layer 11 is in a high-resistivity state, the semiconductor material forming the memory layer 11 and the metal material forming the first metal layer 12 satisfy the conditions for generating a Schottky barrier, and the barrier voltage corresponding to the Schottky barrier generated at the interface between the memory layer 11 and the first metal layer 12 is opposite in direction to the operating voltage applied to the memory cell. When the memory layer 11 is in a low-resistivity state, the semiconductor material forming the memory layer 11 and the metal material forming the first metal layer 12 do not satisfy the conditions for generating a Schottky barrier.

[0051] In this embodiment, the Schottky barrier generated at the interface between the storage layer 11 and the first metal layer 12 will hinder the operating voltage of the storage cell in the high-resistivity state, which means that the operating voltage of the storage cell in the high-resistivity state needs to be increased, which is equivalent to increasing the threshold voltage of the storage cell in the high-resistivity state.

[0052] Thus, when storage layer 11 is in a high-resistivity state, such as storing "0", the presence of the Schottky barrier necessitates an additional voltage applied across the storage cell to overcome its influence, effectively increasing the threshold voltage for storing "0". Conversely, when storage layer 11 is in a low-resistivity state, such as storing "1", the absence of the Schottky barrier necessitates only enabling storage layer 11 to conduct, effectively keeping the threshold voltage for storing "1" unchanged. This increases the difference between the threshold voltage of the low-resistivity and high-resistivity states, effectively expanding the voltage operating window of the storage cell and thereby improving the stability of stored data.

[0053] Figure 3 is a schematic diagram of a threshold voltage distribution provided in an embodiment of this application. In Figure 3, the solid curves represent the threshold voltage distribution of the memory cell without the first metal layer 12, and the dashed curves represent the threshold voltage distribution of the memory cell with the first metal layer 12 added. As can be seen from Figure 3, after adding the first metal layer 12, the threshold voltage of the low-resistivity memory cell remains unchanged, while the overall threshold voltage of the high-resistivity memory cell increases. Therefore, the voltage operating window between the low-resistivity and high-resistivity memory cells is increased, thereby improving the stability of data storage in the memory cell.

[0054] In one example, the storage unit provided in this application embodiment can be a 1S1R storage unit. The storage layer 11, first metal layer 12, first electrode layer 13, and second electrode layer 14 in the storage unit can constitute the storage device in the 1S1R storage unit. The storage unit also includes a gating device. Figure 4 is a schematic diagram of the structure of a 1S1R storage unit provided in an embodiment of this application. As shown in Figure 4, the 1S1R storage unit includes a storage device and a gating device. The storage device includes a stacked storage layer 11, a first metal layer 12, a first electrode layer 13, and a second electrode layer 14. The gating device includes a stacked OTS layer 21 and a third electrode layer 22, wherein the OTS layer 21 can be located between the second electrode layer 14 and the third electrode layer 22.

[0055] The first electrode layer 13, the second electrode layer 14, and the third electrode layer 22 can be inert metal electrode layers, meaning the electrode materials can be W (tungsten), Co (cobalt), Cu (copper), Al (aluminum), Pt (platinum), Au (gold), Ru (ruthenium), Ti (titanium), TiW (titanium-tungsten alloy), TiN (titanium nitride), TaN (tantalum nitride), C (carbon), polycrystalline silicon, doped silicon, etc. The OTS layer 21 is composed of OTS material. The first metal layer 12 can be composed of metallic materials, such as W, Ru, Ti, or titanium alloys. The semiconductor materials constituting the memory layer 11 can include P-type semiconductors and N-type semiconductors.

[0056] When the types of semiconductor materials are different, the conditions for forming a Schottky barrier differ between the semiconductor material constituting the memory layer 11 and the metal material constituting the first metal layer 12. The conditions for forming a Schottky barrier are described below for different types of semiconductor materials and the direction of the memory cell operating voltage:

[0057] Case 1: The direction of the operating voltage is from the first electrode layer 13 to the second electrode layer 14, the storage layer 11 is a P-type semiconductor, and the first metal layer 12 is adjacent to the first electrode layer 13.

[0058] When memory layer 11 is a P-type semiconductor, the work function φ of memory layer 11 in the high-resistivity state a The work function W is greater than that of the first metal layer 12. mA Schottky barrier can only be formed at the interface between the storage layer 11 and the first metal layer 12, and the direction of the barrier voltage corresponding to the formed Schottky barrier is from the storage layer 11 to the first metal layer 12. Figure 5 is a schematic diagram of the formation of a Schottky barrier according to an embodiment of this application. As shown in Figure 5, the direction of the barrier voltage corresponding to the Schottky barrier formed between the first metal layer 12 and the storage layer 11 is from the storage layer 11 to the first metal layer 12. When the operating voltage applied to the storage cell is from the first electrode layer 13 to the second electrode layer 14, the direction of the operating voltage is opposite to the direction of the barrier voltage corresponding to the Schottky barrier. Thus, when the storage cell is in a high-resistivity state, the formed Schottky barrier can impede the operating voltage, which is equivalent to increasing the threshold voltage corresponding to the storage cell.

[0059] When memory layer 11 is a P-type semiconductor, the work function φ of memory layer 11 in the low-resistivity state c The work function W is less than that of the first metal layer 12 m The interface between storage layer 11 and first metal layer 12 does not form a Schottky barrier. Therefore, when the storage cell is in a low-resistivity state, the presence of first metal layer 12 does not affect the threshold voltage of the storage cell.

[0060] In this way, when the memory cell is in a low-resistance state, the threshold voltage of the memory cell remains unchanged. When the memory cell is in a high-resistance state, the threshold voltage of the memory cell increases, thereby increasing the operating voltage window.

[0061] In one example, to further ensure that a Schottky barrier can be generated between the storage layer 11 and the first metal layer 12, a first compensation value may be provided in this embodiment. That is, when the storage layer 11 is in a high-resistivity state, the work function of the storage layer 11 is greater than the sum of the work function of the first metal layer 12 and the first compensation value, wherein the first compensation value is a positive number. This embodiment does not limit the specific value of the first compensation value; for example, the first compensation value can be 0.3 electron volts (eV). Additionally, when the storage layer 11 is in a low-resistivity state, the work function of the storage layer 11 is less than the sum of the work function of the first metal layer 12 and the first compensation value. Alternatively, to further avoid the generation of a Schottky barrier between the storage layer 11 and the first metal layer when the storage layer 11 is in a low-resistivity state, the work function of the storage layer 11 may be less than the difference between the work function of the first metal layer 12 and the first compensation value.

[0062] In the memory cell shown in Figure 5, from top to bottom, the layers are a first electrode layer 13, a first metal layer 12, a memory layer 11, and a second electrode layer 14. In another example, as shown in Figure 6, the memory cell from top to bottom consists of a second electrode layer 14, a memory layer 11, a first metal layer 12, and a first electrode layer 13. In the memory cell shown in Figure 6, the direction of the corresponding operating voltage is still from the first electrode layer 13 to the second electrode layer 14. The work function corresponding to the first metal layer 12 and the memory layer 11 also satisfies the requirement when the memory layer 11 is a P-type semiconductor, that is, the work function φ when the memory layer 11 is in a high-resistivity state. a The work function W is greater than that of the first metal layer 12. m The work function φ of storage layer 11 in the low-resistance state c The work function W needs to be less than that of the first metal layer 12. m .

[0063] It should be noted that the work function of the metal material corresponding to the first metal layer 12 and the work function of the semiconductor material corresponding to the storage layer 11 in the high-resistivity and low-resistivity states, respectively, can both be measured experimentally. In practice, the material combination of the semiconductor material corresponding to the storage layer 11 and the metal material corresponding to the first metal layer 12 in the storage cell can be determined based on actual experimental data. The specific material combinations are not listed in the embodiments of this application.

[0064] Case 2: The direction of the operating voltage is from the first electrode layer 13 to the second electrode layer 14, the storage layer 11 is an N-type semiconductor, and the first metal layer 12 is adjacent to the second electrode layer 14.

[0065] When memory layer 11 is an N-type semiconductor, the work function φ of memory layer 11 in the high-resistivity state a The work function W is less than that of the first metal layer 12 m A Schottky barrier can only be formed at the interface between the storage layer 11 and the first metal layer 12, and the barrier voltage direction corresponding to the formed Schottky barrier is from the first metal layer 12 to the storage layer 11. Figure 7 is a schematic diagram of the formation of a Schottky barrier according to an embodiment of this application. As shown in Figure 7, the barrier voltage direction corresponding to the Schottky barrier formed by the first metal layer 12 and the storage layer 11 is from the first metal layer 12 to the storage layer 11. When the operating voltage applied to the storage cell is from the first electrode layer 13 to the second electrode layer 14, the direction of the operating voltage is opposite to the direction of the barrier voltage corresponding to the Schottky barrier. Thus, when the storage cell is in a high-resistivity state, the formed Schottky barrier can impede the operating voltage, which is equivalent to increasing the threshold voltage corresponding to the storage cell.

[0066] When memory layer 11 is an N-type semiconductor, the work function φ of memory layer 11 in the low-resistivity state cThe work function W is greater than that of the first metal layer 12. m The interface between storage layer 11 and first metal layer 12 does not form a Schottky barrier. Therefore, when the storage cell is in a low-resistivity state, the presence of first metal layer 12 does not affect the threshold voltage of the storage cell.

[0067] In this way, when the memory cell is in a low-resistance state, the threshold voltage of the memory cell remains unchanged. When the memory cell is in a high-resistance state, the threshold voltage of the memory cell increases, thereby increasing the operating voltage window.

[0068] In one example, to further ensure that a Schottky barrier can be generated between the storage layer 11 and the first metal layer 12, a second compensation value may be provided in this embodiment. That is, when the storage layer 11 is in a high-resistivity state, the work function of the storage layer 11 is less than the difference between the work function of the first metal layer 12 and the second compensation value, wherein the second compensation value is a positive number. This embodiment does not limit the specific value of the second compensation value; for example, the second compensation value can be 0.3 eV. Additionally, when the storage layer 11 is in a low-resistivity state, the work function of the storage layer 11 is greater than the difference between the work function of the first metal layer 12 and the second compensation value. Alternatively, to further avoid the generation of a Schottky barrier between the storage layer 11 and the first metal layer when the storage layer 11 is in a low-resistivity state, the work function of the storage layer 11 can be greater than the sum of the work function of the first metal layer 12 and the second compensation value.

[0069] In the memory cell shown in Figure 7, from top to bottom, the layers are a first electrode layer 13, a memory layer 11, a first metal layer 12, and a second electrode layer 14. In another example, as shown in Figure 8, the memory cell from top to bottom consists of a second electrode layer 14, a first metal layer 12, a memory layer 11, and a first electrode layer 13. In the memory cell shown in Figure 8, the direction of the corresponding operating voltage is still from the first electrode layer 13 to the second electrode layer 14. The work function corresponding to the first metal layer 12 and the memory layer 11 also satisfies the requirement when the memory layer 11 is an N-type semiconductor, that is, the work function φ when the memory layer 11 is in a high-resistivity state... a The work function W is less than that of the first metal layer 12 m The work function φ of storage layer 11 in the low-resistance state c The work function W needs to be greater than that of the first metal layer 12. m .

[0070] In one possible implementation, the memory cell further includes a second metal layer 15. The memory layer 11 is located between the first metal layer 12 and the second metal layer 15, and the memory layer 11, the first metal layer 12, and the second metal layer 15 are located between the first electrode layer 13 and the second electrode layer 14. As shown in Figure 9, in one example, the memory layer 11 can be adjacent to both the first metal layer 12 and the second metal layer 15. The thickness of the second metal layer 15 can be the same as the thickness of the first metal layer 12, i.e., the thickness can be between 2 and 20 nm. Setting the thickness between 2 and 20 nm facilitates the fabrication of the memory cell, and the first metal layer 12 can normally generate a Schottky barrier at the interface with the memory layer 11.

[0071] In this configuration, the storage layer 11 does not generate a Schottky barrier with the second metal layer 15 when it is in both the high-resistivity and low-resistivity states. For example, when the material of the storage layer 11 is a P-type semiconductor, the work functions corresponding to the high-resistivity and low-resistivity states of the storage layer 11 are both less than the work function of the second metal layer 15. Similarly, when the material of the storage layer 11 is an N-type semiconductor, the work functions corresponding to the high-resistivity and low-resistivity states of the storage layer 11 are both greater than the work function of the second metal layer 15. The fact that the second metal layer 15 does not generate a Schottky barrier with the storage layer 11 does not affect the effect of the Schottky barrier generated between the first metal layer 12 and the storage layer 11 on increasing the voltage operating window of the memory cell. Adding a second metal layer 15 between the storage layer 11 and the second electrode layer 14 prevents the storage material of the storage layer 11 from diffusing with the electrode material of the second electrode layer 14. Likewise, adding a first metal layer 12 between the storage layer 11 and the first electrode layer 13 also prevents the storage material of the storage layer 11 from diffusing with the electrode material of the first electrode layer 13. This can further improve the stability and lifespan of the stored data in the storage unit.

[0072] Figure 10 is a schematic diagram of a memory chip provided in an embodiment of this application. As shown in Figure 10, the memory chip may include a control circuit and at least one memory array, with the control circuit connected to the at least one memory array. The memory array includes multiple memory cells arranged in rows and columns as described in the above embodiments. Because the memory cells provided in this embodiment have an additional metal intercalation layer (first metal layer), the Schottky barrier generated at the interface between the first metal layer and the memory layer can increase the voltage operating window of the memory cell. Therefore, using the memory chip provided in this embodiment can also improve the stability of stored data.

[0073] Based on the same inventive concept, this application also provides a storage system. Figure 11 is a schematic diagram of the structure of a storage system provided in this application embodiment. As shown in Figure 11, the storage system may include a storage controller and at least one storage chip as shown in Figure 10. The storage controller can send read and write instructions to the storage chip to enable the storage chip to complete data read and write operations. The storage chip provided in this application embodiment can improve the stability of stored data. Therefore, a storage system using the storage chip provided in this application embodiment can also improve the stability of stored data.

[0074] Based on the same inventive concept, this application also provides an electronic device. Figure 12 is a schematic diagram of the structure of an electronic device provided in this application embodiment. As shown in Figure 12, the electronic device includes a processor and a storage system as shown in Figure 11. The processor is used to send read and write instructions to the storage system to enable the storage system to perform read and write operations. Since the storage system provided in this application embodiment can improve the stability of stored data, the stability of data stored in the electronic device using the storage system provided in this application embodiment can also be improved.

[0075] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items that have essentially the same function. It should be understood that there is no logical or temporal dependency between "first" and "second," nor does it limit the quantity or order of execution. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another.

[0076] In this application, the term "at least one" means one or more, and the term "multiple" means two or more.

[0077] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory chip, characterized in that, The memory chip includes multiple memory cells, each memory cell including a stacked memory layer (11), a first metal layer (12), a first electrode layer (13), and a second electrode layer (14), wherein the memory layer (11) and the first metal layer (12) are located between the first electrode layer (13) and the second electrode layer (14). When the storage layer (11) is in a high-resistivity state, a barrier is generated at the interface between the storage layer (11) and the first metal layer (12), and the barrier voltage of the generated barrier is opposite in direction to the voltage corresponding to the operating voltage applied to the storage cell. When the storage layer (11) is in a low-resistivity state, no barrier is generated at the interface between the storage layer (11) and the first metal layer (12).

2. The memory chip according to claim 1, characterized in that, The direction of the operating voltage is from the first electrode layer (13) to the second electrode layer (14), the storage layer (11) is a P-type semiconductor, and the first metal layer (12) is adjacent to the first electrode layer (13); When the storage layer (11) is in a high-resistivity state, the work function of the storage layer (11) is greater than the work function of the first metal layer (12) to generate a potential barrier at the interface; When the storage layer (11) is in a low-resistivity state, the work function of the storage layer (11) is less than the work function of the first metal layer (12) to avoid generating a potential barrier at the interface.

3. The memory chip according to claim 2, characterized in that, When the storage layer (11) is in a high-resistivity state, the work function of the storage layer (11) is greater than the sum of the work function of the first metal layer (12) and the first compensation value, where the first compensation value is a positive number.

4. The memory chip according to claim 1, characterized in that, The direction of the operating voltage is from the first electrode layer (13) to the second electrode layer (14), the storage layer (11) is an N-type semiconductor, and the first metal layer (12) is adjacent to the second electrode layer (14); When the storage layer (11) is in a high-resistivity state, the work function of the storage layer (11) is less than the work function of the first metal layer (12) to generate a potential barrier at the interface; When the storage layer (11) is in a low-resistivity state, the work function of the storage layer (11) is greater than the work function of the first metal layer (12) to avoid generating a potential barrier at the interface.

5. The memory chip according to claim 3, characterized in that, When the storage layer (11) is in a high-resistivity state, the work function of the storage layer (11) is less than the difference between the work function of the first metal layer (12) and the second compensation value, where the second compensation value is a positive number.

6. The memory chip according to any one of claims 1 to 5, characterized in that, The storage unit further includes a second metal layer (15), wherein the storage layer (11) is located between the first metal layer (12) and the second metal layer (15), and the storage layer (11), the first metal layer (12) and the second metal layer (15) are located between the first electrode layer (13) and the second electrode layer (14).

7. The memory chip according to any one of claims 1 to 6, characterized in that, The thickness of the first metal layer (12) is between 2 and 20 nm.

8. The memory chip according to any one of claims 1 to 7, characterized in that, The material forming the storage layer (11) is a phase change material, a ferroelectric material, or a resistive switching material.

9. A storage system, characterized in that, The storage system includes the storage chip as described in claim 8, and a storage controller connected to the storage chip.

10. An electronic device, characterized in that, The electronic device includes a processor and the storage system as described in claim 9; The processor is used to send read and write instructions to the storage system so that the storage system can perform read and write operations.

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