Storage medium controller, memory, and storage device

Abstract

The present application relates to the technical field of storage, and discloses a storage medium controller, a memory, and a storage device. The storage medium controller is connected, by means of a hot-swap interface and in a hot-swappable manner, to an interface circuit into which a plurality of memories are plugged, or is directly connected to interface circuits of a plurality of first memories in a hot-swappable manner. When the storage medium controller is applied to a storage device in a storage system, during operation of the storage device, if the storage medium controller fails, the failed storage medium controller in the storage device can be replaced in a hot-swappable manner, so that there is no need to replace the storage device, reducing the maintenance cost of the storage system.

Description

Storage media controller, memory, and storage device

[0001] This application claims priority to Chinese Patent Application No. 202411223362.7, filed on August 30, 2024, entitled "Storage Medium Controller, Memory and Storage Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of storage technology, and in particular to a storage medium controller, a memory, and a storage device. Background Technology

[0003] For the massive data storage needs of scenarios such as artificial intelligence (AI), cloud computing, and the Internet, high-capacity solid-state drives (SSDs) can meet customers' demands for higher density, lower energy efficiency, and reduced total cost of ownership (TCO) of storage devices in storage systems.

[0004] Currently, storage systems store data using high-capacity SSDs. A high-capacity SSD includes a controller and multiple storage media, all integrated into one unit. If the controller of one of the SSDs in the storage system fails, the faulty SSD needs to be replaced, which increases the maintenance cost of the storage system. Summary of the Invention

[0005] This application provides a storage medium controller, a memory, and a storage device, which can reduce the maintenance cost of storage systems. The technical solution is as follows:

[0006] In a first aspect, a storage medium controller is provided, the storage medium controller comprising:

[0007] Host interface, used to connect to the host;

[0008] A hot-swappable interface is used to connect to an interface circuit that connects to multiple first memories via hot-swapping, or to connect directly to an interface circuit that connects to multiple first memories via hot-swapping, each first memory including at least one storage medium.

[0009] The first control chip is used to connect to the host interface and hot-swappable interface to manage the storage medium;

[0010] The first control chip is also used to perform data access between the host and the storage media in the multiple first memories based on the first mapping relationship between logical addresses and multiple first memories.

[0011] The storage medium controller can be hot-swapped to the interface circuits of multiple memory devices, or directly hot-swapped to the interface circuits of multiple first memory devices. When the storage medium controller is used in the storage device of the storage system, if the storage medium controller fails during the operation of the storage device, the faulty storage medium controller in the storage device can be replaced by hot-swapping without replacing the storage device, thereby reducing the maintenance cost of the storage system.

[0012] In one possible implementation, the first control chip is further configured to: receive input / output (I / O) requests from the host via a host interface, wherein the I / O requests indicate data access to a target logical address; send I / O requests to target memories in a plurality of first memories based on the aforementioned first mapping relationship, wherein the target memories are memories mapped to the target logical addresses; receive I / O responses from the target memories via a hot-plug interface, wherein the I / O responses are access results to the physical addresses corresponding to the target logical addresses; and send I / O responses to the host via the host interface.

[0013] In one possible implementation, the first control chip is further configured to: allocate a target memory for the I / O request from multiple first memories when the I / O request is a write request; send the I / O request to the target memory; and establish a first mapping relationship between the target logical address and the target memory.

[0014] In one possible implementation, the first control chip is further configured to: when the I / O request is a read request, query the target memory mapped to the target logical address based on the first mapping relationship between the logical address and multiple first memories; and send an I / O request to the queried target memory.

[0015] Based on the above possible implementation methods, the ability of the storage medium controller in the storage device to access physical addresses is offloaded to the control circuit in the memory. When data access is required, the storage medium controller determines the target memory based on the first mapping relationship between logical addresses and multiple memories. The control circuit in the target memory then accesses the data at the physical address corresponding to the logical address based on the second mapping relationship between the logical address and the physical address in the storage medium of the target memory. This eliminates the need for the storage medium controller to access the physical address in the physical address space of the storage device, saving the computing power of the storage medium controller and allowing it to control more memories with sufficient computing power.

[0016] In one possible implementation, the first control chip further includes a cache area for storing the aforementioned first mapping relationship.

[0017] Based on the above possible implementation methods, the occupation of the control chip's internal storage space by the first mapping relationship can be reduced.

[0018] In one possible implementation, the hot-swappable interface is hot-swappable to the connector, which includes interface circuitry for inserting multiple first memories; alternatively, the connector is directly hot-swappable to the interface circuitry of the multiple first memories.

[0019] In one possible implementation, a second control chip is also connected to the connector, and the second control chip stores the first mapping relationship;

[0020] The second control chip is used to access data between the host and storage media in multiple first memories based on the first mapping relationship stored in the memory.

[0021] The first control chip is also used to obtain a first mapping relationship from the second control chip through a connector, and to perform data access between the host and the storage media in the multiple first memories based on the obtained first mapping relationship.

[0022] Based on the above possible implementation methods, the storage medium controller synchronizes the logical address with the backup storage medium controller to establish a first mapping relationship between the storage medium controller and the memory it controls. This allows the backup storage medium controller to access the memory controlled by the storage medium controller based on the synchronized first mapping relationship in the event of a failure of the storage medium controller. This eliminates the need for the host to wait for the storage medium controller to recover from the failure, thus improving the efficiency of the host accessing the memory.

[0023] In one possible implementation, a storage device is also connected to the connector. The storage device includes a third control chip and multiple second memories. The third control chip stores a first mapping relationship between logical addresses and multiple second memories.

[0024] The third control chip is used to access data between the host and the storage media in the multiple second memories based on the first mapping relationship between the stored logical address and the multiple second memories;

[0025] The first control chip is also used to obtain a first mapping relationship between a logical address and multiple second memories from the third control chip through a connector, and to perform data access between the host and the storage media in the multiple second memories based on the obtained first mapping relationship between the logical address and the multiple second memories.

[0026] Based on the above possible implementation methods, the first mapping relationship between the logical address and the second memory in the storage device is synchronized to the first storage medium controller by the third storage medium controller in the storage device. This allows the first storage medium controller to access the data in the second memory in the storage device based on the synchronized first mapping relationship in the event of a failure of the third storage medium controller, without the host having to wait for the third storage medium controller to recover from the failure, thus improving the efficiency of the host accessing the memory.

[0027] In one possible implementation, the first control chip further includes a cache area for storing a first mapping relationship between logical addresses and multiple second memories.

[0028] Based on the above possible implementation methods, the occupation of the control chip's internal storage space by the first mapping relationship can be reduced.

[0029] In one possible implementation, the first control chip is further configured to: determine a first physical address space, which is a physical address space in multiple first memories to be garbage collected; copy valid data stored in the first physical address space to a second physical address space in the multiple first memories; and delete all data stored in the first physical address space. Based on the above possible implementation, the requirements for garbage collection of the memory can be met.

[0030] In a second aspect, a memory is provided, the memory including a hot-swappable interface, control circuitry, and at least one storage medium;

[0031] A hot-swappable interface is used to connect to the interface circuit of the storage media controller via hot-swapping, or to connect directly to the interface circuit of the storage media controller via hot-swapping.

[0032] Control circuitry, used to connect to the hot-swappable interface and storage media, and to manage the storage media;

[0033] The control circuit is also used to receive input / output I / O requests from the storage medium controller via a hot-swappable interface. The I / O requests indicate data access to a target logical address.

[0034] The control circuit is also used to access data on the physical address mapped to the target logical address in at least one storage medium based on a second mapping relationship between the logical address and the physical address in at least one storage medium, and to send an I / O response to the storage medium controller through a hot-plug interface. The I / O response is the access result of the physical address corresponding to the target logical address.

[0035] The memory can be hot-swapped to the interface circuit of the storage medium controller via a hot-swappable interface, or directly hot-swapped to the interface circuit of the storage medium controller. When the memory is used in the storage device of the storage system, if the memory fails during the operation of the storage device, the faulty memory in the storage device can be replaced by hot-swapping without replacing the storage device, thereby reducing the maintenance cost of the storage system.

[0036] In one possible implementation, the control circuit is further configured to: allocate a target physical address for the I / O request from a physical address in at least one storage medium when the I / O request is a write request; write the first data carried by the I / O request to the storage space corresponding to the target physical address; and establish a second mapping relationship between the target logical address and the target physical address.

[0037] In one possible implementation, the control circuit is further configured to: when the I / O request is a read request, query the target physical address mapped to the target logical address based on a second mapping relationship between the logical address and the physical address in at least one storage medium; and read the data stored in the storage space corresponding to the target physical address.

[0038] Based on the above possible implementation methods, the ability of the storage medium controller in the storage device to access physical addresses is offloaded to the control circuit in the memory. When data access is required, the storage medium controller determines the target memory based on the first mapping relationship between logical addresses and multiple memories. The control circuit in the memory then accesses the data at the physical address corresponding to the logical address based on the second mapping relationship between the logical address and the physical address in the storage medium of the memory. This eliminates the need for the storage medium controller to access the physical address in the physical address space of the storage device, saving the computing power of the storage medium controller and allowing it to control more memories with sufficient computing power.

[0039] In one possible implementation, the memory also includes a buffer for storing a second mapping.

[0040] Based on the above possible implementation methods, the internal storage space occupied by the second mapping relationship in the control circuit can be reduced.

[0041] Thirdly, a storage device is provided, comprising any of the storage medium controllers provided in the first aspect and any of the memory provided in the second aspect. Attached Figure Description

[0042] Figure 1 is a schematic diagram of the structure of a storage device provided in an embodiment of this application;

[0043] Figure 2 is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0044] Figure 3 is a schematic diagram of another storage device provided in an embodiment of this application;

[0045] Figure 4 is a comparative schematic diagram of an FTL mapping table provided in an embodiment of this application;

[0046] Figure 5 is a flowchart of a data access method provided in an embodiment of this application;

[0047] Figure 6 is a schematic diagram of another storage device provided in an embodiment of this application;

[0048] Figure 7 is a schematic diagram of another storage device provided in an embodiment of this application;

[0049] Figure 8 is a schematic diagram of the switching of a primary and backup storage media controller provided in an embodiment of this application;

[0050] Figure 9 is a flowchart of another data access method provided in an embodiment of this application;

[0051] Figure 10 is a schematic diagram of the synchronization of a first-level FTL mapping table provided in an embodiment of this application;

[0052] Figure 11 is a schematic diagram of the switching of a primary and backup storage media controller provided in an embodiment of this application;

[0053] Figure 12 is a flowchart of another data access method provided in an embodiment of this application;

[0054] Figure 13 is a schematic diagram of the structure of a storage device group provided in an embodiment of this application;

[0055] Figure 14 is a schematic diagram of a storage system provided in an embodiment of this application;

[0056] Figure 15 is a schematic diagram of a storage system provided in an embodiment of this application;

[0057] Figure 16 is a flowchart of a data reconstruction method provided in an embodiment of this application. Detailed Implementation

[0058] In traditional solid-state drives (SSDs), the SSD controller and the individual NAND flash memory chips (NAND chips) within the SSD are integrated into a single board. This means that if the SSD controller fails, the entire SSD becomes unusable. Therefore, when such SSDs are used in storage systems, if the SSD controller fails, the SSD containing the failed controller needs to be replaced, increasing the maintenance costs of the storage system. Furthermore, if a large number of NAND chips in such an SSD fail, the usable storage capacity decreases, requiring the replacement of the faulty NAND chips. However, because the SSD controller and individual NAND chips are integrated, individual chip replacement is not supported. Therefore, in storage systems, if a large number of NAND chips in such an SSD fail, the SSD containing the faulty NAND chips needs to be replaced, further increasing the maintenance costs of the storage system.

[0059] Based on this, this application provides a storage device, which is a device with data storage capability for storing data. The storage device can be, for example, an SSD or other types of storage devices. It is sufficient that the storage media controller and the memory can be hot-swapped. Here, this application does not limit the type of storage device. In this embodiment of the invention, when the storage device is directly connected to the host, it communicates with the host through, for example, an M.2 interface or a Serial Advanced Technology Attachment (SATA) interface. The M.2 interface is also called a Next Generation Form Factor (NGFF) interface. The communication protocol between the storage device and the host is, for example, the Peripheral Component Interconnect Express (PCIE) standard or the SATA bus.

[0060] The storage device includes at least one storage medium controller and multiple memories. The storage medium controller is the control module of the storage device, used to control the memories in the storage device. Each memory provides physical address storage space for storing data. Exemplarily, each memory includes at least one storage medium. In other words, the storage device includes at least one storage medium controller and multiple storage media, which are encapsulated within multiple memories. The storage media provide physical address space, and each memory encapsulates at least one storage medium. Each storage medium can be a NAND flash chip, a 3D NAND chip, or other types of storage media. Here, the embodiments of this application do not limit the number of storage medium controllers, the number of memories, the number of storage media in each memory, or the type of storage media in the storage device.

[0061] The storage media controller controls the storage media in the storage device, with memory as the unit. Optionally, the storage device also includes interface circuitry, and each storage media controller and each memory is connected to the interface circuitry via hot-plugging.

[0062] At the hardware level, the storage media controller is treated as an independent hardware unit and connected to the interface circuit via hot-swapping, making it a field-replaceable unit (FRU). This allows the storage media controller to be replaced in case of failure. Thus, when this type of storage device is used in a storage system, if the storage media controller of a storage device in the system fails, only the faulty storage media controller needs to be replaced, without replacing the entire storage device, thereby reducing the maintenance cost of the storage system.

[0063] Multiple storage media in a storage device are packaged into multiple memories, with each memory as an independent unit. Each memory is connected to the interface circuit via a pluggable connection, making each memory an FRU (Free Memory Unit). This allows for the replacement of a faulty memory in the storage device if any memory fails. Thus, when this type of storage device is used in a storage system, if a memory in a storage device fails, only the faulty memory needs to be replaced, without replacing the entire storage device, thereby reducing the maintenance cost of the storage system.

[0064] At the logical level, the individual storage media controllers in a storage device reside in the management layer, while the individual storage media reside in the storage layer. Through interface circuits and hot-swappable connections, the storage media controllers are physically separated from the storage layer, decoupling them from the storage media within the storage layer. This achieves a decoupling design between the storage media controllers and the storage media. Furthermore, by encapsulating the storage media within a memory, the storage media in the storage layer are physically separated, allowing the storage media controller to control the storage media in the storage layer as a single memory unit. This further decouples the storage media controller from the storage media in the storage layer, achieving a refined decoupling design between the storage media controllers and the storage media.

[0065] The connection relationships between the various components in the storage device provided in this application will be described below with reference to Figure 1.

[0066] Figure 1 is a schematic diagram of a storage device provided in an embodiment of this application. As shown in Figure 1, the storage device 100 includes a storage medium controller 101 and a plurality of memories 102, each memory 102 including at least one storage medium 21. Figure 1 illustrates an example with 24 memories 102, but the number of memories 102 is not limited to 24. Figure 1 also illustrates an example with each memory 102 including 4 storage media 21, but the number of storage media 21 in each memory 102 is not limited to 4. Figure 1 further illustrates an example with the storage medium 21 being a NAND chip, but the type of storage medium 21 is not limited to NAND chips. In this embodiment of the application, the number of storage medium controllers 101, the number of memories 102, the number of storage media 21 in each memory 102, and their types are not limited.

[0067] Optionally, the storage device 100 further includes an interface circuit for hot-swapping to the memory 102 and the storage medium controller 101 in the storage device 100, so that the storage medium controller 101 and the multiple memories 102 can communicate through the interface circuit.

[0068] In one possible implementation, the interface circuit is located within the memory 102, serving as the external interface of the memory 102. For example, each memory 102 includes an interface circuit, and the storage medium controller 101 is hot-swappable to the interface circuits of multiple memories 102. For instance, the storage medium controller 101 includes multiple first hot-swappable interfaces, each supporting hot-swappable connection, and each first hot-swappable interface is plugged into the interface circuit of one memory 102.

[0069] In another possible implementation, the interface circuitry is not located in memory 102, but in a component outside of memory 102 within storage device 100. For example, as shown in FIG1, storage device 100 further includes connector 103, which includes interface circuitry and connects memory 102 and storage media controller 101 via the interface circuitry. For instance, connector 103 may also include multiple third hot-swappable interfaces supporting hot-swappable connections. Each third hot-swappable interface in connector 103 is connected to the interface circuitry and is used to connect to storage media controller 101 or memory 102 via hot-swappable connection.

[0070] Based on the different connected objects, the multiple third hot-swappable interfaces are divided into hot-swappable control interfaces and hot-swappable storage interfaces.

[0071] A hot-swappable storage interface is used to connect the memory 102. There are multiple hot-swappable storage interfaces, and each memory 102 is hot-swappably connected to the interface circuit in the connector 103 through the hot-swappable storage interface. For example, each memory 102 includes a gold finger area, which includes multiple gold fingers. The gold finger area of ​​the memory 102 is inserted into the hot-swappable storage interface to achieve a hot-swappable connection between the memory 102 and the interface circuit in the connector 103.

[0072] Optionally, at least one hot-swappable storage interface on the connector 103 is idle. An idle hot-swappable storage interface means that no memory 102 is plugged into the hot-swappable storage interface. In this way, if the storage capacity of the storage device 100 needs to be expanded, a new memory 102 can be plugged into the idle hot-swappable storage interface to achieve the expansion.

[0073] Optionally, the hot-swappable storage interface is a serializer deserializer (SERDes) interface. Taking the memory 102 shown in Figure 2 as an example, the control circuit 22 in the memory 102 is connected to the SERDes interface on the connector 103.

[0074] In traditional SSDs, the SSD storage media controller connects to NAND chips through an open NAND flash interface (ONFI). ONFI is a parallel interface, and the traces leading out from ONFI tend to be crowded together, resulting in traces that can only extend to a few centimeters at most. The extension range of the traces is relatively small, and the number of NAND chips connected to the traces is small, thus limiting the number of NAND chips in traditional SSDs, and consequently limiting the storage capacity of traditional SSDs. Even for large-capacity traditional SSDs, the storage capacity of traditional SSDs can only reach the terabyte (TB) level, and cannot reach higher capacity levels.

[0075] Compared to the routing range of the parallel interface, the routing range of the SERDE interface is larger. When the SERDE interface is used as a hot-swappable storage interface, the connector 103 can connect a large number of memory devices 102 within the routing range of the SERDE interface, thereby increasing the number of storage media 21 in the storage device 100 and increasing the storage capacity of the storage device 100, so that the storage capacity of the storage device 100 can reach the petabyte (PB) level or higher.

[0076] A hot-swap control interface is used to connect the storage media controller 101. There is at least one hot-swap control interface, and each storage media controller 101 is hot-swap connected to the interface circuit in the connector 103 via one hot-swap control interface. For example, each storage media controller 101 has a gold finger area comprising multiple gold fingers. The gold finger area of ​​each storage media controller 101 is inserted into the hot-swap control interface to achieve a hot-swap connection between the storage media controller 101 and the interface circuit in the connector 103. The gold finger area of ​​each storage media controller 101 may or may not be located on the storage media controller 101. Taking the example where the gold finger area is not located in the storage medium controller 101, as shown in Figure 1, the storage medium controller 101 and other components are encapsulated into a control module 104. The control module 104 includes a gold finger area, which is connected to the storage medium controller 101. The gold finger area connected to the storage medium controller 101 is the gold finger area that the storage medium controller 101 has. The gold finger area on the control module 104 is inserted into the hot-swap control interface to realize the hot-swap connection between the storage medium controller 101 and the interface circuit in the connector 103.

[0077] Other components in the control module 104 can be a cache area or other hardware besides a cache area. This application embodiment does not limit the type of other components. Any cache area involved in this application includes at least two types of memory. For example, the cache area can be random access memory (RAM) or read-only memory (ROM). For instance, RAM can be dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), or storage class memory (SCM). DDR SDRAM can also be simply referred to as DDR. DRAM is a semiconductor memory, and like most random access memory (RAM), it belongs to the category of volatile memory devices. SCM is a composite storage technology that combines the characteristics of traditional storage devices and memory. Storage class memory can provide faster read and write speeds than hard drives, but its access speed is slower than DRAM, and it is also cheaper than DRAM. However, DRAM and SCM are only illustrative examples in this embodiment. The cache area may also include other random access memories, such as static random access memory (SRAM). For read-only memory, for example, it may be programmable read-only memory (PROM) or erasable programmable read-only memory (EPROM). Additionally, the cache area may be a dual in-line memory module (DIMM), i.e., a module composed of DRAM, or it may be an SSD. In practical applications, the storage device 100 may be configured with multiple cache areas and different types of cache areas. This application embodiment does not limit the number and type of cache areas in the storage device. Furthermore, the cache area can be configured to have a power-saving function. The power-saving function means that when the system experiences a power outage and then power is restored, the data stored in the cache area will not be lost.

[0078] Taking other components in the control module 104 as examples of cache areas, the storage device 100 also includes at least one cache area 105. When the storage device 100 includes a storage medium controller 101, the at least one cache area 105 is associated with the storage medium controller 101. When the storage device 100 includes multiple storage medium controllers 101, each storage medium controller 101 is associated with at least one cache area 105. For any storage medium controller 101, any storage medium controller 101 and the associated cache area 105 are encapsulated into a control unit 104. That is, the storage device 100 includes at least one control module 104, and each control module 104 includes a storage medium controller 101 and at least one cache area 105.

[0079] Figure 1 illustrates a storage device 100 including two cache areas 10, but the number of cache areas 105 in the storage device 100 is not limited to two. Figure 1 also illustrates a storage medium controller 101 associated with two cache areas 105, but the number of cache areas 105 associated with the storage medium controller 101 is not limited to two. In this embodiment, the number of cache areas 105 in the storage device 100 and the number of cache areas 105 associated with the storage medium controller 101 are not limited. Figure 1 illustrates a cache area 105 as DDR, but the type of cache area 105 is not limited to DDR; it can be any type of cache area described above. The cache area 105 can also be configured to have a power-saving function, which can prevent data loss in the cache area 105 when the system experiences a power failure.

[0080] The storage medium controller 101 is connected to its associated caches 105. The caches 105 provide data caching services for the associated storage medium controller 101. The caches 105 are internal storage units for direct data exchange between the storage medium controller 101 and the storage medium controller 101. They can read and write data at any time with high speed, serving as temporary data storage for running software programs. For example, when the storage medium controller 101 receives a write request from outside the storage device, it temporarily stores the data to be written in the associated cache 105. When the total amount of data in the cache 105 reaches a certain threshold, the storage medium controller 101 then sends the data stored in the cache 105 to the storage module for persistent storage.

[0081] Figure 1 illustrates an example where the cache area 105 is located outside the storage medium controller 101 in the storage device 100. In other embodiments, the cache area 105 is located in the storage medium controller 101, that is, the storage medium controller 101 also includes the cache area 105. The cache area 105 is connected to the control chip in the storage medium controller 101 and is used to provide data caching services for the control chip.

[0082] Optionally, the storage device 100 further includes a network interface 106, which is an external communication interface for the storage device 100, used to communicate with devices outside the storage device 100. The network interface 106 is connected to the connector 103. For example, the network interface 106 is fixedly connected to the connector 103 by soldering. Alternatively, the network interface 106 and the connector 103 are hot-swappable. Taking Figure 1 as an example, the third hot-swappable interface of the connector 103 also includes a hot-swappable network interface. The gold finger area on the network interface 106 is inserted into the hot-swappable network interface to achieve a hot-swappable connection between the network interface 106 and the connector 103. The gold finger area on the network interface 106 includes multiple gold fingers. Figure 1 illustrates an example of a network interface 106 being indirectly connected to a storage media controller 101 via a connector 103. In other embodiments, the network interface 106 is directly connected to the storage media controller 101 so that the network interface 106 can communicate directly with the storage media controller 101. In this case, the network interface 106 is not connected to the connector 103.

[0083] For any component in storage device 100 other than connector 103 (such as storage media controller 101, network interface 106, or memory 102), since the component supports hot-swappable connection with connector 103, in the event of a component failure, the faulty component can be replaced while storage device 100 is operating. This allows components in storage device 100 to be replaced independently online without affecting the normal operation of storage device 100. Thus, when storage device 100 is used in a storage system, if a component of a storage device 100 fails, only the faulty component needs to be replaced, without replacing the entire storage device 100, reducing the maintenance cost of the storage system.

[0084] Multiple components of storage device 100, excluding connector 103 (such as storage media controller 101, network interface 106, and memory 102), are connected to connector 103 to mount (access) these components. This allows any one of these components to communicate with the others through connector 103. For example, any storage media controller 101 can read and write data to any memory 102 via connector 103. Different memories 102 can also communicate via connector 103; for instance, different memories 102 can exchange stored data with each other. Any storage media controller 101 can also communicate via network interface 106 through connector 103. In other words, different components of storage device 100 connected to connector 103 can communicate.

[0085] It can be seen that connector 103 provides a communication link for other components in storage device 100, so that different components in storage device 100 can communicate through connector 103. Therefore, different components among these multiple components can communicate through connector 103. Communication connection refers to the connection method in which different components communicate with each other through a communication link.

[0086] The overall architecture of storage device 100 has been introduced above. Next, based on Figure 3, and in conjunction with the following two parts (1) and (2), the internal structure of storage medium controller 101 and memory 102 will be introduced respectively.

[0087] Figure 3 shows a simplified version of the storage device 100, highlighting the internal structure of the storage medium controller 101 and the memory 102. In the storage device 100 shown in Figure 1, each storage medium controller 101 is communicatively connected to each memory 102 in the storage device 100 via a connector 103. In Figure 3, the connector 103 is not shown, and the communication connection between the storage medium controller 101 and the memory 102 is represented by the connection line between them.

[0088] (1) Storage Media Controller 101

[0089] As shown in Figure 3, the storage medium controller 101 includes a host interface 11, a first hot-swappable interface 12, and a control chip 13. The host interface 11 is used to connect to a host so that requests from the host can be sent to the control chip 13 through the host interface 11. The host can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, server, or any other suitable electronic device capable of connecting to the storage device 100.

[0090] Optionally, the host interface 11, connector 103, and network interface 106 support the same communication protocol to enable communication between them, as shown in Figure 3. This communication protocol can be a memory consistency protocol, including Compute Express Link (CXL), general-purpose PCIe, Fibre Channel (FC), Small Computer System Interface (SCSI), Ethernet, Remote Direct Memory Access (RDMA), or Memory Fabric protocols, etc. RDMA protocols include InfiniBand (IB) and RDMA over Converged Ethernet (ROCE). This embodiment does not limit the specific memory consistency protocol used. A memory consistency protocol allows multiple hosts outside of storage device 100 to simultaneously access the physical address space of storage device 100, improving the access efficiency of the storage device.

[0091] Optionally, the host interface 11 is connected to the connector 103. For example, the host interface 11 is connected to the gold finger area of ​​the storage medium controller 101, so as to connect to the connector 103 through the gold finger area. The host interface 11 communicates with the network interface 106 in the storage device through the connector 103. For example, the control chip 13 can communicate with other devices through the communication link formed by the host interface 11, the connector 103, and the network interface 106. These other devices can be any device other than the storage device 600.

[0092] The first hot-swappable interface 12 is used to connect to the interface circuitry of multiple memory modules 102 via hot-swapping. For example, the first hot-swappable interface 12 is hot-swappably connected to a connector 103, which includes the interface circuitry for connecting multiple memory modules 102. Exemplarily, the first hot-swappable interface 12 is connected to the gold finger area of ​​the storage medium controller 101 to connect to the connector 103 via the gold finger area. The first hot-swappable interface 12 communicates with the multiple memory modules 102 via the connector 103, so that the control chip 13 can access these multiple memory modules 102 through the first hot-swappable interface 12.

[0093] Alternatively, the first hot-swappable interface 12 is used to directly connect to the interface circuits of multiple memories 102 via hot-swapping. For example, each memory 102 includes an interface circuit, and there may be multiple first hot-swappable interfaces 12, each connected to the interface circuit of one memory 102.

[0094] Since the first hot-swappable interface 12 is connected to the interface circuit of multiple memory 102 via hot-swapping, or directly to the interface circuit of multiple memory 102 via hot-swapping, if the storage medium controller 101 fails during the operation of the storage device 100, the faulty storage medium controller 101 can be directly replaced via hot-swapping without replacing the entire storage device 100. When the storage device 100 is used in a storage system, the maintenance cost of the storage system can be reduced.

[0095] The control chip 13 is a programmable electronic component, such as a central processing unit (CPU) or a data processing unit (DPU). A DPU possesses the versatility and programmability of a CPU, but is more specialized, capable of efficiently operating on network packets, storage requests, or analysis requests. A DPU differs from a CPU in its high degree of parallelism (requiring the processing of numerous requests). When the control chip 13 is a CPU, the CPU includes one or more cores; however, this embodiment does not limit the number of CPU cores. Optionally, the control chip 13 can also be a graphics processing unit (GPU), an embedded neural network processing unit (NPU), or other processing chip. This embodiment does not limit the type of control chip 13. The number of control chips 13 in the storage medium controller 101 can be one, two, or more. As the storage capacity of the storage device 100 increases and / or the number of devices communicating with the storage device 100 increases, the computing power required by the storage medium controller 101 increases, and the number of control chips 13 can increase accordingly.

[0096] The control chip 13 is used to connect to the host interface 11 and the first hot-swappable interface 12, so that the control chip 13 can communicate with other devices outside the storage device 100 through the host interface 11, and communicate with each memory 102 in the storage device 100 through the first hot-swappable interface 12.

[0097] The control chip 13 is the control center of the storage medium controller 101, used to manage the storage media 21 in the multiple memories 102. The management method includes data access between the host and the storage media 21 in the multiple memories 102 based on the first mapping relationship between logical addresses and the multiple memories 102.

[0098] Optionally, the control chip 13 has a flash translation layer (FTL) function, which is used to access data between the host and the storage media in the multiple memories 102 based on the mapping relationship between logical addresses and multiple memories 102.

[0099] In a traditional SSD controller, the FTL function is used to map the host's logical address (LA) space to the entire SSD's physical address (PA) space. The logical address space includes multiple LAs, which are cache addresses generated by the host's CPU. The physical address space includes multiple PAs, and the storage medium 21 includes multiple storage units, where PA is the actual address of the storage unit.

[0100] For FTL functionality, traditional SSD controllers store an FTL mapping table. The FTL mapping table is used to record the mapping relationship between PAs that have been written to the SSD. Traditional SSD controllers uniformly address the physical addresses within all NAND chips in the SSD. As shown in Figure 4, taking a traditional SSD as an example, assuming that the physical address space of the traditional SSD includes PA0-PA15 and the logical address space of the host includes LA0-LA15, the address segments LA0-LA16 in the logical address space are mapped to the physical address space PA0-PA15 of the traditional SSD. If data has been written to PA0-PA15, the FTL mapping table of the traditional SSD will record 16 mapping relationships between LA0-LA15 and PA0-PA15. Each LA in LA0-LA15 is mapped to one PA in PA0-PA15. Different LAs are mapped to different PAs. For example, there is a mapping relationship between LA0 and PA7 to indicate that LA0 is mapped to PA7, there is a mapping relationship between LA5 and PA3 to indicate that LA5 is mapped to PA3, and there is a mapping relationship between LA8 and PA15 to indicate that LA8 is mapped to PA15.

[0101] In the control chip 13 provided in this application, the FTL function is used to complete the mapping between the host's logical address space and multiple memories 102. For example, this application designs a two-level FTL mapping table, namely a first-level FTL mapping table and a second-level FTL mapping table, which are represented as FTL1 and FTL2 in Figure 3, respectively.

[0102] The first-level FTL mapping table is managed by the control chip 13, specifically by the storage medium controller 101 where the control chip 13 resides. When the storage medium controller 101 has an associated cache 105, the control chip 13 can store the first-level FTL mapping table in the associated cache 105. The cache 105 is used to store the first-level FTL mapping table. The first-level FTL mapping table records the mapping relationship (referred to as the first mapping relationship) between logical addresses and multiple memories 102 in the storage device 100. For example, the first-level FTL mapping table includes multiple entries, each representing a first mapping relationship. Each mapping entry includes at least one address space (LA) in the logical address space and an identifier for a memory 102. The logical address space includes multiple LAs. The identifier of any memory 102 is used to represent that memory 102 and can be the memory 102's number. In this embodiment, the identifier of the memory 102 is not limited.

[0103] There are multiple secondary FTL mapping tables, each corresponding to a memory 102, and each secondary FTL mapping table is managed by its corresponding memory 102. The secondary FTL mapping table records the mapping relationship (called the second mapping relationship) between logical addresses and physical addresses in the storage medium within the memory 102, where the logical address is the logical address in the primary FTL mapping table. The physical addresses of all storage cells in all storage media 21 within any memory 102 are uniformly addressed. The physical addresses of all storage cells in any storage medium 21 constitute the physical address space of that storage medium 21. The physical addresses in the physical address space of the storage medium 21 are the physical addresses within the storage medium 21. The physical address spaces of all storage media 21 within any memory 102 constitute the physical address space of that memory 102; that is, the physical address space of any memory 102 includes the physical addresses of all storage media 21 within that memory 102.

[0104] For example, for any second-level FTL mapping table corresponding to any memory 102, the second-level FTL mapping table includes multiple mapping table entries, each mapping table entry represents a second mapping relationship, and each mapping table entry includes a logical address and a physical address in the physical address space of the memory 102, the logical address corresponding to the memory 102 in the first-level FTL mapping table.

[0105] Taking Figure 4 as an example, assuming the storage device includes memories 1-4, after the storage medium controller uniformly addresses the physical addresses in all storage media within each memory, the physical address space of each memory includes four physical addresses: PA0-PA3. Memory 1-4 provide a total of 16 PAs, which constitute the physical address space of the storage medium controller 101. Assuming the host's logical address space includes LA0-LA16, LA0-LA15 in the logical address space are mapped to these 16 PAs through a first-level FTL mapping table and four second-level FTL mapping tables. The first-level FTL mapping table includes four first mapping relationships; for example, the first-level FTL mapping table is shown in Table 1 below.

[0106] Table 1

[0107] Each of the memories 1-4 stores a second-level FTL mapping table. The second-level FTL mapping table in any memory includes 4 second mapping relationships. Taking memory 1 as an example, the second-level FTL mapping table stored in memory 1 is shown in Table 2 below.

[0108] Table 2

[0109] Since the FTL mapping table in a traditional SSD controller (referred to as the traditional FTL mapping table) records the mapping relationship between the physical address space and logical address of the entire SSD, the first-level FTL mapping table in this application records the mapping relationship between the identifiers of multiple memory devices and logical addresses. Since the memory identifiers contain less data than the physical addresses, the first-level FTL mapping table records less information compared to the traditional FTL mapping table. Storing the first-level FTL mapping table can reduce the storage space occupied by the storage medium controller 101.

[0110] The control chip 13 can also store the first mapping relationship (i.e., the first-level FTL mapping table) between the storage logical address and multiple memories 102 through the cache area 105. This can reduce the occupation of the internal storage space of the control chip 13 by the first mapping relationship, and make it easier for the control chip 13 to quickly query the memory to be accessed from the stored first mapping relationship when performing data access, thereby improving data access efficiency.

[0111] Optionally, the control chip 13 also has other functions for managing the storage medium besides the FTL function, such as erasure coding (EC) / catchup and reBalance (CRB) offloading, garbage collection (GC), and triple parity redundant disk array (RAID-TP). The various functions of the control chip 13 can be implemented in hardware, software, or a combination of both. This application does not limit the implementation method of these functions. In the case of any function implemented in hardware, that function may not be integrated into the control chip 13 but may reside outside of it, such as the RAID-TP function.

[0112] (2) Memory 102

[0113] As shown in Figures 1 and 3, each memory 102 includes at least one storage medium 21, a control circuit 22, and a second hot-swappable interface 24.

[0114] The second hot-swappable interface 24 is used to connect to the interface circuit of the storage medium controller 101 via hot-swapping, enabling other components in the memory 102 to communicate with the storage medium controller 101 through the second hot-swappable interface 24. For example, the second hot-swappable interface 24 is hot-swappably connected to the interface circuit in the connector 103 of the storage device 100. Exemplarily, the second hot-swappable interface 24 is the gold finger area of ​​the memory 102, and the second hot-swappable interface 24 is plugged into the connector 103 to hot-swappably connect with the interface circuit in the connector 103. In other embodiments, the storage medium controller 101 includes interface circuitry, and the second hot-swappable interface 24 is used to directly connect to the interface circuitry of the storage medium controller 101 via hot-swapping.

[0115] Since the second hot-swappable interface 24 is connected to the interface circuit of the storage medium controller 101 via hot-swapping, or directly to the interface circuit of the storage medium controller 101 via hot-swapping, if the memory 102 fails during the operation of the storage device 100, the faulty memory 102 can be directly replaced via hot-swapping without replacing the entire storage device 100. When the storage device 100 is used in a storage system, the maintenance cost of the storage system can be reduced.

[0116] The control circuit 22 is used to connect to the second hot-swappable interface 24 and each storage medium 21 in the memory 102. The control circuit 22 is also used to manage each storage medium 21 in the memory 102. This management can be achieved by storing a second mapping relationship between logical addresses and physical addresses in the storage medium 21 within the memory 102, such as a secondary FTL mapping table (e.g., FTL2) stored in the control circuit 22. The control circuit 22 can access data between the storage medium controller 101 and the storage medium 21 in the memory 102 based on the second mapping relationship recorded in the secondary FTL mapping table.

[0117] Optionally, as shown in Figure 3, the control circuit 22 includes a front-end interface 221, a back-end interface 222, and a processor 223, wherein both the front-end interface 221 and the back-end interface 222 are connected to the processor 223. The processor 223 communicates with the storage medium controller 101 through the front-end interface 221, and the processor 223 communicates with each storage medium 21 in the memory 102 through the back-end interface 222.

[0118] The front-end interface 221 is connected to the storage media controller 101 via the second hot-swappable interface 24, enabling communication between the front-end interface 221 and the storage media controller 101. The front-end interface 221, the second hot-swappable storage interface 24, and the first hot-swappable interface 12 in the storage media controller 101 have the same interface type, allowing them to communicate. All three are ONFI, SERDES, or other types of interfaces.

[0119] The back-end interface 222 is connected to each storage medium 21 in the memory 102 so that the processor 223 can access each storage medium 21 in the memory 102 through the back-end interface 222. The back-end interface 222 can be an ONFI interface, a SERDES interface, or other types of interfaces supported by the storage medium 21. In this embodiment, the interface type of the back-end interface 222 is not limited.

[0120] The implementation of processor 223 is similar to that of control chip 13, so the implementation of processor 223 will not be described in detail here. Processor 223 is the control center of the control circuit 22, and is used to manage the various storage media 21 connected to the back-end interface 222.

[0121] Optionally, the processor 223 has an FTL function, which is used to map logical addresses to physical addresses in the storage medium 21 within the memory 102. For example, the processor 223 can store a two-level FTL mapping table and perform the FTL function based on the two-level FTL mapping table. The two-level FTL mapping table has been introduced above and will not be repeated here.

[0122] Optionally, the processor 223 can cache the secondary FTL mapping table in a cache area within the processor 223, or store the secondary FTL mapping table on the connected storage medium 21 for persistent storage. Alternatively, as shown in FIG1, each memory 102 further includes at least one cache area 23, which is connected to the control circuit 22 in the memory 102. The at least one cache area 23 is used to provide data caching services for the connected control circuit 22. For example, the cache area 23 is used to store the second mapping relationship between logical addresses and physical addresses in the storage medium within the memory. The cache area 23 is an internal memory in the memory 102 that directly exchanges data with the control circuit 22. The processor 223 can store the secondary FTL mapping table in the cache area 23. When the amount of data in the secondary FTL mapping table reaches a certain threshold, the processor 223 then permanently stores the secondary FTL mapping table in the cache area 23 on the storage medium 21. When processor 223 receives a write request, it can temporarily store the data to be written carried by the write request in cache 23. When the total amount of data in cache 23 reaches a certain threshold, processor 223 will then send the data stored in cache 23 to storage medium 21 for persistent storage. Alternatively, when the total amount of data in the secondary FTL mapping table and the data to be written in cache 23 reaches a certain threshold, the secondary FTL mapping table and the data to be written in cache 23 will be permanently stored in storage medium 21.

[0123] By storing the second mapping relationship between logical addresses and physical addresses in the storage medium of the memory in the cache area 23, the occupation of the internal storage space of the control circuit 22 by the second mapping relationship can be reduced, and the control circuit 22 can quickly query the physical address to be accessed from the stored second mapping relationship when performing data access, thereby improving data access efficiency.

[0124] Optionally, buffer 23 can be configured to have a power-saving function. With the power-saving function enabled, data (such as secondary FTL mapping tables or data to be written) in buffer 23 can be prevented from being lost when the system experiences a power outage.

[0125] Figure 1 illustrates a DDR cache 23 as an example, but it is not limited to DDR. The cache 23 can be any type of cache 23 described above. Figure 1 illustrates an example where each memory 102 includes one cache 23, but the number of cache 23s in the memory 102 is not limited to one; it can be two or more. Here, this embodiment does not limit the number and type of cache 23s in the memory 102. Optionally, the memory 102 may not include cache 23. Here, this embodiment does not limit whether the memory 102 includes cache 23.

[0126] It should be understood that, compared to a traditional SSD storage media controller, in this application, some functions of the FTL are offloaded to the processor 223 in the memory 102 so that the processor 223 can manage the storage media 21 in the memory 102 by means of these FTL functions.

[0127] Optionally, the processor 223 also has other functions for managing the storage medium besides the FTL function, such as low density parity-check codes (LDPC) function. In this application, these functions are offloaded to the processor 223 in the memory 102, compared to the traditional SSD storage medium controller. Optionally, the processor 223 may not have these functions, and these functions are provided by the control chip 13 in the storage medium controller 101. Here, this application embodiment does not limit whether the processor 223 has these functions.

[0128] The various functions in processor 223 can be implemented by hardware, software, or a combination of both. This application does not limit the implementation method of these functions.

[0129] The physical addresses of the storage media in storage device 100 are uniformly addressed to the physical address space. The storage media controller 101 determines the logical address space based on the physical address space. When the host is running an application, it requests storage space from the storage media controller 101. The storage media controller 101 provides the host with the logical address space or a logical address segment in the logical address space according to the request, so that the host can access the memory 102 in storage device 100 based on the logical address space or logical address segment provided by the storage media controller 101 when running the application.

[0130] Next, with reference to FIG5, we will describe the process by which the control chip 13 in the storage medium controller 101 accesses data between the host and the storage medium 21 in the multiple memories 102, and the process by which the control circuit 22 accesses data between the storage medium controller 101 and the storage medium 21 in the memory 102.

[0131] Figure 5 is a flowchart of a data access method provided in an embodiment of this application. As shown in Figure 5, the method is applied to a storage device (such as storage device 100), which includes a storage medium controller and multiple memories. The method includes the following steps.

[0132] 501. The control chip in the storage medium controller receives input / output (I / O) requests from the host through the host interface. These I / O requests indicate data access to a target logical address.

[0133] The storage device can be the aforementioned storage device 100, the control chip can be the control chip 13 of the storage medium controller 101 in the storage device 100, and the host interface can be the host interface 11 in the storage medium controller 101. The host can be any host connected to the host interface. The target logical address is the logical address to be accessed by the I / O request, and the I / O request carries the target logical address. The I / O request can be a write request or a read request. When the I / O request is a write request, the I / O request indicates that data is written to the target logical address. At this time, the I / O request also carries first data, which is the data to be written. When the I / O request is a read request, the I / O request indicates that data is read from the target logical address.

[0134] 502. The control chip sends I / O requests to the target memory among the multiple memories based on the first mapping relationship between the logical address and multiple memories. The target memory is the memory mapped to the target logical address.

[0135] The multiple memories referred to here are memories 102 within the storage device 100 where the control chip is located. The first mapping relationship between logical addresses and the multiple memories is the mapping relationship recorded in the first-level FTL mapping table in the control chip. The target memory is the memory where the physical address corresponding to the target logical address is located, and it is the memory accessed by the I / O request.

[0136] When the I / O request is a write request, the mapping relationship between the target logical address and the target memory has not yet been established in the control chip upon receiving the I / O request. Therefore, the control chip first allocates memory for the I / O request from multiple first memories in the storage device. The memory allocated for the I / O request is the target memory. After allocating the target memory for the I / O request, the control chip sends the I / O request to the target memory to establish the first mapping relationship between the target logical address and the target memory. For example, the control chip adds a new entry to the first-level FTL mapping table in the storage, which includes the target logical address and the identifier of the target memory. The control chip then establishes the first mapping relationship between the target logical address and the target memory based on this first mapping relationship. In some embodiments, the control chip executes the step of establishing the first mapping relationship between the target logical address and the target memory in response to the target memory successfully writing the first data carried by the I / O request. For example, if an I / O response is received indicating that data has been successfully written to the target logical address (or the physical address corresponding to the target logical address), the step of establishing the first mapping relationship between the target logical address and the target memory is executed.

[0137] When the I / O request is a read request, the control chip has already established a mapping relationship between the target logical address and the target memory upon receiving the I / O request. Based on this, the control chip queries the target memory mapped to the target logical address according to the first mapping relationship between the logical address and multiple memories. For example, the control chip searches for an entry containing the target logical address in the stored first-level FTL mapping table. If any entry in the first-level FTL mapping table contains the target logical address, the memory indicated by the memory identifier in that entry is determined as the target memory. An I / O request is then sent to the queried target memory.

[0138] The above description illustrates the process of establishing a first mapping relationship between the target logical address and the target memory in the first-level FTL mapping table during data writing. In other embodiments, the first mapping relationship in the first-level FTL mapping table is fixed. For example, during initialization, the storage medium controller allocates a logical address range for each memory and establishes a mapping relationship between each first memory and the allocated logical address range in the first mapping table, as shown in Table 1. Subsequently, each time the storage medium controller receives an I / O request, it queries the first mapping table for the target memory corresponding to the target logical address carried by the I / O request and sends an I / O request to the queried target memory. This I / O request can be a read request or a write request.

[0139] 503. The control circuit in the target memory accesses data to the physical address corresponding to the target logical address in the storage medium based on the second mapping relationship between the logical address and the physical address in the storage medium.

[0140] For ease of description, the physical address corresponding to the target logical address is referred to as the target physical address.

[0141] When the I / O request is a write request, the mapping relationship between the target logical address and the physical address has not yet been established in the control circuit when the I / O request is received. Therefore, the control circuit first allocates a physical address for the I / O request from the physical address in the storage medium of the memory. For example, it allocates at least one unused physical address in the physical address space of the memory to the first data carried by the I / O request. The physical address allocated to the first data is the target physical address. After allocating the target physical address for the first data, the first data is written to the storage space corresponding to the target physical address, establishing a second mapping relationship between the target logical address and the target physical address. For example, the control circuit adds a new entry to the stored secondary FTL mapping table, which includes both the target logical address and the target physical address.

[0142] When the I / O request is a read request, upon receiving the I / O request, the control circuit has already established a second mapping relationship between the target logical address and the target physical address. Based on this, the control circuit queries the target physical address mapped to the target logical address according to the second mapping relationship between the logical address and the physical address in the storage medium within the memory. For example, the control circuit searches for an entry containing the target logical address in the stored secondary FTL mapping table. If any entry in the secondary FTL mapping table contains the target logical address, the physical address in that entry is determined as the target physical address. The data stored in the memory space corresponding to the target physical address is then read.

[0143] 504. The control circuit sends an I / O response to the storage medium controller through the second hot-swappable interface in the memory. The I / O response is the access result of the physical address corresponding to the target logical address.

[0144] When the I / O request is a write request, the I / O response is a write response, indicating whether data was successfully written to the target logical address (or the physical address corresponding to the target logical address). When the I / O request is a read request, the I / O response is a read response, indicating whether data was successfully read from the target logical address (or the physical address corresponding to the target logical address). If successfully read, the I / O response includes the data read from the physical address corresponding to the target logical address.

[0145] 505. The control chip in the storage medium controller receives I / O responses through the first hot-swappable interface in the storage medium controller and sends I / O responses to the host through the host interface in the storage medium controller.

[0146] The method provided in this application offloads the ability of the storage medium controller in the storage device to access physical addresses to the control circuit in the memory. When data access is required, the storage medium controller determines the target memory based on a first mapping relationship between logical addresses and multiple memories. The control circuit in the target memory then accesses the physical address corresponding to the logical address based on a second mapping relationship between the logical address and the physical address in the storage medium of the target memory. This eliminates the need for the storage medium controller to access the physical address in the physical address space of the storage device, saving the computing power of the storage medium controller and allowing it to control more memories with sufficient computing power.

[0147] The above describes the structure of a storage device and the data access process within it, assuming the storage device includes a storage media controller 101. In other embodiments, the storage device includes multiple storage media controllers 101. The structure of the storage device with multiple storage media controllers 101 will be described below with reference to Figures 6 and 7.

[0148] Figure 6 is a schematic diagram of another storage device provided in an embodiment of this application. As shown in Figure 6, the storage device 600 includes a plurality of storage medium controllers 101 and a plurality of memories 102. The internal structure of each storage medium controller 101 and the connection method between each storage medium controller 101 and the memory 102 are as described in Figures 1 and 3 above. Specifically, it can be shown in Figure 7, and will not be repeated here.

[0149] Figure 6 illustrates an example of a storage device 600 including two storage medium controllers 101, but the number of storage medium controllers 101 in the storage device 600 is not limited to two. Figure 6 also illustrates an example of a storage device 600 including 24 memories 102, but the number of memories 102 in the storage device 600 is not limited to 24. Figure 6 further illustrates an example of each memory 102 including four storage media 21, but the number of storage media 21 in each memory 102 is not limited to four. Figure 6 also illustrates an example of storage media 21 being a NAND chip, but the type of storage media 21 is not limited to NAND chips. In this embodiment, the number of storage medium controllers 101, the number of memories 102, the number of storage media 21 in the memory 102, and their types are not limited.

[0150] Figure 6 illustrates a storage device 600 comprising four caches 105, but the number of caches 105 in the storage device 600 is not limited to four. Figure 6 also illustrates a storage medium controller 101 associated with two caches 105, but the number of caches 105 associated with each storage medium controller 101 is not limited to two. Figure 6 illustrates a cache 105 as DDR, but the type of cache 105 is not limited to DDR and can be any type of cache described above. The cache 105 can also be configured to have a power-saving function to prevent data loss in the cache 105 during a power outage. Figure 6 illustrates an example where the cache 105 is located outside the associated storage medium controller 101. In other embodiments, the storage medium controller 101 may also include a cache 105, which is connected to a control chip in the storage medium controller 101. The cache 105 is used to provide data caching services for the control chip, such as storing a first-level FTL mapping table.

[0151] Optionally, the storage device 600 also includes a network interface 106, which is an external communication interface for the storage device 600, used to communicate with devices outside the storage device 600. The network interface 106 is connected to the connector 103. For example, the network interface 106 is fixedly connected to the connector 103 by soldering. Alternatively, the network interface 106 and the connector 103 can be hot-swapped. As shown in Figure 6, the hot-swappable interface of the connector 103 also includes a hot-swappable network interface. The gold finger area on the network interface 106 is inserted into the hot-swappable network interface to achieve a hot-swappable connection between the network interface 106 and the connector 103. Figure 6 illustrates an example of the network interface 106 being indirectly connected to each storage media controller 101 via the connector 103. In other embodiments, the network interface 106 is directly connected to each storage media controller 101 so that the network interface 106 can communicate directly with each storage media controller 101. In this case, the network interface 106 is not connected to the connector 103.

[0152] The internal structure of each memory 102 in the storage device 600 is similar to that of each memory 102 shown in Figures 1-3 above. The difference is that each memory 102 in the storage device 600 includes multiple second hot-swappable interfaces 24, and the control circuit 22 in each memory 102 includes multiple front-end interfaces 221, as shown in Figure 7. Each second hot-swappable interface 24 corresponds to a storage medium controller 101 and a front-end interface 221. Each second hot-swappable interface 24 is connected to the corresponding storage medium controller 101 and the corresponding front-end interface 221 so that each second hot-swappable interface 24, the corresponding storage medium controller 101, and the corresponding front-end interface 221 form a communication link, enabling the control chip 13 to communicate with the processor 223 through this communication link. The connection method between each second hot-swappable interface 24 and the storage medium controller 101 has been described above and will not be repeated here.

[0153] For any storage medium controller 101 in the storage device 600, the storage medium controller 101 may have control over all the memories 102 in the storage device 100, or it may have control over some of the memories 102 in the storage device 100. The memories recorded in the first-level FTL mapping table managed by the storage medium controller 101 are the memories 102 that the storage medium controller 101 has control over. That is, when the storage medium controller 101 has control over any memory 102, the mapping relationship between this memory 102 and its logical address can be recorded in the first-level FTL mapping table of the storage medium controller 101.

[0154] For any of the storage devices 100 and 600 described above, each storage medium controller 101 in the storage device can communicate with each memory 102 in the storage device 100. Based on this, control permissions for the memory 102 can be configured in any storage medium controller 101. When a storage medium controller 101 has control permissions for at least one memory 102, it manages the storage media in that at least one memory 102. For example, the storage medium controller 101 records the mapping address corresponding to the at least one memory 102 through a first-level FTL mapping table, and performs data access on the storage media in the at least one memory 102 based on the first-level FTL mapping table.

[0155] For example, when the storage device includes a storage media controller 101, the storage media controller 101 is configured with control permissions for each memory 102 in the storage device, so that the storage media controller 101 can control each memory 102 in the storage device. At this time, the first-level FTL mapping table in the storage media controller 101 is used to record the first mapping relationship between logical addresses and each memory 102 in the storage device.

[0156] When a storage device includes multiple storage media controllers 101, each storage media controller 101 can be configured with control permissions for each memory 102 in the storage device, so that each storage media controller 101 controls each memory 102 in the storage device. In this case, a first-level FTL mapping table in each storage media controller 101 is used to record the first mapping relationship between logical addresses and each memory 102 in the storage device. Alternatively, each storage media controller 101 can be configured with control permissions for at least one memory 102 in the storage device 100, and each storage media controller 101 controls the configured at least one memory 102. For example, a storage device includes storage media controller 1, storage media controller 2, and memories 1-6. Storage media controller 1 has control permissions for memories 1-3, and storage media controller 2 has control permissions for memories 4-6. Storage media controller 1 manages memories 1-3, and storage media controller 2 manages memories 4-6. In this case, a first-level FTL mapping table in each storage media controller 101 is used to record the first mapping relationship between logical addresses and the configured at least one memory 102.

[0157] For ease of description, any one of the multiple storage media controllers 101 within the storage device 600 is referred to as the first storage media controller, and any other storage media controller 101 in the storage device 600 besides the first storage media controller is referred to as the second storage media controller. The control chip 13 in the first storage media controller is referred to as the first control chip, and the control chip 13 in the second storage media controller is referred to as the second control chip.

[0158] Optionally, the first storage medium controller is configured as a backup storage medium controller for the second storage medium controller. In the event of a failure of the second storage medium controller, the backup storage medium controller takes over the control of each memory 102 in the storage device 600 and manages each memory 102.

[0159] Taking Figure 8 as an example, storage medium controller 81 and storage medium controller 82 are the second storage medium controller and the first storage medium controller, respectively. Each memory 83 has two second hot-swappable interfaces (i.e., dual ports), and each memory 83 communicates with storage medium controller 81 and storage medium controller 82 through these two second hot-swappable interfaces. Initially, storage medium controller 82 serves as the backup storage medium controller for each memory 83, and storage medium controller 81 serves as the primary storage medium controller for each memory 83. Storage medium controller 81 has control over each memory 83. When storage medium controller 81 is functioning correctly, it manages each memory 83, while storage medium controller 82 either does not operate or distributes workload evenly. In the event of a failure of storage medium controller 81, storage medium controller 82 takes over the control of each memory 83, becoming the primary storage medium controller for each memory 83, and manages each memory 83. After the storage medium controller 81 recovers from the fault, it can regain control of each memory 83 and become the main storage medium controller to manage each memory 83. Alternatively, it can take over control of each memory 83 and become the main storage medium controller after the storage medium controller 82 fails.

[0160] In storage device 600, a second storage medium controller acts as the primary storage medium controller, managing the first mapping relationship between logical addresses and multiple memories 102 within the storage device 600. This mapping relationship is stored, for example, through a first-level FTL mapping table. A second control chip within the second storage medium controller is used to perform data access between the host and the storage media 21 within the multiple memories 102 based on this stored first mapping relationship. A first control chip in the first storage medium controller can obtain this first mapping relationship from the second control chip via a connector in the storage device 600, and then perform data access between the host and the storage media 21 within the multiple memories 102 based on this obtained first mapping relationship.

[0161] Furthermore, if the second storage medium controller recovers from a fault while the first storage medium controller is managing the memory 102, the second storage medium controller can immediately regain control of the first storage medium controller and manage the memory 102 in the storage device 600 to avoid excessive consumption of the first storage medium controller's computing power. Alternatively, after the first storage medium controller fails, the second storage medium controller can regain control of the first storage medium controller and manage the memory 102 in the storage device 600.

[0162] Alternatively, the second storage medium controller can be configured as a backup storage medium controller for the first storage medium controller. In this case, the second storage medium controller and the first storage medium controller are each other's backup storage medium controllers. If either the first storage medium controller or the second storage medium controller fails, the other storage medium controller will manage the various memories 102 in the storage device 600.

[0163] Next, referring to the flowchart of another data access method provided by the embodiment of this application in Figure 9, the process of the second storage medium controller synchronizing the first mapping relationship with the first storage medium controller, and the first storage medium controller accessing data in the storage medium of the first memory based on the first storage mapping relationship will be introduced.

[0164] 901. The second storage medium controller synchronizes the first mapping relationship between the logical address and the multiple first memories to the first storage medium controller.

[0165] The first storage medium controller and the second storage medium controller are located in the same storage device, and the first memory is the memory in the storage device. Optionally, this step 901 can be executed by the second control chip in the second storage medium controller.

[0166] Taking Figure 8 as an example, it is assumed that storage medium controller 81 and storage medium controller 82 are located in the same storage device, storage medium controller 81 is the first storage medium controller, storage medium controller 82 is the second storage medium controller, and each memory 83 is the first memory.

[0167] The second storage medium controller records the first mapping relationship through a first-level FTL mapping table. The second storage medium controller can synchronize its stored first-level FTL mapping table with the backup storage medium controller (i.e., the first storage medium controller) to realize the synchronization of the first mapping relationship with the backup storage medium controller.

[0168] Taking Figure 10 as an example, assume that the logical address spaces LA0-LA15 are mapped to the physical address spaces provided by memories 1-4, and the physical address spaces provided by each memory in memories 1-4 include PA0-PA3. Storage medium controller 1001 has control over memories 1 and 2, and storage medium controller 1002 has control over memories 3 and 4. Storage medium controller 1001 records the first mapping relationship between LA0-LA7 and memories 1-2 through a first-level FTL mapping table 1003, and storage medium controller 1002 records the first mapping relationship between LA8-LA15 and memories 3-4 through a first-level FTL mapping table 1004. For example, first-level FTL mapping table 1003 and first-level FTL mapping table 1004 are shown in Tables 3 and 4 below, respectively.

[0169] Table 3

[0170] Table 4

[0171] Each memory in memories 1-4 records a second mapping relationship between its corresponding LA and PA in its respective physical address space through a two-level FTL mapping table 1005. For example, each two-level FTL mapping table 1005 can be as shown in Table 2 above.

[0172] If storage medium controller 1002 is the first storage medium controller and storage medium controller 1001 is the second storage medium controller, then storage medium controller 1001 synchronizes the first-level FTL mapping table 1003 to storage medium controller 1002. Storage medium controller 1002 uses the first-level FTL mapping table 1003 synchronized by storage medium controller 1001 as a backup table of the first-level FTL mapping table 1003. If storage medium controller 1001 fails, storage medium controller 1002 can access the physical address in memory 1-2 through the backup table to manage the storage medium in memory 1-2. If storage medium controller 1001 is the first storage medium controller and storage medium controller 1002 is the second storage medium controller, then storage medium controller 1002 synchronizes the first-level FTL mapping table 1004 to storage medium controller 1001. Storage medium controller 1001 uses the first-level FTL mapping table 1004 synchronized by storage medium controller 1002 as a backup table of the first-level FTL mapping table 1004. If storage medium controller 1002 fails, storage medium controller 1001 can access the physical address in memory 3-4 through the backup table to control and manage memory 3-4.

[0173] The second control chip in the second storage medium controller sends a locally stored first-level FTL mapping table to the first storage medium controller via a connector in the storage device. The first control chip in the first storage medium controller receives the synchronized first-level FTL mapping table from the second control chip to obtain the first mapping relationship between logical addresses and multiple first memories. After receiving the synchronized first-level FTL mapping table, the first control chip stores the first-level FTL mapping table and associates it with the identifier of the second storage medium controller to indicate that the first-level FTL mapping table is a backup table of the second storage medium controller.

[0174] The second storage medium controller can periodically synchronize the first mapping relationship between logical addresses and multiple first memories with the first storage medium controller. For example, it can synchronize the first mapping relationship between logical addresses and multiple first memories with the first storage medium controller after a certain period of time. Alternatively, it can synchronize the first mapping relationship between logical addresses and multiple first memories with the first storage medium controller when the first mapping relationship stored in the second storage medium controller is updated. An update to the first mapping relationship includes an increase or decrease in the number of first mapping relationships, or a change in the logical address or memory identifier in the first mapping relationship.

[0175] Step 901 is an optional step. In some embodiments, it is not necessary for the second storage medium controller to synchronize the first mapping relationship with the first storage medium controller. Alternatively, the first mapping relationship stored by the second storage medium controller can be configured manually or by other devices in the first storage medium controller.

[0176] 902. If the second storage medium controller fails, the first control chip in the first storage medium controller receives an I / O request from the host through the host interface. The I / O request indicates that data access should be performed on the target logical address.

[0177] The storage device also includes a distributor for distributing I / O requests sent by the host. The distributor can be a network interface within the storage device. Upon receiving an I / O request, the distributor checks if the second storage media controller is faulty. If the second storage media controller is faulty, the distributor sends an I / O request to the host interface of the first storage media controller, so that the control chip in the first storage media controller can receive the I / O request through the host interface, and performs step 903 based on the I / O request. If the second storage media controller is not faulty, the distributor sends an I / O request to the host interface of the second storage media controller, so that the control chip in the second storage media controller can receive the I / O request through the host interface, and performs step 903 based on the I / O request.

[0178] 903. The first control chip sends an I / O request to a target memory in the multiple first memories based on the first mapping relationship between the logical address and multiple first memories. The target memory is a memory mapped to a target logical address.

[0179] Step 903 is similar to step 502 above, and will not be described again in this embodiment.

[0180] 904. The control circuit in the target memory accesses data to the physical address corresponding to the target logical address in the storage medium based on the second mapping relationship between the logical address and the physical address in the storage medium.

[0181] Step 904 is similar to step 503 above, and will not be described again in this embodiment.

[0182] 905. The control circuit sends an I / O response to the first storage medium controller through the second hot-swappable interface in the memory. The I / O response is the access result of the physical address corresponding to the target logical address.

[0183] Step 905 is similar to step 504 above, and will not be described again in this embodiment.

[0184] 906. The first control chip receives I / O responses through the first hot-plug interface in the storage medium controller and sends I / O responses to the host through the host interface in the storage medium controller.

[0185] The method provided in this application synchronizes a first mapping relationship between the logical address and the memory controlled by the storage medium controller and the backup storage medium controller. This allows the backup storage medium controller to access data in the memory controlled by the storage medium controller based on the synchronized first mapping relationship in the event of a failure of the storage medium controller, eliminating the need for the host to wait for the storage medium controller to recover and improving the efficiency of host access to the memory. Furthermore, in the event of a failure of a single storage medium controller in the storage device, the backup storage medium controller manages the memory in the storage device without affecting the operation of the storage device.

[0186] In other embodiments, any two storage devices provided in the above embodiments can communicate, and the storage medium controller in one storage device can be a backup controller for the storage medium controller in the other storage device. For ease of description, the two storage devices are referred to as the first storage device and the second storage device, respectively. Any storage medium controller 101 in the first storage device is referred to as the first storage medium controller, the memory 102 in the first storage device is referred to as the first memory, and the control chip in the first storage medium controller is referred to as the first control chip. The first control chip is used to perform data access between the host and the storage medium in the first memory based on a first mapping relationship between logical addresses and multiple first memories. The first storage device may or may not include a second storage medium controller. Any storage medium controller in the second storage device is referred to as the third storage medium controller, the memory 101 in the second storage device is referred to as the second memory, and the control chip in the third storage medium controller is referred to as the third control chip. The third control chip stores the first mapping relationship between logical addresses and multiple second memories, for example, by recording the first mapping relationship between logical addresses and multiple second memories through a first-level FTL mapping table. The third control chip is used to access data between the host and the storage media in the second memory based on the first mapping relationship between logical addresses and multiple second memories.

[0187] The second storage device and the first storage device are connected via a bus, enabling components in the first storage device to communicate with components in the second storage device, thus achieving communication connections between different components in the second and first storage devices. For example, the network interfaces of both the first and second storage devices are connected to the same bus. Since these two network interfaces are each connected to a connector of their respective storage device, and the connectors of each storage device are connected to various storage media controllers within that storage device, the connectors, network interfaces, bus, network interfaces, and connectors of the second storage device, together with those of the first storage device, form a communication link between the third and first storage media controllers. Through this communication link, the first and third storage media controllers can communicate, and the first and second storage devices can communicate.

[0188] The first storage medium controller is configured as a backup storage medium controller for the third storage medium controller. In the event of a failure of the third storage medium controller, the first storage medium controller can take over control of the second memory and manage it through the connector between the first storage medium controller and the second storage device. For example, the first control chip in the first storage medium controller is used to obtain a first mapping relationship between logical addresses and multiple second memories from the third control chip through the connector in the first storage device. The first control chip is also used to perform data access between the host and the storage media in the multiple second memories based on the obtained first mapping relationship between logical addresses and multiple second memories. The data access process can be referred to Figure 5 above, and will not be described in detail here.

[0189] As shown in Figure 11, the storage medium controller 1111 in storage device 111 is communicatively connected to each memory 1112 and each memory 1122 in storage device 111. The storage medium controller 1121 in storage device 112 is communicatively connected to each memory 1112 and each memory 1122. The storage medium controller 1111 and the storage medium controller 1112 are communicatively connected. The communication connections are represented by straight lines in Figure 11. Storage device 111 and storage medium controller 1111 are respectively the first storage device and the second storage medium controller. Storage medium controller 1111 and storage medium controller 1121 are respectively the first storage medium controller and the third storage medium controller. Each memory 1112 in storage device 111 is the first memory, and each memory 1122 in storage device 112 is the second memory.

[0190] Because the second storage device and the different components in the first storage device are connected in communication, when the third storage medium controller has control over the second storage device, if the third storage medium controller is not faulty, the third storage medium controller will manage the second storage device. If the third storage medium controller fails, the first storage medium controller can take over control of the second storage device while managing the first storage device, and manage the second storage device. After the fault of the third storage medium controller is recovered, the third storage medium controller will take over control of the second storage device again and manage the second storage device, so as to prevent the second storage device from consuming too much computing power of the first storage medium controller and affecting the control efficiency of the first storage device.

[0191] In other embodiments, the third storage medium controller can be configured as a backup storage medium controller for the first storage medium controller. The third and first storage medium controllers serve as backups for each other. If the first storage medium controller fails, the third storage medium controller can take over control of the first memory and manage it. Subsequently, after the first storage medium controller recovers from its failure, the first storage medium controller regains control of the first memory and manages it again, preventing the first memory from excessively consuming the computing power of the third storage medium controller and affecting the control efficiency of the second memory. In this application, managing the memory refers to managing the storage medium within the memory.

[0192] Taking Figure 11 as an example, storage medium controller 1111 has control over each memory 1112, and storage medium controller 1121 has control over each memory 1122. Storage medium controller 1111 and storage medium controller 1121 serve as backup storage medium controllers for each other. When either storage medium controller 1111 or storage medium controller 1121 fails, the other storage medium controller takes over the control of the other and manages each memory 1112 and each memory 1122.

[0193] Next, referring to the flowchart of another data access method provided by the embodiment of this application in Figure 12, the process of the third storage medium controller synchronizing the first mapping relationship with the first storage medium controller, and the first storage medium controller accessing data in the storage medium of the second memory based on the first storage mapping relationship will be introduced.

[0194] 1201. The third control chip in the third storage medium controller synchronizes the first mapping relationship between the logical address of the first storage medium controller and multiple second memories.

[0195] The third control chip is the control chip in the third storage medium controller. The third storage medium controller and the second memory are located in the second storage device. The first storage medium controller and the first memory are located in the first storage device.

[0196] Taking Figure 10 as an example, assuming that storage medium controller 1001 is the third storage medium controller and storage medium controller 1002 is the first storage medium controller, the control chip in storage medium controller 1001 synchronizes the first-level FTL mapping table 1003 to storage medium controller 1002. Assuming that storage medium controller 1002 is the third storage medium controller and storage medium controller 1001 is the first storage medium controller, the control chip in storage medium controller 1002 synchronizes the first-level FTL mapping table 1004 to storage medium controller 1001.

[0197] The third control chip in the third storage medium controller sends a first-level FTL mapping table to the first storage medium controller in the first storage device via a bus. The bus then sends the first-level FTL mapping table to the first storage medium controller in the first storage device. The first control chip in the first storage medium controller receives the first-level FTL mapping table sent by the bus to obtain the first mapping relationship between logical addresses and multiple second memories from the third control chip. After receiving the synchronized first-level FTL mapping table, the first control chip stores the first-level FTL mapping table and associates it with the identifier of the third storage medium controller to indicate that the first-level FTL mapping table is a backup table of the third storage medium controller.

[0198] Step 1201 is an optional step. In some embodiments, it is not necessary for the third storage medium controller to synchronize the first mapping relationship with the first storage medium controller. Alternatively, the first mapping relationship stored by the third storage medium controller can be configured manually or by other devices in the first storage medium controller.

[0199] 1202. If the third storage medium controller fails, the first control chip in the first storage medium controller receives an I / O request from the host through the host interface. The I / O request indicates that data access should be performed on the target logical address.

[0200] The I / O request also carries the identifier of the second storage device. The bus between the first and second storage devices is also connected to a control device, which distributes the I / O requests sent by the host. Upon receiving the host's I / O request, the control device, based on the identifier of the second storage device carried in the I / O request, determines that the second storage device is the storage device to be accessed. It then checks whether the third storage media controller in the second storage device is faulty. If the third storage media controller is faulty, the control device sends an I / O request to the network interface in the first storage device. The network node then sends the I / O request to the host interface in the first storage media controller. The first control chip in the first storage media controller receives the I / O request through the host interface and executes step 1202 based on the I / O request. If the third storage media controller is not faulty, the control device sends an I / O request to the network interface of the second storage device, so that the I / O request is sent to the second control chip in the third storage media controller through the network interface of the second storage device. The second control chip receives the I / O request and executes step 1203 based on the I / O request.

[0201] 1203. The first control chip sends I / O requests to the target memory in the multiple second memories based on the first mapping relationship between the logical address and multiple second memories. The target memory is the memory mapped to the target logical address.

[0202] The process of determining the target memory can be referred to in section 502 above, and will not be repeated here. After the target memory is determined, the first control chip sends an I / O request to the target memory in the second storage device through the connector and network interface in the first storage device.

[0203] 1204. The control circuit in the target memory accesses data to the physical address corresponding to the target logical address in the storage medium based on the second mapping relationship between the logical address and the physical address in the storage medium.

[0204] Step 1204 is similar to step 503 above, and will not be described again in this embodiment of the application.

[0205] 1205. The control circuit sends an I / O response to the first storage medium controller through the second hot-swappable interface in the memory. The I / O response is the access result of the physical address corresponding to the target logical address.

[0206] The control circuit sends I / O requests to the first storage medium controller in the first storage device through the connector and network interface in the second storage device.

[0207] 1206. The first control chip receives I / O responses through the first hot-plug interface in the storage medium controller and sends I / O responses to the host through the host interface in the storage medium controller.

[0208] The first control chip sends I / O responses to the network interface in the first storage device through the host interface, and the network interface sends I / O responses to the control device through the bus. The control device then sends the received I / O responses to the host.

[0209] The method provided in this application embodiment synchronizes a first mapping relationship between the logical address and the second memory in the second storage device to the first storage device via the third storage medium controller in the second storage device. This allows the first storage medium controller to access data in the second memory in the second storage device based on the first mapping relationship synchronized by the third storage medium controller in the event of a failure of the third storage medium controller. This eliminates the need for the host to wait for the third storage medium controller to recover from the failure, thereby improving the efficiency of the host accessing the memory.

[0210] In the above embodiments, a device including a storage medium controller and a storage medium hot-swappably connected to the storage medium controller is referred to as a storage device. In other embodiments, the device may also be referred to as a storage apparatus, memory, or other names, etc. Here, the name of the device in this application embodiment is not limited. In the above embodiments, the module used to manage the storage medium in the storage device provided in this application is referred to as a storage medium control module. In other embodiments, the module may also be referred to as a storage control board or other names, here, the name of the module in this application embodiment is not limited. In the above embodiments, the module in the storage device provided in this application that encapsulates at least one storage medium is referred to as a memory. In other embodiments, the module may also be referred to as a storage medium board or other names, here, the name of the module in this application embodiment is not limited.

[0211] Based on the storage devices provided above, this application embodiment also provides a storage device group, as shown in FIG13. The storage device group 900 includes a bus 901 and multiple storage devices 902. The multiple storage devices 902 are connected to the bus 901. Each storage device 902 is any of the storage devices described above (such as storage device 100 or storage device 600). Here, this application embodiment will not elaborate on the internal structure of the storage device 902. When the storage device 902 is an SSD, the storage device group 900 can also be called a disk enclosure. When the storage device 902 is a cache disk, the storage device group 900 can also be called a cache enclosure or cache device.

[0212] In the storage device group 900, each storage device 902 is connected to the bus 901 via an internal network interface (network interface 106 shown in FIG1) so that different storage devices 902 in the storage device group 900 can communicate via the bus 901.

[0213] Optionally, the storage device group 900 also includes at least one of a network interface 903 and a control device 904, wherein the network interface 903 is connected to the bus 901 so that the network interface 903 can communicate with each storage device through the bus 901.

[0214] Network interface 903 is the external interface of storage device group 900, used to communicate with devices outside storage device group 900. Each storage device 902 in storage device 900 can communicate with devices outside storage device group 900 through the communication link composed of bus 901 and network interface 903, and devices outside storage device group 900 can also access each storage device 902 through this communication link.

[0215] The control device 904 is connected to the bus 901 so that the control device 904 can communicate with each storage device 902 through the bus 901. The control device 904 can also be used to communicate with devices outside the storage device group 900. Any device outside the storage device group 900 can access each storage device 902 through the control device 904.

[0216] The control device 904 is the control center of the storage device group 900, used to control each storage device 902. The control device 904 is a programmable electronic component used to perform calculations and processing on data. The implementation of the control device 904 is similar to that of the control chip 13 described above. Therefore, the implementation of the control device 904 will not be described again in this embodiment of the application.

[0217] The network interfaces in bus 901, network interface 903, control device, and storage device 902 support the same communication protocol. For example, they all support the memory consistency protocol, which has been listed above. Here, this application embodiment does not limit the memory consistency protocol.

[0218] The storage device group described above can also be applied to storage systems. Figure 14 is a schematic diagram of a storage system provided in an embodiment of this application. As shown in Figure 14, the storage system provided in this embodiment includes a compute node cluster and a storage node cluster. The compute node cluster includes one or more compute nodes 710 (Figure 14 shows three compute nodes 710, but is not limited to three compute nodes 710), and the compute nodes 710 can communicate with each other. A compute node 710 is an electronic device, such as a server, desktop computer, or storage media controller of a storage array. Taking the storage system shown in Figure 15 as an example, in Figure 15, the compute nodes 710 can be large-scale supernodes, or third-party compute nodes in the cloud or the Internet. Here, this embodiment of the application does not limit the application scenario of the compute nodes 710. The compute node 710 can also be any of the hosts described above.

[0219] In terms of hardware, as shown in Figure 14, the compute node 710 includes at least a processor 712, a cache 713, and a network interface 714. The processor 712 is a CPU used to process requests from outside the compute node 710 or requests generated internally within the compute node 710. For example, when the processor 712 receives a write request from a user, it temporarily stores the data in the cache 713. When the total amount of data in the cache 713 reaches a certain threshold, the processor 712 sends the data stored in the cache 713 to the storage node 720 for persistent storage. In addition, the processor 712 is also used for data computation or processing, such as metadata management, deduplication, data compression, virtualization of storage space, and address translation. Figure 14 shows only one CPU 712; in practical applications, there are often multiple CPUs 712, each with one or more CPU cores. This embodiment does not limit the number of CPUs or CPU cores.

[0220] Cache 713 refers to the internal memory that directly exchanges data with processor 712. It can read and write data at any time at high speed, serving as temporary data storage for the operating system or other running programs. For example, processor 712 temporarily stores data to be written in cache 713. When the total amount of data in cache 713 reaches a certain threshold, processor 713 then stores the data stored in cache 713 to storage device 700. Cache 713 can be any type of cache described above. Figure 14 illustrates an example where each computing node 710 includes one cache 713, but the number of caches 713 in computing node 710 is not limited to one; it can be two or more. Here, this embodiment does not limit the number and type of caches 713 in computing node 710. Optionally, a power-saving function can also be configured for cache 713 to prevent data loss during system scheduling.

[0221] Network interface 714 is used to communicate with storage node 720. For example, when the total amount of data in cache 713 reaches a certain threshold, compute node 710 can send a request to storage node 720 via network interface 714 to persistently store the data. Additionally, compute node 710 may include a bus for communication between components within compute node 710. Functionally, since the primary function of compute node 710 in Figure 14 is computing, it can utilize remote storage for persistent data storage, thus requiring less local storage than a conventional server, thereby saving cost and space. However, this does not mean that compute node 710 cannot have local storage; in practical implementations, compute node 710 can also have a small amount of built-in storage or a small amount of external storage.

[0222] Any compute node 710 can communicate with storage nodes 720 in the storage node cluster through network 730. For example, network interface 714 in compute node 710 is connected to network 730, and compute node 710 can access any storage node 720 in the storage node cluster through network interface 714.

[0223] Network 730 supports a memory consistency protocol, enabling fast and reliable data transmission between different components connected to network 730. Therefore, network 730 can also be called a high-speed interconnect network. The memory consistency protocol is also used to share the storage space of multiple storage nodes 720 in a storage node cluster with multiple compute nodes 710, allowing multiple compute nodes 710 to access the storage space of multiple storage nodes 720 simultaneously. As shown in Figure 15, the memory consistency protocols supported by network 730 are CXL and ROCE as examples, but the type of memory consistency protocol is not limited to CXL and ROCE; it can also be other types of memory consistency protocols described above. This application embodiment does not limit the memory consistency protocol. Network interface 714 also supports the memory consistency protocol, allowing any component in compute node 710 (such as processor 712 or cache 713) to connect to network 730 through network interface 714, thereby enabling the component to communicate with storage devices 700 in storage node 720 through network 730.

[0224] The storage node cluster includes at least one storage node 720 (three storage nodes 720 are shown in Figure 14, but it is not limited to three storage nodes 720). The storage node 720 may be a server, a desktop computer, or a storage media controller, hard disk enclosure, etc. of a storage array. The storage node 720 may also be the storage device group 900 described above.

[0225] A storage node 720 includes a network interface 721 and at least one storage device 700. Figure 14 shows three storage devices 700, but is not limited to three. The storage device 700 shown in Figure 14 is an SSD, but is not limited to an SSD. The storage device 700 can be any of the storage devices described in the above embodiments (such as storage device 100 or storage device 600). Taking the storage system in Figure 15 as an example, the storage system shown in Figure 15 includes a first storage node cluster, which includes multiple storage nodes 720. Each storage node 720 includes multiple storage devices 700, and each storage device 700 includes two storage media controllers and multiple memories. As shown in Figure 15, the number of storage media controllers in the storage device 700 is not limited to two. Here, the embodiments of this application do not limit the number of storage media controllers in the storage device 700.

[0226] As shown in Figure 14, each storage device 700 in storage node 720 is connected to network interface 721, which is used to communicate with compute node 710. Both network interface 721 and network interface 714 are connected to network 730 to connect storage node 720 and compute node 710 to network 730. Both network interface 721 and network interface 714 support memory consistency protocols, allowing any component in compute node 710 (such as processor 712 or cache 713) to communicate with any component in storage node 720 (such as storage device 700 or the control device of storage node 720) through the communication link formed by network interface 714, network 730, and network interface 721. Therefore, through network interface 101 in each compute node 101, network 730, and network interface 721 in each storage node 720, the storage system shown in Figure 14 becomes a fully switched, fully pass-through cluster architecture. Storage device 700 can support direct network output, end-to-end data pass-through, and storage as soon as data is accessed, resulting in a multi-fold increase in storage capacity. In traditional storage systems, when any component connected to the network (such as a compute node) needs to access components on other hosts (such as storage nodes) connected to the network, the CPU of those other hosts must be interrupted, and the CPU must be scheduled before access can be made. This wastes CPU computing power and results in significant access latency. However, the storage system shown in Figure 14 is a fully switched, fully pass-through cluster architecture. Any component connected to network 730 (such as compute node 710) can directly access components on other connected components (such as storage node 720) without waiting for CPU scheduling. This avoids wasting CPU computing power on other components and reduces access latency.

[0227] In another possible implementation, storage node 720 also includes a control device connected to network interface 721. Storage node 720 can communicate with compute node 710 through the control device, and can also communicate with other storage nodes through the control device. The control device can also be connected to each storage device 700 in the storage node 720 and can communicate with each storage device 700 in the storage node 720. Compute node 710 can access each storage device 700 in any storage node 720 through the control device of any storage node 720, or it can access each storage device 700 in any storage node 720 through the network interface 721 in any storage node 720.

[0228] In other embodiments, the data stored by storage nodes 720 in the storage node cluster also includes metadata, which describes the storage location of the data in the storage system. The storage system also includes a storage node cluster for storing metadata. To distinguish between the storage node cluster for storing data and the storage node cluster for storing data metadata, the storage node cluster for storing data is referred to as the first storage node cluster, and the storage node cluster for storing metadata is referred to as the second storage node cluster. For example, the storage system shown in Figure 15 further includes a second storage node cluster, which includes at least one storage node for storing metadata. The second storage node cluster is connected to network 730 so that it can communicate with storage nodes 720 in the first storage node cluster and computing nodes 710 in the computing cluster via network 730. For example, when a computing node 710 finishes storing a piece of data on a storage node 720, the storage node 720 stores at least one of the following as metadata: the logical address corresponding to the physical address of the data, the identifier of the memory where the data is located, and the identifier of the storage device 700 where the data is located. This metadata is stored on a storage node in the second storage node cluster. In this way, before the computing node reads the data, it can first query the metadata of the data from the storage node in the second storage node cluster, and then read the data from the physical address of the data based on the queried metadata.

[0229] When storage device 902 is used in a storage system, the central control device of the storage system uniformly addresses the physical addresses of the storage media in each storage device 902 in the storage system to the physical address space. Based on the physical address space, the logical address space corresponding to the physical address space is determined. When the computing node (i.e. the host) is running an application, it requests storage space from the central control device. The central control device provides a logical address segment in the logical address space to the computing node so that the computing node can access data in the memory of storage device 902 based on the logical address in the logical address segment provided by the central control device when running the application.

[0230] Based on the storage devices and storage systems described above, this application provides a data reconstruction method, which is illustrated in Figure 16.

[0231] Figure 16 is a flowchart of a data reconstruction method provided in an embodiment of this application. The method is applied to any of the storage devices described above. The storage device includes a storage medium controller and multiple memories, each memory including at least one storage medium. The method includes the following steps.

[0232] 1601. The storage media controller in the storage device performs fault detection on multiple storage devices.

[0233] The smallest area in a storage device that requires data reconstruction in the event of a single point of failure is called the fault domain. A single point of failure is a failure of a component in the storage device, such as a failure in the control circuitry or the storage media controller. The fault domain is not the area in the storage device that has already failed, but rather the smallest area in the storage device that requires data reconstruction in the event of a single point of failure.

[0234] The memory can be considered as a fault domain within the storage device. Taking Figure 8 as an example, assuming the storage media controller is either storage media controller 81 or storage media controller 82, each memory 83 represents a fault domain. Taking Figure 11 as another example, the storage media controller can be either storage media controller 1111 or storage media controller 1121, with each memory 1112 and 1122 representing an independent fault domain. Memory 83, 1112, and 1122 are all independent fault domains.

[0235] In the case where the memory is the fault domain, the storage medium controller detects faults in multiple memories through heartbeat communication in order to reconstruct the data of the faulty memory (as in step 1602 below).

[0236] 1602. If a fault is detected in any of the multiple memories, the storage media controller reconstructs the data stored in the storage medium of that memory.

[0237] When the storage device containing the storage medium controller is used in a storage system (as shown in Figure 14 or Figure 15), each storage device in the storage system stores data in the form of stripes. Each stripe includes multiple user data blocks and at least one parity data block. The user data block includes user data, and the parity data block includes parity data of the user data block. The data blocks and parity data blocks in the stripe are distributed in different memories of different storage devices. When any memory fails, for any data block (user data block or parity data block) stored in the storage medium of that memory, the storage medium controller obtains other data blocks in the stripe containing that data block in the storage system. Based on the other data blocks in the stripe, the controller determines the data block to recover it.

[0238] The storage medium controller can also store the data blocks recovered from the faulty memory into other fault-free memory in the storage system for subsequent access by computing nodes. These other fault-free memory can be located on the storage device where the storage medium controller is located, or on other storage devices within the storage system besides the storage device where the storage medium controller is located. This application embodiment does not limit the location of the other fault-free memory.

[0239] The above description uses the example of a storage medium controller reconstructing data for a faulty memory among multiple memories. If the storage medium controller has a backup storage medium controller (such as a first storage medium controller), and that storage medium controller fails, the backup storage medium controller will reconstruct data for the faulty memory among the multiple memories by executing the above steps 1601 and 1602.

[0240] For example, the backup storage media controller detects whether the first storage media controller is faulty, for instance, by using a heartbeat detection method. If a fault is detected in the first storage media controller, the backup storage media controller takes over control of the plurality of memories and performs data reconstruction on the faulty memory by executing steps 1601 and 1602 described above.

[0241] Taking Figure 8 as an example, storage medium controller 81 and storage medium controller 82 are each other's backup storage medium controllers. Initially, either storage medium controller 81 or storage medium controller 82 is the primary storage medium controller, and the other storage medium controller is the backup storage medium controller. During the process of the primary storage medium controller controlling multiple memories 83, if the backup storage medium controller detects a failure in the primary storage medium controller, the backup storage medium controller takes over the control of the multiple memories 83, making the original primary storage medium controller the backup storage medium controller and the original backup storage medium controller the new primary storage medium controller. The new primary storage medium controller manages the multiple memories 83 in ways such as detecting failures in the multiple memories 83, reconstructing data in the failed memories 83, and accessing data in the storage media of the memories 83.

[0242] The method provided in this application uses the memory in a storage device as the fault domain. It performs fault testing on each memory within the storage device individually through the storage media controller, and reconstructs the data for the faulty memory. This eliminates the need to reconstruct data for all storage media in the storage device, reducing the amount of data to be reconstructed and improving efficiency. In traditional SSD applications, if the NAND chip in a traditional SSD fails, the software in the compute node controls the traditional SSD storage media controller to reconstruct the NAND chip. This requires upper-layer software support, which may not be supported in general software ecosystems, limiting the applicability of traditional SSDs. However, the storage media controller in this application can reconstruct data for the memory in the storage device without upper-layer software support, enabling the storage device to be used in general software ecosystems and broadening its applicability. The storage capacity of the storage device provided in this application is far greater than that of traditional SSDs. For example, the storage capacity of the storage device provided in this application can reach the petabyte (PB) level or higher. Through the method provided in the embodiments of this application, the storage device provided in this application can support data reconstruction at the petabyte level or higher. Furthermore, the embodiments of this application use the memory as the fault domain, rather than the entire storage device as the fault domain. According to calculations, a single point of failure in the storage device provided in this application is 10% of the failure domain when the entire storage device is considered as the fault domain. Compared to traditional SSDs, the fault domain in the storage device provided in this application can be reduced by more than 90%. In data reconstruction scenarios, the data reconstruction efficiency of the storage device provided in this application will be higher. Moreover, in the event of a failure in a memory in the storage device provided in this application, the storage media controller can reconstruct the data in the failed memory, while other unfailed memories in the storage device can still be accessed normally, without affecting the operation of the entire storage device.

[0243] When traditional SSDs are used in storage systems, a failure of a traditional SSD renders the entire SSD unusable. Therefore, reconstructing the data stored in all NAND chips within the entire SSD, treating the entire SSD as the fault domain, is a common practice. However, as the SSD capacity increases, the amount of reconstructed data increases linearly with the capacity of the single storage device, severely reducing the availability of the storage system. In this embodiment, a backup storage media controller is provided for the storage media controller in the storage device. In the event of a storage media controller failure, the backup controller manages the memory in the storage device, achieving a second-level switchover without requiring data reconstruction. This avoids the linear increase in reconstructed data with the capacity of the single storage device, thus preventing a decrease in storage system availability due to data reconstruction. As shown in Table 5 below, when the 1PB storage device provided in this application is used in a storage system, the availability of the storage system reaches five nines.

[0244] Table 5

[0245] MTTR is the mean time to repair of the storage system, and MTBF is the mean time between failures. Unit availability is one of the metrics for measuring system performance; it represents the probability that the system is in a normal state at any given time. Switchover success rate refers to the probability that the backup controller will successfully take over in the event of a failure.

[0246] Compared to traditional SSD controllers, the storage medium controller in any of the storage devices provided in this application offloads some functions of the FTL to the control circuit in the memory, such as storing the second mapping relationship between logical addresses and storage media through the control circuit. However, the storage medium controller in the storage device may also have other functions for managing storage media in traditional SSD controllers, such as garbage collection.

[0247] For example, the control chip in the storage media controller is used to determine the first physical address space, which is the physical address space of multiple memories within the storage device that needs to be garbage collected. Regarding garbage collection, there are generally two scenarios: one is that the host specifies the release of data in the physical address space corresponding to a certain logical address segment in the storage device, and the storage media controller uses the physical address space corresponding to that logical address segment as the first physical address space. The other scenario is that the storage media controller periodically determines the physical address space within the storage device that needs to be garbage collected and uses the determined physical address space as the first physical address space.

[0248] The control chip in the storage medium controller is also used to copy valid data stored in the first physical address space to a second physical address space in the plurality of memories. The second physical address space and the first physical address space are different physical address spaces. For example, after determining the first physical address space, the control chip reads valid data from the memory where the first physical address space is located, and writes the read valid data into the second physical address space of the plurality of memories.

[0249] The control chip in the storage medium controller is also used to delete all data stored in the first physical address space to free up the first physical address space and complete garbage collection for the first physical address space.

[0250] In the description of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0251] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0252] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the data involved in this application was obtained with full authorization.

[0253] All of the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of this disclosure, and will not be described in detail here.

[0254] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A storage medium controller, characterized in that, The storage medium controller includes: Host interface, used to connect to the host; A hot-swappable interface is used to connect to the interface circuit of a plurality of first memories by hot-swapping, or to directly connect to the interface circuit of the plurality of first memories by hot-swapping, wherein each first memory includes at least one storage medium. A first control chip is used to connect to the host interface and the hot-swappable interface to manage the storage medium; The first control chip is also used to perform data access between the host and the storage medium in the plurality of first memories based on a first mapping relationship between logical addresses and the plurality of first memories.

2. The storage medium controller according to claim 1, characterized in that, The first control chip is also used for: The host interface receives input / output I / O requests from the host, the I / O requests indicating data access to a target logical address; Based on the first mapping relationship, the I / O request is sent to the target memory among the plurality of first memories, wherein the target memory is a memory mapped to the target logical address; The hot-swappable interface receives I / O responses from the target memory, where the I / O response is the access result of the physical address corresponding to the target logical address. The I / O response is sent to the host through the host interface.

3. The storage medium controller according to claim 2, characterized in that, The first control chip is also used for: If the I / O request is a write request, the target memory is allocated for the I / O request from the plurality of first memories; Send the I / O request to the target memory; Establish a first mapping relationship between the target logical address and the target memory.

4. The storage medium controller according to claim 2, characterized in that, The first control chip is also used for: When the I / O request is a read request, the target memory mapped to the target logical address is queried based on the first mapping relationship between the logical address and the plurality of first memories. Send the I / O request to the target memory that has been queried.

5. The storage medium controller according to any one of claims 1-4, characterized in that, The first control chip also includes a cache area for storing the first mapping relationship.

6. The storage medium controller according to any one of claims 1-5, characterized in that, The hot-swappable interface is hot-swappably connected to the connector, which includes the interface circuit for inserting multiple first memories, or the connector is directly connected to the interface circuit of the multiple first memories via hot-swapping.

7. The storage medium controller according to claim 6, characterized in that, The connector is also connected to a second control chip, which stores the first mapping relationship. The second control chip is used to access data between the host and the storage media in the plurality of first memories based on the stored first mapping relationship; The first control chip is further configured to obtain the first mapping relationship from the second control chip through the connector, and to perform data access between the host and the storage media in the plurality of first memories based on the obtained first mapping relationship.

8. The storage medium controller according to claim 6 or 7, characterized in that, The connector is also connected to a storage device, which includes a third control chip and multiple second memories. The third control chip stores a first mapping relationship between logical addresses and the multiple second memories. The third control chip is used to access data between the host and the storage medium in the plurality of second memories based on the first mapping relationship between the stored logical address and the plurality of second memories; The first control chip is further configured to obtain a first mapping relationship between a logical address and the plurality of second memories from the third control chip via the connector, and to perform data access between the host and the storage media in the plurality of second memories based on the obtained first mapping relationship between the logical address and the plurality of second memories.

9. The storage medium controller according to claim 8, characterized in that, The first control chip further includes a cache area, which is used to store a first mapping relationship between logical addresses and the plurality of second memories.

10. The storage medium controller according to any one of claims 1-4, characterized in that, The first control chip is also used for: A first physical address space is determined, wherein the first physical address space is the physical address space in the plurality of first memories to be garbage collected; Copy the valid data stored in the first physical address space to the second physical address space in the plurality of first memories; Delete all data stored in the first physical address space.

11. A memory, characterized in that, The memory includes a hot-swappable interface, control circuitry, and at least one storage medium; The hot-swappable interface is used to connect to the interface circuit of the storage medium controller via hot-swapping, or to connect directly to the interface circuit of the storage medium controller via hot-swapping. The control circuit is used to connect to the hot-swappable interface and the storage medium, and to manage the storage medium; The control circuit is also configured to receive input / output I / O requests from the storage medium controller via the hot-plug interface, wherein the I / O requests indicate data access to a target logical address; The control circuit is further configured to access data on the physical address mapped to the target logical address in the at least one storage medium based on a second mapping relationship between the logical address and the physical address in the at least one storage medium, and to send an I / O response to the storage medium controller through the hot-plug interface, wherein the I / O response is the access result of the physical address corresponding to the target logical address.

12. The memory according to claim 11, characterized in that, The control circuit is also used for: In the case that the I / O request is a write request, a target physical address is allocated for the I / O request from the physical address in the at least one storage medium; Write the first data carried by the I / O request into the storage space corresponding to the target physical address; Establish a second mapping relationship between the target logical address and the target physical address.

13. The memory according to claim 11, characterized in that, The control circuit is also used for: When the I / O request is a read request, the target physical address mapped to the target logical address is queried based on the second mapping relationship between the logical address and the physical address in the at least one storage medium. Read the data stored in the storage space corresponding to the target physical address.

14. The memory according to any one of claims 11-13, characterized in that, The memory further includes a buffer for storing the second mapping relationship.

15. A storage device, characterized in that, The storage device includes: Multiple primary memories are used to provide physical storage space; Storage media controller, including: Host interface, used to connect to the host; The first hot-swappable interface is used to connect to the interface circuit of the plurality of first memories by hot-swapping, or to directly connect to the interface circuit of the plurality of first memories by hot-swapping. A first control chip is used to connect to the host interface and the first hot-swappable interface to manage the storage media in the plurality of first memories; The first control chip is also used to perform data access between the host and the storage medium in the plurality of first memories based on a first mapping relationship between logical addresses and the plurality of first memories.

16. The storage device according to claim 15, characterized in that, Each first memory also includes a second hot-swappable interface and control circuitry; The second hot-swappable interface is used to connect to the interface circuit of the storage medium controller via hot-swapping, or to connect directly to the interface circuit of the storage medium controller via hot-swapping. The control circuit is used to connect to the second hot-swappable interface and the storage medium in the memory, and to manage the storage medium in the memory. The control circuit is also used to perform data access between the storage medium controller and the storage medium in the memory based on the mapping relationship between the logical address and the physical address in the storage medium in the memory.

17. The storage device according to claim 16, characterized in that, The first control chip is also configured to receive input / output (I / O) requests from the host via the host interface, wherein the I / O requests indicate data access to a target logical address; The first control chip is also used to send the I / O request to a target memory among the plurality of first memories based on the mapping relationship between the logical address and the plurality of first memories, wherein the target memory is a memory mapped to the target logical address; The control circuit in the target memory is used to receive the I / O request through the second hot-plug interface in the memory, read and write data to the physical address corresponding to the target logical address in the storage medium based on the second mapping relationship between the logical address and the physical address in the storage medium, and send an I / O response to the storage medium controller through the second hot-plug interface in the memory. The I / O response is the access result of the physical address corresponding to the target logical address. The first control chip is also configured to receive the I / O response through the first hot-plug interface and send the I / O response to the host through the host interface.

18. The storage device according to claim 17, characterized in that, The first control chip is further configured to allocate the target memory for the I / O request from the plurality of first memories when the I / O request is a write request; Send the I / O request to the target memory to establish a first mapping relationship between the target logical address and the target memory; The control circuit in the target memory is used to allocate a target physical address for the I / O request from the physical address in the storage medium of the memory; write the first data carried by the I / O request into the storage space corresponding to the target physical address; and establish a binary mapping relationship between the target logical address and the target physical address.

19. The storage device according to claim 17, characterized in that, The first control chip is further configured to, when the I / O request is a read request, query the target memory mapped to the target logical address based on the first mapping relationship between the logical address and the plurality of first memories; Send the read / write I / O request to the target memory that has been queried; The control circuit in the target memory is used to query the target physical address mapped by the target logical address based on the second mapping relationship between the logical address and the physical address in the storage medium of the memory; and to read the data stored in the storage space corresponding to the target physical address.

20. The storage device according to any one of claims 15-19, characterized in that, The storage device further includes a connector, which includes an interface circuit for inserting into a plurality of first memories and the storage medium controller. Alternatively, the connector can be directly connected to the interface circuits of the plurality of first memories and the interface circuit of the storage medium controller via hot-plugging.

21. The storage device according to claim 20, characterized in that, The connector is also connected to a second control chip, which stores a first mapping relationship between logical addresses and the plurality of first memories. The second control chip is used to perform data access between the host and the storage medium in the plurality of first memories based on the stored logical address and the first mapping relationship between them; The first control chip is further configured to obtain a first mapping relationship between a logical address and the plurality of first memories from the second control chip via the connector, and to perform data access between the host and the storage medium in the plurality of first memories based on the obtained first mapping relationship between the logical address and the plurality of first memories.

22. The storage device according to claim 20 or 21, characterized in that, The connector is also connected to a storage device, which includes a third control chip and multiple second memories. The third control chip stores a first mapping relationship between logical addresses and the multiple second memories. The third control chip is used to access data between the host and the storage medium in the plurality of second memories based on the first mapping relationship between the stored logical address and the plurality of second memories; The first control chip is further configured to obtain a first mapping relationship between a logical address and the plurality of second memories from the third control chip via the connector, and to perform data access between the host and the storage media in the plurality of second memories based on the obtained first mapping relationship between the logical address and the plurality of second memories.

23. The storage device according to claim 22, characterized in that, The first control chip further includes a cache area, which is used to store a first mapping relationship between logical addresses and the plurality of second memories.

24. The storage device according to any one of claims 15-19, characterized in that, The first control chip is also used for: A first physical address space is determined, wherein the first physical address space is the physical address space in the plurality of first memories to be garbage collected; Copy the valid data stored in the first physical address space to the second physical address space in the plurality of first memories; Delete all data stored in the first physical address space.

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