Clock transmission circuit, phase calibration method, and memory

Abstract

Provided in the present disclosure are a clock transmission circuit, a phase calibration method, and a memory. The clock transmission circuit comprises: a first clock distribution network and a second clock distribution network, which respectively receive a first input clock signal and a second input clock signal, transmit same to an output port area, and output a first target clock signal and a second target clock signal, wherein in a normal operation mode, the phase difference between the second input clock signal and the first input clock signal is a preset value, and in a calibration mode, the second input clock signal is in phase with the first input clock signal; and a phase calibration module, which receives, in the calibration mode, the first target clock signal and the second target clock signal, and outputs, on the basis of the phase difference between the first target clock signal and the second target clock signal, a first phase calibration code for adjusting the delay of the second clock distribution network, wherein when calibration is completed, the phase difference between the first target clock signal and the second target clock signal is less than a preset threshold value. The present disclosure at least facilitates an improvement in the phase difference between multi-phase clocks, thereby shortening the testing time.

Description

Clock transmission circuit, phase calibration method and memory

[0001] This application claims priority to Chinese Patent Application No. 202411206661.X, filed on August 29, 2024, entitled "Clock Transmission Circuit, Phase Calibration Method and Memory", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and in particular to a clock transmission circuit, a phase calibration method, and a memory. Background Technology

[0003] In storage systems, data is typically transmitted in a specific timing sequence. The proper functioning of a memory depends on the accurate timing of its internal commands and clocks. In Dynamic Random Access Memory (DRAM), a delay-locked loop (DLL) requires phase synchronization and locking of four-phase clock signals (i.e., four clock signals with phases differing by 90 degrees sequentially) to generate the data strobe signal DQS, which is used for sampling the data signal DQ. However, as the operating frequency of the memory increases, the phase difference between the four-phase clock signals may deviate significantly from the target value during phase synchronization and locking. Summary of the Invention

[0004] This disclosure provides a clock transmission circuit, a phase calibration method, and a memory, which at least helps to improve the phase difference between multi-phase clock signals and shorten the test time.

[0005] In a first aspect, embodiments of this disclosure provide a clock transmission circuit applied to a memory, comprising:

[0006] A first clock distribution network is configured to receive a first input clock signal and transmit it to the output port area of ​​the memory, and output a first target clock signal.

[0007] The second clock distribution network is configured to receive a second input clock signal and transmit it to the output port area of ​​the memory to output a second target clock signal; when the memory is in normal operating mode, the phase difference between the second input clock signal and the first input clock signal is a preset value; when the memory is in calibration mode, the second input clock signal is in phase with the first input clock signal.

[0008] The phase calibration module is configured to receive the first target clock signal and the second target clock signal when the memory is in calibration mode, and output a first phase calibration code based on the phase difference between the two; the first phase calibration code is used to adjust the delay of the second clock distribution network; when calibration is completed, the phase difference between the first target clock signal and the second target clock signal is less than a preset threshold.

[0009] In some embodiments, the clock transmission circuit further includes:

[0010] A delay phase-locked loop, the delay phase-locked loop including at least a first adjustable delay line, the first adjustable delay line receiving a first clock signal and a control code, performing delay processing on the first clock signal based on the control code, and outputting a first delayed clock signal;

[0011] A multi-phase clock generation circuit, electrically connected to the first adjustable delay line, is configured to receive the first delayed clock signal and generate at least a first phase clock signal and a second phase clock signal based on the first delayed clock signal when the operating frequency of the memory is greater than or equal to a preset frequency. The first phase clock signal and the first delayed clock signal are in phase, and the phase difference between the second phase clock signal and the first phase clock signal is the preset value. When the operating frequency of the memory is less than the preset frequency, the multi-phase clock generation circuit is disabled.

[0012] In some embodiments, the clock transmission circuit further includes:

[0013] A first-mode control circuit, electrically connected to the multi-phase clock generation circuit, the first clock distribution network, and the second clock distribution network, is configured to receive the first phase clock signal and the second phase clock signal; when the operating frequency of the memory is greater than or equal to a preset frequency and is in normal operating mode, the first phase clock signal is transmitted as the first input clock signal to the first clock distribution network, and the second phase clock signal is transmitted as the second input clock signal to the second clock distribution network; when the operating frequency of the memory is greater than or equal to the preset frequency and is in calibration mode, the first phase clock signal is simultaneously transmitted as both the first input clock signal and the second input clock signal to the first clock distribution network and the second clock distribution network.

[0014] In some embodiments, the delay phase-locked loop further includes a second adjustable delay line; the second adjustable delay line is configured to receive a second clock signal when the operating frequency of the memory is less than a preset frequency and in normal operating mode; receive a first clock signal when the operating frequency of the memory is less than the preset frequency and in calibration mode; perform delay processing on the received signal based on the control code to output a second delayed clock signal; and disable the second adjustable delay line when the operating frequency of the memory is greater than or equal to the preset frequency.

[0015] In some embodiments, the first mode control circuit is also electrically connected to the second adjustable delay line to receive the second delayed clock signal; when the operating frequency of the memory is less than a preset frequency, the first delayed clock signal is transmitted to the first clock distribution network as the first input clock signal, and the second delayed clock signal is transmitted to the second clock distribution network as the second input clock signal.

[0016] In some embodiments, the clock transmission circuit further includes:

[0017] The second mode control circuit, electrically connected to the first adjustable delay line and the second adjustable delay line, is configured to: when the operating frequency of the memory is less than a preset frequency and the memory is in normal operating mode, send the first clock signal to the first adjustable delay line and send the second clock signal to the second adjustable delay line; when the operating frequency of the memory is less than the preset frequency and the memory is in calibration mode, send the first clock signal to both the first adjustable delay line and the second adjustable delay line simultaneously; and when the operating frequency of the memory is greater than or equal to the preset frequency, send the first clock signal to the first adjustable delay line.

[0018] In some embodiments, the first adjustable delay line and the second adjustable delay line have the same circuit structure.

[0019] In some embodiments, the clock transmission circuit further includes a replica clock distribution network, receives the first input clock signal, simulates the delay of the first clock distribution network, and outputs a replica target clock signal.

[0020] In some embodiments, the delay phase-locked loop further includes:

[0021] The delay simulation circuit receives the target clock signal for replication and is used to simulate the delay of the clock input path and clock output path in the memory, and outputs a feedback clock signal; the clock input path includes a clock receiver and a frequency divider, and the clock output path includes an output driver circuit;

[0022] The first phase detector, electrically connected to the delay analog circuit, is configured to receive the feedback clock signal and the reference clock signal, and output a first indication signal based on the phase order of the two.

[0023] A control code generation circuit, electrically connected to the first phase detector, is configured to adjust and output the control code based on the first indication signal.

[0024] In some embodiments, the delay-locked loop has completed phase locking before the memory enters the calibration mode.

[0025] In some embodiments, the phase calibration module includes:

[0026] The second phase detector receives the first target clock signal and the second target clock signal, and outputs a second indication signal based on the phase order of the two.

[0027] The first calibration code generation circuit, electrically connected to the second phase detector, is configured to adjust and output the first phase calibration code based on the second indication signal.

[0028] In some embodiments, the second clock distribution network includes an adjustable delay module that receives the first phase calibration code and adjusts its own delay in response to the first phase calibration code.

[0029] In some embodiments, the adjustable delay module includes a plurality of delay units, each of the delay units being turned on or off in response to a bit in the first phase calibration code.

[0030] In some embodiments, the first calibration code generation circuit includes:

[0031] The shift register is configured to receive the second indication signal, shift left or right according to the second indication signal, and output the first phase calibration code.

[0032] In some embodiments, the clock transmission circuit further includes:

[0033] The register is configured to store the first phase calibration code after the calibration mode ends, and to send the first phase calibration code to the second clock distribution network when the memory is in normal operating mode.

[0034] In some embodiments, the phase calibration module stops working after the calibration mode ends.

[0035] In some embodiments, the clock transmission circuit further includes:

[0036] A third clock distribution network is configured to receive a third input clock signal and transmit it to the output port area of ​​the memory to output a third target clock signal; when the memory is in normal operating mode, the phase difference between the third input clock signal and the second input clock signal is 90 degrees; when the memory is in calibration mode, the third input clock signal is in phase with the first input clock signal.

[0037] A fourth clock distribution network is configured to receive a fourth input clock signal and transmit it to the output port area of ​​the memory to output a fourth target clock signal; when the memory is in normal operating mode, the phase difference between the fourth input clock signal and the third input clock signal is 90 degrees; when the memory is in calibration mode, the fourth input clock signal is in phase with the first input clock signal.

[0038] The phase calibration module is further configured to, when the memory is in calibration mode, receive the third target clock signal and the fourth target clock signal, and output a second phase calibration code based on the phase difference between the third target clock signal and the first target clock signal; the second phase calibration code is used to adjust the delay of the third clock distribution network; and output a third phase calibration code based on the phase difference between the fourth target clock signal and the first target clock signal; the third phase calibration code is used to adjust the delay of the fourth clock distribution network; when calibration is complete, the phase difference between the first target clock signal and the third target clock signal is less than a preset threshold, and the phase difference between the first target clock signal and the fourth target clock signal is less than a preset threshold.

[0039] In some embodiments, the delay phase-locked loop further includes:

[0040] The third adjustable delay line is configured to receive a third clock signal when the operating frequency of the memory is less than a preset frequency and in normal operating mode; receive a first clock signal when the operating frequency of the memory is less than the preset frequency and in calibration mode; perform delay processing on the received signal based on the control code and output a third delayed clock signal; and disable the third adjustable delay line when the operating frequency of the memory is greater than or equal to the preset frequency.

[0041] The fourth adjustable delay line is configured to receive a fourth clock signal when the operating frequency of the memory is less than a preset frequency and in normal operating mode; receive the first clock signal when the operating frequency of the memory is less than the preset frequency and in calibration mode; perform delay processing on the received signal based on the control code and output a fourth delayed clock signal; and disable the fourth adjustable delay line when the operating frequency of the memory is greater than or equal to the preset frequency.

[0042] The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially 90 degrees apart in phase.

[0043] In some embodiments, the multiphase clock generating circuit is further configured to generate a third phase clock signal and a fourth phase clock signal based on the first delayed clock signal, wherein the phases of the first phase clock signal, the second phase clock signal, the third phase clock signal and the fourth phase clock signal are sequentially 90 degrees apart;

[0044] The first mode control circuit is also electrically connected to the third adjustable delay line and the fourth adjustable delay line, and is configured to receive the third phase clock signal, the fourth phase clock signal, the third delay clock signal, and the fourth delay clock signal; when the operating frequency of the memory is greater than or equal to a preset frequency and is in normal operating mode, the third phase clock signal is transmitted to the third clock distribution network as the third input clock signal, and the fourth phase clock signal is transmitted to the fourth clock distribution network as the fourth input clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency and is in calibration mode, the first phase clock signal is transmitted to both the third and fourth input clock signals to the third and fourth clock distribution networks simultaneously; when the operating frequency of the memory is less than the preset frequency, the third delay clock signal is transmitted to the third clock distribution network as the third input clock signal, and the fourth delay clock signal is transmitted to the fourth clock distribution network as the fourth input clock signal.

[0045] The second mode control circuit is also electrically connected to the third adjustable delay line and the fourth adjustable delay line, and is configured to send the third clock signal to the third adjustable delay line and the fourth clock signal to the fourth adjustable delay line when the operating frequency of the memory is less than the preset frequency and the memory is in normal operating mode; and to send the first clock signal to both the third adjustable delay line and the fourth adjustable delay line simultaneously when the operating frequency of the memory is less than the preset frequency and the memory is in calibration mode.

[0046] In some embodiments, the clock frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are half the clock frequency of the initial clock signal received by the memory, wherein the clock frequency of the initial clock signal is equal to the operating frequency of the memory.

[0047] In some embodiments, the phase calibration module includes:

[0048] The third phase detector receives the first target clock signal and the third target clock signal, and outputs a third indication signal based on the phase order of the two.

[0049] The second calibration code generation circuit, which is electrically connected to the third phase detector, is configured to adjust and output the second phase calibration code based on the third indication signal.

[0050] The fourth phase detector receives the first target clock signal and the fourth target clock signal, and outputs a fourth indication signal based on the phase order of the two.

[0051] The third calibration code generation circuit, electrically connected to the fourth phase detector, is configured to adjust and output the third phase calibration code based on the fourth indication signal.

[0052] Secondly, embodiments of this disclosure provide a phase calibration method applied to a memory, comprising:

[0053] A first input clock signal is input to a first clock distribution network and transmitted to the output port area of ​​the memory to output a first target clock signal.

[0054] A second input clock signal is input to a second clock distribution network and transmitted to the output port area of ​​the memory to output a second target clock signal.

[0055] When the memory is in calibration mode, the second input clock signal is controlled to be in phase with the first input clock signal;

[0056] Receive the first target clock signal and the second target clock signal, and output the first phase calibration code based on the phase difference between them;

[0057] The delay of the second clock distribution network is adjusted according to the first phase calibration code; when the calibration is completed, the phase difference between the first target clock signal and the second target clock signal is less than a preset threshold.

[0058] Thirdly, embodiments of this disclosure provide a memory that includes at least the clock transmission circuit described in the first aspect.

[0059] The technical solutions provided in this disclosure have at least the following advantages:

[0060] When the memory is in calibration mode, the first and second clock distribution networks transmit clock signals in phase. The delay of the second clock distribution network is adjusted based on the phase difference between the transmitted signals, thus matching the delays of the first and second clock distribution networks. In this way, when the memory is operating normally, the deviation (Skew) between the phase difference between the first and second target clock signals and the target value can be reduced, which is beneficial for data transmission. Furthermore, the calibration mode setting can shorten the test time. Attached Figure Description

[0061] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] Figure 1 is a schematic diagram of a clock transmission circuit;

[0063] Figure 2 is a schematic diagram of a clock transmission circuit provided in an embodiment of this disclosure;

[0064] Figure 3 is a schematic diagram of another clock transmission circuit provided in an embodiment of this disclosure;

[0065] Figure 4 is a waveform diagram of a clock transmission circuit provided in an embodiment of this disclosure;

[0066] Figure 5 is a schematic diagram of another clock transmission circuit provided in an embodiment of this disclosure;

[0067] Figure 6 is a schematic flowchart of the phase calibration method provided in the embodiments of this disclosure;

[0068] Figure 7 is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0069] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant applications and not for limiting the applications. It should also be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0070] Dynamic Random Access Memory (DRAM)

[0071] Synchronous Dynamic Random Access Memory (SDRAM)

[0072] Double Data Rate SDRAM (DDR)

[0073] Low-power DDR (LPDDR)

[0074] The nth generation DDR standard (DDRn Specification, DDRn), such as DDR3, DDR4, DDR5, DDR6.

[0075] The nth generation LPDDR standard (LPDDRn Specification, LPDDRn), such as LPDDR3, LPDDR4, LPDDR5, LPDDR6.

[0076] Delay Locked Loop (DLL)

[0077] Clocks are a crucial component of digital circuits, providing a stable time base that allows different parts of the circuit to operate according to a predetermined timing sequence. Clocks also play a vital role in memory. Data in memory is typically transferred in a specific timing sequence. Clock signals control data input and output, ensuring that data is read or written at the correct time. Through clock synchronization, memory can coordinate with other digital circuit components, guaranteeing the accuracy and reliability of data transmission.

[0078] As memory operating frequencies increase, the frequency of the received initial clock signal also increases. This necessitates internal frequency division within the memory to generate internal multi-phase clock signals for data processing. The phase difference between these multi-phase clock signals is related to the quality of the final output data from the memory. Taking DDR5 DRAM as an example, to achieve high-frequency operation, a four-phase clock signal is generated internally based on the initial clock signal for data processing. Ideally, the four-phase clock signal consists of four clock signals with phases differing by 90 degrees. However, under high-frequency conditions, due to the influence of factors such as process technology, voltage, and temperature, the phase difference between the internal four-phase clock signals can deviate significantly from the ideal value (skew).

[0079] Referring to Figure 1, a clock transmission circuit structure is shown. The clock receiver (Clock Input Buffer, CLK IB) receives the initial clock signal CK_t, and then generates four-phase clock signals CLKI, CLKQ, CLKIB, and CLKQB via a divider. Currently, memory is gradually moving towards higher speeds. Taking DDR5 as an example, due to its speed increase and process limitations, the high-speed clock signal at the interface needs to be converted into a low-speed clock signal internally. Therefore, the phases of CLKI, CLKQ, CLKIB, and CLKQB differ by 90 degrees, and their frequencies are half the frequency of the initial clock signal CK_t. Subsequently, the four-phase clock signals CLKI, CLKQ, CLKIB, and CLKQB are fed into four adjustable delay lines. Each adjustable delay line includes a coarse delay line (CDL), a fine delay line (FDL), a duty cycle corrector (DCC), a quadrant error corrector (QEC), and a driver (DRV). These four-phase clock signals are then transmitted to the output port area via four read clock distribution networks (RD CLK CDN) for sampling the data signal DQ. The output port area is shown in the diagram as LDQ and UDQ, where LDQ represents the output port area for low-order data and UDQ represents the output port area for high-order data. This delay-locked loop also includes a replica adjustable delay line to simulate the delay of the aforementioned adjustable delay lines. The replica adjustable delay line receives CLKI and also includes the same CDL, FDL, DCC+QEC, and DRV modules. The clock signal output from the replicated adjustable delay line passes through a replicated read clock distribution network (RD CLK CDN Replica) to simulate the delay of the read clock distribution network. The clock signal output from the replicated read clock distribution network then passes through an input / output replica (I / O Replica) to generate a feedback clock signal FBCLK. A phase detector (PD) compares the phases of the reference clock signal REFCLK and the feedback clock signal FBCLK, and then the delay control module (CDL / FDL Control) controls the delays of CDL and FDL so that the phase difference between the final reference clock signal REFCLK and the feedback clock signal FBCLK is approximately zero, thus locking the DLL.Ideally, when the DLL is locked, the rising edges of the reference clock signal REFCLK and the feedback clock signal FBCLK are aligned, and their phase difference is equal to 0. However, in practice, as long as the phase difference between REFCLK and FBCLK is approximately 0 within the allowable error range, the DLL can be considered to be locked. CLKI can be selected as the reference clock signal REFCLK. Ideally, the phase difference between the four-phase clock signals transmitted to the output port area should be 90 degrees, i.e., the target value is 90 degrees. However, due to the influence of other factors such as process, voltage, and temperature, it is difficult to achieve completely consistent delays for the four transmission paths. Even if the phases of CLKI, CLKQ, CLKIB, and CLKQB generated by the frequency divider differ by 90 degrees sequentially, the phase difference between them may deviate from 90 degrees when transmitted to the output port area. On the one hand, a quadrant error corrector (QEC) circuit can be used to adjust the phase difference between the four-phase clock signals. On the other hand, an adjustment unit is set in each read clock distribution network, which is a fuse-controlled delay unit. After chip mass production, testers conduct extensive testing. Based on the phase information of the four-phase clock signals, they blow corresponding fuses to select the appropriate delay level, thereby calibrating the phase difference between the four-phase clock signals. This method requires a significant amount of testing time and cannot guarantee that the phase difference between the four-phase clock signals will still reach the target value when the operating environment of the memory changes. This is detrimental to generating the data strobe signal DQS and sampling the data signal DQ.

[0080] Based on this, this disclosure provides a clock transmission circuit applied to a memory, comprising: a first clock distribution network configured to receive a first input clock signal and transmit it to the output port area of ​​the memory to output a first target clock signal; a second clock distribution network configured to receive a second input clock signal and transmit it to the output port area of ​​the memory to output a second target clock signal; when the memory is in normal operating mode, the phase difference between the second input clock signal and the first input clock signal is a preset value; when the memory is in calibration mode, the second input clock signal and the first input clock signal are in phase; a phase calibration module configured to, when the memory is in calibration mode, receive the first target clock signal and the second target clock signal, and output a first phase calibration code based on the phase difference between them; the first phase calibration code is used to adjust the delay of the second clock distribution network; when calibration is complete, the phase difference between the first target clock signal and the second target clock signal is less than a preset threshold. Thus, in calibration mode, the first clock distribution network and the second clock distribution network transmit clock signals in phase, and adjusting the delay of the second clock distribution network based on the phase difference between the transmitted signals can match the delays of the first clock distribution network and the second clock distribution network. Thus, when the memory is working normally, the phase difference between the first target clock signal and the second target clock signal can be reduced, which is beneficial for data transmission. Furthermore, the calibration mode setting can also shorten the test time.

[0081] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0082] In one embodiment of this disclosure, referring to FIG2, a schematic diagram of a clock transmission circuit 10 provided in this embodiment is shown. As shown in FIG2, the clock transmission circuit 10 includes:

[0083] The first clock distribution network 11 is configured to receive a first input clock signal and transmit it to the output port area 31 of the memory to output a first target clock signal.

[0084] The second clock distribution network 12 is configured to receive the second input clock signal and transmit it to the output port area 31 of the memory to output the second target clock signal; when the memory is in normal operating mode, the phase difference between the second input clock signal and the first input clock signal is a preset value; when the memory is in calibration mode, the second input clock signal is in phase with the first input clock signal.

[0085] The phase calibration module 13 is configured to receive a first target clock signal and a second target clock signal when the memory is in calibration mode, and output a first phase calibration code based on the phase difference between the two; the first phase calibration code is used to adjust the delay of the second clock distribution network; when calibration is completed, the phase difference between the first target clock signal and the second target clock signal is less than a preset threshold.

[0086] It should be noted that the clock transmission circuit 10 of this disclosure embodiment can be applied to, but is not limited to, memory, such as DRAM, SDRAM, etc. In addition, in other analog / digital circuits, such as controllers, processors, etc., the clock transmission circuit 10 provided in this disclosure embodiment can generate a set of clock signals with different phases.

[0087] The first clock distribution network 11 and the second clock distribution network 12 transmit the first input clock signal and the second input clock signal to the output port area 31 of the memory, respectively, and output the first target clock signal and the second target clock signal for subsequent generation of the data strobe signal DQS and sampling processing of the data signal DQ. The output port area 31 refers to the circuit area near the data pin (DQ Pad) in the memory for outputting data-related circuits, including the data DQ sampling circuit and the output drive circuit.

[0088] When the memory is in normal operating mode, the phase difference between the second input clock signal and the first input clock signal is a preset value. In some examples, this preset value can be 90 degrees, 180 degrees, or 270 degrees. Ideally, the phase difference between the second target clock signal and the first target clock signal should be equal to the target value, that is, equal to the preset value. However, in practice, due to the influence of other factors such as process technology, voltage, and temperature, the delays of the uncalibrated first clock distribution network 11 and the second clock distribution network 12 are inconsistent, causing the phase difference between the second target clock signal and the first target clock signal to deviate from the target value, that is, deviate from the preset value.

[0089] When the memory is in calibration mode, the first input clock signal entering the first clock distribution network 11 is in phase with the second input clock signal entering the second clock distribution network 12. The phase calibration module 13 outputs a first phase calibration code based on the phase difference between the first target clock signal and the second target clock signal, thereby adjusting the delay of the second clock distribution network. When calibration is complete, the delays of the first clock distribution network 11 and the second clock distribution network 12 are matched. Ideally, the first target clock signal and the second target clock signal should also be in phase. In practice, the calibration is considered complete when the phase difference between the first target clock signal and the second target clock signal is less than a preset threshold. This preset threshold can be set according to the memory's working environment and actual needs, as long as the accuracy of data sampling and transmission during memory operation is guaranteed.

[0090] When calibration is complete, the phase difference between the first target clock signal and the second target clock signal is less than a preset threshold. At this point, when the calibrated memory returns to normal operating mode, the phase difference between the second input clock signal and the first input clock signal is the preset value, and the difference between the phase difference between the second target clock signal and the first target clock signal and the target value should also be less than the preset threshold. Thus, when the memory is operating normally, the deviation (Skew) between the phase difference between the first and second target clock signals and the target value can be reduced, which is beneficial for the subsequent generation of the data strobe signal DQS and the sampling processing of the data signal DQ. Furthermore, the calibration mode setting can shorten the test time.

[0091] It should be understood that the limitations on phase difference and in-phase in this disclosure allow for a certain degree of error. That is, when the memory is in normal operating mode, the phase difference between the second input clock signal and the first input clock signal is equal to a preset value within the allowable error range. When the memory is in calibration mode, the second input clock signal is in phase with the first input clock signal within the allowable error range. Subsequent limitations regarding phase values, signal edge alignment, or identical signal waveforms all refer to the allowable error range.

[0092] In some embodiments, as shown in FIG3, the clock transmission circuit 10 further includes:

[0093] The delay phase-locked loop 14 includes at least a first adjustable delay line 141. The first adjustable delay line 141 receives a first clock signal and a control code, performs delay processing on the first clock signal based on the control code, and outputs a first delayed clock signal.

[0094] The multiphase clock generation circuit 15, electrically connected to the first adjustable delay line 141, is configured to receive a first delayed clock signal when the operating frequency of the memory is greater than or equal to a preset frequency, and generate at least a first phase clock signal and a second phase clock signal based on the first delayed clock signal. The first phase clock signal and the first delayed clock signal are in phase, and the phase difference between the second phase clock signal and the first phase clock signal is a preset value. When the operating frequency of the memory is less than the preset frequency, the multiphase clock generation circuit 15 is disabled.

[0095] When the memory's operating frequency is greater than or equal to a preset frequency, the multiphase clock generation circuit 15 generates at least a first-phase clock signal and a second-phase clock signal based on a first delayed clock signal. The first-phase clock signal and the first delayed clock signal are in phase, and the phase difference between the second-phase clock signal and the first delayed clock signal is a preset value. In some examples, this preset value can be 90 degrees, 180 degrees, or 270 degrees. The multiphase clock generation circuit can be a four-phase clock generation circuit, also generating a third-phase clock signal and a fourth-phase clock signal, wherein the phases of the first-phase clock signal, the second-phase clock signal, the third-phase clock signal, and the fourth-phase clock signal differ by 90 degrees sequentially. Because the adjustable delay line consumes a lot of power when the memory operates at high speed, using only one adjustable delay line and a multiphase clock generation circuit to generate multiphase clock signals reduces the clock transmission path, lowers circuit power consumption, reduces power supply noise, thereby reducing clock jitter and improving clock signal quality. When the memory's operating frequency is less than the preset frequency, the multiphase clock generation circuit 15 is disabled, further saving circuit power consumption.

[0096] It is understandable that the operating frequency of the memory is equal to the clock frequency of the initial clock signal CK_t received by the memory. The aforementioned preset frequency can be set to the required value according to the actual scenario. For example, in DDR5, the preset frequency can be set to 5.6Gbps. In some embodiments, the multiphase clock generation circuit 15 can be an analog phase generator (APG). The APG can generate a first phase clock signal, a second phase clock signal, a third phase clock signal, and a fourth phase clock signal, which are sequentially 90 degrees out of phase with each other. However, the APG can only operate in a specific frequency band and cannot cover a sufficiently wide operating frequency band. For example, when the APG is designed to operate at a higher frequency, it may not be able to generate the correct four-phase clock signal at a lower frequency. Therefore, the setting of the preset frequency also needs to take into account the operating frequency band of the multiphase clock generation circuit 15 to ensure that the multiphase clock generation circuit 15 can work normally when the operating frequency of the memory is greater than or equal to the preset frequency.

[0097] In some embodiments, as shown in FIG3, the clock transmission circuit 10 further includes:

[0098] The first mode control circuit 16 is electrically connected to the multiphase clock generation circuit 15, the first clock distribution network 11, and the second clock distribution network 12. It is configured to receive a first phase clock signal and a second phase clock signal. When the operating frequency of the memory is greater than or equal to a preset frequency and is in normal operating mode, the first phase clock signal is transmitted to the first clock distribution network 11 as the first input clock signal, and the second phase clock signal is transmitted to the second clock distribution network 12 as the second input clock signal. When the operating frequency of the memory is greater than or equal to the preset frequency and is in calibration mode, the first phase clock signal is transmitted to both the first and second input clock signals simultaneously to the first clock distribution network 11 and the second clock distribution network 12.

[0099] When the memory's operating frequency is greater than or equal to a preset frequency and it is in normal operating mode, the first mode control circuit 16 transmits the first phase clock signal to the first clock distribution network 11 and the second phase clock signal to the second clock distribution network 12, thereby ensuring that the phase difference between the second input clock signal and the first input clock signal is a preset value. When the memory's operating frequency is greater than or equal to the preset frequency and it is in calibration mode, the first mode control circuit 16 transmits the first phase clock signal to both the first clock distribution network 11 and the second clock distribution network 12 simultaneously, thereby ensuring that the second input clock signal is in phase with the first input clock signal. It can be understood that the first mode control circuit 16 can also transmit the second phase clock signal to both the first clock distribution network 11 and the second clock distribution network 12 simultaneously, which can also ensure that the second input clock signal is in phase with the first input clock signal.

[0100] The first mode control circuit 16 can be implemented using a multiplexer (Mux). The multiplexer's first input receives a first-phase clock signal, its second input receives a second-phase clock signal, its first output is connected to a first clock distribution network 11, its second output is connected to a second clock distribution network 12, and its control terminal receives a mode control signal. This mode control signal indicates whether the memory is in normal operating mode or calibration mode. The multiplexer always transmits the signal from the first input to the first output, and simultaneously, in response to the mode control signal, selects whether to transmit the signal from the first or second input to the second output.

[0101] In some embodiments, as shown in FIG3, the delay phase-locked loop 14 further includes a second adjustable delay line 142; the second adjustable delay line 142 is configured to receive a second clock signal when the operating frequency of the memory is less than a preset frequency and in normal operating mode; receive a first clock signal when the operating frequency of the memory is less than the preset frequency and in calibration mode; perform delay processing on the received signal based on the control code and output a second delayed clock signal; and disable the second adjustable delay line 142 when the operating frequency of the memory is greater than or equal to the preset frequency.

[0102] When the operating frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line 142 is disabled. The multi-phase clock signal is generated by the first adjustable delay line 141 and the multi-phase clock generation circuit 15. This can reduce the clock transmission path, reduce circuit power consumption, reduce power supply noise, thereby reducing clock jitter and improving the quality of the clock signal.

[0103] When the memory's operating frequency is lower than a preset frequency and it is in normal operating mode, the second adjustable delay line 142 receives and transmits a second clock signal. The phase difference between the second clock signal and the first clock signal is a preset value. The multi-phase clock generation circuit 15 is disabled, and two clock signals with different phases are transmitted by the first adjustable delay line 141 and the second adjustable delay line 142. When the memory's operating frequency is lower than the preset frequency and it is in calibration mode, the second adjustable delay line 142 receives and transmits a first clock signal. Both the first adjustable delay line 141 and the second adjustable delay line 142 transmit the first clock signal for phase calibration.

[0104] In some embodiments, the first mode control circuit 16 is also electrically connected to the second adjustable delay line 142 to receive the second delayed clock signal; when the operating frequency of the memory is less than the preset frequency, the first delayed clock signal is transmitted to the first clock distribution network 11 as the first input clock signal, and the second delayed clock signal is transmitted to the second clock distribution network 12 as the second input clock signal.

[0105] It is understandable that when the operating frequency of the memory is less than the preset frequency, the first mode control circuit 16 does not distinguish between the normal working mode and the calibration mode, and always transmits the first delayed clock signal output by the first adjustable delay line 141 to the first clock distribution network 11, and transmits the second delayed clock signal output by the second adjustable delay line 142 to the second clock distribution network 12.

[0106] In some embodiments, as shown in FIG3, the clock transmission circuit 10 further includes:

[0107] The second mode control circuit 17, electrically connected to the first adjustable delay line 141 and the second adjustable delay line 142, is configured to: when the operating frequency of the memory is less than a preset frequency and in normal operating mode, send a first clock signal to the first adjustable delay line 141 and a second clock signal to the second adjustable delay line 142; when the operating frequency of the memory is less than the preset frequency and in calibration mode, send the first clock signal to both the first adjustable delay line 141 and the second adjustable delay line 142; and when the operating frequency of the memory is greater than or equal to the preset frequency, send the first clock signal to the first adjustable delay line 141.

[0108] When the memory's operating frequency is lower than a preset frequency and it is in normal operating mode, a first clock signal is sent to the first adjustable delay line 141, and a second clock signal is sent to the second adjustable delay line 142. The phase difference between the first and second clock signals is a preset value, ensuring that clock signals of different phases are transmitted in the two transmission paths. When the memory's operating frequency is lower than the preset frequency and it is in calibration mode, the first clock signal is sent simultaneously to both the first and second adjustable delay lines 141 and 142, ensuring that clock signals of the same phase are transmitted in both transmission paths for phase calibration.

[0109] When the memory's operating frequency is greater than or equal to a preset frequency, a first clock signal is sent to the first adjustable delay line 141. At this time, a second clock signal can be sent to the second adjustable delay line 142, or it can be left unsent. Because the second adjustable delay line 142 is disabled at this time, it does not transmit regardless of whether a second clock signal is received.

[0110] The following explanations, based on Table 1, illustrate several scenarios.

[0111] Table 1

[0112] In the first scenario: when the operating frequency of the memory is greater than or equal to the preset frequency and is in normal operating mode, the second mode control circuit 17 sends the first clock signal to the first adjustable delay line 141; the second adjustable delay line 142 is disabled, and the first adjustable delay line 141 performs delay processing on the first clock signal based on the control code, outputting the first delayed clock signal; the multi-phase clock generation circuit 15 generates a first phase clock signal and a second phase clock signal based on the first delayed clock signal; the first mode control circuit 16 transmits the first phase clock signal to the first clock distribution network 11 and transmits the second phase clock signal to the second clock distribution network 12; the first clock distribution network 11 and the second clock distribution network 12 respectively transmit the first phase clock signal and the second phase clock signal to the output port area for sampling processing of the data signal DQ.

[0113] In the second scenario: when the operating frequency of the memory is greater than or equal to the preset frequency and is in calibration mode, the second mode control circuit 17 sends the first clock signal to the first adjustable delay line 141; the second adjustable delay line 142 is disabled, and the first adjustable delay line 141 performs delay processing on the first clock signal based on the control code, outputting the first delayed clock signal; the multi-phase clock generation circuit 15 generates a first phase clock signal and a second phase clock signal based on the first delayed clock signal; the first mode control circuit 16 transmits the first phase clock signal to the first clock distribution network 11 and the second clock distribution network 12 simultaneously; at this time, the first clock distribution network 11 and the second clock distribution network 12 both transmit the first phase clock signal, which is used for phase calibration.

[0114] In the third scenario: when the operating frequency of the memory is lower than the preset frequency and it is in normal operating mode, the second mode control circuit 17 sends the first clock signal to the first adjustable delay line 141 and the second clock signal to the second adjustable delay line 142; the first adjustable delay line 141 delays the first clock signal based on the control code and outputs the first delayed clock signal; the second adjustable delay line 142 delays the second clock signal based on the control code and outputs the second delayed clock signal; the multiphase clock generation circuit 15 is disabled; the first mode control circuit 16 transmits the first delayed clock signal to the first clock distribution network 11 and the second delayed clock signal to the second clock distribution network 12; the first clock distribution network 11 and the second clock distribution network 12 respectively transmit the first delayed clock signal and the second delayed clock signal to the output port area for sampling processing of the data signal DQ.

[0115] The fourth scenario: When the operating frequency of the memory is less than the preset frequency and is in calibration mode, the second mode control circuit 17 sends the first clock signal to the first adjustable delay line 141 and the second adjustable delay line 142 simultaneously; the first adjustable delay line 141 and the second adjustable delay line 142 both perform delay processing on the first clock signal based on the control code, and output the first delayed clock signal and the second delayed clock signal respectively; the multiphase clock generation circuit 15 is disabled; the first mode control circuit 16 transmits the first delayed clock signal to the first clock distribution network 11 and the second delayed clock signal to the second clock distribution network 12; at this time, the signals transmitted in the first clock distribution network 11 and the second clock distribution network 12 are all derived from the first clock signal and are used for phase calibration.

[0116] As the above analysis shows, the settings of the first mode control circuit 16 and the second mode control circuit 17 under different conditions allow the memory to transmit clock signals of the same phase in the first clock distribution network 11 and the second clock distribution network 12, regardless of whether the frequency is high or low, during calibration mode. The delay of the second clock distribution network 12 is adjusted according to the phase difference between the transmitted signals, thus matching the delays of the first clock distribution network 11 and the second clock distribution network 12. In this way, when the memory is working normally, the deviation (skew) between the phase difference and the target value of the first target clock signal and the second target clock signal can be reduced, which is beneficial for data transmission. Furthermore, the calibration mode setting can shorten the test time. Simultaneously, during normal operation, only the first adjustable delay line 141 and the multi-phase clock generation circuit 15 are enabled to generate multi-phase clock signals, which reduces the clock transmission path, lowers circuit power consumption, reduces power supply noise, thereby reducing clock jitter and improving the quality of the clock signal.

[0117] Both the first-mode control circuit 16 and the second-mode control circuit 17 can be implemented using one or more multiplexers (Mux). The control logic between the input and output terminals of the multiplexers can be set according to Table 1 above and the analysis logic for several scenarios, which will not be elaborated here.

[0118] In some embodiments, the first adjustable delay line 141 and the second adjustable delay line 142 have the same circuit structure. In some embodiments, the first clock distribution network 11 and the second clock distribution network 12 have the same circuit structure. This can match the delays between different paths as much as possible, reduce the deviation (Skew) of the phase difference between the first target clock signal and the second target clock signal from the target value when the memory is working normally, and also help to shorten the calibration time in calibration mode.

[0119] In some embodiments, the first adjustable delay line 141 and the second adjustable delay line 142 both include a coarse delay line CDL, a fine delay line FDL, and a driver DRV.

[0120] The coarse-adjustment delay line (CDL) and the fine-adjustment delay line (FDL) receive control codes and adjust the delay time in response to the control codes. The adjustment step size of the coarse-adjustment delay line (CDL) is larger than that of the fine-adjustment delay line (FDL). The first adjustable delay line 141 and the second adjustable delay line 142 mainly rely on the coarse-adjustment delay line (CDL) and the fine-adjustment delay line (FDL) to adjust their own delay time. The driver (DRV) is generally located at the end of the first adjustable delay line 141 and the second adjustable delay line 142, and is used to enhance the driving capability of the output signal, which can improve the quality of the clock signal transmitted to subsequent circuits. The driver (DRV) can be constructed using an even number of inverters, and the size of the inverters can be set according to the length of the subsequent transmission path and the load size.

[0121] In some embodiments, the first adjustable delay line 141 and the second adjustable delay line 142 further include a duty cycle correction circuit DCC. Because the clock signal undergoes long-distance transmission, rising and falling edge offsets may occur, causing duty cycle distortion and phase shift. The duty cycle correction circuit DCC is used to adjust the duty cycle of the clock signal, making it as close to 50% as possible, which is beneficial for the accurate sampling of the subsequent data signal DQ.

[0122] In some embodiments, as shown in FIG3, the clock transmission circuit 10 further includes:

[0123] The replica clock distribution network 18 receives the first input clock signal, simulates the delay of the first clock distribution network, and outputs the replica target clock signal.

[0124] It is understandable that the replica clock distribution network 18 directly receives the first input clock signal output by the first mode control circuit 16 and simulates the delay of the first clock distribution network, rather than receiving the first delayed clock signal or the first phase clock signal. This eliminates the need to simulate the delay of the multi-phase clock generation circuit 15 and the first mode control circuit 16, thereby simplifying the circuit and saving circuit power consumption.

[0125] In some embodiments, as shown in FIG3, the delay phase-locked loop 14 further includes:

[0126] The delay simulation circuit 143 receives the target clock signal for replication and is used to simulate the delay of the clock input path and clock output path in the memory, and outputs a feedback clock signal; the clock input path includes a clock receiver and a frequency divider, and the clock output path includes an output driver circuit.

[0127] The first phase detector 144, electrically connected to the delay analog circuit 143, is configured to receive a feedback clock signal and a reference clock signal, and output a first indication signal based on the phase order of the two.

[0128] The control code generation circuit 145, electrically connected to the first phase detector 144, is configured to adjust and output a control code based on a first indication signal.

[0129] It should be noted that the delay simulation circuit 143 simulates the delay of the clock input path and clock output path within the memory, that is, it makes the delay of the delay simulation circuit 143 as similar as possible to the delay of the clock input path and clock output path, in order to reduce the phase error during DLL locking. The clock input path includes a clock receiver CLK IB that receives the initial clock signal CK_t and a frequency divider (Divider), and the clock output path includes an output driver circuit that outputs the data signal DQ and the data strobe signal DQS.

[0130] The first phase detector 144 receives a feedback clock signal and a reference clock signal. The reference clock signal can be the first clock signal or a signal with the same phase waveform as the first clock signal. The first phase detector 144 compares the phases of the reference clock signal and the feedback clock signal, and then controls the delay of the first adjustable delay line and the second adjustable delay line through the control code generation circuit 145. Under the action of the closed-loop feedback mechanism, the phase difference between the final reference clock signal and the feedback clock signal is approximately 0, and the DLL reaches the locked state. Ideally, when the DLL is locked, the rising edges of the reference clock signal and the feedback clock signal are aligned, and their phase difference is equal to 0. However, in practice, as long as the phase difference between the reference clock signal and the feedback clock signal is approximately 0 within the allowable error range, the DLL can be considered to have reached the locked state.

[0131] In some embodiments, the delay-locked loop (DLL) has completed phase locking before the memory enters calibration mode. In other words, calibration mode can only be entered and phase difference calibration performed after the DLL is locked. Otherwise, if DLL locking and calibration occur simultaneously, the delays of the first adjustable delay line 141, the second adjustable delay line 142, and the second clock distribution network 12 may be adjusted at the same time, which will interfere with each other, increase the locking time and calibration time, and may even lead to locking or calibration failure. Ensuring that the DLL is locked before the memory enters calibration mode helps to guarantee successful phase difference calibration and shorten the calibration time.

[0132] In some embodiments, as shown in FIG3, the phase calibration module 13 includes:

[0133] The second phase detector 131 receives the first target clock signal and the second target clock signal, and outputs a second indication signal based on the phase order of the two.

[0134] The first calibration code generation circuit 132, which is electrically connected to the second phase detector 131, is configured to adjust and output the first phase calibration code based on the second indication signal.

[0135] It should be noted that, in calibration mode, the second phase detector 131 receives the first target clock signal and the second target clock signal, compares their phase relationship, and outputs a second indication signal indicating whether the first target clock signal leads or lags the second target clock signal. If the first target clock signal leads the second target clock signal, the first phase calibration code output by the first calibration code generation circuit 132 can shorten the delay of the second clock distribution network 12; if the first target clock signal lags the second target clock signal, the first phase calibration code output by the first calibration code generation circuit 132 can prolong the delay of the second clock distribution network 12. Under the action of the closed-loop feedback mechanism, the calibration is considered complete when the phase difference between the first target clock signal and the second target clock signal is less than a preset threshold. It can be understood that the first phase calibration code can also adjust the delay of the first clock distribution network according to the phase relationship between the first target clock signal and the second target clock signal, as long as the phase difference is less than the preset threshold when the calibration is completed. Because in calibration mode, the first input clock signal and the second input clock signal received by the first clock distribution network 11 and the second clock distribution network 12 are in phase, the phase calibration module 13 performs the operation of detecting and aligning the first target clock signal and the second target clock signal. This is simpler and more accurate than adjusting the target value in normal working mode.

[0136] Referring to Figure 4, which shows the waveforms of the first target clock signal and the second target clock signal. In normal operating mode, before the memory is calibrated, the first clock distribution network 11 and the second clock distribution network 12 receive the first input clock signal and the second input clock signal, respectively, with a preset phase difference. After transmission, the phase difference between the output first target clock signal and the second target clock signal still deviates significantly from the target value, i.e., from the preset value. Upon entering calibration mode, the first input clock signal and the second input clock signal received by the first clock distribution network 11 and the second clock distribution network 12 are in phase. After transmission, the phase difference between the output first target clock signal and the second target clock signal remains at the aforementioned deviation value during the initial calibration phase. During calibration, the first phase calibration code adjusts the delay of the second clock distribution network. Ideally, when calibration is complete, the second target clock signal and the first target clock signal are aligned. In practice, calibration is considered complete as long as the phase difference between them is less than a preset threshold. After calibration, upon returning to normal operating mode, the deviation between the phase difference between the second target clock signal and the first target clock signal and the target value should also be less than the preset threshold.

[0137] In some embodiments, as shown in FIG3, the second clock distribution network 12 includes an adjustable delay module 19. The adjustable delay module 19 receives a first phase calibration code and adjusts its own delay in response to the first phase calibration code. It is understood that the second clock distribution network 12 primarily relies on the adjustable delay module to adjust its own delay. The first clock distribution network 11 may also include an adjustable delay module, with its delay set to a default value. In some examples, the first phase calibration code is used to adjust the delay of the adjustable delay module in the first clock distribution network, while the adjustable delay module in the second clock distribution network 12 is set to a default value.

[0138] In some embodiments, the adjustable delay module 19 includes a plurality of delay units (not shown in the figure), each delay unit being enabled or disabled in response to a single bit in the first phase calibration code. For example, the adjustable delay module 19 includes N delay units, where N is an integer greater than 1, and the delay of each delay unit is T. The first phase calibration code has N bits, each bit being used to control the enabling or disabling of one delay unit. When a delay unit is enabled, it means that the delay unit is connected to the second clock distribution network 12, and its delay T is included in the delay of the second clock distribution network 12. When a delay unit is disabled, it means that the delay unit is not connected to the second clock distribution network 12, it is short-circuited, and its delay T is not included in the delay of the second clock distribution network 12. If A delay units are enabled, where A is an integer greater than or equal to 0 and less than or equal to N, then the delay of the adjustable delay module is A*T. In some cases, the delay of multiple delay units can be set to gradient values ​​such as T, 2T, 4T, 8T, etc., which can expand the adjustable range of delay.

[0139] In some embodiments, the first calibration code generation circuit 132 includes a shift register (not shown in the figure), configured to receive a second indication signal, shift left or right according to the second indication signal, and output a first phase calibration code. For example, the first phase calibration code has 8 bits, with an initial value of 00001111. A value of 1 indicates that the delay unit is enabled, and a value of 0 indicates that the delay unit is disabled, so initially 4 delay units are enabled. If the first target clock signal leads the second target clock signal, the second indication signal output by the second phase detector indicates that the shift register shifts right, the most significant bit is padded with 0, the first phase calibration code becomes 00000111, controlling 3 delay units to be enabled, thus shortening the delay of the second clock distribution network 12; if the first target clock signal lags the second target clock signal, the second indication signal output by the second phase detector indicates that the shift register shifts left, the least significant bit is padded with 1, the first phase calibration code becomes 00011111, controlling 5 delay units to be enabled, thus extending the delay of the second clock distribution network 12. In some examples, the delay of the adjustable delay module in the first clock distribution network can be set to a default value, which is the midpoint of the adjustable range of the adjustable delay module. The first phase calibration code output by the shift register is used to adjust the delay of the adjustable delay module in the second clock distribution network. Alternatively, the delay of the adjustable delay module in the second clock distribution network can also be set to a default value, which is the midpoint of the adjustable range of the adjustable delay module. The first phase calibration code output by the shift register is used to adjust the delay of the adjustable delay module in the first clock distribution network. The number of bits in the shift register can be set in conjunction with the delay of the delay unit, according to requirements.

[0140] In some embodiments, the clock transmission circuit 10 further includes a register (not shown) configured to store a first phase calibration code after the calibration mode ends, and to send the first phase calibration code to the second clock distribution network 12 when the memory is in normal operating mode.

[0141] In some embodiments, the phase calibration module 13 stops working after the calibration mode ends.

[0142] After the calibration mode ends, the phase calibration module 13 sends the first phase calibration code to the register, which stores the first phase calibration code. In normal operation mode, the register sends the first phase calibration code. This ensures that in normal operation mode, the deviation between the phase difference of the second target clock signal and the first target clock signal and the target value is less than a preset threshold, and also allows the phase calibration module 13 to stop working, saving circuit power consumption.

[0143] In some embodiments, as shown in FIG5, the clock transmission circuit 10 further includes:

[0144] The third clock distribution network 24 is configured to receive the third input clock signal and transmit it to the output port area 31 of the memory (shown as DQ in Figure 5), and output the third target clock signal; when the memory is in normal operating mode, the phase difference between the third input clock signal and the second input clock signal is 90 degrees; when the memory is in calibration mode, the third input clock signal is in phase with the first input clock signal.

[0145] The fourth clock distribution network 26 is configured to receive the fourth input clock signal and transmit it to the output port area 31 of the memory to output the fourth target clock signal; when the memory is in normal operating mode, the phase difference between the fourth input clock signal and the third input clock signal is 90 degrees; when the memory is in calibration mode, the fourth input clock signal is in phase with the first input clock signal.

[0146] The phase calibration module 13 is further configured to, when the memory is in calibration mode, receive a third target clock signal and a fourth target clock signal, and output a second phase calibration code based on the phase difference between the third target clock signal and the first target clock signal; the second phase calibration code is used to adjust the delay of the third clock distribution network 24; output a third phase calibration code based on the phase difference between the fourth target clock signal and the first target clock signal; the third phase calibration code is used to adjust the delay of the fourth clock distribution network 26; when calibration is completed, the phase difference between the first target clock signal and the third target clock signal is less than a preset threshold, and the phase difference between the first target clock signal and the fourth target clock signal is less than a preset threshold.

[0147] Four Read Clock Distribution Networks (RD CLK CDNs), shown as 11, 12, 24, and 26 in Figure 5, respectively, receive the first, second, third, and fourth input clock signals in normal operation. These signals are 90 degrees out of phase with each other and are transmitted to the output port area of ​​the memory for sampling the data signal DQ. In calibration mode, the four clock distribution networks receive clock signals of the same phase. Based on the phase difference between the second and first target clock signals, a first phase calibration code is output to adjust the delay of the second clock distribution network 12; based on the phase difference between the third and first target clock signals, a second phase calibration code is output to adjust the delay of the third clock distribution network 24; and based on the phase difference between the fourth and first target clock signals, a third phase calibration code is output to adjust the delay of the fourth clock distribution network 26. Thus, when calibration is complete, the phase differences between the first, second, third, and fourth target clock signals should all be less than a preset threshold. When they return to normal operation, the phase difference between them should also be less than the preset threshold, even if the deviation from 90 degrees is less than the preset threshold.

[0148] In some embodiments, as shown in FIG5, the delay phase-locked loop 14 further includes:

[0149] The third adjustable delay line 146 is configured to receive a third clock signal CLKIB when the operating frequency of the memory is less than a preset frequency and in normal operating mode; receive a first clock signal CLKI when the operating frequency of the memory is less than a preset frequency and in calibration mode; perform delay processing on the received signal based on the control code and output a third delayed clock signal; and disable the third adjustable delay line 146 when the operating frequency of the memory is greater than or equal to the preset frequency.

[0150] The fourth adjustable delay line 147 is configured to receive the fourth clock signal CLKQB when the memory's operating frequency is less than the preset frequency and it is in normal operating mode; receive the first clock signal CLKI when the memory's operating frequency is less than the preset frequency and it is in calibration mode; perform delay processing on the received signal based on the control code and output the fourth delayed clock signal; and disable the fourth adjustable delay line 147 when the memory's operating frequency is greater than or equal to the preset frequency.

[0151] Among them, the phases of the first clock signal CLKI, the second clock signal CLKQ, the third clock signal CLKIB and the fourth clock signal CLKQB are 90 degrees apart.

[0152] When the operating frequency of the memory is greater than or equal to the preset frequency, the third adjustable delay line 146 and the fourth adjustable delay line 147 are disabled. The four-phase clock signal is generated by the first adjustable delay line 141 and the multi-phase clock generation circuit 15, which can reduce the clock transmission path, reduce circuit power consumption, reduce power supply noise, thereby reducing clock jitter and improving the quality of the clock signal.

[0153] When the memory's operating frequency is lower than the preset frequency and it is in normal operating mode, the first adjustable delay line 141, the second adjustable delay line 142, the third adjustable delay line 146, and the fourth adjustable delay line 147 respectively receive and transmit the first clock signal CLKI, the second clock signal CLKQ, the third clock signal CLKIB, and the fourth clock signal CLKQB. The multiphase clock generation circuit 15 is disabled, and the four adjustable delay lines transmit four clock signals with a phase difference of 90 degrees. When the memory's operating frequency is lower than the preset frequency and it is in calibration mode, the first adjustable delay line 141, the second adjustable delay line 142, the third adjustable delay line 146, and the fourth adjustable delay line 147 all receive and transmit the first clock signal CLKI for phase calibration.

[0154] Referring to Figure 5, the first adjustable delay line 141, the second adjustable delay line 142, the third adjustable delay line 146, and the fourth adjustable delay line 147 all have the same circuit structure, including a coarse adjustment delay line CDL and a fine adjustment delay line FDL. The duty cycle correction circuit DCC and the driver DRV can be located within the four adjustable delay lines or after the first mode control circuit 16. The figure shows an example where the DCC and DRV are placed after the first mode control circuit 16. In this way, in calibration mode, the clock signals received by the four DCCs are all in phase, and the phase deviation introduced by the DCC and DRV can also be corrected in calibration mode. The second adjustable delay line 142, the third adjustable delay line 146, and the fourth adjustable delay line 147 are indicated by dashed boxes to illustrate that they are disabled when the memory's operating frequency is greater than or equal to a preset frequency, and are only enabled when the memory's operating frequency is less than the preset frequency. The first adjustable delay line 141 is indicated by a solid box, signifying that it is enabled at any operating frequency. This reduces circuit power consumption during high-frequency memory operation, decreases power supply noise, and reduces clock signal jitter.

[0155] Referring again to Figure 5, the first clock distribution network 11, the second clock distribution network 12, the third clock distribution network 24, the fourth clock distribution network 26, and the replicated clock distribution network 18 all have the same circuit structure to reduce the delay deviation between different paths.

[0156] In some embodiments, the multiphase clock generating circuit 15 is further configured to generate a third phase clock signal and a fourth phase clock signal based on a first delayed clock signal, wherein the phases of the first phase clock signal, the second phase clock signal, the third phase clock signal and the fourth phase clock signal are sequentially 90 degrees apart.

[0157] The multi-phase clock generation circuit 15 can be an analog phase generator (APG). When the memory's operating frequency is greater than or equal to a preset frequency, it also generates a third-phase clock signal and a fourth-phase clock signal. The phases of the first-phase clock signal, the second-phase clock signal, the third-phase clock signal, and the fourth-phase clock signal are sequentially 90 degrees apart. Thus, when the memory is operating at high speed, it is only necessary to enable the first adjustable delay line 11 and the first clock distribution network 12 to transmit the first clock signal CLKI to the APG, and then generate the required four-phase clock signals for sampling the data signal DQ. This significantly saves circuit power consumption, reduces power supply noise, and consequently reduces clock jitter.

[0158] In some embodiments, the first mode control circuit (1) st The Mode Control 16 is also electrically connected to the third adjustable delay line 146 and the fourth adjustable delay line 147, and is configured to receive a third phase clock signal, a fourth phase clock signal, a third delayed clock signal, and a fourth delayed clock signal; when the operating frequency of the memory is greater than or equal to a preset frequency and is in normal operating mode, the third phase clock signal is transmitted as the third input clock signal to the third clock distribution network 24, and the fourth phase clock signal is transmitted as the fourth input clock signal to the fourth clock distribution network 26; when the operating frequency of the memory is greater than or equal to a preset frequency and is in calibration mode, the first phase clock signal is transmitted as both the third and fourth input clock signals to the third clock distribution network 24 and the fourth clock distribution network 26; when the operating frequency of the memory is less than a preset frequency, the third delayed clock signal is transmitted as the third input clock signal to the third clock distribution network 24, and the fourth delayed clock signal is transmitted as the fourth input clock signal to the fourth clock distribution network 26.

[0159] Second mode control circuit (2) ndThe Mode Control 17 is also electrically connected to the third adjustable delay line 146 and the fourth adjustable delay line 147, and is configured to send the third clock signal CLKIB to the third adjustable delay line 146 and the fourth clock signal CLKQB to the fourth adjustable delay line 147 when the operating frequency of the memory is less than the preset frequency and the memory is in normal operating mode; and to send the first clock signal CLKI to both the third adjustable delay line 146 and the fourth adjustable delay line 147 when the operating frequency of the memory is less than the preset frequency and the memory is in calibration mode.

[0160] The first mode control circuit 16 and the second mode control circuit 17 are configured in conjunction such that when the operating frequency of the memory is greater than or equal to a preset frequency, the first adjustable delay line 141 receives the first clock signal CLKI, the other three adjustable delay lines are disabled, and the multi-phase clock generation circuit APG generates four phase clock signals. In normal operation mode, the first mode control circuit 16 transmits the four phase clock signals to the four clock distribution networks respectively, and finally transmits them to the output port area 31 for sampling and processing of the data signal DQ. In calibration mode, the first mode control circuit 16 only transmits the first phase clock signal to the four clock distribution networks respectively for phase calibration. When the operating frequency of the memory is lower than the preset frequency and it is in normal operating mode, the first adjustable delay line 141, the second adjustable delay line 142, the third adjustable delay line 146, and the fourth adjustable delay line 147 receive CLKI, CLKQ, CLKIB, and CLKQB respectively, and transmit them to the four clock distribution networks, and finally to the output port area 31 for sampling processing of the data signal DQ; when the operating frequency of the memory is lower than the preset frequency and it is in calibration mode, the second mode control circuit 17 sends the first clock signal CLKI to the four adjustable delay lines simultaneously, and then transmits it to the four clock distribution networks for phase calibration.

[0161] As the above analysis shows, the settings of the first mode control circuit 16 and the second mode control circuit 17 under different conditions allow the memory to transmit clock signals of the same phase across the four clock distribution networks in calibration mode, regardless of whether the frequency is high or low. The delays of the second clock distribution network 12, the third clock distribution network 24, and the fourth clock distribution network 26 are adjusted based on the phase difference between the transmitted signals, thus matching the delays of the four clock distribution networks. In this way, when the memory is working normally, the phase difference between the first, second, third, and fourth target clock signals and the 90-degree deviation (skew) can be reduced, which is beneficial for data transmission. Furthermore, the calibration mode setting can shorten the test time. Simultaneously, during normal operation, only the first adjustable delay line 141 and the multi-phase clock generation circuit 15 are enabled to generate four-phase clock signals, reducing the clock transmission path, lowering circuit power consumption, reducing power supply noise, thereby reducing clock jitter and improving the quality of the clock signal.

[0162] In some embodiments, the clock frequencies of the first clock signal CLKI, the second clock signal CLKQ, the third clock signal CLKIB, and the fourth clock signal CLKQB are half the clock frequency of the initial clock signal CK_t received by the memory, wherein the clock frequency of the initial clock signal CK_t is equal to the operating frequency of the memory.

[0163] As shown in Figure 5, the clock receiver (Clock Input Buffer, CLK IB) 23 receives the initial clock signal CK_t, and then the frequency divider (Divider) 24 generates the first clock signal CLKI, the second clock signal CLKQ, the third clock signal CLKIB, and the fourth clock signal CLKQB, which are respectively sent to four adjustable delay lines for transmission.

[0164] In some embodiments, as shown in FIG5, the phase calibration module 13 further includes:

[0165] The third phase detector receives the first target clock signal and the third target clock signal, and outputs a third indication signal based on the phase order of the two.

[0166] The second calibration code generation circuit, which is electrically connected to the third phase detector, is configured to adjust and output the second phase calibration code based on the third indication signal.

[0167] The fourth phase detector receives the first target clock signal and the fourth target clock signal, and outputs a fourth indication signal based on the phase order of the two.

[0168] The third calibration code generation circuit, electrically connected to the fourth phase detector, is configured to adjust and output the third phase calibration code based on the fourth indication signal.

[0169] The diagram does not specifically show the third phase detector, fourth phase detector, second calibration code generation circuit, and third calibration code generation circuit. Their working principles are similar to those of the second phase detector and first calibration code generation circuit, and will not be elaborated here. However, the second phase calibration code output by the third phase detector and second calibration code generation circuit is used to calibrate the delay of the third clock distribution network 24, and the third phase calibration code output by the fourth phase detector and third calibration code generation circuit is used to calibrate the delay of the fourth clock distribution network 26. Thus, with three groups of circuits, each including a phase detector and calibration code generation circuit, a total of three sets of phase calibration codes are output to adjust the delays of the second clock distribution network 12, the third clock distribution network 24, and the fourth clock distribution network 26, respectively. The advantage of this is that four clock distribution networks can be calibrated simultaneously, that is, the first target clock signal and the second target clock signal, the first target clock signal and the third target clock signal, and the first target clock signal and the fourth target clock signal can be calibrated simultaneously, saving calibration time.

[0170] In some examples, the third and fourth phase detectors, the second calibration code generation circuit, and the third calibration code generation circuit may not be necessary. Only the second phase detector and the first calibration code generation circuit are used to sequentially calibrate the second clock distribution network 12, the third clock distribution network 24, and the fourth clock distribution network 26. This approach saves circuit area, but it takes longer to calibrate all phase clock signals. Furthermore, multiplexers need to be added to the input of the second phase detector and the output of the first calibration code generation circuit to select which of the three target clock signals (second, third, and fourth) to receive into the phase detector, and to select the first phase calibration code to adjust the delay of one of the three clock distribution networks (second, third, and fourth).

[0171] In some examples, each clock distribution network (RD CLK CDN) includes its own adjustable delay module (Trim Cell) to receive the corresponding phase calibration code to adjust its own delay. Each clock distribution network's adjustable delay module has the same circuit structure, for example, it includes N delay units, but the number of delay units activated for calibration may differ depending on the phase calibration code. When not calibrated, the delay of each clock distribution network's adjustable delay module can be set to a default value, which is the midpoint of the adjustable range of the adjustable delay module.

[0172] In summary, the clock transmission circuit provided in this embodiment, in calibration mode, transmits clock signals of the same phase between the first clock distribution network and the second clock distribution network. The delay of the second clock distribution network is adjusted based on the phase difference between the transmitted signals, thus matching the delays of the first and second clock distribution networks. Therefore, when the memory is operating normally, the deviation (Skew) between the phase difference between the first and second target clock signals and the target value can be reduced, which is beneficial for data transmission. Furthermore, the calibration mode setting can shorten the test time.

[0173] In another embodiment of this disclosure, referring to FIG7, a schematic diagram of the composition structure of a memory 30 provided in an embodiment of this disclosure is shown. As shown in FIG7, the memory 30 includes at least the aforementioned clock transmission circuit 10.

[0174] In some embodiments, the memory conforms to at least one of the following specifications: DDR3, DDR4, DDR5, DDR6, LPDDR3, LPDDR4, LPDDR5, LPDDR6.

[0175] The memory includes a clock transmission circuit 10. In memory calibration mode, the first clock distribution network and the second clock distribution network transmit clock signals with the same phase. The delay of the second clock distribution network is adjusted according to the phase difference between the transmitted signals, thus matching the delays of the first and second clock distribution networks. Therefore, when the memory is working normally, the deviation (Skew) between the phase difference between the first and second target clock signals and the target value can be reduced, which is beneficial for data transmission. Furthermore, the calibration mode setting can shorten the test time. This allows for accurate generation of the data strobe signal DQS and more accurate sampling processing of the data signal DQ, improving the signal quality of the DQS and DQ output from the memory.

[0176] In another embodiment of this disclosure, referring to FIG6, a flowchart of a phase calibration method provided by an embodiment of this disclosure is shown. As shown in FIG6, the method is applied to a memory and may include:

[0177] S101. Input a first input clock signal to a first clock distribution network and transmit it to the output port area of ​​the memory to output a first target clock signal; input a second input clock signal to a second clock distribution network and transmit it to the output port area of ​​the memory to output a second target clock signal.

[0178] S102. When the memory is in calibration mode, control the second input clock signal to be in phase with the first input clock signal;

[0179] S103. Receive the first target clock signal and the second target clock signal, and output the first phase calibration code based on the phase difference between the two.

[0180] S104. Adjust the delay of the second clock distribution network according to the first phase calibration code; when the calibration is completed, the phase difference between the first target clock signal and the second target clock signal is less than a preset threshold.

[0181] This phase calibration method ensures that the first and second clock distribution networks transmit clock signals of the same phase. The delay of the second clock distribution network is adjusted based on the phase difference between the transmitted signals, thus matching the delays of the first and second clock distribution networks. Therefore, when the memory is operating normally, the deviation (Skew) between the phase difference and the target value of the first and second target clock signals can be reduced, which is beneficial for data transmission. Furthermore, this phase calibration method, which detects and aligns the first and second target clock signals, is simpler and more accurate than adjusting the target value during normal operation, and can also shorten testing time.

[0182] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A clock transmission circuit, characterized in that, Applied to memory, including: The first clock distribution network (11) is configured to receive a first input clock signal and transmit it to the output port area of ​​the memory, and output a first target clock signal; The second clock distribution network (12) is configured to receive a second input clock signal and transmit it to the output port area of ​​the memory to output a second target clock signal; when the memory is in normal working mode, the phase difference between the second input clock signal and the first input clock signal is a preset value; when the memory is in calibration mode, the second input clock signal is in phase with the first input clock signal. The phase calibration module (13) is configured to receive the first target clock signal and the second target clock signal when the memory is in calibration mode, and output a first phase calibration code based on the phase difference between the two; the first phase calibration code is used to adjust the delay of the second clock distribution network; when calibration is completed, the phase difference between the first target clock signal and the second target clock signal is less than a preset threshold.

2. The clock transmission circuit according to claim 1, characterized in that, Also includes: A delay phase-locked loop (14) includes at least a first adjustable delay line (141), which receives a first clock signal and a control code, performs delay processing on the first clock signal based on the control code, and outputs a first delayed clock signal. A multiphase clock generation circuit (15), electrically connected to the first adjustable delay line, is configured to receive the first delayed clock signal when the operating frequency of the memory is greater than or equal to a preset frequency, and generate at least a first phase clock signal and a second phase clock signal based on the first delayed clock signal, wherein the first phase clock signal and the first delayed clock signal are in phase, and the phase difference between the second phase clock signal and the first phase clock signal is the preset value; when the operating frequency of the memory is less than the preset frequency, the multiphase clock generation circuit is disabled.

3. The clock transmission circuit according to claim 2, characterized in that, Also includes: The first mode control circuit (16) is electrically connected to the multiphase clock generation circuit, the first clock distribution network and the second clock distribution network, and is configured to receive the first phase clock signal and the second phase clock signal. When the operating frequency of the memory is greater than or equal to a preset frequency and is in normal operating mode, the first phase clock signal is transmitted to the first clock distribution network as the first input clock signal, and the second phase clock signal is transmitted to the second clock distribution network as the second input clock signal; when the operating frequency of the memory is greater than or equal to a preset frequency and is in calibration mode, the first phase clock signal is transmitted to both the first clock distribution network and the second clock distribution network as both the first input clock signal and the second input clock signal.

4. The clock transmission circuit according to claim 3, characterized in that, The delay phase-locked loop further includes a second adjustable delay line (142); the second adjustable delay line is configured to receive a second clock signal when the operating frequency of the memory is less than a preset frequency and in normal operating mode; and to receive the first clock signal when the operating frequency of the memory is less than the preset frequency and in calibration mode. The received signal is delayed based on the control code, and a second delayed clock signal is output; when the operating frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line is disabled.

5. The clock transmission circuit according to claim 4, characterized in that, The first mode control circuit is also electrically connected to the second adjustable delay line to receive the second delayed clock signal; when the operating frequency of the memory is less than the preset frequency, the first delayed clock signal is transmitted to the first clock distribution network as the first input clock signal, and the second delayed clock signal is transmitted to the second clock distribution network as the second input clock signal.

6. The clock transmission circuit according to claim 5, characterized in that, Also includes: The second mode control circuit (17), electrically connected to the first adjustable delay line and the second adjustable delay line, is configured to: when the operating frequency of the memory is less than a preset frequency and is in normal operating mode, send the first clock signal to the first adjustable delay line and send the second clock signal to the second adjustable delay line; when the operating frequency of the memory is less than the preset frequency and is in calibration mode, send the first clock signal to both the first adjustable delay line and the second adjustable delay line; when the operating frequency of the memory is greater than or equal to the preset frequency, send the first clock signal to the first adjustable delay line.

7. The clock transmission circuit according to claim 4, characterized in that, The first adjustable delay line and the second adjustable delay line have the same circuit structure.

8. The clock transmission circuit according to claim 2, characterized in that, It also includes a replica clock distribution network (18), which receives the first input clock signal, simulates the delay of the first clock distribution network, and outputs a replica target clock signal.

9. The clock transmission circuit according to claim 8, characterized in that, The delay phase-locked loop also includes: The delay simulation circuit (143) receives the target clock signal for replication and is used to simulate the delay of the clock input path and clock output path in the memory, and outputs a feedback clock signal; the clock input path includes a clock receiver and a frequency divider, and the clock output path includes an output driver circuit; The first phase detector (144), electrically connected to the delay analog circuit, is configured to receive the feedback clock signal and the reference clock signal, and output a first indication signal based on the phase order of the two. A control code generation circuit (145), electrically connected to the first phase detector, is configured to adjust and output the control code based on the first indication signal.

10. The clock transmission circuit according to claim 2, characterized in that, The delay-locked loop has completed phase locking before the memory enters the calibration mode.

11. The clock transmission circuit according to claim 1, characterized in that, The phase calibration module includes: The second phase detector (131) receives the first target clock signal and the second target clock signal, and outputs a second indication signal based on the phase order of the two; The first calibration code generation circuit (132), electrically connected to the second phase detector, is configured to adjust and output the first phase calibration code based on the second indication signal.

12. The clock transmission circuit according to claim 11, characterized in that, The second clock distribution network includes an adjustable delay module, which receives the first phase calibration code and adjusts its own delay in response to the first phase calibration code.

13. The clock transmission circuit according to claim 12, characterized in that, The adjustable delay module includes multiple delay units, each of which is turned on or off in response to a bit in the first phase calibration code.

14. The clock transmission circuit according to claim 13, characterized in that, The first calibration code generation circuit includes a shift register configured to receive the second indication signal, shift left or right according to the second indication signal, and output the first phase calibration code.

15. The clock transmission circuit according to claim 1, characterized in that, Also includes: The register is configured to store the first phase calibration code after the calibration mode ends; When the memory is in normal operating mode, the first phase calibration code is sent to the second clock distribution network.

16. The clock transmission circuit according to claim 1, characterized in that, The phase calibration module stops working after the calibration mode ends.

17. The clock transmission circuit according to claim 6, characterized in that, Also includes: The third clock distribution network is configured to receive a third input clock signal and transmit it to the output port area of ​​the memory, and output a third target clock signal. When the memory is in normal operating mode, the phase difference between the third input clock signal and the second input clock signal is 90 degrees; when the memory is in calibration mode, the third input clock signal is in phase with the first input clock signal. The fourth clock distribution network is configured to receive a fourth input clock signal and transmit it to the output port area of ​​the memory, and output a fourth target clock signal; When the memory is in normal operating mode, the phase difference between the fourth input clock signal and the third input clock signal is 90 degrees; when the memory is in calibration mode, the fourth input clock signal is in phase with the first input clock signal. The phase calibration module is further configured to, when the memory is in calibration mode, receive the third target clock signal and the fourth target clock signal, and output a second phase calibration code based on the phase difference between the third target clock signal and the first target clock signal; The second phase calibration code is used to adjust the delay of the third clock distribution network; Based on the phase difference between the fourth target clock signal and the first target clock signal, a third phase calibration code is output; The third phase calibration code is used to adjust the delay of the fourth clock distribution network; when the calibration is completed, the phase difference between the first target clock signal and the third target clock signal is less than a preset threshold, and the phase difference between the first target clock signal and the fourth target clock signal is less than a preset threshold.

18. The clock transmission circuit according to claim 17, characterized in that, The delay phase-locked loop also includes: The third adjustable delay line is configured to receive a third clock signal when the operating frequency of the memory is less than a preset frequency and in normal operating mode; receive a first clock signal when the operating frequency of the memory is less than the preset frequency and in calibration mode; perform delay processing on the received signal based on the control code and output a third delayed clock signal; and disable the third adjustable delay line when the operating frequency of the memory is greater than or equal to the preset frequency. The fourth adjustable delay line is configured to receive a fourth clock signal when the operating frequency of the memory is less than a preset frequency and in normal operating mode; receive the first clock signal when the operating frequency of the memory is less than the preset frequency and in calibration mode; perform delay processing on the received signal based on the control code and output a fourth delayed clock signal; and disable the fourth adjustable delay line when the operating frequency of the memory is greater than or equal to the preset frequency. The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially 90 degrees apart in phase.

19. The clock transmission circuit according to claim 18, characterized in that, The multiphase clock generating circuit is further configured to generate a third phase clock signal and a fourth phase clock signal based on the first delayed clock signal, wherein the phases of the first phase clock signal, the second phase clock signal, the third phase clock signal and the fourth phase clock signal are sequentially 90 degrees apart; The first mode control circuit is also electrically connected to the third adjustable delay line and the fourth adjustable delay line, and is configured to receive the third phase clock signal, the fourth phase clock signal, the third delay clock signal, and the fourth delay clock signal; when the operating frequency of the memory is greater than or equal to a preset frequency and is in normal operating mode, the third phase clock signal is transmitted to the third clock distribution network as the third input clock signal, and the fourth phase clock signal is transmitted to the fourth clock distribution network as the fourth input clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency and is in calibration mode, the first phase clock signal is transmitted to both the third and fourth input clock signals to the third and fourth clock distribution networks simultaneously; when the operating frequency of the memory is less than the preset frequency, the third delay clock signal is transmitted to the third clock distribution network as the third input clock signal, and the fourth delay clock signal is transmitted to the fourth clock distribution network as the fourth input clock signal. The second mode control circuit is also electrically connected to the third adjustable delay line and the fourth adjustable delay line, and is configured to send the third clock signal to the third adjustable delay line and the fourth clock signal to the fourth adjustable delay line when the operating frequency of the memory is less than the preset frequency and the memory is in normal operating mode; and to send the first clock signal to both the third adjustable delay line and the fourth adjustable delay line simultaneously when the operating frequency of the memory is less than the preset frequency and the memory is in calibration mode.

20. The clock transmission circuit according to claim 18, characterized in that, The clock frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are half the clock frequency of the initial clock signal received by the memory, wherein the clock frequency of the initial clock signal is equal to the operating frequency of the memory.

21. The clock transmission circuit according to claim 17, characterized in that, The phase calibration module includes: The third phase detector receives the first target clock signal and the third target clock signal, and outputs a third indication signal based on the phase order of the two. The second calibration code generation circuit, which is electrically connected to the third phase detector, is configured to adjust and output the second phase calibration code based on the third indication signal. The fourth phase detector receives the first target clock signal and the fourth target clock signal, and outputs a fourth indication signal based on the phase order of the two. The third calibration code generation circuit, electrically connected to the fourth phase detector, is configured to adjust and output the third phase calibration code based on the fourth indication signal.

22. A phase calibration method, characterized in that, Applied to memory, including: A first input clock signal is input to a first clock distribution network and transmitted to the output port area of ​​the memory to output a first target clock signal. A second input clock signal is input to a second clock distribution network and transmitted to the output port area of ​​the memory to output a second target clock signal. When the memory is in calibration mode, the second input clock signal is controlled to be in phase with the first input clock signal; Receive the first target clock signal and the second target clock signal, and output the first phase calibration code based on the phase difference between them; The delay of the second clock distribution network is adjusted according to the first phase calibration code; when the calibration is completed, the phase difference between the first target clock signal and the second target clock signal is less than a preset threshold.

23. A memory, characterized in that, Includes the clock transmission circuit as described in any one of claims 1-21.

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