Solar cell and cell assembly

Abstract

The present disclosure is applicable to the technical field of photovoltaics. Provided are a solar cell and a cell assembly. The solar cell comprises: a plurality of first doped regions and second doped regions, which are alternately distributed in a first direction; and a plurality of mark points, wherein some of the plurality of mark points are arranged in the first doped regions, and others are arranged in the second doped regions. The present disclosure avoids the problem of a mask at a mark point location being prone to experiencing damage.

Description

Solar cells and battery modules

[0001] Cross-referencing

[0002] This disclosure incorporates, in its entirety, Chinese Patent Publication No. 202411217039.9, filed on August 30, 2024, entitled “A Solar Cell and Photovoltaic Module,” and Chinese Patent Publication No. 202411217218.2, filed on August 30, 2024, entitled “A Solar Cell and a Battery Module,” which are incorporated herein by reference. Technical Field

[0003] This disclosure pertains to the field of photovoltaic technology, and particularly relates to a solar cell and a battery module. Background Technology

[0004] In the related technology, during the manufacturing of back-contact batteries, electrodes are formed through screen printing after various processing steps. The screen consists of warp and weft threads that intersect perpendicularly. To avoid printing defects at the junctions of warp and weft threads, the weft threads of the p-area or n-area pattern are removed during the screen printing process to better complete the grid line printing. Usually, the grid lines in the p-area or n-area and the mark points are printed in the same process step. In this synchronous printing process, the warp threads at the mark point positions are prone to breakage during repeated printing. Due to the lack of warp support, the mask at the mark point positions is quickly damaged during repeated scraping with the squeegee, the mark point gradually expands, resulting in ink leakage, and ultimately causing the screen to become damaged and unusable.

[0005] Public content

[0006] This disclosure provides a solar cell designed to solve the problem that existing mark points suffer rapid mask damage during repeated scraping with a squeegee, leading to the gradual expansion of the mark points, resulting in paste leakage and ultimately causing the stencil to become damaged and unusable.

[0007] This disclosure is implemented as follows: a solar cell includes a silicon substrate, the silicon substrate including a plurality of first doped regions and second doped regions that are staggered along a first direction; the first doped regions and the second doped regions extend along a second direction and intersect the first direction and the second direction; a first grid line is disposed in the first doped region and a second grid line is disposed in the second doped region; a plurality of mark points, a portion of the plurality of mark points being disposed in the first doped region and another portion of the plurality of mark points being disposed in the second doped region.

[0008] In some implementations, at least a portion of the multiple mark points are disposed between the first and second grid lines.

[0009] In some implementations, a portion of the multiple mark points is located below the first grid line, and another portion of the multiple mark points is located above the second grid line.

[0010] In some embodiments, the silicon substrate has a first central axis in a first direction and a second central axis in a second direction. The intersection of the first and second central axes divides the silicon substrate into a first region, a second region, a third region, and a fourth region. The plurality of mark points include at least a first mark point disposed in the first region, a second mark point disposed in the second region, a third mark point disposed in the third region, and a fourth mark point disposed in the fourth region. The first mark point, the second mark point, the third mark point, and the fourth mark point are connected sequentially to form a rectangle, and the center point of the rectangle is a positioning base point.

[0011] In some implementations, within the first doped region, the mark point has a first size along a first direction, the first size being greater than the width of the first gate line and less than the width of the first doped region.

[0012] In some implementations, the ratio of the first dimension to the width of the first doped region is greater than 1 / 5 and less than or equal to 1 / 3.

[0013] In some embodiments, within the second doped region, the mark point has a second size along a first direction, the second size being larger than the width of the second gate line and smaller than the width of the second doped region.

[0014] In some implementations, the ratio of the second dimension to the width of the second doped region is greater than 1 / 5 and less than or equal to 1 / 3.

[0015] In some embodiments, the silicon substrate further includes an isolation region disposed between the first doped region and the second doped region, and a plurality of mark points are disposed at least partially in the isolation region.

[0016] In some implementations, within the isolation zone, the mark point has a third dimension along a first direction, the third dimension being smaller than the width of the isolation zone.

[0017] In some implementations, the ratio of the third dimension to the width of the isolation zone is greater than or equal to 1 / 3 and less than 1.

[0018] In some embodiments, a plurality of first doped regions and a plurality of second doped regions are arranged alternately in parallel along a first direction, and a plurality of first gate lines and a plurality of second gate lines are arranged alternately in parallel along a first direction.

[0019] In some embodiments, the first gate line is disposed at the center of the first doped region, and the second gate line is disposed at the center of the second doped region.

[0020] In some embodiments, the ratio of the width of the first gate line to the width of the first doped region is greater than 1 / 10 and less than or equal to 1 / 5, and the ratio of the width of the second gate line to the width of the second doped region is greater than 1 / 10 and less than or equal to 1 / 5.

[0021] In some embodiments, each of the first gate line, the second gate line, and the mark point includes a glass paste component, wherein the mass percentage of the glass paste component in the first gate line is the same as the mass percentage of the glass paste component in the mark point of the second doped region, and the mass percentage of the glass paste component in the second gate line is the same as the mass percentage of the glass paste component in the mark point of the first doped region.

[0022] In some embodiments, the mass percentage of the glass paste component in the first grid line is different from the mass percentage of the glass paste component in the second grid line.

[0023] In some embodiments, the first grid line is a P-type grid line, and the second grid line is an N-type grid line, wherein the mass percentage of the glass paste component in the first grid line is greater than the mass percentage of the glass paste component in the second grid line. A portion of the plurality of mark points is disposed above the first grid line, and another portion of the plurality of mark points is disposed below the second grid line.

[0024] In some embodiments, the first doped region includes a first doped layer, the second doped region includes a second doped layer, a first gate line is disposed on the first doped layer and forms an ohmic contact with the first doped layer, and a second gate line is disposed on the second doped layer and forms an ohmic contact with the second doped layer.

[0025] In some embodiments, a portion of the plurality of mark points is disposed on a first doped layer and isolated from the silicon substrate, and another portion of the plurality of mark points is disposed on a second doped layer and isolated from the silicon substrate.

[0026] In some embodiments, a first passivation layer disposed on the first doped layer and a second passivation layer disposed on the second doped layer are also included, with a portion of the first gate line passing through the first passivation layer and contacting the first doped layer, and a portion of the second gate line passing through the second passivation layer and contacting the second doped layer.

[0027] In some embodiments, a portion of the multiple mark points are disposed on the first passivation layer, a portion of the multiple mark points penetrate the first passivation layer and contact the first doped layer, and another portion of the multiple mark points are disposed on the second passivation layer, and another portion of the multiple mark points penetrate the second passivation layer and contact the second doped layer.

[0028] This disclosure allows for the placement of a portion of multiple mark points in a first doped region and another portion in a second doped region. This enables the mark points to be placed in the second doped region during the printing of the first gate line and in the first doped region during the printing of the second gate line. The mark points and gate lines are printed in separate steps, avoiding the problem of easy damage to the mask at the mark point locations and improving the reliability of the stencil.

[0029] A battery assembly includes the aforementioned solar cell. The technical effects of this disclosure are the same as those of the aforementioned solar cell, and will not be repeated here. Attached Figure Description

[0030] Figure 1 is a front view of the structure of a solar cell currently publicly available;

[0031] Figure 2 is a schematic diagram of the structure of a solar cell currently publicly available.

[0032] Figure 3 is an enlarged schematic diagram of the structure at point A in Figure 2;

[0033] Figure 4 is a second enlarged schematic diagram of the structure at point A in Figure 2;

[0034] Figure 5 is a schematic diagram of the mark point distribution structure of the solar cell currently available.

[0035] Figure 6 is a schematic diagram of the mark point distribution structure of the solar cell currently available.

[0036] Figure 7 is a schematic diagram of the mark point distribution structure of the solar cell currently available.

[0037] Figure 8 is a schematic diagram of the mark point distribution structure of the solar cells currently available.

[0038] Figure 9 is a schematic diagram of the mark point distribution structure of the solar cells currently available.

[0039] Figure 10 is a side view of the structure of a solar cell that is currently publicly available.

[0040] Explanation of reference numerals in the attached figures: 10, silicon substrate; 20, first gate line; 30, second gate line; 40, mark point; 50, first doped region; 60, second doped region; 70, isolation region; 80, first doped layer; 90, second doped layer; 100, first passivation layer; 110, second passivation layer. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this disclosure and are not intended to limit this disclosure.

[0042] In the description of this disclosure, it should be understood that the terms “length”, “width”, “upper”, “lower”, “left”, “right”, “horizontal”, “top”, “bottom”, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0044] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0045] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0046] The following disclosure provides numerous different embodiments or examples for implementing various structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this disclosure. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this disclosure, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0047] In this embodiment of the disclosure, as shown in Figures 1 to 3, a solar cell includes a silicon substrate 10. The silicon substrate 10 can be a P-type silicon substrate 10 or an N-type silicon substrate 10; the silicon substrate 10 can be monocrystalline silicon or polycrystalline silicon. The specific type of the silicon substrate 10 is not limited here. The silicon substrate 10 includes a plurality of first doped regions 50 and second doped regions 60 staggered along a first direction. In some embodiments, the first and second regions may have the same shape and size. For example, both the first and second regions are rectangular, and their lengths and widths are the same. It is understood that in other embodiments, the first and second regions may have different shapes and sizes. The staggered distribution of the plurality of first doped regions 50 and the plurality of second doped regions 60 in the first direction means that a second region is formed between two adjacent first regions in the first direction, and a first region is formed between two adjacent second regions. The first doped regions 50 and the second doped regions 60 extend along a second direction, and the first and second directions intersect. In this embodiment of the disclosure, the second direction intersects the first direction. Specifically, the second direction may be perpendicular to the first direction. For example, the first direction can be the length direction of the silicon substrate 10, and the second direction can be the width direction of the silicon substrate 10.

[0048] For example, the doped region can be formed by methods such as ion implantation, diffusion, or vapor deposition, introducing impurity atoms (such as phosphorus, boron, etc.) into a specific region of the silicon substrate 10 to form a doped source region. These impurity atoms will change the conductivity of the silicon substrate 10, thereby forming a first doped region 50 or a second doped region 60.

[0049] In some embodiments, a first gate line 20 is disposed in the first doped region 50, and a second gate line 30 is disposed in the second doped region 60. The first gate line 20 and the first doped region 50 have the same polarity. In other words, the first gate line 20 is a P-type fine gate, and the first doped region 50 is a P-type doped region; or the first gate line 20 is an N-type fine gate, and the first doped region 50 is an N-type doped region. The second gate line 30 and the second doped region 60 have the same polarity. In other words, the second gate line 30 is a P-type fine gate, and the second doped region 60 is a P-type doped region; or the second gate line 30 is an N-type fine gate, and the second doped region 60 is an N-type doped region. Alternatively, screen printing can be used to dispose of the first gate line 20 in the first doped region 50 and the second gate line 30 in the second doped region 60. The printing of the first gate line 20 and the second gate line 30 can be performed sequentially or alternately. This disclosure does not limit the comparison order, thus allowing for more accurate positioning of the first gate line 20 and the second gate line 30, resulting in higher efficiency in setting the first gate line 20 and the second gate line 30. It is understood that in other embodiments, a coating process can also be used to set the first gate line 20 in the first doped region 50 and the second gate line 30 in the second doped region 60; this disclosure does not impose any limitations on this.

[0050] In some embodiments, a plurality of first doped regions 50 and a plurality of second doped regions 60 are alternately arranged in parallel along a first direction, and a plurality of first gate lines 20 and a plurality of second gate lines 30 are alternately arranged in parallel along the first direction. The alternating arrangement of the first doped regions 50 and the second doped regions 60 helps to more effectively collect and separate photogenerated carriers, while the alternating arrangement of the first gate lines 20 and the second gate lines 30 optimizes the current transmission path, reduces resistance loss, improves current collection efficiency, and helps to achieve a uniform current distribution on the cell, reducing the risk of localized overheating or performance degradation. In some embodiments, the alternating arrangement of doped regions and gate lines helps to form a more stable cell structure, reducing performance degradation caused by material mismatch or stress concentration.

[0051] In this embodiment, the first gate line 20 is disposed at the center of the first doped region 50, and the second gate line 30 is disposed at the center of the second doped region 60. The gate lines being located at the center of the doped region allows for more efficient collection of photogenerated carriers generated by the doped region. This arrangement ensures that carriers can be rapidly and directly transported through the gate lines to the two electrodes of the battery, reducing recombination losses during transport. Because the gate lines are precisely placed at the center of the doped region, this arrangement minimizes the obstruction of incident light by the gate lines. Compared to arrangements where the gate lines are off-center from the doped region, this design can capture more photons and convert them into electrical energy, thereby improving photoelectric conversion efficiency.

[0052] In some embodiments, the ratio of the width of the first gate line 20 to the width of the first doped region 50 is greater than 1 / 10 and less than or equal to 1 / 5, and the ratio of the width of the second gate line 30 to the width of the second doped region 60 is greater than 1 / 10 and less than or equal to 1 / 5. In some embodiments, the ratio of the width of the first gate line 20 to the width of the first doped region 50 is greater than or equal to 1 / 8 and less than or equal to 1 / 6, and the ratio of the width of the second gate line 30 to the width of the second doped region 60 is greater than or equal to 1 / 8 and less than or equal to 1 / 6. In embodiments of this disclosure, an appropriate increase in the gate line width helps to more effectively collect photogenerated carriers generated by the doped region. When the ratio of the gate line width to the doped region width is within the above range, sufficient contact area between the gate line and the doped region can be ensured, thereby reducing recombination losses of carriers during transport. Although the gate line blocks some incident light, an appropriate ratio of the gate line width to the doped region width can balance the relationship between light blocking losses and current collection. Too narrow a grid line may result in insufficient current collection, while too wide a grid line will increase shading losses. Within the above ratio range, a balance can be found that minimizes shading losses while ensuring sufficient current collection.

[0053] In some embodiments, as shown in Figures 1 to 9, a solar cell includes a plurality of mark points 40, a portion of which is disposed in a first doped region 50, and another portion of which is disposed in a second doped region 60. The mark points 40 serve as positioning references, and automatic identification of the mark points 40 using technologies such as machine vision can ensure high-precision alignment in subsequent manufacturing processes (such as printing, coating, etc.).

[0054] This disclosure, by setting a portion of multiple mark points 40 in the first doped region 50 and another portion of multiple mark points 40 in the second doped region 60, allows mark points 40 to be set in the second doped region 60 when printing the first gate line 20, and in the first doped region 50 when printing the second gate line 30. In other words, the stencil prints mark points 40 in the second doped region 60 simultaneously when printing the first gate line 20, and mark points 40 in the first doped region 50 simultaneously when printing the second gate line 30. Compared to previous methods where the stencil simultaneously prints mark points 40 in both the first gate line 20 and the first doped region 50, or simultaneously prints mark points 40 in both the second gate line 30 and the second doped region 60, this method achieves staggered, step-by-step printing of the gate lines and mark points 40 in the same region. This avoids the problem of easy damage to the mask at the mark point 40 position in the same region of the printed gate lines, improving the reliability of the stencil.

[0055] As shown in Figures 2 and 3, in some embodiments, the silicon substrate 10 has a first central axis L1 in a first direction and a second central axis L2 in a second direction. The intersection of the first central axis L1 and the second central axis L2 divides the silicon substrate 10 into a first region, a second region, a third region, and a fourth region. It is understood that the first, second, third, and fourth regions are of the same size and occupy the four corners of the silicon substrate 10, respectively. The plurality of mark points 40 includes at least a first mark point in the first region, a second mark point in the second region, a third mark point in the third region, and a fourth mark point in the fourth region. The first, second, third, and fourth mark points are sequentially connected to form a rectangle, with the center point of the rectangle serving as the positioning base point. Specifically, the number of mark points 40 can be four, six, or eight. For example, the four mark points 40 are distributed in a rectangle, with the sides of the rectangle parallel to the edge of the silicon wafer. This distribution significantly simplifies the calculation of printing position offset while ensuring printing alignment accuracy. In this embodiment, the screen printing position coordinate information includes, but is not limited to, the coordinate information of the four mark points 40 after alignment. Specifically, the positioning system is activated to scan the solar cell in the laser device to obtain a scanned image; the scanned image obtained by the positioning system is transmitted to the image processing unit to identify the mark points 40 on the surface of the cell, and the positioning base point is calculated based on the identified mark points 40. The positioning deviation from the center point of the silicon substrate 10 is calculated based on the positioning base point; based on the positioning deviation and the size parameters of the silicon substrate 10, the adaptive spot control system automatically adjusts the position of the laser working head to the initial position and sets the initial laser spot size and shape.

[0056] As shown in Figures 4 to 7, in some embodiments, at least a portion of the plurality of mark points 40 are disposed between the first gate line 20 and the second gate line 30. That is, a portion of the plurality of mark points 40 are disposed within the first doped region 50 or the second doped region 60, with some mark points 40 not contacting the first gate line 20 of the first doped region 50, and some mark points 40 not contacting the second gate line 30 of the second doped region 60; some mark points 40 are disposed between the gate lines. Of course, in other embodiments, some mark points 40 may be disposed between the gate lines, while other mark points 40 may be disposed on the gate lines. The placement of the mark points 40 can be flexibly arranged, and this disclosure does not impose any limitations on this arrangement.

[0057] As shown in Figures 8 and 9, in some embodiments, a portion of the plurality of mark points 40 are disposed below the first gate line 20, and another portion of the plurality of mark points 40 are disposed above the second gate line 30. In this embodiment of the present disclosure, all mark points 40 are disposed on the gate line, with a portion of mark points 40 disposed below the first gate line 20 and another portion of mark points 40 disposed above the second gate line 30; in other embodiments, a portion of the plurality of mark points 40 are disposed above the first gate line 20, and another portion of the plurality of mark points 40 are disposed below the second gate line 30. In this embodiment of the present disclosure, all mark points 40 are disposed on the gate line, with a portion of mark points 40 disposed above the first gate line 20 and another portion of mark points 40 disposed below the second gate line 30. In other words, the mark point 40 and the gate line in the same doped region are not on the same layer; the gate line and the mark point 40 are superimposed on each other. This allows the first gate line 20 and the mark point 40 in the first doped region 50 to be printed separately, and the second gate line 30 and the mark point 40 in the second doped region 60 to be printed separately. Specifically, the second gate line 30 and the mark point 40 in the first doped region 50 are printed simultaneously first, and then the first gate line 20 and the mark point 40 in the second doped region 60 are printed simultaneously. This results in the mark point 40 in the first doped region 50 being positioned below the first gate line 20, and the mark point 40 in the second doped region 60 being positioned above the second gate line 30; similarly, the first gate line 20 and the mark point 40 in the second doped region 60 are printed simultaneously first, and then the second gate line 30 and the mark point 40 in the first doped region 50 are printed simultaneously. This results in the mark point 40 in the first doped region 50 being positioned above the first gate line 20, and the mark point 40 in the second doped region 60 being positioned below the second gate line 30. This disclosure separates the printing of the first gate line 20 in the first doped region 50 and the mark point 40 disposed in the first doped region 50, and the printing of the second gate line 30 in the second doped region 60 and the mark point 40 disposed in the second doped region 60. This allows the mark point 40 to be placed in the second doped region 60 when printing the first doped region 50, and the mark point 40 to be placed in the first doped region 50 when printing the second doped region 60. This avoids the problem of the mask at the mark point 40 being easily damaged when the mark point 40 is printed synchronously with the gate line of the p region or the gate line of the n region.

[0058] In some embodiments, within the first doped region 50, the mark point 40 has a first size along a first direction. The first size is greater than the width of the first grid line 20 and less than the width of the first doped region 50. The mark point 40 serves as a positioning reference during the manufacturing process, and its size design directly affects the positioning accuracy. When the first size of the mark point 40 is greater than the width of the first grid line 20, it ensures that the mark point 40 can be clearly distinguished from the grid line during visual recognition or machine positioning, avoiding misidentification or positioning deviation. Simultaneously, this size being less than the width of the first doped region 50 means that the mark point 40 will not occupy too much effective photoelectric conversion area, thereby ensuring the overall performance and stability of the solar panel. Preferably, in this embodiment, the ratio of the first size to the width of the first doped region 50 is greater than 1 / 5 and less than or equal to 1 / 3.

[0059] In some embodiments, within the second doped region 60, the mark point 40 has a second size along a first direction. This second size is greater than the width of the second grid line 30 but less than the width of the second doped region 60. The mark point 40 serves as a positioning reference during the manufacturing process, and its size design directly affects the positioning accuracy. When the first size of the mark point 40 is greater than the width of the second grid line 30, it ensures that the mark point 40 can be clearly distinguished from the grid line during visual recognition or machine positioning, avoiding misidentification or positioning deviation. Simultaneously, this size being less than the width of the second doped region 60 means that the mark point 40 will not occupy too much effective photoelectric conversion area, thereby ensuring the overall performance and stability of the solar panel. Preferably, in this embodiment, the ratio of the second size to the width of the second doped region 60 is greater than 1 / 5 and less than or equal to 1 / 3.

[0060] In some embodiments, as shown in Figures 5 to 9, the silicon substrate 10 further includes an isolation region 70 disposed between the first doped region 50 and the second doped region 60, and a plurality of mark points 40 are disposed at least partially within the isolation region 70. The main function of the isolation region 70 is to form electrical insulation between the first doped region 50 and the second doped region 60, preventing direct current flow between them and thus avoiding short circuits. Some of the mark points 40 can be disposed within the isolation region 70, which allows for effective utilization of the space within the isolation region 70 and also serves as a positioning marker. In some embodiments, within the isolation region 70, the mark points 40 have a third dimension along a first direction, the third dimension being smaller than the width of the isolation region 70. In this embodiment, by disposing of the mark points 40 within the isolation region 70 and controlling their size to be smaller than the width of the isolation region 70, it is possible to prevent the mark points 40 within the isolation region 70 from forming a connection between adjacent first doped regions 50 and second doped regions 60, thus avoiding local short circuits in the solar cell. Preferably, in this embodiment, the ratio of the third dimension to the width of the isolation region 70 is greater than or equal to 1 / 3 and less than 1. When the third dimension occupies at least one-third of the width of the isolation zone 70, it ensures that the mark point 40 has sufficient feature size during positioning, thereby reducing positioning errors. Since the size of the mark point 40 does not reach the full width of the isolation zone 70, the potential impact on the electrical performance and physical integrity of the isolation zone 70 during the manufacturing of the mark point 40 is relatively small. This helps maintain the stability and reliability of the isolation zone 70.

[0061] In some embodiments, as shown in Figures 1 and 10, the first doped region 50 includes a first doped layer 80, the second doped region 60 includes a second doped layer 90, a first gate line 20 is disposed on the first doped layer 80 and forms an ohmic contact with the first doped layer 80, and a second gate line 30 is disposed on the second doped layer 90 and forms an ohmic contact with the second doped layer 90. In this embodiment, the first gate line 20 is used to collect and transmit charge carriers of the first doped layer 80, and the second gate line 30 is used to collect and transmit charge carriers of the second doped layer 90. The charge carriers collected by the first gate line 20 and the second gate line 30 transmit current to an external circuit through a metal wire.

[0062] In some embodiments, as shown in Figures 3, 4, and 10, a portion of the plurality of mark points 40 are disposed on the first doped layer 80 and isolated from the silicon substrate 10, while another portion of the plurality of mark points 40 are disposed on the second doped layer 90 and isolated from the silicon substrate 10. The mark points 40 serve as positioning references, ensuring precise alignment of each layer or component in subsequent manufacturing processes (such as printing, dicing, and packaging). By placing the mark points 40 on the doped layer and isolating them from the silicon substrate 10, contamination of the silicon substrate 10 can be prevented during the printing process.

[0063] A battery assembly further includes a first passivation layer 100 disposed on a first doped layer 80 and a second passivation layer 110 disposed on a second doped layer 90. A first gate line 20 partially passes through the first passivation layer 100 and contacts the first doped layer 80, and a second gate line 30 partially passes through the second passivation layer 110 and contacts the second doped layer 90. The first gate line 20 and the second gate line 30 respectively pass through their respective passivation layers and doped layers and contact the electrodes, thereby achieving efficient collection of charge carriers.

[0064] In some embodiments, a portion of the plurality of mark points 40 are disposed on the first passivation layer 100, a portion of the plurality of mark points 40 penetrate the first passivation layer 100 and contact the first doped layer 80, and another portion of the plurality of mark points 40 are disposed on the second passivation layer 110, and another portion of the plurality of mark points 40 penetrate the second passivation layer 110 and contact the second doped layer 90. When the mark points 40 penetrate the passivation layer and contact the doped layer, they may serve as additional current collection channels, helping to reduce recombination losses of charge carriers during transport, thereby improving photoelectric conversion efficiency.

[0065] Of course, in other embodiments, some of the multiple mark points 40 are disposed on the first passivation layer 100 and isolated from the first doped layer 80, and another portion of the multiple mark points 40 are disposed on the second passivation layer 110 and isolated from the second doped layer 90. The mark points 40 only need to serve as markers for observation and do not conduct current. This disclosure is not limiting.

[0066] In some embodiments, each of the first gate line 20, the second gate line 30, and the mark point 40 includes a glass paste component, wherein the mass percentage of the glass paste component in the first gate line 20 is the same as the mass percentage of the glass paste component in the mark point 40 of the second doped region, and the mass percentage of the glass paste component in the second gate line 30 is the same as the mass percentage of the glass paste component in the mark point 40 of the first doped region.

[0067] This disclosure sets the mass percentage of the glass paste component in the first grid line 20 to be the same as the mass percentage of the glass paste component in the mark point 40 of the second doped region, and the mass percentage of the glass paste component in the second grid line 30 to be the same as the mass percentage of the glass paste component in the mark point 40 of the first doped region. This allows for the simultaneous printing of the mark point 40 of the second doped region while printing the first grid line 20, and the simultaneous printing of the mark point 40 of the first doped region while printing the second grid line 30. The mark point 40 and the grid line of the same doped region are printed in separate steps, avoiding the problem of easy damage to the mask at the mark point 40 position of the same doped region when printing the grid line, thus improving the reliability of the stencil.

[0068] In other embodiments, each of the first gate line 20, the second gate line 30, and the mark point 40 further includes a conductive component, a doping component, and an organic carrier. Thus, each of the first gate line 20, the second gate line 30, and the mark point 40 can possess conductivity and doping characteristics through the conductive component and the doping component. Moreover, the slurry can be modified by the glass slurry component to achieve a low recombination effect. The first gate line 20 and the mark point 40 of the second doped region use the same paste, namely the first paste; the second gate line 30 and the mark point 40 of the first doped region use the same paste, namely the second paste; the first paste contains 70%-88% by mass of the first conductive component, 0.2%-18% by mass of the first doped component, 0.2%-18% by mass of the first organic carrier component, and 0.1%-10% by mass of the first glass paste component; the second paste contains 70%-88% by mass of the second conductive component, 0.2%-18% by mass of the second doped component, 0.2%-18% by mass of the second organic carrier component, and 0.1%-10% by mass of the second glass paste component. Specifically, the conductive component includes at least one of silver particles, aluminum particles, copper particles, nickel particles, and tin particles; the doping component includes at least one of boron nitride, elemental aluminum, elemental gallium, gallium oxide, gallium hydroxide, gallium salt, elemental nickel, nickel oxide, and nickel salt; the organic carrier component includes at least one of organosilicon, silica gel, and terpineol; and the glass paste component includes at least one of lead glass, bismuthate glass, borate glass, and zinc glass. This disclosure is not intended to be limiting.

[0069] In some embodiments, the mass percentage of the glass paste component in the first gate line 20 is different from the mass percentage of the glass paste component in the second gate line 30. Preferably, the first gate line is a P-type gate line, the second gate line is an N-type gate line, and the mass percentage of the glass paste component in the first gate line is greater than the mass percentage of the glass paste component in the second gate line. The paste for the first gate line 20 is a P-type paste, and the paste for the second gate line is an N-type paste. This results in a greater mass percentage of the glass component in the P-type paste than in the N-type paste. Since the thickness of the poly layer in the P-region is greater than the thickness of the poly layer in the N-region, this design allows for better electrical contact between the P-type paste and the P-type poly layer.

[0070] A battery assembly includes the aforementioned solar cell. Based on the aforementioned solar cell, those skilled in the art will know that a corresponding battery assembly can be obtained by using multiple of the aforementioned solar cells and / or other corresponding existing accessories.

[0071] In the description of this specification, references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0072] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A solar cell, comprising a silicon substrate, the silicon substrate including a plurality of first doped regions and second doped regions staggered along a first direction; the first doped regions and the second doped regions extending along a second direction, the first direction and the second direction intersecting, a first grid line disposed in the first doped region, and a second grid line disposed in the second doped region; a plurality of mark points, a portion of the plurality of mark points disposed in the first doped region, and another portion of the plurality of mark points disposed in the second doped region.

2. The solar cell as claimed in claim 1, wherein, At least a portion of the plurality of mark points are disposed between the first grid line and the second grid line.

3. The solar cell as claimed in claim 1, wherein, A portion of the plurality of mark points is disposed below the first grid line, and another portion of the plurality of mark points is disposed above the second grid line.

4. The solar cell as claimed in claim 1, wherein, The silicon substrate has a first central axis in the first direction and a second central axis in the second direction. The intersection of the first and second central axes divides the silicon substrate into a first region, a second region, a third region, and a fourth region. The plurality of mark points include at least a first mark point disposed in the first region, a second mark point disposed in the second region, a third mark point disposed in the third region, and a fourth mark point disposed in the fourth region. The first mark point, the second mark point, the third mark point, and the fourth mark point are connected sequentially to form a rectangle, and the center point of the rectangle is a positioning base point.

5. The solar cell as claimed in claim 1, wherein, Within the first doped region, the mark point has a first size along the first direction, the first size being greater than the width of the first gate line and less than the width of the first doped region.

6. The solar cell of claim 5, wherein, The ratio of the first dimension to the width of the first doped region is greater than 1 / 5 and less than or equal to 1 / 3.

7. The solar cell of claim 1, wherein, Within the second doped region, the mark point has a second size along the first direction, the second size being greater than the width of the second gate line and less than the width of the second doped region.

8. The solar cell of claim 7, wherein, The ratio of the second dimension to the width of the second doped region is greater than 1 / 5 and less than or equal to 1 / 3.

9. The solar cell of claim 1, wherein, The silicon substrate further includes an isolation region disposed between the first doped region and the second doped region, and the plurality of mark points are at least partially disposed in the isolation region.

10. The solar cell of claim 9, wherein, Within the isolation zone, the mark point has a third dimension along the first direction, the third dimension being smaller than the width of the isolation zone.

11. The solar cell of claim 10, wherein, The ratio of the third dimension to the width of the isolation zone is greater than or equal to 1 / 3 and less than 1.

12. The solar cell of claim 1, wherein, A plurality of first doped regions and a plurality of second doped regions are arranged alternately in parallel along the first direction, and a plurality of first gate lines and a plurality of second gate lines are arranged alternately in parallel along the first direction.

13. The solar cell of claim 12, wherein, The first gate line is disposed at the center of the first doped region, and the second gate line is disposed at the center of the second doped region.

14. The solar cell of claim 1, wherein, The ratio of the width of the first gate line to the width of the first doped region is greater than 1 / 10 and less than or equal to 1 / 5, and the ratio of the width of the second gate line to the width of the second doped region is greater than 1 / 10 and less than or equal to 1 / 5.

15. The solar cell of claim 1, wherein, Each of the first gate line, the second gate line, and the mark point includes a glass paste component, wherein the mass percentage of the glass paste component in the first gate line is the same as the mass percentage of the glass paste component in the mark point of the second doped region, and the mass percentage of the glass paste component in the second gate line is the same as the mass percentage of the glass paste component in the mark point of the first doped region.

16. The solar cell of claim 15, wherein, The mass percentage of the glass paste component in the first grid line is different from the mass percentage of the glass paste component in the second grid line.

17. The solar cell of claim 16, wherein, The first grid line is a P-type grid line, the second grid line is an N-type grid line, and the mass percentage of the glass paste component in the first grid line is greater than the mass percentage of the glass paste component in the second grid line.

18. The solar cell of claim 15, wherein, A portion of the plurality of mark points is positioned above the first grid line, and another portion of the plurality of mark points is positioned below the second grid line.

19. The solar cell of claim 15, wherein, The first doped region includes a first doped layer, the second doped region includes a second doped layer, the first gate line is disposed on the first doped layer and forms an ohmic contact with the first doped layer, and the second gate line is disposed on the second doped layer and forms an ohmic contact with the second doped layer.

20. The solar cell of claim 19, wherein, A portion of the plurality of mark points is disposed on the first doped layer and isolated from the silicon substrate, and another portion of the plurality of mark points is disposed on the second doped layer and isolated from the silicon substrate.

21. The solar cell of claim 19, wherein, It also includes a first passivation layer disposed on the first doped layer and a second passivation layer disposed on the second doped layer, wherein the first gate line portion passes through the first passivation layer and contacts the first doped layer, and the second gate line portion passes through the second passivation layer and contacts the second doped layer.

22. The solar cell of claim 21, wherein, A portion of the plurality of mark points are disposed on the first passivation layer, a portion of the plurality of mark points penetrate the first passivation layer and contact the first doped layer, and another portion of the plurality of mark points are disposed on the second passivation layer, and another portion of the plurality of mark points penetrate the second passivation layer and contact the second doped layer.

23. A battery assembly comprising the solar cell of any one of claims 1-22.

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