Semiconductor structure and manufacturing method therefor

Abstract

The present application provides a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises a chip unit, a plastic packaging layer, a first redistribution structure, a second redistribution structure, an insulating layer, and a solder layer. The chip unit comprises at least one chip, and a chip front surface of the chip is provided with a plurality of solder pads. The plastic packaging layer at least encapsulates side surfaces of the chip. The first redistribution structure is located on one side of the chip front surface and is electrically connected to the solder pads. The second redistribution structure is located on the side of the first redistribution structure away from the chip, and comprises a plurality of sub-distribution structures; and each sub-distribution structure is in contact with the first redistribution structure. The orthographic projection of each sub-distribution structure on a plane perpendicular to the thickness direction of the sub-distribution structure does not overlap the orthographic projection of a solder pad led out from the sub-distribution structure on the plane. In the thickness direction, first side surfaces of the sub-distribution structures away from the chip unit are continuous. The insulating layer covers at least part of surfaces of the first and second redistribution structures, and the first side surfaces are exposed from the insulating layer. The solder layer at least covers the first side surfaces.

Description

Semiconductor structure and manufacturing method Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] A chip packaging technology may include the following process: first, a chip is mounted on a carrier board, with multiple solder pads on the front side of the chip; then, a plastic encapsulation layer is formed to encapsulate the chip, with the solder pads exposed in the plastic encapsulation layer; then, a redistribution layer is formed on the plastic encapsulation layer using an electroplating process; then, a groove is formed to expose the sides of the redistribution layer; then, a tin plating layer is formed on the exposed surface of the redistribution layer using an electroplating process.

[0003] The chip packaging structure formed by the above-mentioned chip packaging technology is prone to warping, which affects the connection between the chip packaging structure and other structures such as circuit boards. Summary of the Invention

[0004] This application provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] According to a first aspect of the embodiments of this application, a semiconductor structure is provided. The semiconductor structure includes:

[0006] A chip unit includes at least one chip, each chip including a front side, a back side opposite to the front side, and a plurality of side surfaces connecting the front side and the back side, wherein the front side of the chip is provided with a plurality of solder pads;

[0007] A molding compound layer, at least encapsulating the sides of the chip;

[0008] The first rewiring structure is located on one side of the front of the chip and is electrically connected to the solder pad.

[0009] The second rewiring structure is located on the side of the first rewiring structure away from the chip, and includes a plurality of spaced sub-wiring structures; each sub-wiring structure contacts the first rewiring structure and leads out at least one of the solder pads; the orthographic projection of the sub-wiring structure on a plane perpendicular to its thickness direction and the orthographic projection of the solder pads it leads out on the same plane do not overlap; in the thickness direction of the sub-wiring structure, the first side of the sub-wiring structure away from the chip cell is continuous.

[0010] An insulating layer covers at least a portion of the surfaces of the first rewiring structure and the second rewiring structure, with the first side of the sub-wiring structure exposed by the insulating layer;

[0011] A solder layer that at least covers the first side of the sub-wiring structure.

[0012] In one embodiment, the sub-wiring structure includes a first trace and at least one conductive connection layer, the conductive connection layer including at least one first type of conductive post; the first side of the sub-wiring structure includes the side of the first type of conductive post.

[0013] The conductive connection layer is provided between the first rewiring structure and the adjacent first trace.

[0014] The sub-wiring structure includes at least two layers of stacked first traces and at least one conductive connection layer, the conductive connection layer including at least one first type of conductive post; the first side of the sub-wiring structure includes the side of the first type of conductive post; the conductive connection layer is provided between at least two adjacent layers of first traces.

[0015] In one embodiment, the sub-wiring structure includes at least two layers of stacked first traces, and at least two adjacent layers of first traces are in direct contact; of the two directly contacting layers of first traces, the orthographic projection of the first trace away from the encapsulation layer on the plane falls within the orthographic projection of the first trace near the encapsulation layer on the plane, and at least a portion of the edge of the orthographic projection of the first trace away from the encapsulation layer on the plane is located inside the edge of the orthographic projection of the first trace near the encapsulation layer on the plane.

[0016] In one embodiment, the first rewiring structure includes a plurality of spaced second traces, each of the sub-wiring structures being in contact with the second traces; the second trace includes a second side surface, and the second side surface and the first side surface of the sub-wiring structure in contact with it are located on the same side of the chip cell;

[0017] The first side of the sub-wiring structure is located on the side of the second side of the second trace that contacts it, close to the chip cell.

[0018] In one embodiment, the first rewiring structure includes a plurality of spaced second traces, each of the sub-wiring structures being in contact with the second traces; the second trace includes a second side surface, and the second side surface and the first side surface of the sub-wiring structure in contact with it are located on the same side of the chip cell;

[0019] The first side of the sub-wiring structure and the second side of the second trace that contacts it are on the same plane, and the solder layer covers the second side.

[0020] In one embodiment, the sub-wiring structure includes a first trace and at least one conductive connection layer. The conductive connection layer includes at least one first-type conductive post and at least one second-type conductive post. The first side of the sub-wiring structure includes the side of the first-type conductive post. In the same conductive connection layer, in a direction perpendicular to the thickness direction and parallel to the first side, the width of the side of the first-type conductive post is greater than or equal to the maximum width of the second-type conductive post.

[0021] In one embodiment, the sub-wiring structure is exposed away from the surface of the chip, exposed to the insulating layer, and covered by the solder layer.

[0022] In one embodiment, the first sides of at least two of the sub-wiring structures are located on the same side of the chip unit; the first sides of each sub-wiring structure located on the same side of the chip unit are located on the same plane.

[0023] According to a second aspect of the present application, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0024] A chip unit is provided, the chip unit including at least one chip; the chip includes a chip front side, a chip back side opposite to the chip front side, and a plurality of chip sides connecting the chip front side and the chip back side, the chip front side having a plurality of solder pads;

[0025] A molding compound is formed, which at least encapsulates the sides of the chip;

[0026] A first rewiring structure, a second rewiring structure, and an insulating layer are formed on the side of the molding compound located on the front side of the chip. The first rewiring structure is electrically connected to the solder pads. The second rewiring structure is located on the side of the first rewiring structure away from the chip and includes multiple sub-wiring structures. Each sub-wiring structure contacts the first rewiring structure and leads out at least one solder pad. The orthographic projection of each sub-wiring structure on a plane perpendicular to its thickness direction and the orthographic projection of the solder pad it leads out on the same plane do not overlap. The insulating layer covers the first rewiring structure and the second rewiring structure.

[0027] The insulating layer and the sub-wiring structure are cut along the cutting path, so that the sub-wiring structure forms a first side away from the chip unit. The orthographic projection of the cutting path on the plane does not overlap with the orthographic projection of the chip unit on the plane. The first side of the sub-wiring structure exposes the insulating layer, and the first side of the sub-wiring structure is continuous in the thickness direction of the sub-wiring structure.

[0028] A solder layer is formed, the solder layer covering at least a first side of the sub-wiring structure.

[0029] In one embodiment, the sub-wiring structure includes a first trace and at least one conductive connection layer, the conductive connection layer including at least one first type of conductive post;

[0030] The conductive connection layer is provided between the rewiring and the adjacent first trace; the orthographic projection of the edge line of the cutting track on the plane overlaps with the orthographic projection of the surface of the first type of conductive post near the encapsulation layer on the plane, and the orthographic projection of the surface of the first type of conductive post away from the encapsulation layer on the plane.

[0031] In one embodiment, the sub-wiring structure includes at least two layers of stacked first traces and at least one conductive connection layer, the conductive connection layer including at least one first type of conductive post; the conductive connection layer is provided between at least two adjacent layers of first traces;

[0032] The orthographic projection of the edge line of the cut channel on the plane overlaps with the orthographic projection of the surface of the first type of conductive post near the encapsulation layer on the plane, and the orthographic projection of the surface of the first type of conductive post away from the encapsulation layer on the plane.

[0033] In one embodiment, the conductive connection layer further includes at least one second type of conductive post; before the insulating layer and the sub-wiring structure are cut along the cutting path, in the same conductive connection layer, in a direction perpendicular to the thickness direction and parallel to the first side surface, the maximum width of the first type of conductive post is greater than the maximum width of the second type of conductive post.

[0034] In one embodiment, the first rewiring structure includes a plurality of spaced second traces, and each of the sub-wiring structures is in contact with the second traces; in the step of cutting the insulating layer and the sub-wiring structure along the cutting path, the first rewiring structure is not cut; after the cutting of the insulating layer and the sub-wiring structure along the cutting path, the portion of the second trace extending beyond the first side of the sub-wiring structure in contact with it is exposed away from the surface of the encapsulation layer.

[0035] In one embodiment, the first rewiring structure includes a plurality of spaced second traces, and each of the sub-wiring structures is in contact with the second traces; in the step of cutting the insulating layer and the sub-wiring structures along the dicing path, the first rewiring structure is cut simultaneously, and the second trace forms a second side surface that is located on the same plane as the first side surface of the sub-wiring structure in contact with it; the solder layer covers the second side surface of the second trace.

[0036] In one embodiment, the molding compound encapsulates at least two chip units, and the first rewiring structure is connected to the connector; in the step of cutting the insulating layer and the sub-wiring structure along the dicing path, the first rewiring structure is not cut; after cutting the insulating layer and the sub-wiring structure along the dicing path, the portion of the connector away from the surface of the molding compound is exposed.

[0037] The formation of the solder layer includes: connecting the connection portion to the electroplating electrode and forming the solder layer using an electroplating process;

[0038] After forming the solder layer, the method for manufacturing the semiconductor structure further includes: cutting the obtained structure to remove the connecting portion, thereby obtaining at least two semiconductor structures, each of which includes one chip unit.

[0039] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0040] Figure 1 is a cross-sectional view of a semiconductor structure provided in an exemplary embodiment of this application;

[0041] Figure 2 is a partial structural schematic diagram of a semiconductor structure provided in an exemplary embodiment of this application;

[0042] Figure 3 is a cross-sectional view of a semiconductor structure provided in another exemplary embodiment of this application;

[0043] Figure 4 is a flowchart of a semiconductor structure manufacturing method provided in an exemplary embodiment of this application;

[0044] Figure 5 is a partial cross-sectional view of the first intermediate structure provided in an exemplary embodiment of this application;

[0045] Figure 6 is a partial cross-sectional view of the second intermediate structure provided in an exemplary embodiment of this application;

[0046] Figure 7 is a partial structural schematic diagram of the second intermediate structure shown in Figure 6;

[0047] Figure 8 is a partial cross-sectional view of the third intermediate structure provided in an exemplary embodiment of this application;

[0048] Figure 9 is a partial cross-sectional view of a third intermediate structure provided in another exemplary embodiment of this application;

[0049] Figure 10 is a partial cross-sectional view of the fourth intermediate structure provided in an exemplary embodiment of this application;

[0050] Figure 11 is a partial cross-sectional view of the fourth intermediate structure provided in another exemplary embodiment of this application. Detailed Implementation

[0051] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0052] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0053] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0054] This application provides a semiconductor structure. As shown in Figures 1 and 2, the semiconductor structure includes a chip unit, a molding compound 20, a first redistribution structure 30, a second redistribution structure, an insulating layer 40, and a solder layer 50.

[0055] The chip unit includes at least one chip 10. Each chip 10 includes a front side, a back side opposite to the front side, and multiple side surfaces connecting the front and back sides. The front side has multiple solder pads 11. The molding compound 20 encapsulates at least the side surfaces. A first rewiring structure 30 is located on one side of the front side and is electrically connected to the solder pads 11. A second rewiring structure is located on the side of the first rewiring structure 30 away from the molding compound 20. The second rewiring structure includes multiple spaced sub-wiring structures 32. Each sub-wiring structure 32 contacts the first rewiring structure 30 and leads out at least one solder pad 11. As shown in FIG1, the orthographic projection of each sub-wiring structure 32 on a plane perpendicular to its thickness direction and the orthographic projection of the solder pad 11 it leads out on the same plane do not overlap; in the thickness direction of the sub-wiring structure 32, the sub-wiring structure 32 is continuous away from the first side surface 301 of the chip unit. The insulating layer 40 covers at least a portion of the surfaces of the first rewiring structure 30 and the second rewiring structure, and the first side 301 of the sub-wiring structure 32 exposes the insulating layer 40. The solder layer 50 at least covers the first side 301 of the sub-wiring structure 32. The thickness direction of the sub-wiring structure 32 refers to the direction in which the molding compound 20 points towards the first rewiring structure 30.

[0056] In the semiconductor structure provided in this application embodiment, the sub-wiring structure 32 is in contact with the first rewiring structure 30, and the first rewiring structure 30 is electrically connected to the pad 11. Thus, the sub-wiring structure 32 can lead out the pad 11, thereby covering the solder layer 50 on the first side 301 of the sub-wiring structure 32 to lead out the signal from the pad 11. Since the orthographic projection of the sub-wiring structure 32 on a plane perpendicular to its thickness direction does not overlap with the orthographic projection of the led-out pad 11 on the same plane, the contact area between the sub-wiring structure 32 and the first rewiring structure 30 is small. The sub-wiring structure 32 can achieve the fan-out of the pad 11 while simultaneously reducing the total thickness of the first and second rewiring structures in a local area, thus improving the performance of the first rewiring structure and... The large overall thickness of the second rewiring structure addresses the problem of semiconductor structure warping, thereby improving the difficulty of soldering the semiconductor structure to other structures, such as circuit boards, due to warping. Furthermore, the smaller total thickness of the first and second rewiring structures in local areas helps reduce the stress between the first and second rewiring structures and the insulating layer 40, improving the problem of separation between the first and second rewiring structures and the insulating layer 40. When the sub-wiring structure 32 is fabricated using an electroplating process, the smaller area of ​​the sub-wiring structure 32 allows for increased current density and shorter electroplating time, thus improving the manufacturing efficiency of the semiconductor structure.

[0057] In one embodiment, as shown in FIG1, the insulating layer 40 covers the side surface of the first rewiring structure 30 and a portion of the surface away from the chip 10, and the insulating layer 40 covers the side surface of the sub-wiring structure 32 of the second rewiring structure.

[0058] In one embodiment, the orthographic projection of the sub-wiring structure 32 on the plane does not overlap with the orthographic projection of each pad 11 of the chip unit on the plane.

[0059] In one embodiment, as shown in Figures 1 and 2, the first rerouting structure 30 includes a plurality of spaced second traces 31, each of the subrouting structures 32 contacting a second trace 31. Each second trace 31 is electrically connected to at least one pad 11. In the embodiment shown in Figure 2, each second trace 31 contacts one subrouting structure 32. In other embodiments, each second trace 31 may contact two or more subrouting structures 32.

[0060] In one embodiment, when the chip unit includes two or more chips 10, at least one second trace 31 is electrically connected to the pads 11 of the two chips 10 to achieve electrical connection between adjacent chips 10.

[0061] In one embodiment, as shown in FIG1, the semiconductor structure further includes a protective layer 60 located on the front side of the chip 10. The protective layer 60 has an opening 61, and the first redistribution structure 30 further includes a conductive portion 70 located within the opening 61. The second trace 31 is electrically connected to the pad 11 through the conductive portion 70. The chip 10 may include multiple pads 11, and the protective layer 60 has an opening 61 corresponding to each pad 11. Each opening 61 has a conductive portion 70 electrically connected to the corresponding pad 11. Each second trace 31 may be electrically connected to one pad 11 or to multiple pads 11. In one embodiment, as shown in FIG1, the surface of the sub-wiring structure 32 away from the molding compound 20 exposes the insulating layer 40, and the solder layer 50 covers the surface of the sub-wiring structure 32 away from the molding compound 20.

[0062] In one embodiment, as shown in FIG1, the orthographic projection of the first side surface 301 on the plane does not overlap with the orthographic projection of the chip 10 on the plane.

[0063] In one embodiment, the orthographic projection of the sub-wiring structure 32 onto the plane overlaps with the orthographic projection of the chip 10 onto the plane. In other embodiments, the orthographic projection of the sub-wiring structure 32 onto the plane does not overlap with the orthographic projection of the chip 10 onto the plane.

[0064] In one embodiment, as shown in FIG2, the first side surface 301 of at least two sub-wiring structures 32 is located on the same side of the chip cell. Further, the first side surface 301 of each sub-wiring structure 32 located on the same side of the chip cell is located on the same plane.

[0065] In one embodiment, as shown in Figures 1 and 2, the sub-wiring structure 32 includes a first trace 321 and at least one conductive connection layer 322. The conductive connection layer 322 includes at least one first-type conductive post 325 and at least one second-type conductive post 326. The first side surface 301 of the sub-wiring structure 32 includes the side surface of the first-type conductive post 325. By setting the first side surface 301 of the sub-wiring structure 32 to include the side surface of the first-type conductive post 325, the first side surface 301 of the sub-wiring structure 32 can be continuous in its thickness direction, ensuring that the portion of the solder layer covering the first side surface 301 is a continuous film layer. The conductive connection layer 322 can further reduce the total thickness of the local areas of the first rewiring structure 30 and the second rewiring structure while ensuring the thickness of the sub-wiring structure 32. This can further improve the problem of semiconductor structure warping and separation between the first rewiring structure 30 and the second rewiring structure and the insulating layer, and can also further improve the manufacturing efficiency of the semiconductor structure. In the embodiment shown in Figure 2, the conductive connection layer 322 includes a plurality of second-type conductive posts 326.

[0066] In one embodiment, the sub-wiring structure 32 includes at least two layers of first traces 321 stacked together, with a conductive connection layer 322 disposed between at least two adjacent layers of first traces 321. In some embodiments, the sub-wiring structure 32 may include two layers of traces 321 and a conductive connection layer 322 located between the two layers of traces 321. In other embodiments, the sub-wiring structure 32 may include three or more layers of traces, with a conductive connection layer 322 disposed between at least two adjacent layers of traces 321.

[0067] In one embodiment, as shown in FIG1, the conductive connection layer 322 is provided between the first redistribution structure 30 and the adjacent first trace 321.

[0068] In one embodiment, as shown in FIG2, in the same conductive connection layer 322, in direction X perpendicular to the thickness direction and parallel to the first side surface 301, the width of the side surface of the first type of conductive post 325 is greater than or equal to the maximum width of the second type of conductive post 326. This configuration allows for a larger area of ​​the side surface of the first type of conductive post 325, thereby increasing the area of ​​the first side surface 301. Consequently, the area of ​​the solder layer 50 covering the first side surface 301 is larger, improving the reliability of soldering the semiconductor structure to other structures.

[0069] In one embodiment, as shown in Figures 1 and 2, the insulating layer 40 includes a first insulating film layer 41 located on the molding layer 20. The first insulating film layer 41 is provided with a plurality of through holes 43 and an opening groove 44. Each second type conductive post 326 is located in a through hole 43 and a first type conductive post 325 is located in the opening groove 44.

[0070] In one embodiment, as shown in FIG1, the insulating layer 40 further includes a second insulating film layer 42 located on the molding layer 20, the second insulating film layer 42 covering a portion of the side surface of each first trace 321.

[0071] In one embodiment, the sub-wiring structure 32 includes at least two layers of first traces 321 stacked together, and at least two adjacent layers of first traces 321 in the same sub-wiring structure 30 are in direct contact. A second insulating film layer 42 covers a portion of the side surfaces of the directly contacting first traces 321. In the embodiment shown in FIG1, the sub-wiring structure 32 includes two layers of first traces 321, and the two layers of first traces 321 are in direct contact.

[0072] Further, as shown in Figures 1 and 2, in the same sub-wiring structure 30, when two adjacent layers of the first trace 321 are in direct contact, the orthographic projection of the first trace 321 away from the molding layer 20 on the plane falls within the orthographic projection of the first trace 321 near the molding layer 20 on the plane, and at least a portion of the edge of the orthographic projection of the first trace 321 away from the molding layer 20 on the plane is located inside the edge of the orthographic projection of the first trace 321 near the molding layer 20 on the plane. Thus, the stepped structure on some sides of the sub-wiring structure 32 can improve the bonding force between the sub-wiring structure 32 and the insulating layer 40. When the second insulating film layer covering the two directly contacting first traces 321 is formed by the lamination process, the above-mentioned arrangement can prevent the first trace 321 away from the molding compound 20 from exceeding the trace 321 near the molding compound 20, which would result in a void between the formed second insulating film layer and the first trace 321 near the molding compound 20, thereby affecting the reliability of the semiconductor structure. Furthermore, given that the area of ​​the first trace 321 away from the molding compound 20 is fixed, the above-mentioned arrangement can make the area of ​​the first trace 321 near the molding compound 20 larger, which is beneficial for the heat generated by the chip to be conducted to the outside through the sub-wiring structure 32. In the embodiment shown in Figure 2, among two adjacent first traces 321, the edge of the first trace 321 away from the molding layer 20 in the orthogonal projection on the plane has part of its edge coinciding with the edge of the first trace 321 near the molding layer 20 in the orthogonal projection on the plane, and the other part of its edge is located inside the edge of the first trace 321 near the molding layer 20 in the orthogonal projection on the plane.

[0073] In one embodiment, the second trace 31 is in direct contact with the adjacent first trace 321, and the conductive connection layer 322 is located between the two adjacent first traces 321. The edge of the orthographic projection of the second trace 31 on the plane is located outside the edge of the orthographic projection of the first trace 321 in contact with it on the plane. This prevents voids between the insulating layer and the second trace 31 from affecting the reliability of the semiconductor structure.

[0074] In one embodiment, as shown in FIG1, the first side surface 301 of the sub-wiring structure 32 is flush at all points. During the fabrication of the semiconductor structure, the first side surface 301 can be formed by cutting the sub-wiring structure 32, thereby making the first side surface 301 of the sub-wiring structure 32 flush at all points.

[0075] In one embodiment, as shown in Figures 1 and 3, the second trace 31 includes a second side surface 302, and the second side surface 302 of the second trace 31 and the first side surface 301 of the sub-wiring structure 32 in contact with it are located on the same side of the chip unit.

[0076] In one embodiment, as shown in FIG1, the first side 301 of the sub-wiring structure 32 is located on the side of the second side 302 of the second trace 31 that contacts it, closer to the chip cell. With this configuration, during the fabrication of the semiconductor structure, the second trace 31 extends beyond the first side 301, and during the formation of the solder layer using an electroplating process, the portion of the second trace 31 extending beyond the first side 301 can be electrically connected to the electroplating electrode. In this embodiment, the solder layer 50 covers the surface of the second trace 31 extending beyond the first side 301 away from the molding compound 20.

[0077] In another embodiment, as shown in FIG3, the first side 301 of the sub-wiring structure 32 and the second side 302 of the second trace 31 in contact with it are on the same plane, and the solder layer 50 covers the first side 301 and the second side 302. With this configuration, the thickness of the sub-wiring structure 32 can be reduced when the height of the solder layer 50 is constant, further improving the problem of semiconductor structure warping caused by the large total thickness of the sub-wiring structure 32 and the first trace 31 in contact with it. In this embodiment, a chemical plating process can be used to form the solder layer 50. During the semiconductor structure manufacturing process, the second side 302 and the first side 301 can be formed by the same cutting process, thus the first side 301 and the second side 302 are on the same plane.

[0078] In one embodiment, the solder layer 50 is made of tin.

[0079] This application also provides a method for manufacturing a semiconductor structure. As shown in FIG4, the method for manufacturing the semiconductor structure includes the following steps 110 to 150. Each step will be described in detail below.

[0080] In step 110, a chip unit is provided, the chip unit including at least one chip, the chip including a front side of the chip, a back side of the chip opposite to the front side of the chip, and a plurality of chip sides connecting the front side of the chip and the back side of the chip, the front side of the chip having a plurality of solder pads.

[0081] In one embodiment, the chip can be obtained by dicing a wafer.

[0082] In step 120, a molding compound is formed, which at least encapsulates the sides of the chip.

[0083] In one embodiment, prior to the step of forming the molding compound, the method of manufacturing the semiconductor structure further includes the step of mounting each chip of at least one chip unit onto a carrier board, with the front side of the chip facing away from the carrier board.

[0084] This step yields the first intermediate structure shown in Figure 5. It should be noted that the carrier board is not shown in Figure 5 or subsequent intermediate structure diagrams. As shown in Figure 5, the molding compound 20 encapsulates the chip sides and back sides of each chip 10. A protective layer 60 is formed on the front side of the chip 10. The protective layer 60 has openings 61, which correspond one-to-one with the solder pads 11, exposing a portion of the surface of the corresponding solder pad 11. The surface of the molding compound 20 on the front side of the chip is flush with the surface of the protective layer 60 on the same side.

[0085] In one embodiment, before forming the molding compound 20, some pretreatment steps, such as chemical cleaning or plasma cleaning, can be performed to remove impurities from the chip 10 and the substrate surface, so that the molding compound can be more closely connected to the chip 10 and the substrate, and delamination or cracking will not occur.

[0086] In one embodiment, the material of the encapsulation layer 20 can be a polymer resin, resin composite material, polymer composite material, etc. For example, the encapsulation layer 20 can be a resin with fillers, wherein the fillers can be inorganic particles. The encapsulation layer 20 can be formed by injection molding, compression molding, or transfer molding.

[0087] In step 130, a first rewiring structure, a second rewiring structure, and an insulating layer are formed on the side of the molding compound located on the front side of the chip. The first rewiring structure is electrically connected to the solder pads. The second rewiring structure is located on the side of the first rewiring structure away from the chip and includes multiple sub-wiring structures. Each sub-wiring structure contacts the first rewiring structure and leads out at least one solder pad. The orthographic projection of the sub-wiring structure on a plane perpendicular to its thickness direction and the orthographic projection of the solder pad it leads out on the same plane do not overlap. The insulating layer covers the first rewiring structure and the second rewiring structure.

[0088] This step yields the second intermediate structure shown in Figures 6 and 7. As shown in Figures 6 and 7, the first rewiring structure 30 includes a conductive portion 70 located within the opening 61 and electrically connected to the solder pad 11, and a second trace 31 located on the side of the conductive portion 70 away from the molding compound 20 and electrically connected to the conductive portion 70. The sub-wiring structure 32 includes a first trace 321 and a conductive connection layer 322. The conductive connection layer 322 includes at least one first-type conductive post 325 and at least one second-type conductive post 326. The insulating layer 40 includes a first insulating film layer 41 and a second insulating film layer 42 located on the side of the first insulating film layer 41 away from the molding compound 20. The first insulating film layer 41 covers the side surfaces of the first-type conductive posts 325 and the second-type conductive posts 326, and the second insulating film layer 42 covers the side surfaces of each second trace 321. The insulating layer 40 is exposed on the surface of the sub-wiring structure 32 away from the molding compound 20.

[0089] In one embodiment, as shown in FIG6, the conductive connection layer 322 is provided between the second trace 31 and the adjacent first trace 321.

[0090] In one embodiment, the sub-wiring structure 32 includes at least two layers of first traces 321 stacked together, and the conductive connection layer 322 is provided between at least two adjacent layers of first traces 321.

[0091] In one embodiment, as shown in FIG6, the sub-wiring structure 32 includes at least two layers of first traces 321 stacked together, and at least two adjacent layers of first traces 321 are in direct contact.

[0092] Furthermore, as shown in Figure 6, in the same sub-wiring structure 30, when two adjacent layers of the first trace 321 are in direct contact, the edge of the orthographic projection of the first trace 321 away from the molding layer 20 on the plane is located inside the edge of the orthographic projection of the first trace 321 on the plane close to the molding layer 20.

[0093] In one embodiment, the second trace 31 is in direct contact with the adjacent first trace 321, the conductive connection layer 322 is located between two adjacent first traces 321, and the edge of the orthographic projection of the second trace 31 on the plane is located outside the edge of the orthographic projection of the first trace 321 in contact with it on the plane.

[0094] In one embodiment, as shown in FIG6, a conductive connection layer 322 is provided between the second trace 31 and the adjacent first trace 321. The sub-wiring structure 32 includes two stacked layers of first traces 321, and the two layers of first traces 321 are in direct contact. In this embodiment, step 130 may include the following process:

[0095] First, a first redistribution structure 30 is formed on the surface of the first intermediate structure located on the front side of the chip. The first redistribution structure 30 includes a plurality of spaced second traces 31.

[0096] Subsequently, a first insulating film layer 41 is formed to cover the second trace 31, and a plurality of through holes 43 are opened in the first insulating film layer 41, each through hole 43 exposing a portion of the surface of the second trace 31.

[0097] Subsequently, a first photoresist layer is formed, the first photoresist layer having multiple first cutouts, and each first cutout exposes multiple through holes 43;

[0098] Subsequently, a first trace 321 is formed in a plurality of conductive pillars and in a first cutout portion. The surface of the first trace 321 away from the molding layer 20 is flush with the surface of the first photoresist layer away from the molding layer 20. Each conductive pillar is located in a through hole 43. The plurality of conductive pillars include at least one first type conductive pillar 325 and at least one second type conductive pillar 326.

[0099] Subsequently, a second photoresist layer is formed on the side of the first photoresist layer away from the molding layer 20. The second photoresist layer has a second cutout portion, and a second cutout portion exposes a portion of the surface of a first trace 321 located in the first cutout portion.

[0100] Subsequently, the first trace 321 is formed within the second hollow section;

[0101] Subsequently, the first and second photoresist layers are removed;

[0102] Subsequently, a second insulating film layer is formed. This second insulating film layer can be formed using a lamination process.

[0103] In one embodiment, the molding compound encapsulates at least two chip units. The solder pads of each chip unit are electrically connected to the first redistribution structure 30. In one embodiment, as shown in FIG7, the second intermediate structure further includes a connecting portion 80, which includes multiple connecting rods 81 connected to adjacent connecting rods 81. The connecting portion 80 and the second traces 31 can be formed simultaneously, and each second trace 31 is connected to the connecting portion 80. With this configuration, when a solder layer is subsequently formed using an electroplating process, electrically connecting the connecting portion 80 to the electroplating electrode allows the first side of each sub-wiring structure 32 to simultaneously form a solder layer, simplifying the operation.

[0104] In step 140, the insulating layer and the sub-rewiring structure are cut along the cutting path, so that the sub-wiring structure forms a first side away from the chip cell, and the orthographic projection of the cutting path on the plane does not overlap with the orthographic projection of the chip cell on the plane; the first side of the sub-wiring structure exposes the insulating layer, and the first side of the sub-wiring structure is continuous in the thickness direction of the sub-wiring structure.

[0105] The portion between the two opposing cut edge lines 91 shown in Figures 6 and 7 constitutes the cut track. As shown in Figure 6, the orthographic projection of the cut track edge line 91 onto the plane overlaps with the orthographic projections of the surface of the first type conductive post 325 near the molding compound 20 and the surface of the first type conductive post 325 away from the molding compound 20 onto the plane. After cutting, the first type conductive post 325 is exposed, with its side away from the chip cell exposed. This arrangement ensures that in the structure obtained in step 140, the first side of the sub-wiring structure 32 is continuous in the direction away from the molding compound 20, preventing discontinuity of the first side from affecting the formation of the solder layer.

[0106] In one embodiment, as shown in FIG6, the orthographic projection of the edge of the cutting path corresponding to the sub-wiring structure on the plane overlaps with the orthographic projection of the first trace 321 on the plane.

[0107] Step 140 yields the third intermediate structure shown in Figure 8 or Figure 9. As shown in Figures 8 and 9, a groove 103 is formed by cutting the insulating layer and the sub-wiring structure along the cutting path, exposing the first side surface 301 of the sub-wiring structure 32. The first side surfaces 301 of multiple sub-wiring structures 32 located on the same side of the chip unit can be on the same plane.

[0108] In the embodiment shown in Figure 8, during the step of cutting the insulating layer and the sub-wiring structure along the cutting path, the first trace 31 is not cut; after cutting the insulating layer and the sub-wiring structure along the cutting path, the portion of the first trace 31 extending beyond the first side 301 away from the encapsulation layer 20 and the surface of the connecting portion 80 away from the encapsulation layer are exposed.

[0109] In the embodiment shown in Figure 9, during the step of cutting the insulating layer and the sub-wiring structure along the cutting path, the first rewiring structure 30 is cut simultaneously, and the second trace 31 forms a second side 302 located on the same side as the first side 301 of the sub-wiring structure 32, and the second side 302 of the second trace 31 and the first side 301 of the sub-wiring structure 32 are on the same plane.

[0110] In one embodiment, before cutting the insulating layer and the sub-wiring structure along the cutting path in the same conductive connection layer 322, in the same conductive connection layer 322, in a direction perpendicular to the thickness direction and parallel to the first side surface, the maximum width of the first type of conductive post 325 is greater than the maximum width of the second type of conductive post. This configuration ensures that even if offset occurs during the cutting process, the side surface area of ​​the first type of conductive post is larger after cutting. In some embodiments, before step 140, both the first type of conductive post 325 and the second type of conductive post 326 can be cylindrical, in which case the diameter of the cross-section of the first type of conductive post 325 parallel to the aforementioned plane is greater than the diameter of the cross-section of the second type of conductive post parallel to the aforementioned plane.

[0111] In step 150, a solder layer is formed, which at least covers a first side of the sub-wiring structure.

[0112] When the third intermediate structure is as shown in Figure 8, this step can yield the fourth intermediate structure as shown in Figure 10, and the solder layer 50 can be formed using an electroplating process. When the third intermediate structure is as shown in Figure 9, this step can yield the fourth intermediate structure as shown in Figure 11. As shown in Figure 11, the solder layer 50 covers the second side surface of the second trace 31, and the solder layer 50 can be formed using a chemical plating process.

[0113] In one embodiment, after step 150, the method for manufacturing the semiconductor structure further includes: cutting the obtained structure to obtain at least two semiconductor structures, each semiconductor structure including at least one chip.

[0114] The area between the dicing edge lines 92 shown in Figures 10 and 11 is the dicing track in this step. In this step, the orthographic projection of the dicing track on the aforementioned plane does not overlap with the orthographic projection of the solder layer on the aforementioned plane, and there is a gap between them to avoid damage to the solder layer during cutting. As shown in Figure 10, the fourth intermediate structure involves removing the connecting portion 80 during the cutting process of the obtained structure, and the semiconductor structure shown in Figure 1 can be obtained through this step. When the fourth intermediate structure is shown in Figure 11, the semiconductor structure shown in Figure 3 can be obtained through this step.

[0115] The embodiments of the semiconductor structure manufacturing method provided in this application and the embodiments of the semiconductor structure belong to the same inventive concept. The descriptions of relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0116] It should be noted that, in the embodiments of this application, the cross-sectional views shown in Figures 1, 3, 5, 6, 8 to 11 are cross-sectional views obtained by cutting the corresponding three-dimensional structure along a direction perpendicular to the back of the chip.

[0117] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0118] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0119] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: A chip unit includes at least one chip, each chip including a front side, a back side opposite to the front side, and a plurality of side surfaces connecting the front side and the back side, wherein the front side of the chip is provided with a plurality of solder pads; A molding compound layer, at least encapsulating the sides of the chip; The first rewiring structure is located on one side of the front of the chip and is electrically connected to the solder pad. The second rewiring structure is located on the side of the first rewiring structure away from the chip, and includes a plurality of spaced sub-wiring structures; each sub-wiring structure contacts the first rewiring structure and leads out at least one of the solder pads; the orthographic projection of the sub-wiring structure on a plane perpendicular to its thickness direction and the orthographic projection of the solder pads it leads out on the same plane do not overlap; in the thickness direction of the sub-wiring structure, the first side of the sub-wiring structure away from the chip cell is continuous. An insulating layer covers at least a portion of the surfaces of the first rewiring structure and the second rewiring structure, with the first side of the sub-wiring structure exposed by the insulating layer; A solder layer that at least covers the first side of the sub-wiring structure.

2. The semiconductor structure according to claim 1, characterized in that, The sub-wiring structure includes a first trace and at least one conductive connection layer, the conductive connection layer including at least one first type of conductive post; the first side of the sub-wiring structure includes the side of the first type of conductive post; The conductive connection layer is provided between the first rewiring structure and the adjacent first trace.

3. The semiconductor structure according to claim 1, characterized in that, The sub-wiring structure includes at least two layers of stacked first traces and at least one conductive connection layer, the conductive connection layer including at least one first type of conductive post; the first side of the sub-wiring structure includes the side of the first type of conductive post; the conductive connection layer is provided between at least two adjacent layers of first traces.

4. The semiconductor structure according to claim 1, characterized in that, The sub-wiring structure includes at least two layers of stacked first traces, and at least two adjacent layers of first traces are in direct contact; among the two directly contacting layers of first traces, the orthographic projection of the first trace away from the encapsulation layer on the plane falls within the orthographic projection of the first trace near the encapsulation layer on the plane, and at least a portion of the edge of the orthographic projection of the first trace away from the encapsulation layer on the plane is located inside the edge of the orthographic projection of the first trace near the encapsulation layer on the plane.

5. The semiconductor structure according to claim 1, characterized in that, The first rewiring structure includes a plurality of spaced second traces, and each of the sub-wiring structures is in contact with the second traces; the second trace includes a second side surface, and the second side surface and the first side surface of the sub-wiring structure in contact with it are located on the same side of the chip cell; The first side of the sub-wiring structure is located on the side of the second side of the second trace that contacts it, close to the chip cell.

6. The semiconductor structure according to claim 1, characterized in that, The first rewiring structure includes a plurality of spaced second traces, and each of the sub-wiring structures is in contact with the second traces; the second trace includes a second side surface, and the second side surface and the first side surface of the sub-wiring structure in contact with it are located on the same side of the chip cell; The first side of the sub-wiring structure and the second side of the second trace that contacts it are on the same plane, and the solder layer covers the second side.

7. The semiconductor structure according to claim 1, characterized in that, The sub-wiring structure includes a first trace and at least one conductive connection layer. The conductive connection layer includes at least one first-type conductive post and at least one second-type conductive post. The first side of the sub-wiring structure includes the side of the first-type conductive post. In the same conductive connection layer, in a direction perpendicular to the thickness direction and parallel to the first side, the width of the side of the first-type conductive post is greater than or equal to the maximum width of the second-type conductive post.

8. The semiconductor structure according to claim 7, characterized in that, The sub-wiring structure is exposed away from the surface of the chip, away from the insulating layer, and is covered by the solder layer.

9. The semiconductor structure according to claim 1, characterized in that, At least two of the sub-wiring structures have their first sides located on the same side of the chip cell; the first sides of each sub-wiring structure located on the same side of the chip cell are located on the same plane.

10. A method for manufacturing a semiconductor structure, characterized in that, The method for manufacturing the semiconductor structure includes: A chip unit is provided, the chip unit including at least one chip; the chip includes a chip front side, a chip back side opposite to the chip front side, and a plurality of chip sides connecting the chip front side and the chip back side, the chip front side having a plurality of solder pads; A molding compound is formed, which at least encapsulates the sides of the chip; A first rewiring structure, a second rewiring structure, and an insulating layer are formed on the side of the molding compound located on the front side of the chip. The first rewiring structure is electrically connected to the solder pads. The second rewiring structure is located on the side of the first rewiring structure away from the chip and includes multiple sub-wiring structures. Each sub-wiring structure contacts the first rewiring structure and leads out at least one solder pad. The orthographic projection of each sub-wiring structure on a plane perpendicular to its thickness direction and the orthographic projection of the solder pad it leads out on the same plane do not overlap. The insulating layer covers the first rewiring structure and the second rewiring structure. The insulating layer and the sub-wiring structure are cut along the cutting path, so that the sub-wiring structure forms a first side away from the chip unit. The orthographic projection of the cutting path on the plane does not overlap with the orthographic projection of the chip unit on the plane. The first side of the sub-wiring structure exposes the insulating layer, and the first side of the sub-wiring structure is continuous in the thickness direction of the sub-wiring structure. A solder layer is formed, the solder layer covering at least a first side of the sub-wiring structure.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The sub-wiring structure includes a first trace and at least one conductive connection layer, the conductive connection layer including at least one first type of conductive post; the conductive connection layer is provided between the rewiring and the adjacent first trace; The orthographic projection of the edge line of the cut channel on the plane overlaps with the orthographic projection of the surface of the first type of conductive post near the encapsulation layer on the plane, and the orthographic projection of the surface of the first type of conductive post away from the encapsulation layer on the plane.

12. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The sub-wiring structure includes at least two layers of stacked first traces and at least one conductive connection layer, wherein the conductive connection layer includes at least one first type of conductive post; the conductive connection layer is provided between at least two adjacent layers of first traces. The orthographic projection of the edge line of the cut channel on the plane overlaps with the orthographic projection of the surface of the first type of conductive post near the encapsulation layer on the plane, and the orthographic projection of the surface of the first type of conductive post away from the encapsulation layer on the plane.

13. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, The conductive connection layer further includes at least one second type of conductive post; before the insulating layer and the sub-wiring structure are cut along the cutting path, in the same conductive connection layer, in a direction perpendicular to the thickness direction and parallel to the first side surface, the maximum width of the first type of conductive post is greater than the maximum width of the second type of conductive post.

14. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The first rerouting structure includes a plurality of second traces arranged at intervals, and each of the subrouting structures is in contact with the second traces; In the step of cutting the insulating layer and the sub-wiring structure along the cutting path, the first rewiring structure is not cut; after cutting the insulating layer and the sub-wiring structure along the cutting path, the portion of the second trace that extends beyond the first side of the sub-wiring structure in contact with it is exposed away from the surface of the encapsulation layer.

15. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The first rerouting structure includes a plurality of second traces arranged at intervals, and each of the subrouting structures is in contact with the second traces; In the step of cutting the insulating layer and the sub-wiring structure along the cutting path, the first rewiring structure is cut at the same time, and the second trace forms a second side surface that is located on the same plane as the first side surface of the sub-wiring structure that is in contact with it; the solder layer covers the second side surface of the second trace.

16. The method for manufacturing a semiconductor structure according to claim 14 or 15, characterized in that, The molding compound encapsulates at least two chip units, and the first rewiring structure is connected to the connector; in the step of cutting the insulating layer and the sub-wiring structure along the dicing path, the first rewiring structure is not cut; after cutting the insulating layer and the sub-wiring structure along the dicing path, the portion of the connector away from the surface of the molding compound is exposed. The formation of the solder layer includes: connecting the connecting portion to the electroplating electrode and forming the solder layer using an electroplating process; After forming the solder layer, the method for manufacturing the semiconductor structure further includes: cutting the obtained structure to remove the connecting portion, thereby obtaining at least two semiconductor structures, each of which includes one chip unit.

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