Solar cell, photovoltaic module and preparation method for solar cell

Abstract

The present application relates to a solar cell, a photovoltaic module, and a preparation method for a solar cell. The solar cell comprises a silicon substrate, a transport layer, and a first electrode; the transport layer is located on a side of the silicon substrate, metal crystals being provided in the transport layer; the first electrode is located on the side of the transport layer away from the silicon substrate, and is electrically connected to the transport layer and the metal crystals; in the width direction of the first electrode, the number of the metal crystals distributed at two end parts of the first electrode is less than the number thereof distributed at other positions of the first electrode except the two end parts. The metal crystals are located below the first electrode and distributed at positions near the middle of the first electrode, which can reduce a transmission path of carriers in the first electrode so as to help the carriers to be directly exported from the first electrode, improving the efficiency of the first electrode collecting the carriers.

Description

Solar cells, photovoltaic modules, and methods for manufacturing solar cells Technical Field

[0001] This application relates to the field of solar photovoltaic technology, and in particular to a solar cell, a photovoltaic module, and a method for preparing a solar cell. Background Technology

[0002] A solar cell is a thin-film photovoltaic semiconductor that directly generates electricity using sunlight. Under certain illumination conditions, a solar cell can instantly output voltage and, if a circuit is present, generate current. It is a device that directly converts light energy into electrical energy through the photoelectric effect or photochemical effect. The electrodes in a solar cell are a crucial component, and their primary function is to collect charge carriers generated by sunlight. However, current solar cells suffer from a slow rate of charge carrier collection by the electrodes. Summary of the Invention

[0003] In view of this, this application proposes a solar cell, a photovoltaic module, and a method for fabricating a solar cell, aiming to at least partially solve the technical problem of slow carrier collection rate at the electrodes in existing solar cells.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] In a first aspect, embodiments of this application provide a solar cell, the solar cell including a silicon substrate, a transport layer and a first electrode; the transport layer is located on one side of the silicon substrate, and a metal crystal is disposed within the transport layer; the first electrode is located on the side of the transport layer away from the silicon substrate, and the first electrode is electrically connected to the transport layer and the metal crystal; along the width direction of the first electrode, the number of metal crystals distributed at the two ends of the first electrode is less than the number distributed at the remaining positions of the first electrode other than the two ends.

[0006] Optionally, along the width direction of the first electrode, the width of each end of the first electrode accounts for 8%-22% of the width of the first electrode.

[0007] Optionally, along the width direction of the first electrode, a preset width L2 is selected within the first electrode, and the total width of the plurality of metal crystals within the preset width range is L1, with L1 / L2 ranging from 50% to 90%.

[0008] Optionally, along the width direction of the first electrode, the width of the first electrode is L4; the total width of the plurality of metal crystals connected to the first electrode is L3, and the range of L3 / L4 is 70%-85%.

[0009] Optionally, the width of the metal crystal along the width direction of the first electrode ranges from 100 nm to 600 nm.

[0010] Optionally, the metal crystal includes a first metal crystal and a second metal crystal; along the width direction of the first electrode, the width range of the first metal crystal is 100nm-200nm, and the width range of the second metal crystal is 300nm-600nm.

[0011] Optionally, the number of the first metal crystals is greater than the number of the second metal crystals.

[0012] Optionally, the thickness of the metal crystal ranges from 50 nm to 300 nm along the thickness direction of the silicon substrate.

[0013] Optionally, the solar cell further includes a second electrode, wherein the melting point of the first electrode is higher than that of the second electrode.

[0014] Optionally, the solar cell further includes: a passivation layer located on the surface of the transport layer away from the silicon substrate; wherein the transport layer is located on the surface of the side of the silicon substrate, and the transport layer includes an electrode region; wherein the first electrode is located on the passivation layer, and the first electrode contacts a portion of the passivation layer and the electrode region; wherein the passivation layer has a first etched region in a portion corresponding to the edge of the electrode region, and the first etched region has a plurality of first pores.

[0015] Optionally, the electrode region includes a pore-free transition region located on the side of the first etched region away from the edge of the electrode region.

[0016] Optionally, at least a portion of the plurality of first holes are blind holes.

[0017] Optionally, the distribution density of the blind holes is 1 to 40 per μm. 2 .

[0018] Optionally, the electrode region includes a second corrosion region located in the middle of the electrode region, the second corrosion region having a plurality of second pores, and the metal crystal located within the second pores.

[0019] Optionally, the diameter of the second hole is larger than the diameter of the first hole.

[0020] Optionally, the surface of the silicon substrate includes an N-region and a P-region, which are located on the same surface or different surfaces of the solar cell, respectively; the transport layer includes an N-type doped semiconductor layer and a P-type doped semiconductor layer, wherein the N-type doped semiconductor layer is located on the N-region and the P-type doped semiconductor layer is located on the P-region; the electrode region of the N-type doped semiconductor layer is designated as the first electrode region, and the electrode region of the P-type doped semiconductor layer is designated as the second electrode region, wherein the area ratio of the second hole located in the first electrode region on the first electrode region is smaller than the area ratio of the second hole located in the second electrode region on the second electrode region.

[0021] Optionally, the area of ​​the second hole located in the first electrode region on the first electrode region is 0% to 60%, and the area of ​​the second hole located in the second electrode region on the second electrode region is 10% to 90%; and / or, the difference between the area of ​​the second hole located in the first electrode region on the first electrode region and the area of ​​the second hole located in the second electrode region on the second electrode region is 10% to 30%.

[0022] Optionally, the surface of the silicon substrate includes an N-region and a P-region, which are located on the same surface or different surfaces of the solar cell, respectively; the passivation layer includes a first passivation layer and a second passivation layer, the first passivation layer being located on the transport layer on the N-region and the second passivation layer being located on the transport layer on the P-region; the first etched region is strip-shaped and extends along the extension direction of the electrode region; along a direction perpendicular to the extension direction of the electrode region, the width of the first etched region located on the first passivation layer is different from the width of the first etched region located on the second passivation layer.

[0023] Optionally, the width of the first etched region in the first passivation layer is greater than the width of the first etched region in the second passivation layer.

[0024] Optionally, the surface of the silicon substrate includes N-regions and P-regions, which are located on the same surface or different surfaces of the solar cell, respectively; the passivation layer includes a first passivation layer and a second passivation layer, the first passivation layer being located on the transport layer on the N-region, and the second passivation layer being located on the transport layer on the P-region; the distribution density of the first pores in the first etched region of the first passivation layer is greater than the distribution density of the first pores in the first etched region of the second passivation layer.

[0025] Optionally, the surface of the silicon substrate includes an N-region and a P-region, which are located on the same surface or different surfaces of the solar cell, respectively; the transport layer includes an N-type doped semiconductor layer and a P-type doped semiconductor layer, wherein the N-type doped semiconductor layer is located on the N-region and the P-type doped semiconductor layer is located on the P-region; the electrode region of the N-type doped semiconductor layer is designated as the first electrode region, and the electrode region of the P-type doped semiconductor layer is designated as the second electrode region, wherein the width of the first electrode region is smaller than the width of the second electrode region.

[0026] Secondly, embodiments of this application provide a photovoltaic module, comprising: a battery string, the battery string including solar cells as described above; and a plurality of solder strips, the solder strips connecting at least two adjacent solar cells.

[0027] Thirdly, embodiments of this application also provide a method for fabricating a solar cell, the method comprising: forming a transport layer on one side of a silicon substrate; forming a first slurry on the side of the transport layer away from the silicon substrate; performing a first sintering of the first slurry at a temperature lower than the melting point of the first slurry to form a first electrode; performing a second sintering of the first electrode to form a metal crystal within the transport layer; and electrically connecting the first electrode to the metal crystal.

[0028] Optionally, the solar cell further includes a second electrode, the second electrode having a melting point lower than that of the first electrode; the fabrication method includes: forming a transport layer on one side of a silicon substrate; forming a first slurry and a second slurry on the side of the transport layer away from the silicon substrate; performing a first sintering on the first slurry and the second slurry at a temperature lower than or equal to the melting point of the second slurry to form a first electrode and a second electrode, respectively; performing a second sintering on the first electrode to form a metal crystal within the transport layer; and electrically connecting the first electrode and / or the second electrode to the metal crystal.

[0029] Optionally, the step of performing a second sintering on the first electrode to form a metal crystal within the transport layer includes: applying a reverse voltage to the first electrode and the second electrode; and performing laser scanning on the first electrode to form a metal crystal within the transport layer.

[0030] In the solar cell of this application, the number of metal crystals distributed at the two ends of the first electrode along the width direction is less than the number distributed at the other positions of the first electrode. The metal crystals are located below the first electrode and distributed near the middle of the first electrode, which reduces the transport path of charge carriers in the first electrode, facilitating the direct extraction of charge carriers from the first electrode and improving the collection efficiency of the first electrode for charge carriers.

[0031] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0033] Figure 1 is a schematic diagram of the structure of a solar cell according to an embodiment of this application;

[0034] Figure 2 is a schematic diagram of another solar cell structure in an embodiment of this application;

[0035] Figure 3 is a transmission electron microscope test image of a solar cell according to an embodiment of this application;

[0036] Figure 4 is a schematic diagram of the electrode sintering temperature curve of a solar cell according to an embodiment of this application;

[0037] Figure 5 is a schematic flowchart of a method for preparing a solar cell according to an embodiment of this application;

[0038] Figure 6 is a schematic flowchart of another method for preparing a solar cell according to an embodiment of this application.

[0039] Figure 7 is a partial structural schematic diagram of the solar cell according to an embodiment of this application;

[0040] Figure 8 is a schematic diagram of the structure of the solar cell according to an embodiment of this application after the electrodes are removed and acid pickling exposes the first corrosion zone and the transition zone;

[0041] Figure 9 is a SEM image of the electrode area of ​​the solar cell according to an embodiment of this application after the electrodes have been removed and acid-washed.

[0042] Figure 10 is a schematic diagram of the overall structure of the back contact battery of an exemplary embodiment of this application;

[0043] Figure 11 is a schematic diagram of the overall structure of a back contact battery in another exemplary embodiment of this application;

[0044] Figure 12 is a schematic diagram of the overall structure of the bifacial battery according to an exemplary embodiment of this application.

[0045] Explanation of reference numerals in the attached figures: 10-Silicon substrate; 21-Dielectric layer; 22-Doped conductive layer; 23-First passivation layer; 24-Transport layer; 25-Tunneling oxide layer; 26-Doped polysilicon layer; 27-Electrode region; 28-Second hole; 29-First etched region; 31-First electrode; 32-Second electrode; 33-Ablation-affected region; 38-First hole; 40-Metal crystal; 50-Fifth passivation layer and second antireflection layer; 111-N-region; 112-P-region; 201-N-type doped semiconductor layer; 202-Doped conductive layer; 203-P-type doped semiconductor layer; 211-Transition region; 212-Second etched region; 301-First passivation and antireflection layer; 302-Third passivation and antireflection layer; 303-Second passivation and antireflection layer. Detailed Implementation

[0046] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art. An embodiment of the present application discloses a solar cell comprising a silicon substrate 10, a transport layer 24, and a first electrode 31; the transport layer 24 is located on one side of the silicon substrate 10, and a metal crystal 40 is disposed within the transport layer 24; the first electrode 31 is located on the side of the transport layer 24 away from the silicon substrate 10, and the first electrode 31 is electrically connected to the transport layer 24 and the metal crystal 40; along the width direction of the first electrode 31, the number of metal crystals 40 distributed at the two ends of the first electrode 31 is less than the number distributed at the remaining positions of the first electrode 31 excluding the two ends. The width direction of the first electrode 31 is the second direction B in FIG1.

[0047] According to embodiments of this application, the silicon substrate 10 can be an N-type silicon substrate or a P-type silicon substrate. Specifically, the silicon substrate 10 can be, for example, a semiconductor material selected from monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon, preferably an N-type or P-type monocrystalline silicon substrate. Cells based on monocrystalline silicon substrates have higher conversion efficiency compared to other types, such as polycrystalline silicon cells. An N-type silicon substrate is obtained by introducing donor impurities such as group VA elements like phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, or a P-type silicon substrate is obtained by introducing acceptor impurities such as group IIIA elements like boron (B), aluminum (Al), or gallium (Ga). Here, no particular limitation is placed on the specific type of silicon substrate 10; in practical applications, those skilled in the art can select a suitable silicon substrate 10 as needed.

[0048] According to embodiments of this application, the surface of the silicon substrate 10 can be the front and / or back of the battery, without limitation. Generally, the front of the battery serves as the light-receiving surface and the back as the backlight surface, or it can be light-receiving on both sides, in which case both the front and back serve as light-receiving surfaces.

[0049] According to embodiments of this application, the transport layer 24 may include semiconductor materials such as monocrystalline silicon, polycrystalline silicon, or microcrystalline silicon, and its doping type may be N-type doping and / or P-type doping. For example, N-type doping can be achieved by introducing donor impurities, such as group VA elements such as phosphorus (P), arsenic (As), or antimony (Sb), into the semiconductor material; or P-type doping can be achieved by introducing acceptor impurities, such as group IIIA elements such as boron (B), aluminum (Al), or gallium (Ga), into the aforementioned semiconductor material.

[0050] According to embodiments of this application, the first passivation layer 23 can be a single-layer film formed of silicon dioxide, aluminum dioxide, silicon nitride, or silicon oxynitride, or a multilayer film composed of one or more of the aforementioned materials. It can simultaneously protect and passivate the underlying silicon substrate 10 or functional layers, such as the transport layer 24, and reduce the reflection of light incident on the surface of the silicon substrate 10. It can be prepared using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD) to form a relatively dense first passivation layer 23.

[0051] According to embodiments of this application, the first electrode 31 can be made of silver, silver-clad copper, aluminum, or copper, etc. Preferred electrode types include silver electrodes, doped aluminum electrodes (doped with group IIIA elements), or silver-aluminum electrodes. The first electrode 31 can be fabricated by printing with a suitable electrode paste, followed by drying, sintering, and photoinjection treatments. The printing method can be, for example, screen printing or inkjet printing, and more preferably, the lower-cost screen printing method. The electrode can include structures such as current collector lines, bus lines, or pads.

[0052] In a solar cell, the first electrode 31 and the second electrode 32 serve to collect charge carriers (including free electrons and holes) generated by illumination and guide them into an external circuit to form an electric current. The first electrode 31 and the second electrode 32 possess high conductivity, good chemical stability, and appropriate mechanical strength, while also being able to effectively collect and transport charge carriers, reduce resistance losses, and improve the efficiency of the solar cell.

[0053] In some embodiments, the width of the first electrode 31 ranges from 10 μm to 80 μm.

[0054] In this embodiment, the metal crystal 40 can be located within the transport layer 24. The metal crystal 40 is electrically connected to a portion of the surface of the first electrode 31 facing the silicon substrate 10. The metal crystal 40 can form a carrier flow channel, which can improve the efficiency of the solar cell.

[0055] In this embodiment, along the width direction of the first electrode 31, the number of metal crystals 40 distributed at the two ends of the first electrode 31 is less than the number distributed at the other positions of the first electrode 31. The metal crystals 40 are located below the first electrode 31 and distributed near the middle of the first electrode 31, which reduces the transport path of charge carriers in the first electrode 31, facilitating the direct extraction of charge carriers from the first electrode 31 and improving the collection efficiency of the first electrode 31 for charge carriers.

[0056] Furthermore, by setting more metal crystals in the transmission layer corresponding to the middle part of the first electrode 31 along the width direction and fewer metal crystals in the transmission layers corresponding to the left and right ends, the etching of the passivation layer at the edge of the first electrode 31 can be reduced, thus reducing the impact on its passivation performance.

[0057] In some embodiments, along the width direction of the first electrode 31, the width of each end of the first electrode 31 accounts for 8%-22% of the width of the first electrode 31.

[0058] In this embodiment of the application, referring to FIG1, along the second direction B, the number of metal crystals 40 distributed at the left and right ends of the first electrode 31 is relatively small. The width of the left end of the first electrode 31, where the number of metal crystals 40 is relatively small, accounts for 8%-22% of the width of the first electrode 31, and the width of the right end of the first electrode 31, where the number of metal crystals 40 is relatively small, accounts for 8%-22% of the width of the first electrode 31. The proportions of the widths of the left and right ends can be the same or different.

[0059] In some embodiments, the specific value of the ratio of each end of the first electrode 31 to the width of the first electrode 31 is set according to the usage requirements. The ratio may be, for example, 8%, 10%, 12%, 14%, 15%, 16%, 18%, 20%, or 22%, but is not limited to the values ​​listed. The ratio may also be a value within the range of the example points.

[0060] In some embodiments, the first electrode 31 includes a busbar and a current collector, with the current collector located on top of the busbar. The current collector is electrically connected to the transport layer 24 and is used to collect charge carriers in the transport layer. The busbar is connected to the solder ribbon during the series connection of the battery string and is used to collect the charge carriers collected in the current collector to the solder ribbon. Along the width direction of the busbar, i.e., the width direction of the first electrode 31, the number of metal crystals 40 distributed at the two ends of the busbar is less than the number distributed at the other positions of the busbar. By placing more metal crystals in the transport layer corresponding to the middle part of the busbar along the width direction and fewer metal crystals in the transport layer corresponding to the left and right ends, the etching of the passivation layer and transport layer 24 at the left and right ends of the busbar can be reduced, thus reducing the impact on its passivation performance. At the same time, the metal crystals placed in the middle part of the busbar, where the transport efficiency is higher, play the role of quickly transporting charge carriers to the busbar, ensuring higher efficiency of charge carrier transport.

[0061] In some embodiments, a preset width L2 is selected within the first electrode 31 along the width direction of the first electrode 31, and the total width of the plurality of metal crystals 40 within the range of the preset width is L1, and the range of L1 / L2 is 50%-90%.

[0062] The preset width L2 within the first electrode 31 is selected according to usage requirements, and this preset width L2 is smaller than the width of the first electrode 31. For example, along the second direction B, a region with a width of 1um-5um is selected below the first electrode 31, and the sum of the horizontal widths of the multiple metal crystals 40 along the second direction B is calculated, which is L1.

[0063] In this embodiment, a preset width L2 is selected within the first electrode 31 along the width direction. The total width of the plurality of metal crystals 40 within the preset width range is L1. When L1 / L2 is within the above range, the ratio of the total width of the plurality of metal crystals 40 within the preset width range to the preset width is relatively large. The metal crystals 40 can form a highly efficient carrier flow channel. A larger number of metal crystals facilitates the movement of carriers to the first electrode 31, accelerates the carrier transport rate, and shortens the time required for carriers to pass through the transport layer 24, effectively improving the efficiency of the solar cell.

[0064] In practical applications, the specific value of L1 / L2 is set according to the usage requirements. For example, L1 / L2 can be 50%, 53%, 55%, 58%, 60%, 65%, 68%, 70%, 72%, 75%, 78%, 80%, 83%, 85%, 87%, or 90%, but it is not limited to the values ​​mentioned. The percentage may also be a value within the range of the example points.

[0065] In some embodiments, the metal crystal 40 contains the same element as the first electrode 31, such as Ag.

[0066] In some embodiments, along the width direction of the first electrode 31, the width of the first electrode 31 is L4, and the total width of the plurality of metal crystals 40 connected to the first electrode 31 is L3, and the range of L3 / L4 is 70%-85%.

[0067] In this embodiment, when L3 / L4 is within the aforementioned range, the ratio of the total width of the plurality of metal crystals 40 to the width of the first electrode 31 is relatively suitable. This can form a highly efficient carrier flow channel, which is beneficial for carriers to move to the first electrode 31, accelerates the carrier transport rate, and forms a highly efficient metal-semiconductor contact structure, effectively improving the efficiency of the solar cell. It can also help reduce the risk of the metal crystals 40 damaging the passivation effect of the transport layer 24, thus taking into account both the contact and passivation performance of the solar cell.

[0068] In some embodiments, the specific values ​​of L3 / L4 are set according to usage requirements. For example, L3 / L4 may be 70%, 72%, 74%, 76%, 78%, 80%, 82%, 84%, or 85%, but are not limited to the values ​​listed. The percentage may also be a value within the range of the example points.

[0069] In some embodiments, the width of the metal crystal 40 along the width direction of the first electrode 31 ranges from 100 nm to 600 nm. When the width of the metal crystal 40 is within the above range along the width direction of the first electrode 31, the width of the metal crystal 40 is relatively large, and the contact area between the metal crystal 40 and the first electrode 31 and the transport layer 24 is large, thereby forming a wider carrier transport channel, which is beneficial for carriers to move to the first electrode 31, accelerates the carrier transport rate, and makes current transport more efficient.

[0070] It is understandable that the width of the metal crystal 40 along the width direction of the first electrode 31 is set according to the usage requirements. For example, the width of the metal crystal 40 is 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, or 600nm, but is not limited to the values ​​mentioned. The width may also be a value within the range of the example points.

[0071] In some embodiments, the metal crystal 40 includes a first metal crystal and a second metal crystal; along the width direction of the first electrode 31, the width range of the first metal crystal is 100nm-200nm, and the width range of the second metal crystal is 300nm-600nm.

[0072] It is understandable that the width of the first metal crystal along the width direction of the first electrode 31 is set according to the usage requirements. For example, the width of the first metal crystal is 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, or 200nm, but is not limited to the values ​​mentioned. The width may also be a value within the range of the example points.

[0073] Similarly, along the width direction of the first electrode 31, the width of the second metal crystal is set according to the usage requirements. For example, the width of the second metal crystal is 300nm, 320nm, 340nm, 360nm, 380nm, 400nm, 420nm, 440nm, 460nm, 480nm, 500nm, 520nm, 540nm, 560nm, 580nm, or 600nm, but is not limited to the values ​​listed. The width may also be a value within the range of the example points.

[0074] In the embodiments of this application, when the width of the first metal crystal is within the above-mentioned range and the width of the second metal crystal is within the above-mentioned range, multiple widths of carrier flow channels can be formed, which is more conducive to the movement of carriers to the first electrode 31, further accelerating the carrier transmission rate and further shortening the time required for carriers to pass through the transmission layer 24.

[0075] Compared with the prior art, the second metal crystal has a larger width in the width direction of the first electrode 31, which can provide a better transmission channel for charge carriers, improve the longitudinal transmission efficiency of charge carriers in the transmission layer 24, and provide more space for the lateral transmission of charge carriers in width, further improving the contact performance of the electrode on the transmission layer 24 of the same thickness.

[0076] In some embodiments, the number of first metal crystals is greater than the number of second metal crystals, which can prevent the second metal crystals from piercing the tunnel oxide layer and can form a highly efficient carrier flow channel, thereby reducing the contact resistance between the first electrode 31 and the transport layer 24.

[0077] In some embodiments, the first metal crystal and the second metal crystal are arranged alternately, and the distance between them cannot be too large, so that electrons can be transferred between adjacent first metal crystals and second metal crystals, thereby improving the photocurrent extraction efficiency of the solar cell.

[0078] In other embodiments, there is a connection between the first metal crystal and the second metal crystal.

[0079] In some embodiments, the thickness of the metal crystal 40 along the thickness direction of the silicon substrate 10 ranges from 50 nm to 300 nm.

[0080] The metal crystal 40 is disposed in the doped conductive layer 22 in the transport layer 24. The thickness of the doped conductive layer 22 ranges from 50nm to 300nm. The metal crystal 40 is of the above size in order to match the thickness of the doped conductive layer 22 and avoid puncturing the doped conductive layer 22.

[0081] In practical applications, the specific thickness of the metal crystal 40 in this embodiment is set according to the usage requirements. For example, along the thickness direction of the silicon substrate 10, the thickness of the metal crystal 40 is 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm, or 300nm, but it is not limited to the values ​​listed. The thickness may also be a value within the range of the example points.

[0082] In some embodiments, the width of the second metal crystal is in the range of 300nm-600nm and the thickness of the second metal crystal is in the range of 50nm-300nm. In this case, the width of the second metal crystal is greater than the thickness of the second metal crystal, which can provide space for the lateral transport of charge carriers, improve the transport efficiency of the doped conductive layer 22, and is beneficial to the improvement of battery efficiency.

[0083] In some embodiments, the solar cell further includes a second electrode 32, and the transport layer 24 includes a doped conductive layer 22. The side of the doped conductive layer 22 facing away from the silicon substrate 10 is connected to the first electrode 31 and / or the second electrode 32. The first metal crystal has a first end and a second end in opposite directions. The first end is connected to the first electrode 31 and / or the second electrode 32, and the second end is located in the doped conductive layer 22.

[0084] In this embodiment, the transport layer 24 may include a doped conductive layer 22 and an ultrathin dielectric layer 21 stacked together. The ultrathin dielectric layer 21 is connected to the silicon substrate 10, and the doped conductive layer 22 is connected to the first electrode 31 and the second electrode 32, or the doped conductive layer 22 is connected to the first electrode 31, or the doped conductive layer 22 is connected to the second electrode 32. The second end of the first metal crystal is located in the doped conductive layer 22. The first metal crystal does not penetrate through the ultrathin dielectric layer 21 into the silicon substrate 10, which not only ensures that the ultrathin dielectric layer 21 is not damaged, but also ensures that its function is not affected. That is, it ensures good chemical passivation and tunneling effect of the ultrathin dielectric layer 21. At the same time, it can also reduce the impact on the turn-on voltage to avoid damage to the silicon substrate 10, ensuring that the function of the silicon substrate 10 is not affected, and thus ensuring the performance of the solar cell.

[0085] In some embodiments, the solar cell further includes a second electrode 32, and the transport layer 24 includes a doped conductive layer 22. The side of the doped conductive layer 22 facing away from the silicon substrate 10 is connected to the first electrode 31 and / or the second electrode 32. The second metal crystal has a first end and a second end in opposite directions. The first end is connected to the first electrode 31 and the second electrode 32 respectively, and the second end is connected to the side of the doped conductive layer 22 close to the silicon substrate.

[0086] In this embodiment, the second end is connected to the side of the doped conductive layer 22 closest to the silicon substrate. The second metal crystal also does not penetrate the ultrathin dielectric layer 21 into the silicon substrate 10. This not only ensures that the ultrathin dielectric layer 21 is not damaged, thus preserving its function, but also guarantees good chemical passivation and tunneling effects. Simultaneously, it reduces the impact on the turn-on voltage, preventing damage to the silicon substrate 10 and ensuring its function remains unaffected, thereby ensuring the performance of the solar cell.

[0087] In some embodiments, the thickness of the doped conductive layer 22 is greater than or equal to 50 nm and less than or equal to 300 nm.

[0088] It is understandable that the thickness of the doped conductive layer 22 is set according to the application requirements. For example, the thickness of the doped conductive layer 22 is 50nm, 70nm, 90nm, 110nm, 130nm, 150nm, 170nm, 190nm, 210nm, 220nm, 240nm, 250nm, 270nm, 290nm, 300nm, but is not limited to the values ​​listed. The thickness may also be a value within the range of the example points.

[0089] As one possible implementation, the aforementioned solar cell can be a back-contact solar cell. The following description uses a back-contact solar cell as an example; it should be understood that the following description is for illustrative purposes only and not for specific limitation. Specifically, referring to Figures 1 and 3, the solar cell includes a silicon substrate 10, a first electrode 31, and a second electrode 32. Along the thickness direction of the solar cell, i.e., in the first direction C, the silicon substrate 10 has two surfaces, which are the backlight surface and the light-receiving surface of the silicon substrate 10, respectively. The first electrode 31 and the second electrode 32 are both located on the backlight surface side of the silicon substrate 10. The silicon substrate 10 can be N-doped or P-doped.

[0090] In some embodiments, referring to FIG1, the transport layer 24 includes an ultrathin dielectric layer 21 and a doped conductive layer 22, which are stacked together. The dielectric layer 21 is connected to the backlight surface of the silicon substrate 10. A first electrode 31 is connected to the doped conductive layer 22, and a second electrode 32 is connected to the backlight surface of the silicon substrate 10. A metal crystal 40 is disposed on a portion of the surface of the first electrode 31 facing the silicon substrate 10, and the metal crystal 40 is disposed within the doped conductive layer 22. It should be understood that although FIG1 shows the transport layer 24 including the dielectric layer 21, the dielectric layer 21 is an optional layer, and embodiments of the transport layer 24 excluding the dielectric layer 21 are also within the scope of this application.

[0091] According to the above structure of the embodiments of this application, the solar cell is a back-contact cell, with the metal crystal 40 located within the doped conductive layer 22, and the metal crystal 40 in full contact with the doped conductive layer 22. Under the action of the metal crystal 40, the movement of charge carriers to the first electrode 31 is facilitated, accelerating the carrier transport rate and shortening the time required for charge carriers to pass through the doped conductive layer 22, thereby improving the cell efficiency of the back-contact cell. Since the metal crystal 40 is located within the doped conductive layer 22, it does not disrupt the function of the dielectric layer 21, thus increasing the cell efficiency while ensuring the passivation and tunneling effects of the dielectric layer 21.

[0092] Furthermore, one transport layer includes an ultrathin dielectric layer 21 and a doped conductive layer 22, wherein the doped conductive layer 22 is a doped polysilicon layer; the other transport layer includes a doped conductive layer, wherein the top surface of the doped conductive layer is coplanar with the surface of the silicon substrate 10, and the doped conductive layer is a diffusion layer formed on the surface of the silicon substrate 10.

[0093] The metal crystal 40 is located within the doped conductive layer 22. The metal crystal 40 does not disrupt the function of the dielectric layer 21, thus improving the solar cell efficiency while ensuring the passivation and tunneling effects of the dielectric layer 21. When the metal crystal 40 is located within the diffusion layer, it can still provide a carrier transport path, reducing the time required for carriers to transport to the second electrode 32. However, compared to when the metal crystal 40 is located within the doped polycrystalline silicon layer, the metal crystal 40 carries a greater risk of damaging the silicon substrate.

[0094] In some embodiments, as shown in FIG1, the solar cell further includes a fifth passivation layer and a second antireflection layer 50, the fifth passivation layer and the second antireflection layer 50 being disposed on the light-receiving surface of the silicon substrate 10.

[0095] The antireflection layer is made of one or more of silicon nitride, silicon oxynitride, and aluminum oxide, in a single-layer or stacked structure. The passivation layer is used to reduce charge recombination and surface reflection within the solar cell, thereby improving the cell's efficiency and performance. The passivation layer is made of one or more of silicon oxide, silicon nitride, and aluminum oxide.

[0096] In some embodiments, referring to FIG1, the solar cell further includes a first passivation layer 23, which is disposed on the back surface of the silicon substrate 10 and connected to the side of the silicon substrate 10 and the transport layer 24 opposite to the silicon substrate 10. The first passivation layer 23 includes a single layer or a stacked structure of one or more materials selected from aluminum oxide and silicon nitride.

[0097] In some embodiments, referring to FIG2, the transport layer 24 includes a first transport layer (the first transport layer includes a dielectric layer 21 and a doped conductive layer 22 stacked together) and a second transport layer (the second transport layer includes a tunneling oxide layer 25 and a doped polysilicon layer 26 stacked together); the back surface of the silicon substrate 10 is provided with the first transport layer and the second transport layer respectively, and the first transport layer and the second transport layer are spaced apart; the first electrode 31 is connected to the surface of the first transport layer away from the silicon substrate 10, and the second electrode 32 is connected to the surface of the second transport layer away from the silicon substrate 10; a metal crystal 40 is disposed on a portion of the surface of the first electrode 31 facing the silicon substrate 10, and the metal crystal 40 is disposed within the first transport layer; the metal crystal 40 is disposed on a portion of the surface of the second electrode 32 facing the silicon substrate 10, and the metal crystal 40 is disposed within the second transport layer. Similar to what has been described above, it should be understood that although Figure 2 shows that the transport layer 24 includes a dielectric layer 21 and a tunneling oxide layer 25, the dielectric layer 21 and the tunneling oxide layer 25 are optional layers, and a scheme in which the transport layer 24 does not include the dielectric layer 21 and the tunneling oxide layer 25 is also within the scope of this application.

[0098] In this embodiment, the solar cell is a back-contact cell, with the metal crystal 40 located within the first transport layer and in full contact with it. Under the influence of the metal crystal 40, the movement of charge carriers to the first electrode 31 is facilitated, accelerating the carrier transport rate and improving the cell efficiency of the back-contact cell.

[0099] The metal crystal 40 is located within the second transport layer and is in full contact with the second transport layer. Under the influence of the metal crystal 40, the movement of charge carriers to the second electrode 32 is facilitated, accelerating the charge carrier transport rate and improving the efficiency of the back-contact solar cell.

[0100] Furthermore, in the embodiments of this application, the materials of the dielectric layer 21 and the doped conductive layer 22 can be selected according to the type of solar cell. For example, the dielectric layer 21 includes a tunneling oxide layer, an intrinsic amorphous silicon layer, etc., and the doped conductive layer 22 includes a doped amorphous silicon layer, a doped polycrystalline silicon layer, etc.

[0101] The backlight surface of the silicon substrate 10 is provided with a first transmission layer and a second transmission layer. The first and second transmission layers are spaced apart in two ways: one is that, along the extension direction of the backlight surface of the silicon substrate 10 (i.e., in the second direction B), the first and second transmission layers are alternately spaced on the backlight surface of the silicon substrate 10, and they may be in contact or not in contact along the extension direction of the backlight surface of the silicon substrate 10; the other is that, along the extension direction of the backlight surface of the silicon substrate 10 (i.e., in the second direction B), the first and second transmission layers are alternately spaced on the backlight surface of the silicon substrate 10, and they partially overlap along the thickness direction of the silicon substrate 10 (i.e., in the first direction C). The first and second transmission layers are of different types; one is an electron transmission layer, and the other is a hole transmission layer.

[0102] In some embodiments, the back-side transport layer 24 includes a third passivation layer and a third doped layer, which are stacked together. The third passivation layer is connected to the back surface of the silicon substrate 10. The front-side transport layer 24 includes a doped conductive layer, the top surface of which is coplanar with the light-receiving surface of the silicon substrate 10. The doped conductive layer is a diffusion layer formed on the surface of the silicon substrate. A fourth passivation layer and a first antireflection layer are stacked on the diffusion layer. The first electrode 31 is connected to the surface of the third doped layer facing away from the silicon substrate 10, and the second electrode 32 is connected to the surface of the first antireflection layer facing away from the silicon substrate 10. A metal crystal 40 is disposed on a portion of the surface of the first electrode 31 facing the silicon substrate 10, and the metal crystal 40 is disposed within the third doped layer.

[0103] In this embodiment, the solar cell is a Topcon (Tunnel Oxide Passivated Contact) cell, in which the metal crystal 40 is located within the third doped layer and is in full contact with the third doped layer. Under the influence of the metal crystal 40, the Topcon cell facilitates the movement of charge carriers to the first electrode 31, accelerating the carrier transport rate and improving the cell efficiency.

[0104] In some embodiments, the first electrode 31 is silver, and the second electrode 32 is either silver or aluminum.

[0105] In this embodiment, the materials of the first electrode 31 and the second electrode 32 can be selected according to usage requirements. Silver and aluminum are both materials with high conductivity and good chemical stability. In practical applications, other materials can also be used to fabricate the first electrode 31 and the second electrode 32.

[0106] In some embodiments, the metal crystal 40 may be formed using LECO (Laser-enhanced contact optimization) technology. The metal crystal may also be formed using other electrode sintering methods, which are not specifically limited here.

[0107] Among them, LECO technology is a laser-induced localized and microscopic metal-semiconductor contact optimization process. LECO technology, combined with a special paste, reduces the contact resistance between silicon and metal without increasing recombination in the contact area, thereby improving the passivation of solar cells and significantly increasing their efficiency. Furthermore, it can also improve defects such as haze in solar cells, greatly improving the yield of solar cells.

[0108] In some embodiments, the melting point of the first electrode 31 is higher than that of the second electrode 32. After the first electrode 31 and the second electrode 32 are sintered, the LECO technology enables the first electrode 31 to form a metal crystal 40.

[0109] In a solar cell, the first electrode 31 and the second electrode 32 are sintered together. During the sintering process, under-sintering or over-sintering may occur. (For example, the first electrode 31 includes Ag, and the second electrode 32 includes Al. The melting point of Ag is 961°C, and the melting point of Al is 660°C. When selecting a suitable sintering temperature, this temperature is lower than the melting temperature of Ag and higher than the melting temperature of Al. Therefore, the sintering temperature of Ag and Al is not the optimal temperature, which may result in under-sintering or over-sintering.) Neither under-sintering nor over-sintering meets the ideal sintering requirements of a solar cell. Under-sintering results in incomplete formation of ohmic contacts, leading to a larger series resistance and a lower fill factor. Over-sintering increases the probability of carrier recombination and results in a lower on-state voltage.

[0110] In this embodiment, when the first electrode 31 and the second electrode 32 are sintered, a temperature lower than or equal to that suitable for sintering the second electrode 32 can be used for sintering. At this time, the first electrode 31 is under-sintered. Then, laser-enhanced contact optimization technology is used to sinter the first electrode 31 for the second time, so as to form a metal crystal 40 on the surface of the first electrode 31 facing the silicon substrate 10.

[0111] For example, consider a first electrode 31 comprising Ag and a second electrode 32 comprising Al. The Al paste is kept within an ideal process temperature range during sintering (this ideal process temperature range is lower than the sintering temperature of conventional sintering processes; see Figure 4 for details, which shows a schematic diagram of sintering time and temperature curves for conventional sintering and LECO sintering processes). At this time, the Ag paste is in an under-sintered state. Through the LECO process, the Ag paste forms metal crystals 40 with local micro-regions of the silicon substrate 10 in a short time, forming a contact. Simultaneously, because the Al paste, with its relatively low melting point, is within the ideal process temperature range during sintering, combined with the localized LECO process, recombination losses during production are significantly reduced, enhancing the performance of the metal-semiconductor contact structure and improving solar cell efficiency. Furthermore, it can also improve defects such as haze, significantly increasing product yield.

[0112] In the sintering process with LECO, after the sintering process, an additional LECO process step is added. Referring to Figure 2, a laser of a specific wavelength is used to scan the grid surface of the solar cell. The specific scanning area can be the positive or negative electrode area of ​​the grid surface of the solar cell, or the positive and negative electrode areas can be irradiated simultaneously. The irradiation time and laser scanning method are determined by the process requirements. At the same time, a reverse voltage is applied to the positive and negative electrodes of the solar cell.

[0113] The LECO process is used in the manufacturing process of solar cells. The laser's role is to excite charge carriers with high energy for a short time. Then, under the influence of a reverse voltage, the charge carriers form local current transport channels, thus creating a metal-semiconductor contact. In solar cells, the reverse voltage applied to the LECO process needs to be within a certain range (e.g., 0V–20V), the laser power needs to be within a certain range (e.g., 10%–90% Pmax), and the scanning time needs to be determined by maintaining an appropriate laser scanning speed. This LECO process significantly improves the efficiency of solar cells; furthermore, because the LECO process can further improve the contact, it also significantly improves inefficient cells and EL fogging caused by poor contact.

[0114] In this embodiment, along the width direction of the first electrode 31, the number of metal crystals 40 distributed at the two ends of the first electrode 31 is less than the number distributed at the other positions of the first electrode 31. The metal crystals 40 are located below the first electrode 31 and distributed near the middle of the first electrode 31, which reduces the transport path of charge carriers in the first electrode 31, facilitating the direct extraction of charge carriers from the first electrode 31 and improving the collection efficiency of the first electrode 31 for charge carriers.

[0115] This application discloses a photovoltaic module, which includes a cover plate, a back plate, and a solar cell disposed between the cover plate and the back plate; the solar cell includes the solar cell described above.

[0116] This application does not specifically limit whether the photovoltaic module includes other structures. For example, the photovoltaic module may also include: a first encapsulating film disposed between the cover plate and the solar cell, and a second encapsulating film disposed between the back sheet and the solar cell.

[0117] Photovoltaic modules and solar cells can be referenced to each other and have the same or similar beneficial effects as any of the aforementioned solar cells. To avoid repetition, they will not be described again here.

[0118] The present application will be further described in detail below with reference to specific embodiments.

[0119] Example

[0120] Referring to FIG1, in the solar cell, the back surface of the silicon substrate 10 is provided with a dielectric layer 21 and a doped conductive layer 22, which are stacked. The dielectric layer 21 is connected to the back surface of the silicon substrate 10. The light-receiving surface of the silicon substrate 10 is provided with a fifth passivation layer and a second antireflection layer 50.

[0121] The first electrode 31 is connected to the doped conductive layer 22, and the second electrode 32 is connected to the light-receiving surface of the silicon substrate 10; the metal crystal 40 is disposed on the part of the surface of the first electrode 31 facing the silicon substrate 10, and the metal crystal 40 is disposed within the doped conductive layer 22.

[0122] The metal crystal 40 includes a first metal crystal and a second metal crystal, which are arranged alternately. Along the width direction of the first electrode 31, the width range of the first metal crystal is 100nm-200nm, and the width range of the second metal crystal is 300nm-600nm.

[0123] Comparative Example

[0124] The difference from the above embodiments is that the metal crystal 40 only includes a third metal crystal. Along the width direction of the first electrode 31, the width range of the third metal crystal is 5nm-50nm, and the rest is the same as the above embodiments.

[0125] Performance tests were conducted on 1000 solar cells formed in the above embodiments and 1000 solar cells formed in the above comparative examples under the same test conditions, with different process parameters. The test results are shown in Table 1 below.

[0126] Table 1

[0127] In Table 1, the data for each example (groups SY1, SY2, and SY3) are obtained by arithmetically averaging the test results of 1000 solar cells corresponding to the above examples. In Table 1, bias voltage V, power P, and sweep rate v are all process parameters during testing. Eta represents the conversion efficiency of the solar cell, Uoc represents the open-circuit voltage of the solar cell, Isc represents the short-circuit current of the solar cell, and FF represents the fill factor of the solar cell.

[0128] As can be seen from Table 1 above, the efficiency of the embodiment is higher than that of the comparative example (Group BSL). The main reason is that in the embodiment, the metal crystal 40 includes both a first metal crystal and a second metal crystal. Along the width direction of the first electrode 31, the width range of the first metal crystal is 100nm-200nm, and the width range of the second metal crystal is 300nm-600nm. Multiple widths of carrier flow channels can be formed in the solar cell, which is more conducive to the movement of carriers to the first electrode 31, accelerates the carrier transport rate, further shortens the time required for carriers to pass through the transport layer 24, and effectively improves the efficiency of the solar cell.

[0129] This application also discloses a method for fabricating a solar cell. Referring to FIG5, the method includes the following steps:

[0130] S11, a transport layer 24 is disposed on one side of the silicon substrate 10.

[0131] In this step, a transport layer 24 can be deposited on one side of the silicon substrate 10 using a process such as low-pressure chemical vapor deposition.

[0132] S12, a first paste is disposed on the side of the transport layer 24 away from the silicon substrate 10.

[0133] In this step, the first paste can be printed on the side of the transport layer 24 away from the silicon substrate 10 by printing.

[0134] S13, the first slurry is sintered for the first time at a temperature lower than the melting point of the first slurry to form the first electrode 31.

[0135] In this step, the first slurry is sintered for the first time at a temperature lower than the melting point of the first slurry to form the first electrode 31. At this time, the first electrode 31 formed may be under-sintered, which will result in the ohmic contact not being fully formed and the series resistance being too large.

[0136] S14, the first electrode 31 is sintered for the second time to form a metal crystal 40 in the transport layer 24; the first electrode 31 is electrically connected to the metal crystal 40.

[0137] In this step, the first electrode 31, which was under-sintered in step S13, is sintered a second time to form a metal crystal 40 in the transport layer 24, thereby enhancing the performance of the metal-semiconductor contact structure and improving the efficiency of the solar cell.

[0138] The solar cell fabrication method of this application embodiment employs a two-stage sintering process. The first sintering uses a temperature below the melting point of the first slurry to avoid over-sintering, but under-sintering may occur. The second sintering forms a metal crystal 40 within the transport layer 24. This metal crystal 40 creates a highly efficient carrier flow channel, facilitating carrier movement to the first electrode 31, accelerating carrier transport, and shortening the time required for carriers to traverse the transport layer 24, thus effectively improving the efficiency of the solar cell.

[0139] This application also discloses another method for fabricating a solar cell, wherein the solar cell further includes a second electrode 32, the melting point of which is lower than that of the first electrode 31; referring to FIG6, the fabrication method includes the following steps:

[0140] S21, a transport layer 24 is disposed on one side of the silicon substrate 10.

[0141] This step refers to step S11 above, and will not be repeated in this embodiment of the application.

[0142] S22, a first paste and a second paste are disposed on the side of the transport layer 24 away from the silicon substrate 10.

[0143] In this step, a printing method can be used to print the first paste and the second paste on the side of the transport layer 24 away from the silicon substrate 10.

[0144] S23, the first slurry and the second slurry are sintered for the first time at a temperature lower than or equal to the melting point of the second slurry to form the first electrode 31 and the second electrode 32, respectively.

[0145] In this step, the first slurry and the second slurry are sintered for the first time at a temperature lower than or equal to the melting point of the second slurry, so that the second electrode 32 has a better sintering structure, while the first electrode 31 is under-sintered.

[0146] S24, the first electrode 31 is sintered a second time to form a metal crystal 40 in the transport layer 24; the first electrode 31 and / or the second electrode 32 are electrically connected to the metal crystal 40.

[0147] In some embodiments, referring to FIG2, step S24 further includes the following steps: applying a reverse voltage V to the first electrode 31 and the second electrode 32; performing laser D-scanning on the first electrode 31 to form a metal crystal 40 within the transport layer 24. At this time, when the laser D-scans the first electrode 31, it can excite the charge carriers with high energy for a short time. Then, under the action of the reverse voltage, the charge carriers will form a local current transport channel, thereby forming a metal-semiconductor contact, that is, forming the metal crystal 40.

[0148] The method for preparing a solar cell according to the present application employs a method of simultaneously printing a first paste and a second paste and sintering twice to prepare the first electrode 31 and the second electrode 32. This method can reduce processing steps, improve processing efficiency, and avoid the impact of over-sintering or under-sintering on the efficiency of the solar cell.

[0149] In realizing the concept of this application, it was also discovered that by selecting a suitable fabrication process to control the edge structure of the electrode, a porous structure is formed on the passivation layer at the edge of the electrode region located in the doped semiconductor layer, and metal crystals are set in the porous structure. This can increase the contact area between the electrode edge and the passivation layer, thereby improving the adhesion of the electrode and thus improving the reliability of the battery.

[0150] Specifically, according to one aspect of the present application, a solar cell is provided. FIG7 is a partial structural schematic diagram of the solar cell of the present application embodiment. As shown in FIG7, the solar cell provided in the present application embodiment includes a silicon substrate 10, a transport layer 24, a first passivation layer 23, and a first electrode 31, wherein: the first passivation layer 23 may be a passivation antireflection layer; the transport layer 24 includes the doped conductive layer 22 described above and an optional dielectric layer 21; the transport layer 24 is located on the surface of the silicon substrate 10, and the transport layer 24 includes an electrode region 27, as shown in the dashed box; the first passivation layer 23 is located on the surface of the transport layer 24 away from the silicon substrate 10; the first electrode 31 is located on the first passivation layer 23, and the first electrode 31 is in contact with the portion of the first passivation layer 23 and the electrode region 27.

[0151] The surface of the silicon substrate 10 can be a polished surface, and can have discretely distributed tower base structures, which is suitable for obtaining a relatively flat first passivation layer 23 on the polished surface, so as to facilitate the formation of a first etched area 29 with multiple first pores 38.

[0152] The surface of the silicon substrate 10 can be a region suitable for separating and / or transporting charge carriers. Further, the surface region of the silicon substrate 10 where a doped semiconductor layer is formed can be a conductive region. Optionally, depending on the conductivity type, the surface of the silicon substrate 10 can include N-regions and / or P-regions, which can be located on the same surface or different surfaces of the solar cell. Wherein, if they are on the same surface, the N-region and P-region can be partial regions of one surface of the silicon substrate 10; where they are on different surfaces, the N-region and P-region can each be at least a partial region of one surface of the silicon substrate 10, i.e., either the entire surface of the silicon substrate 10 or a partial region of its surface.

[0153] The electrode region 21 of the transport layer 24 represents the area that can be used to form an electrode, allowing the electrode to contact the transport layer 24 in that region. This is because, considering the precision of the electrode manufacturing process, the electrode region 27 includes an area where the electrode position can be reasonably adjusted.

[0154] According to an embodiment of this application, the first passivation layer 23 located at the edge of the electrode region 27 has a first corrosion region 29, and the first corrosion region 29 has a plurality of first pores 38. This application selects a suitable fabrication process to fabricate the passivation layer and the electrode, so that after sintering, a first corrosion region suitable for contact with the electrode can be formed on the passivation layer located at the edge of the electrode region. The porous structure of the first corrosion region increases the contact area between the electrode edge and the passivation layer, thereby improving the electrode's adhesion and thus improving battery reliability. By providing a first corrosion region with a plurality of first pores on the passivation layer located at the edge of the electrode region, the contact area between the electrode and the passivation layer is increased, improving the electrode's adhesion to the passivation layer, thereby improving the electrode's tensile strength and battery reliability.

[0155] The projection size of the first etched region 29 on the silicon substrate surface is less than or equal to the projection size of the left or right end of the first electrode on the silicon substrate surface. Specifically, the projection size of the first etched region 29 at the left edge of the electrode region 27 along the extension direction of the electrode region on the silicon substrate surface is less than or equal to the projection size of the left end of the first electrode along the extension direction of the first electrode on the silicon substrate surface, and / or the projection size of the first etched region 29 at the right edge of the electrode region 27 along the extension direction of the electrode region on the silicon substrate surface is less than or equal to the projection size of the right end of the first electrode along the extension direction of the first electrode on the silicon substrate surface. The projection size can also be the projection size per unit length along the extension direction of the electrode region.

[0156] According to an embodiment of this application, the first passivation layer 23 located at the edge of the electrode region 27 has a first corrosion region 29, and the first corrosion region 29 has a plurality of first pores 38. This application selects a suitable fabrication process to fabricate the passivation layer and the electrode, so that after sintering, a first corrosion region suitable for contact with the electrode can be formed on the passivation layer located at the edge of the electrode region. The first pores 38 in the first corrosion region are suitable for accommodating the metal crystals or glass formed after sintering the first electrode 31. Based on this, along the width direction of the first electrode 31, the number of metal crystals 40 distributed at the two ends of the first electrode 31 is less than the number distributed at other locations of the first electrode 31. Providing first pores 38 in the passivation layer at the edge of the electrode region 27 increases the contact area between the electrode edge and the passivation layer. Simultaneously, providing a smaller number of metal crystals in the transport layer at the electrode end can increase the contact area with the passivation layer, thereby improving tensile strength. Furthermore, reducing the number of metal crystals in the transport layer at the electrode end avoids excessive corrosion of the passivation layer, ensuring the passivation performance at the electrode end.

[0157] According to embodiments of this application, at least a portion of the plurality of first holes 38 are blind holes, suitable for accommodating the metal crystal or glass body formed after the first electrode 31 is sintered, for improving the tensile strength of the first electrode 31, wherein the metal crystal is an alloy containing the electrode metal element and silicon element, such as a silver-silicon alloy. Further optionally, the distribution density of blind holes is 1 to 40 holes / μm. 2 For example, it could be 1 / μm 2 5 per μm 2 8 per μm 2 10 cells / μm 2 15 cells / μm 2 18 cells / μm 2 20 cells / μm 2 25 cells / μm 2 30 cells / μm 2 35 cells / μm 2 40 cells / μm 2 A small number of blind holes is detrimental to improving the adhesion of the first electrode 31 to the first passivation layer 23. The "distribution density" in this application can refer to the number of characterization objects, such as blind holes, within a characterization area per unit area, such as the first corrosion zone.

[0158] This application does not impose any restrictions on the measurement of the distribution density of blind holes. Those skilled in the art can perform the measurement using conventional methods in the field. For example, an image of the surface of the battery cell after electrode removal and acid washing can be acquired using a scanning electron microscope (SEM). On the SEM top view obtained by measurement, at least one area of ​​the same size, for example 1 μm, can be selected. 2 Within a given region, the number of blind holes observed in each region is counted. The number of blind holes per unit area within each region is then calculated, and the average value is taken as the blind hole distribution density. It is important to note that, to reduce the impact of image acquisition resolution and statistical errors, blind holes with a diameter less than 20 nm are excluded from the measurement range when measuring their diameter and distribution density.

[0159] According to embodiments of this application, optionally, the aperture and distribution of the first hole 38 on the first etched region 29 may differ depending on whether the transport layer 24 is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0160] For example, the passivation layer located on the N-type doped semiconductor layer is the first passivation layer, and the passivation layer located on the P-type doped semiconductor layer is the second passivation layer. The aperture of the first hole in the first passivation layer is 20-300 nm, such as 20 nm, 50 nm, 80 nm, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm, etc. The aperture of the first hole in the second passivation layer is 40-400 nm, such as 40 nm, 50 nm, 80 nm, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm, 330 nm, 350 nm, 380 nm, 400 nm, etc.

[0161] For example, the distribution density of the first pores located on the first corrosion zone of the first passivation layer is 10 to 40 pores / μm. 2 For example, it could be 10 per μm 2 15 cells / μm 2 20 cells / μm 2 25 cells / μm 2 30 cells / μm 2 35 cells / μm 2 40 cells / μm 2 The distribution density of the first pores located in the first corrosion zone of the second passivation layer is 1–20 per μm. 2 For example, it could be 1 / μm 2 5 per μm2 8 per μm 2 10 cells / μm 2 15 cells / μm 2 18 cells / μm 2 20 cells / μm 2 wait.

[0162] For example, the width of the first etched region located in the first passivation layer is 0.2 to 4 μm, such as 0.2 μm, 0.5 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.0 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3.0 μm, 3.3 μm, 3.5 μm, 3.8 μm, 4.0 μm, etc., and the width of the first etched region located in the second passivation layer is 0.1 to 2 μm, such as 0.1 μm, 0.3 μm, 0.5 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.0 μm, etc.

[0163] Regarding the measurement of the aperture of the first hole, this application does not impose any restrictions. Those skilled in the art can measure it using conventional methods in the field. For example, an image can be acquired on the surface of the battery cell after the electrodes have been removed and acid-washed using a scanning electron microscope (SEM). On the top view of the SEM obtained by measurement, the aperture of the observed hole can be statistically analyzed. The maximum diagonal dimension of the first hole in a certain direction can be used as the aperture, or the diameter of an equivalent circle with the same area as the first hole can be used as the aperture, which is beneficial to simplify measurement and statistical analysis.

[0164] This application does not impose any restrictions on the measurement of the distribution density of the first pore. Those skilled in the art can determine it using conventional methods in the field. For example, at least one area of ​​the same size, such as 1 μm, can be taken from the above SEM top view. 2 The number of first holes observed in each region is counted, and the number of first holes per unit area in each region is calculated and averaged to obtain the distribution density of the first holes. It should be noted that, to reduce the impact of image acquisition resolution and statistical errors, first holes with a diameter less than 20 nm are not included in the measurement range when measuring the pore size and distribution density.

[0165] This application does not impose any restrictions on the measurement of the width of the first corrosion zone. Those skilled in the art can measure it using conventional methods in the field. For example, on the above SEM top view, a region within a certain length range, such as 10 μm, can be taken in the extension direction of the first corrosion zone, and the average width of the first corrosion zone within this length range can be calculated.

[0166] Thus, by configuring the passivation layer on the N-type doped semiconductor layer as a porous structure with a fine and / or densely distributed pore pattern, and further combining it with a first etched region of considerable width, the reliability of the electrodes on the N-type doped semiconductor layer can be significantly improved. Alternatively, by configuring the passivation layer on the P-type doped semiconductor layer as a porous structure with a coarse and / or sparsely distributed pore pattern, and further combining it with a first etched region of relatively small width, the reliability of the electrodes on the P-type doped semiconductor layer can be improved while reducing damage to the passivation layer at the electrode edges, thereby reducing recombination losses. Especially for N-type silicon substrates with higher minority carrier lifetimes, the PN junction region involves the injection and recombination of minority carriers, and reducing junction recombination losses is even more beneficial for improving photoelectric conversion efficiency.

[0167] According to an embodiment of this application, Figure 8 is a schematic diagram of the structure of a solar cell according to an embodiment of this application after the electrodes are removed and acid-washed to expose the first etched region and the transition region, wherein the electrode region 27 is indicated by a dashed box. As shown in Figure 8, the electrode region 27 includes a non-porous transition region 211, which is located on the side of the first etched region 29 away from the edge of the electrode region 27. The transition region 211 can disperse the contact stress of the first electrode 31 between the transport layer 24 and the first passivation layer 23, thereby improving the connection reliability of the electrode.

[0168] According to an embodiment of this application, the first passivation layer 23 at both sides of the electrode region 27 has a first corrosion region 29, and a transition region 211 is provided on the side of the two first corrosion regions 29 away from the edge of the electrode region 27, thereby improving the contact stress balance of the first electrode 31 and improving the connection reliability of the first electrode 31.

[0169] To better illustrate the morphology of the electrode region, this application sequentially acid-washes the solar cell with NHNO3-HF-HNO3 solution after electrode removal, exposing the transport layer 24 and the first passivation layer 23. Figure 9 shows the SEM characterization of the electrode region of the solar cell in this embodiment after electrode removal and acid washing, where the dashed line marks part of the boundary between the transition region 211 and the first etched region 29. As shown in Figures 8 and 9, it can be seen that a transition region 211 is provided on the side of the first etched region 29 away from the edge of the electrode region 27. This is a pore-free region, presumably formed due to factors such as the wetting angle of the electrode paste, glass frit distribution, and sintering shrinkage during the solar cell fabrication process. It should be noted that the pore-free region here refers to a region where obvious pores are difficult to observe, for example, a region where the pore size is all less than 20 nm.

[0170] According to an embodiment of this application, at least a portion of the transition region 211 may be covered or not covered by the first passivation layer 23, and obviously the covered first passivation layer 23 is pore-free or has barely observable pores.

[0171] For example, the width of the transition region 211 is 0% to 35% of the width of the electrode region, such as 0%, 5%, 10%, 15%, 20%, 25%, 30%, etc. If the width of the transition region 211 is too large, the contact space between the first electrode 31 and the first passivation layer 23 and the transport layer 24 will be small, resulting in a decrease in the tensile strength of the electrode.

[0172] According to embodiments of this application, as shown in Figures 7, 8, and 9, the electrode region 27 may further include a second etched region 212, located in the middle of the electrode region 27, and having a plurality of second pores 28. The second pores 28 are suitable for accommodating the metal crystal or glass formed after the first electrode 31 is sintered, thereby improving the tensile strength of the first electrode 31. Simultaneously, the increased contact area between the first electrode 31 and the transport layer 24 helps improve the contact performance between the first electrode 31 and the transport layer 24.

[0173] The projection of the second etched region 212 onto the silicon substrate surface and the projection of the remaining positions of the first electrode 31, excluding the two ends, onto the silicon substrate surface at least partially overlap in the width direction of the first electrode 31.

[0174] According to an embodiment of this application, the second etched region 212 has a plurality of second holes 28. The second holes 28 are suitable for accommodating the metal crystals or glass bodies formed after the first electrode 31 is sintered. Compared with the arrangement where the metal crystals are located at the interface between the transport layer 24 and the first electrode 31, the second holes in the second etched region for accommodating the metal crystals increase the contact area between the metal crystals and the transport layer 24, which helps to improve the contact performance between the first electrode 31 and the transport layer 24. On this basis, along the width direction of the first electrode 31, the number of metal crystals 40 distributed at the two ends of the first electrode 31 is less than the number distributed at the other positions of the first electrode 31. This allows more metal crystals 40 to be disposed in the transport layer corresponding to the middle part of the first electrode 31. Taking advantage of the characteristic that the lower resistance of the metal crystals makes them easier to become carrier transport channels, the carriers can be transported from the middle part of the electrode with a higher probability, thereby improving the carrier collection efficiency of the first electrode 31.

[0175] According to an embodiment of this application, the aperture of the second hole 28 is larger than the aperture of the first hole 38. This could mean that the average aperture of the second holes 28 is greater than the average aperture of the first holes 38; or, a certain percentage (e.g., more than 50%, preferably more than 70%, more preferably more than 90%) of the second holes 28 have apertures larger than the maximum aperture of the first holes 38. Thus, a larger aperture of the second holes 28 is beneficial for increasing the contact area between the first electrode 31 and the transport layer 24, thereby improving the adhesion of the electrode, thus improving electrode connection reliability, and improving contact resistance, thus improving carrier collection capability and battery efficiency. Conversely, a relatively smaller aperture of the first holes 38 ensures the adhesion of the first electrode 31 to the first passivation layer 23 while also ensuring the structural strength of the passivation layer at the edge of the electrode region, thereby improving the connection reliability of the first electrode 31.

[0176] According to an embodiment of this application, along the width direction of the first electrode 31, the number of metal crystals 40 distributed at the two ends of the first electrode 31 is less than the number distributed at the remaining positions of the first electrode 31 excluding the two ends, and the aperture of the second hole 28 is larger than the aperture of the first hole 38. By providing different numbers and aperture sizes of holes at the left and right ends and the middle portion of the first electrode, the matching of holes and metal crystals can balance the transmission capacity and passivation performance of the first electrode 31 and the transmission layer. Specifically, a larger number of metal crystals are provided in the transmission layer corresponding to the middle portion of the first electrode along its width direction, and larger apertures 28 are provided. Larger apertures can accommodate more or larger metal crystals. The metal crystals, located in the middle portion where the first electrode has higher transmission efficiency, play a crucial role in rapidly transmitting charge carriers to the first electrode 31, thus ensuring improved contact performance between the first electrode 31 and the transmission layer. Conversely, fewer metal crystals are provided in the transmission layer corresponding to the left and right ends of the first electrode, and smaller apertures are provided in the first hole, which reduces the etching of the passivation layer or transmission layer at the edge of the electrode region, minimizing the impact on its passivation performance.

[0177] According to embodiments of this application, the aperture and distribution of the second holes 28 on the second etched region 212 differ depending on whether the transport layer 24 is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0178] For example, using the electrode region of the N-type doped semiconductor layer as the first electrode region and the electrode region of the P-type doped semiconductor layer as the second electrode region, the area ratio of the second hole located in the first electrode region on the first electrode region is 0% to 60%, for example, it can be 0%, 10%, 20%, 30%, 40%, 50%, 60%, etc.; or, the area ratio of the second hole located in the second electrode region on the second electrode region is 10% to 90%, for example, it can be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, etc. A suitable area ratio of the second hole can balance contact performance and passivation effect.

[0179] Regarding the measurement of the area ratio of the second hole, this application does not impose any restrictions. Those skilled in the art can determine it using conventional methods in the field. For example, at least one area of ​​the same size, such as 4 μm, can be taken from the SEM top view described above. 2 For each region, the area percentage of the second hole observed in each region is calculated. Then, the average area percentage of the second hole in at least one region is calculated, which is the area percentage of the second hole.

[0180] According to an embodiment of this application, the first passivation layer 23 may further include an ablation-affected region 33, located on the side of the first corrosion region 29 near the edge of the electrode region 27. This region is mainly affected by the sintering and photoinjection process of the first electrode 31, and its surface morphology or microstructure may change.

[0181] According to embodiments of this application, the contact structure located at the edge of the electrode region described above is applicable to different types of solar cells, such as bifacial cells or back-contact cells. Figure 10 is a schematic diagram of the overall structure of a back-contact cell according to an exemplary embodiment of this application; Figure 11 is a schematic diagram of the overall structure of a back-contact cell according to another exemplary embodiment of this application; Figure 12 is a schematic diagram of the overall structure of a bifacial cell according to an exemplary embodiment of this application. As shown in Figures 10 and 11, the surface of the silicon substrate includes an N-region 111 and a P-region 112, which are located on the same surface of the solar cell, thereby forming a back-contact cell; or as shown in Figure 12, the N-region 111 and the P-region 112 are located on different surfaces of the solar cell, i.e., two surfaces opposite to each other, thereby forming a bifacial cell.

[0182] In one embodiment, the contact structure located at the edge of the electrode region described above is applicable to one of the N-region 111 and the P-region 112, in which case the transport layer 24 can be an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0183] For example, as shown in Figures 7 and 10, taking an HPBC (Hybrid Passivated Back Contact) battery as an example, the silicon substrate 10 includes opposing first and second surfaces. The surface of the silicon substrate 10 includes alternately distributed N-regions 111 and P-regions 112. The tunneling oxide passivation contact structure can be located in the N-region, and the passivated emitter structure can be located in the P-region. In this case, there is no electrode structure on the second surface of the silicon substrate 10, which can help reduce the shading of the front electrode and thus improve the light utilization rate. The second surface of the silicon substrate 10 can be a textured structure (not shown in the figure).

[0184] Furthermore, the passivated emitter structure includes a doped conductive layer 202 located in the P-region 112 of the silicon substrate 10, and a third passivation antireflection layer 302 located on the doped conductive layer 202. Exemplarily, an aluminum-containing electrode can be fabricated after trenching the third passivation antireflection layer 302, and the silicon substrate in the P-region 112 can be P-type doped using the aluminum-containing electrode to obtain the doped conductive layer 202 on the P-region 112.

[0185] The N-type doped semiconductor layer 201 is located on the N-region 111, and its material can be polycrystalline silicon or microcrystalline silicon. At this time, the first passivation antireflection layer 301 located at the edge of the electrode region 27 of the N-type doped semiconductor layer 201 has a first etched region 29 for contacting the first electrode 31. Further, the electrode region 27 also includes a transition region 211 located on the side of the first etched region 29 away from the edge of the electrode region and a second etched region 212 located in the middle of the electrode region 27. The specific structure and morphology of the first etched region 29, the transition region 211, and the second etched region 212 will not be described in detail.

[0186] At this time, the N-type doped semiconductor layer 201 can be prepared by low-temperature chemical vapor deposition (LPCVD), and the thickness can be 100-600nm, for example, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, etc.

[0187] Optionally, the solar cell may further include a dielectric layer 21 serving as an interface passivation layer, located between the N-type doped semiconductor layer 201 and the silicon substrate 10. This dielectric layer selectively passes through majority carriers to achieve a field passivation effect, thereby improving carrier separation and collection. When serving as an interface passivation layer, the dielectric layer 21 can be made of materials such as aluminum oxide, silicon oxide, or titanium oxide, and can form a tunneling oxide passivation contact structure with the N-type doped semiconductor layer 201. The aforementioned dielectric layer 21 also serves to prevent the first electrode 31 from corroding the silicon substrate 10 inward. In this case, the dielectric layer 21 can be prepared using low-temperature chemical vapor deposition (LPCVD), and its thickness can be 0.5–10 nm, for example, 0.5 nm, 1 nm, 2 nm, 4 nm, 6 nm, 8 nm, 10 nm, etc.

[0188] In another embodiment, the contact structure located at the edge of the electrode region described above can also be applied to both the N region 111 and the P region 112.

[0189] For example, taking a back-contact battery as an example, as shown in Figures 7 and 11, taking a TBC (TopCon-Back Contact) battery as an example, the silicon substrate 10 includes a first surface and a second surface opposite to each other, and N-regions and P-regions can be alternately distributed on the first surface. The transport layer 24 may include an N-type doped semiconductor layer 201 and a P-type doped semiconductor layer 203, with the N-type doped semiconductor layer 201 located on the N-region 111 and the P-type doped semiconductor layer 203 located on the P-region 112.

[0190] As shown in Figure 11, the TBC battery may further include a dielectric layer 21 as an interface passivation layer. Tunneling oxide passivation contact structures are formed between the dielectric layer 21 and the N-type doped semiconductor layer 201, and between the dielectric layer 21 and the P-type doped semiconductor layer 203, respectively. One of these tunneling oxide passivation contact structures is a PN junction, and the other is a high-low junction. They can be further isolated by an isolation region (i.e., an isolation region), which can be, for example, an isolation trench located between the N-region and the P-region. Since one of the two tunneling oxide passivation contact structures is a PN junction and the other is a high-low junction, the composition or components of the dielectric layer 21 on both sides of the isolation region can be different.

[0191] In embodiments of this application, the first passivation layer 23 may include a first passivation antireflection layer 301 and a second passivation antireflection layer 303. The first passivation antireflection layer 301 is located on the N-type doped semiconductor layer 201, and the second passivation antireflection layer 303 is located on the P-type doped semiconductor layer 203. In this case, the electrode region of the N-type doped semiconductor layer 201 is designated as the first electrode region, and the electrode region of the P-type doped semiconductor layer 203 is designated as the second electrode region. The first passivation antireflection layer 301 located at the edge of the first electrode region and the second passivation antireflection layer 303 located at the edge of the second electrode region each have a first etched region 29. Further, the first electrode region and the second electrode region may also include a transition region 211 and a second etched region 212, respectively. The structures of the first etched region 29, the transition region 211, and the second etched region 212 are the same as described above and will not be repeated here.

[0192] In embodiments of this application, the aperture of the first hole 38 located in the first passivation antireflection layer 301 is smaller than the aperture of the first hole 38 located in the second passivation antireflection layer 303. This can be because the average aperture of the first holes in the first passivation antireflection layer 301 is smaller than the average aperture of the first holes in the second passivation antireflection layer 303; or, a certain percentage (e.g., more than 50%, preferably more than 70%, more preferably more than 90%) of the first holes 38 located in the first passivation antireflection layer 301 are smaller than the minimum aperture of the first holes 38 located in the second passivation antireflection layer 303. Exemplarily, the difference between the two can be further selected as 20–100 nm, for example, 20 nm, 30 nm, 45 nm, 50 nm, 75 nm, 80 nm, 95 nm, 100 nm, etc.

[0193] In the embodiments of this application, the distribution density of the first pores on the first corrosion region of the first passivation antireflection layer 301 is greater than the distribution density of the first pores on the first corrosion region of the second passivation antireflection layer 303. Exemplarily, the difference between the two can be further selected as 9 to 20 pores / μm. 2 For example, it could be 9 / μm 2 12 cells / μm 2 14 cells / μm 2 16 cells / μm 2 18 cells / μm 2 20 cells / μm 2 wait.

[0194] Thus, by adjusting the pore size and distribution density of the first pores in the first etched region on the first passivation antireflection layer 301 and the second passivation antireflection layer 303 within the aforementioned range, even with a slight reduction in the width of the first etched region on the P-region, it is beneficial to simultaneously improve the tensile strength of the N-region and P-region electrodes. Furthermore, reducing the width of the first etched region on the P-region helps to reduce recombination losses, thereby further improving the photoelectric conversion efficiency of the battery.

[0195] In embodiments of this application, the silicon substrate 10 includes opposing first and second surfaces. N-regions and P-regions can be alternately distributed on the first surface, with the N-region surface lower than the P-region surface (not shown in FIG. 11). Consequently, the upper surface of the N-region electrode is lower than the upper surface of the P-region electrode. Therefore, during the welding process between the solar cell and the solder ribbon, the tensile force borne by the N-region electrode along the thickness direction of the solar cell is greater than the tensile force borne by the P-region electrode in that direction. Thus, by adjusting the pore size and distribution density of the first pores in the first etched area on the first passivation antireflection layer 301 and the second passivation antireflection layer 303 within the aforementioned relationship range, i.e., the distribution of small and / or dense first pores in the N-region, the distribution of the first pores in the N-region provides greater adhesion between the electrode and the solar cell than the distribution of the first pores in the P-region, which is beneficial for balancing the tensile forces between the P-region and N-region electrodes.

[0196] In the embodiments of this application, the first corrosion region 29 is strip-shaped and extends along the extension direction of the electrode region; along the direction perpendicular to the extension direction of the electrode region, the width of the first corrosion region located in the first passivation antireflection layer 301 is different from the width of the first corrosion region located in the second passivation antireflection layer 303.

[0197] In order to reduce the recombination loss in the P-region, the width of the first etched region located in the first passivation antireflection layer 301 can be greater than the width of the first etched region located in the second passivation antireflection layer 303. For example, the difference between the two can be selected as 0.1 to 2 μm, such as 0.1 μm, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2.0 μm, etc.

[0198] To eliminate the contact difference caused by the lower doping concentration of the P-type doped semiconductor layer compared to the N-type doped semiconductor layer, the width of the first electrode region is smaller than the width of the second electrode region. This reduces the contact resistance between the P-type doped semiconductor layer and the electrode, improves the carrier collection balance between the N and P regions, and increases battery efficiency. For example, the width of the first electrode region can be 20–35 μm, such as 20 μm, 23 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, etc.; the width of the second electrode region can be 25–40 μm, such as 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, 38 μm, 40 μm, etc.; the difference between the two can further be selected as 5–15 μm, such as 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, etc.

[0199] In embodiments of this application, the area ratio of the second hole located in the first electrode region on the first electrode region is smaller than that of the second hole located in the second electrode region on the second electrode region. For example, the difference can be 10% to 30%. By controlling the area ratio of the second hole located in the second electrode region to be larger, when the P-type doped semiconductor layer 203 has a lower doping concentration and higher contact resistance than the N-type doped semiconductor layer 201, it is beneficial to further improve the contact performance between the P-type doped semiconductor layer 203 and the P-region electrode, thereby facilitating a balance in carrier transport between the N-region and P-region.

[0200] Of course, it is not limited to the TBC cell mentioned above. The solar cell of this application can also be a TOPCon cell. As shown in Figures 7 and 12, a TOPCon cell with a tunneling oxide passivation contact structure on one side is shown. The main difference from the TBC cell is that the N region 111 is located on the first surface of the silicon substrate 10, the P region 112 is located on the second surface of the silicon substrate 10, the tunneling oxide passivation contact structure is located in the N region 111, and the passivated emitter structure is located in the P region 112.

[0201] The tunneling oxide passivation contact structure includes an N-type doped semiconductor layer 201 located in the N-region 111, which can be made of polycrystalline silicon or microcrystalline silicon; and a first passivation antireflection layer 301 located on the N-type doped semiconductor layer 201. The passivated emitter structure includes a P-type doped semiconductor layer 203 located in the P-region 112, and a second passivation antireflection layer 303 located on the P-type doped semiconductor layer 203. The P-type doped semiconductor layer 203 can be obtained in the P-region 112 by boron diffusion doping.

[0202] Of course, it is not limited to this. The passivated emitter structure in P region 112 shown in Figure 12 can be replaced with another tunneling oxide passivation contact structure, specifically including a P-type doped semiconductor layer 203 on P region 112, which can be made of polycrystalline silicon or microcrystalline silicon, etc., and another interface passivation layer on P-type doped semiconductor layer 203. The corresponding solar cell is a TOPCon cell with tunneling oxide passivation contact structure on both sides.

[0203] At this time, the electrode region of the N-type doped semiconductor layer 201 is also taken as the first electrode region, and the electrode region of the P-type doped semiconductor layer 203 is taken as the second electrode region. The first passivation antireflection layer 301 located at the edge of the first electrode region and the second passivation antireflection layer 303 located at the edge of the second electrode region each have a first etched region 29. In the embodiments of this application, the first electrode region and the second electrode region may respectively include a transition region 211 and a second etched region 212. The structures of the first etched region 29, the transition region 211 and the second etched region 212 are the same as described above, and will not be repeated here.

[0204] In embodiments of this application, a photovoltaic module is provided, including a cell string comprising the aforementioned solar cells; and a plurality of solder ribbons, wherein the solder ribbons connect at least two adjacent solar cells. By forming a first etched zone suitable for contact with the electrode on the passivation layer at the edge of the electrode region in the solar cell, the porous structure of the first etched zone can increase the contact area between the electrode edge and the passivation layer, thereby improving the adhesion of the electrode. During the connection process between the solar cell and the solder ribbons, the solder ribbons contact the electrode, and the electrode has good adhesion, meaning that the electrode has good tensile strength after connection with the solder ribbons, thus improving the reliability of the connection between the solder ribbons and the solar cell.

[0205] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0206] When using expressions such as "at least one of A, B, and C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). Similarly, when using expressions such as "at least one of A, B, or C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0207] In this application, the relative position between two components (e.g., a membrane or region), as referred to by terms such as "above," "over," or "above," can mean that the two components are in direct contact or that they are not in direct contact. Similarly, the relative position between two components, as referred to by terms such as "below," "under," or "below," can mean that the two components are in direct contact or that they are not in direct contact. For example, when one component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when one component is referred to as "on another component," the two components have a vertical relationship in the planar view, and this component can be above or below the other component, thus this vertical relationship depends on the orientation of the device.

[0208] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. For embodiments of devices, electronic devices, computer-readable storage media, and computer program products containing instructions, the descriptions are relatively simple because they are basically similar to the method embodiments; relevant parts can be referred to the descriptions of the method embodiments.

[0209] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A solar cell, the solar cell comprising a silicon substrate (10), a transport layer (24) and a first electrode (31); The transport layer (24) is located on one side of the silicon substrate (10), and a metal crystal (40) is disposed in the transport layer (24); the first electrode (31) is located on the side of the transport layer (24) away from the silicon substrate (10), and the first electrode (31) is electrically connected to the transport layer (24) and the metal crystal (40); Along the width direction of the first electrode (31), the number of metal crystals (40) distributed at the two ends of the first electrode (31) is less than the number distributed at the other positions of the first electrode (31) excluding the two ends.

2. The solar cell according to claim 1, wherein, Along the width direction of the first electrode (31), the width of each end of the first electrode (31) accounts for 8%-22% of the width of the first electrode (31).

3. The solar cell according to claim 1, wherein, Along the width direction of the first electrode (31), a preset width L2 is selected within the first electrode (31), and the total width of the plurality of metal crystals (40) within the range of the preset width is L1, and the range of L1 / L2 is 50%-90%.

4. The solar cell according to claim 3, wherein, Along the width direction of the first electrode (31), the width of the first electrode (31) is L4; the total width of the plurality of metal crystals (40) connected to the first electrode (31) is L3, and the range of L3 / L4 is 70%-85%.

5. The solar cell according to any one of claims 1-4, wherein, Along the width direction of the first electrode (31), the width range of the metal crystal (40) is 100nm-600nm.

6. The solar cell according to claim 1, wherein, The metal crystal (40) includes a first metal crystal and a second metal crystal; Along the width direction of the first electrode (31), the width range of the first metal crystal is 100nm-200nm, and the width range of the second metal crystal is 300nm-600nm.

7. The solar cell according to claim 6, wherein, The number of the first metal crystals is greater than the number of the second metal crystals.

8. The solar cell according to claim 1, wherein, Along the thickness direction of the silicon substrate (10), the thickness of the metal crystal (40) ranges from 50 nm to 300 nm.

9. The solar cell according to claim 1, wherein, The solar cell also includes a second electrode (32), wherein the melting point of the first electrode (31) is higher than the melting point of the second electrode (32).

10. The solar cell according to claim 1, further comprising: A passivation layer is located on the surface of the transport layer away from the silicon substrate; The transport layer is located on the surface of one side of the silicon substrate, and the transport layer includes an electrode region; Wherein, the first electrode is located on the passivation layer, and the first electrode passes through the passivation layer and is in contact with a portion of the electrode region; The passivation layer has a first corrosion zone in the portion corresponding to the edge of the electrode region, and the first corrosion zone has a plurality of first pores.

11. The solar cell according to claim 10, wherein, The electrode region includes a pore-free transition region located on the side of the first etched region away from the edge of the electrode region.

12. The solar cell according to claim 10, wherein, At least some of the plurality of first holes are blind holes.

13. The solar cell according to claim 12, wherein, The distribution density of the blind holes is 1–40 per μm. 2 .

14. The solar cell according to claim 10, wherein, The electrode region includes a second corrosion region located in the middle of the electrode region, and the second corrosion region has a plurality of second pores.

15. The solar cell according to claim 14, wherein, The diameter of the second hole is larger than the diameter of the first hole.

16. The solar cell according to claim 14, wherein, The surface of the silicon substrate includes N-regions and P-regions, which are located on the same surface or different surfaces of the solar cell, respectively. The transport layer includes an N-type doped semiconductor layer and a P-type doped semiconductor layer, wherein the N-type doped semiconductor layer is located on the N-region and the P-type doped semiconductor layer is located on the P-region; Taking the electrode region of the N-type doped semiconductor layer as the first electrode region and the electrode region of the P-type doped semiconductor layer as the second electrode region, the area ratio of the second hole located in the first electrode region on the first electrode region is smaller than the area ratio of the second hole located in the second electrode region on the second electrode region.

17. The solar cell according to claim 16, wherein: The area of ​​the second hole located in the first electrode region accounts for 0% to 60% of the area of ​​the first electrode region, and the area of ​​the second hole located in the second electrode region accounts for 10% to 90% of the area of ​​the second electrode region; and / or, The difference between the area ratio of the second hole located in the first electrode region and the area ratio of the second hole located in the second electrode region is between 10% and 30%.

18. The solar cell according to claim 10, wherein, The surface of the silicon substrate includes N-regions and P-regions, which are located on the same surface or different surfaces of the solar cell, respectively. The passivation layer includes a first passivation layer and a second passivation layer, wherein the first passivation layer is located on the transport layer on the N region, and the second passivation layer is located on the transport layer on the P region; The first etched zone is strip-shaped and extends along the extension direction of the electrode region; Along the direction perpendicular to the extension direction of the electrode region, the width of the first etched region in the first passivation layer is different from the width of the first etched region in the second passivation layer.

19. The solar cell according to claim 18, wherein, The width of the first etched region located in the first passivation layer is greater than the width of the first etched region located in the second passivation layer.

20. The solar cell according to claim 10, wherein, The surface of the silicon substrate includes N-regions and P-regions, which are located on the same surface or different surfaces of the solar cell, respectively. The passivation layer includes a first passivation layer and a second passivation layer, wherein the first passivation layer is located on the transport layer on the N region, and the second passivation layer is located on the transport layer on the P region; The distribution density of the first pores in the first corrosion zone of the first passivation layer is greater than that in the first corrosion zone of the second passivation layer.

21. The solar cell according to claim 10, wherein, The surface of the silicon substrate includes N-regions and P-regions, which are located on the same surface or different surfaces of the solar cell, respectively. The transport layer includes an N-type doped semiconductor layer and a P-type doped semiconductor layer, wherein the N-type doped semiconductor layer is located on the N-region and the P-type doped semiconductor layer is located on the P-region; The electrode region of the N-type doped semiconductor layer is designated as the first electrode region, and the electrode region of the P-type doped semiconductor layer is designated as the second electrode region. The width of the first electrode region is smaller than the width of the second electrode region.

22. A photovoltaic module, comprising: A battery string, the battery string comprising solar cells as described in any one of claims 1 to 21; A plurality of solder strips, wherein the solder strips connect at least two adjacent solar cells.

23. A method for preparing a solar cell, comprising: A transport layer (24) is disposed on one side of the silicon substrate (10); A first paste is disposed on the side of the transport layer (24) away from the silicon substrate (10); The first electrode (31) is formed by first sintering the first slurry at a temperature lower than the melting point of the first slurry. The first electrode (31) is sintered a second time to form a metal crystal (40) within the transport layer (24); the first electrode (31) is electrically connected to the metal crystal (40).

24. The method for preparing a solar cell according to claim 23, wherein, The solar cell further includes a second electrode (32), the melting point of which is lower than that of the first electrode (31); the preparation method includes: A transport layer (24) is disposed on one side of the silicon substrate (10); A first paste and a second paste are disposed on the side of the transport layer (24) away from the silicon substrate (10); The first slurry and the second slurry are sintered for the first time at a temperature lower than or equal to the melting point of the second slurry to form the first electrode (31) and the second electrode (32), respectively. The first electrode (31) is sintered a second time to form a metal crystal (40) within the transport layer (24); the first electrode (31) and / or the second electrode (32) are electrically connected to the metal crystal (40).

25. The method for preparing a solar cell according to claim 24, wherein, The step of performing a second sintering on the first electrode (31) to form a metal crystal (40) within the transport layer (24) includes, A reverse voltage is applied to the first electrode (31) and the second electrode (32); The first electrode (31) is laser scanned to form a metal crystal (40) within the transport layer (24).

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