Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor wherein the position during mounting and conveyance is stable and the size of a layered body does not become small relative to an external electrode. This multilayer ceramic capacitor 1 has a dimension of 0.08 mm or less in a height direction, a dimension of 0.16 mm or less in a first direction, and a dimension of 0.08 mm or less in a second direction, and comprises a first surface and a second surface facing each other in the height direction, a third surface and a fourth surface facing each other in the first direction, and a first external electrode 3A positioned on the third surface, the first surface, and the second surface. The first external electrode 3A has a first base electrode layer 30A and a first surface plating layer 31A. When viewed from the first surface side, the first external electrode 3A has a first region Q1 that is a region in which the thickness of the first surface plating layer 31A at the perimeter is thicker than the thickness of the first surface plating layer 31A in an inner region that is surrounded by said perimeter, and the area of the first region Q1 is greater than or equal to 33.50% of the area of a second region Q2 that is located at the periphery of the first region Q1.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] As electronic devices become smaller, there is a demand for smaller multilayer ceramic capacitors. For example, a multilayer ceramic capacitor with a length of 0.25 mm, a width of 0.125 mm, and a height of 0.125 mm is known (see Patent Document 1).

[0003] Multilayer ceramic capacitors generally undergo a barreling process during their manufacturing process. In the barreling process, the corners and ridges of the laminate are rounded. For multilayer ceramic capacitors smaller than the above-mentioned sizes, the amount of cutting in the barreling process is relatively large, and the laminate tends to have a rounded, oval-like shape overall. Multilayer ceramic capacitors manufactured from such laminates also have a rounded, oval-like shape overall. This makes the capacitor unstable, increasing the likelihood of tilting or rolling during mounting or transportation, resulting in defects.

[0004] Furthermore, even if the dimensions of the laminate are reduced to manufacture a small multilayer ceramic capacitor, if the external electrodes are formed using a dip process, the surface tension of the conductive paste for the external electrodes causes the external electrodes to become thicker at the center of each of the end faces, main surfaces, and side surfaces, resulting in a larger overall size of the multilayer ceramic capacitor. Therefore, to fit the final size of the multilayer ceramic capacitor into the desired small size, the size of the laminate must be further reduced. This increases the ratio of the external electrodes to the laminate, reducing the effective area of ​​the internal electrodes and resulting in a smaller capacitance of the multilayer ceramic capacitor.

[0005] JP 2023-63887 A

[0006] An object of the present invention is to provide a multilayer ceramic capacitor, particularly a small-sized one, which has a stable posture during mounting and transportation and in which the size of the laminate does not become too small relative to the external electrodes.

[0007] In order to solve the above problems, the present invention provides a laminate comprising: a first surface and a second surface that face each other in a height direction; a third surface and a fourth surface that face each other in a first direction that intersects with the height direction; and a fifth surface and a sixth surface that face each other in a second direction that intersects with the height direction and the first direction; a first external electrode arranged on the third surface, the first surface, and the second surface; and a second external electrode arranged on the fourth surface, the first surface, and the second surface, wherein the first external electrode has a first base electrode layer and a first surface plating layer, and the second external electrode has a second base electrode layer and a second surface plating layer, the dimension in the height direction being 0.08 mm or less, the dimension in the first direction being 0.16 mm or less, and the dimension in the second direction being 0.08 mm or less, and when viewed from the first surface side, the first external electrode has a first region and a second region located around the first region, The first region is a region in which the thickness of the first surface plating layer at the outer periphery of the first region is greater than the thickness of the first surface plating layer in an internal region surrounded by the outer periphery, and the area of ​​the first region is 33.50% or more of the area of ​​the second region.

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor that maintains a stable posture during mounting and transportation and in which the size of the laminate does not become too small relative to the external electrodes.

[0009] 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment; FIG. 2 is a partial cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II in FIG. 1; FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III in FIG. 1; FIG. 4 is an enlarged view of an area P surrounded by a dotted line in FIG. 2; FIG. 5 is a view of the multilayer ceramic capacitor 1 as seen from the first surface A1, which is the mounting surface side, when viewed in a direction connecting the first surface A1 and the second surface A2; FIG. 6 is a flowchart showing a manufacturing method of the multilayer ceramic capacitor 1 according to an embodiment; and FIG. 7 is a table showing verification results of the effects of the multilayer ceramic capacitor 1 according to an embodiment.

[0010] Hereinafter, an embodiment of the present invention will be described. Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment. Fig. 2 is a partial cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III in Fig. 1.

[0011] The multilayer ceramic capacitor 1 includes a laminate 2 having a substantially rectangular parallelepiped shape and a pair of external electrodes 3 provided on both ends of the laminate 2. The laminate 2 also includes an effective portion 6 including a plurality of pairs of dielectric layers 4 and internal electrodes 5.

[0012] In the following description, the direction perpendicular to the mounting surface is referred to as the height direction T, which is a term used to describe the orientation of the multilayer ceramic capacitor 1. In this embodiment, the direction in which the internal electrodes 5 and the dielectric layers 4 are stacked is referred to as the height direction T. However, this is not limiting, and the direction in which the internal electrodes 5 and the dielectric layers 4 are stacked may be referred to as a direction horizontal to the mounting surface, and the height direction T may be referred to as a direction perpendicular to the direction in which the internal electrodes 5 and the dielectric layers 4 are stacked.

[0013] The direction in which the pair of external electrodes 3 are provided is defined as a first direction L. A direction intersecting both the first direction L and the height direction T is defined as a second direction W. In the embodiment, the first direction L, the second direction W, and the height direction T are perpendicular to one another. Although the present invention is not limited to this, the dimension of the multilayer ceramic capacitor 1 of the embodiment, including the external electrodes 3, in the height direction T is 0.08 mm or less, the dimension in the first direction L is 0.16 mm or less, and the dimension in the second direction W is 0.08 mm or less, and further the dimension in the height direction T of the multilayer ceramic capacitor 1 is smaller than the dimension in the second direction W.

[0014] (Laminate 2) The laminate 2 has a first surface A1 and a second surface A2 facing in the height direction T, a third surface C1 and a fourth surface C2 facing in the first direction L, and a fifth surface B1 and a sixth surface B2 facing in the second direction W. In this embodiment, the first surface A1 is a mounting surface to be mounted on a substrate.

[0015] In this embodiment, the ridges R1 between two adjacent faces and the corners between three adjacent faces of the laminate 2 are rounded by a barrel process described below, which makes it possible to prevent chipping at the angular portions of the laminate 2.

[0016] By subjecting the laminate 2 to the barreling process in this manner, the central portion of the first surface A1 of the laminate 2 protrudes in the height direction T more than the edge portions in the first direction L or the second direction W. Furthermore, not only the first surface A1 but also the second surface A2, the third surface C1, the fourth surface C2, the fifth surface B1, and the sixth surface B2 have central portions that protrude more than the edge portions.

[0017] The laminate 2 includes an effective portion 6 and an ineffective portion 7. The effective portion 6 is a region where the internal electrodes 5 and the dielectric layers 4 are laminated. The ineffective portion 7 is a region where the internal electrodes 5 are not arranged, and includes outer layer portions 7A that sandwich the effective portion 6 from the height direction T, and side gap portions 7B that sandwich the effective portion 6 from the second direction W.

[0018] (Dielectric Layer 4) The dielectric layer 4 preferably contains, as a main component, a ceramic material made of, for example, a BT-based or CZ-based material, and may contain a sintering aid as an additive.

[0019] (Internal electrode 5) The internal electrode 5 includes a plurality of first internal electrodes 5A and a plurality of second internal electrodes 5B. For example, the first internal electrode 5A is exposed on the third surface C1, and the second internal electrode 5B is exposed on the fourth surface C2. Note that, unless it is necessary to particularly distinguish between the first internal electrode 5A and the second internal electrode 5B, they will be collectively referred to as the internal electrode 5.

[0020] The components of the internal electrode 5 are not particularly limited, but it is preferable that the internal electrode 5 be formed from a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), a silver-palladium (Ag-Pd) alloy, or gold (Au).

[0021] The internal electrodes 5 include opposing portions 52 that face each other between the first internal electrode 5A and the second internal electrode 5B, and lead portions 51 that do not face each other between the first internal electrode 5A and the second internal electrode 5B and are drawn from the opposing portions 52 toward one of the third surface C1 and the fourth surface C2. The extending directions of the lead portions 51 differ between the first internal electrode 5A and the second internal electrode 5B, and the lead portions 51 are drawn toward the third surface C1 and the fourth surface C2. An end of the lead portion 51 of the first internal electrode 5A is exposed on the third surface C1 and electrically connected to the first external electrode 3A. An end of the lead portion 51 of the second internal electrode 5B is exposed on the fourth surface C2 and electrically connected to the second external electrode 3B. An electric charge is accumulated between the opposing portions 52 of the first internal electrode 5A and the second internal electrode 5B that are adjacent in the height direction T, functioning as a capacitor.

[0022] (Outer Layer Portion 7A) The outer layer portion 7A is disposed on the first surface A1 side and the second surface A2 side of the effective portion 6. The outer layer portion 7A may be made of the same material as the dielectric layer 4 of the effective portion 6.

[0023] (Side gap portion 7B) The side gap portion 7B is disposed on the fifth surface B1 side and the sixth surface B2 side of the effective portion 6 of the laminate 2. The side gap portion 7B may be made of the same material as the dielectric layer 4.

[0024] (External Electrode 3) The external electrode 3 includes a first external electrode 3A and a second external electrode 3B. The first external electrode 3A is disposed on the third surface C1, the first surface A1, and the second surface A2. In addition to this, the first external electrode 3A may also be disposed on the fifth surface B1 and the sixth surface B2. The second external electrode 3B is disposed on the fourth surface C2, the first surface A1, and the second surface A2. In addition to this, the second external electrode 3B may also be disposed on the fifth surface B1 and the sixth surface B2.

[0025] (First external electrode 3A) The first external electrode 3A includes a first base electrode layer 30A and a first surface plating layer 31A. The first base electrode layer 30A is connected to the first internal electrode 5A. The first base electrode layer 30A is disposed on the third surface C1, the first surface A1, and the second surface A2. In addition, the first base electrode layer 30A may also be disposed on the fifth surface B1 and the sixth surface B2.

[0026] The first surface plating layer 31A includes a first inner surface plating layer 31Aa which is a Ni plating layer arranged on the first base electrode layer 30A, and a first outer surface plating layer 31Ab which is a Sn plating layer arranged on the first inner surface plating layer 31Aa.

[0027] (Second External Electrode 3B) The second external electrode 3B includes a second base electrode layer 30B and a second surface plating layer 31B. The second base electrode layer 30B is connected to the second internal electrode 5B. The second base electrode layer 30B is disposed on the fourth surface C2, the first surface A1, and the second surface A2. In addition, the second base electrode layer 30B may also be disposed on the fifth surface B1 and the sixth surface B2.

[0028] The second surface plating layer 31B includes a second inner surface plating layer 31Ba which is a Ni plating layer arranged on the second base electrode layer 30B, and a second outer surface plating layer 31Bb which is a Sn plating layer arranged on the second inner surface plating layer 31Ba.

[0029] Hereinafter, when there is no need to distinguish between the first external electrode 3A and the second external electrode 3B, they will be collectively referred to as the external electrode 3. When there is no need to distinguish between the first base electrode layer 30A and the second base electrode layer 30B, they will be collectively referred to as the base electrode layer 30. When there is no need to distinguish between the first surface plating layer 31A and the second surface plating layer 31B, they will be collectively referred to as the surface plating layer 31. When there is no need to distinguish between the first inner surface plating layer 31Aa and the second inner surface plating layer 31Ba, they will be collectively referred to as the inner surface plating layer 31a. When there is no need to distinguish between the first outer surface plating layer 31Ab and the second outer surface plating layer 31Bb, they will be collectively referred to as the outer surface plating layer 31b.

[0030] (Base electrode layer 30) The base electrode layer 30 may have a configuration including a metal component and a glass component, or a metal component and a ceramic component. In an embodiment, the base electrode layer 30 includes Cu as a component. In an embodiment, the base electrode layer 30 is a coating film manufactured by a dipping method. However, the base electrode layer 30 may also be a plating film (base plating layer) manufactured by plating, or may be a thin film layer.

[0031] In the embodiment, the base electrode layer 30 is formed by a dip coating method, and therefore the base electrode layer 30 disposed on the first surface A1, the second surface A2, the fifth surface B1, and the sixth surface B2 of the laminate 2 is rounded. That is, the base electrode layer 30 is thicker at the center than at the edge portions on each of the first surface A1, the second surface A2, the fifth surface B1, and the sixth surface B2 on which it is disposed. In other words, the base electrode layer 30 protrudes more at the center than at the edge portions on each of the first surface A1, the second surface A2, the fifth surface B1, and the sixth surface B2 on which it is disposed.

[0032] (Top Plated Layer 31) The inner top plated layer 31a, which is a Ni plated layer, can prevent the base electrode layer 30 from being eroded by solder when mounting a ceramic electronic component. The outer top plated layer 31b, which is a Sn plated layer, improves the wettability of solder when mounting the multilayer ceramic capacitor 1. A metal layer may be provided between the top plated layer 31 and the base electrode layer 30. Furthermore, the top plated layer 31 is not limited to a two-layer structure consisting of the inner top plated layer 31a and the outer top plated layer 31b, but may have a one-layer structure or a structure of three or more layers.

[0033] 4 is an enlarged view of the area P surrounded by the dotted line in FIG. 2, and a graph showing the thickness of the surface plating layer 31, which is the sum of the inner surface plating layer 31a and the outer surface plating layer 31b, is shown at the top of the figure. The thickness of the surface plating layer 31 is the thickness in the direction normal to the surface of the base electrode layer 30, as indicated by arrows t1 and t2 in the figure.

[0034] 5 is a view of the multilayer ceramic capacitor 1 as viewed from the first surface A1, which is the mounting surface side, in a direction connecting the first surface A1 and the second surface A2. When the multilayer ceramic capacitor 1 is viewed from the first surface A1, which is the mounting surface side, as shown in the figure, the first external electrode 3A has a first region Q1 and a second region Q2 located around the first region Q1.

[0035] In the embodiment, the second external electrode 3B also has a first region Q1 and a second region Q2 when viewed from the first surface A1. Furthermore, in the embodiment, the first external electrode 3A and the second external electrode 3B also have a first region Q1 and a second region Q2 located around the first region Q1 when viewed from the second surface A2 opposite to the first surface A1, which is the mounting surface. However, it is sufficient that the first region Q1 and the second region Q2 are provided on at least one of the first external electrodes 3A on the first surface A1 side, which is the mounting surface.

[0036] (First Region Q1) The first region Q1 is a region in which the thickness of the surface plating layer 31 at the outer periphery of the first region Q1 is greater than the thickness of the surface plating layer 31 in an internal region surrounded by the outer periphery. In the embodiment, the thickness of the surface plating layer 31 in the first region Q1 gradually increases from the internal region toward the outer periphery.

[0037] As described above, the base electrode layer 30 protrudes more at the center than at the edges on the first surface A1 where it is disposed. However, in the first region Q1, the thickness of the surface plating layer 31 gradually increases from the inner region toward the outer periphery, thereby offsetting this protrusion of the base electrode layer 30. In this embodiment, the outermost surface of the external electrode 3 in the first region Q1 is flat. However, this is not limited thereto, and it is sufficient that the thickness of the surface plating layer 31 at the outer periphery in the first region Q1 is thicker than the thickness of the surface plating layer 31 in the inner region surrounded by the outer periphery.

[0038] 4, the minimum thickness t2 of the surface plating layer 31 in the first region Q1 is preferably 1.2 μm or more, and more preferably 2.0 μm or more. The film thickness of the surface plating layer 31 can be measured by exposing a cross section passing through the height direction T and the first direction L or the second direction W, and then from an image of the cross section taken with a digital microscope or SEM (scanning electron microscope)-EDX (energy dispersive X-ray spectroscopy).

[0039] In this embodiment, the outer periphery of the first region Q1 has a substantially constant thickness t1, which is preferably 2.0 μm or more and 11.0 μm or less. However, the outer periphery of the first region Q1 may have some variation, and in this case, the variation is preferably 1.0 μm or less.

[0040] (Second Region Q2) The thickness of the surface plating layer 31 in the second region Q2 is approximately constant throughout the entire region, and is equal to the outer periphery of the first region, t1.

[0041] (Method for Measuring the Areas of the First Region Q1 and the Second Region Q2) The areas of the first region Q1 and the second region Q2 can be measured from one side in the height direction using a shape-measuring laser microscope. The distinction between the first region Q1 and the second region Q2 is determined by shading, etc., caused by the way the laser light hits the region. Furthermore, if the external electrodes 3 protrude toward the third surface C1 and the fourth surface C2, these regions are also included in the total area of ​​the first region Q1 and the second region Q2. The area of ​​the first region Q1 is at least 33.50% of the area of ​​the second region Q2, and preferably at least 42.90%. The area of ​​the top plating layer 31 in the first region Q1 is more preferably greater than the area of ​​the second region Q2, and even more preferably at least 57.70%.

[0042] There may be a plurality of first regions Q1 and a plurality of second regions Q2. In this case, the total area of ​​the plurality of first regions Q1 is 33.50% or more of the area of ​​the plurality of second regions Q2, preferably 42.90% or more, more preferably 50% or more, and even more preferably 57.70% or more.

[0043] In the embodiment, as described above, the second external electrode 3B also has a first region Q1 and a second region Q2 when the multilayer ceramic capacitor 1 is viewed from the first surface A1 side. The first region Q1 of the first external electrode 3A and the first region Q1 of the second external electrode 3B are located on the same horizontal plane.

[0044] (Manufacturing Method of Multilayer Ceramic Capacitor 1) Next, a manufacturing method of the multilayer ceramic capacitor 1 according to the embodiment will be described. Fig. 6 is a flowchart showing the manufacturing method of the multilayer ceramic capacitor 1 according to the embodiment.

[0045] (Laminate Manufacturing Process S1) First, a material sheet is prepared in which a pattern of the internal electrodes 5 is printed with a conductive paste on a ceramic green sheet for lamination, which is formed by molding a ceramic slurry into a sheet shape. Then, multiple material sheets are stacked so that the patterns of the internal electrodes 5 are shifted by half a pitch between adjacent material sheets in the longitudinal direction. Furthermore, outer layer ceramic green sheets are stacked on both sides of the multiple stacked material sheets, and the stacked sheets are thermocompression-bonded to form a mother block member. The mother block member is then cut along the cutting lines to produce the laminate 2.

[0046] (First Firing Step S2) The divided laminate 2 is degreased under predetermined conditions in a nitrogen atmosphere, and then fired at a predetermined temperature in a nitrogen-hydrogen-water vapor mixed atmosphere.

[0047] (Barrel process S3) Next, the laminate 2 is subjected to barrel polishing. This rounds the ridgeline R1 of the laminate 2. When the ridgeline R1 of the laminate 2 is rounded by barrel polishing, the amount of shaving off of the laminate 2, particularly a small-sized laminate 2, is relatively large, and the laminate 2 is likely to have an overall rounded oval shape.

[0048] (Base electrode layer forming step S4) Thereafter, a base electrode layer paste that will become the base electrode layer 30 is applied from the third surface C1 side and the fourth surface C2 side using a dipping method. At this time, the base electrode layer paste is also applied onto the first surface A1, the second surface A2, the fifth surface B1, and the sixth surface B2 of the laminate 2.

[0049] As described above, when the base electrode layer 30 is formed by the dipping method, the thickness of the base electrode layer 30 disposed on each surface of the laminate 2 is not uniform on each surface, but is thicker at the center than at the edges. In other words, the surface of the base electrode layer 30 is not flat and parallel to each surface, but has a rounded, mountain-like shape that bulges outward.

[0050] In particular, when the ridgeline R1 and corners are rounded in the barrel process as described above, each surface of the laminate 2 having a first dimension of less than 0.16 mm and height and second dimension dimensions of less than 0.08 mm is generally rounded, and the base electrode layer 30 formed on each surface by the dipping method is further rounded.

[0051] (Second Firing Step S5) Thereafter, the laminate 2 on which the base electrode layer 30 has been formed is fired in an oxidizing atmosphere to which nitrogen and water are continuously supplied. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0052] (Plating layer forming step S6) Next, first, an inner surface plating layer 31a, which is a Ni plating layer, is formed on the outer periphery of the base electrode layer 30 so as to cover the base electrode layer 30. Next, an outer surface plating layer 31b, which is a Sn plating layer, is formed on the outer periphery of the inner surface plating layer 31a so as to cover the inner surface plating layer 31a.

[0053] At this time, the inner surface plating layer 31a and the outer surface plating layer 31b are each formed to a substantially constant thickness overall, and the combined thickness of the inner surface plating layer 31a and the outer surface plating layer 31b is t1 as shown in Figure 4.

[0054] (First region forming step S7) Thereafter, for example, in this embodiment, the multilayer ceramic capacitor 1 is sandwiched between two plate-like members from both sides in the height direction T and pressed in the height direction T. This causes the material of the outer surface plating layer 31b (Sn plating layer) located outermost on the first surface A1 and the second surface A2 of the multilayer ceramic capacitor 1 to flow, and the protruding portions of the outer surface plating layer 31b on the first surface A1 and the second surface A2 are flattened, thereby forming the first region Q1.

[0055] Here, the conditions for pressing are, for example, as follows: Pressure: several MPa to several tens of MPa Time: approximately 100 to 300 seconds Note that by increasing the pressure and lengthening the time, it is possible to improve the flatness of the first region Q. Furthermore, by applying pressure while applying heat, it is possible to make the Sn plating more fluid.

[0056] Through the above steps, a multilayer ceramic capacitor 1 is manufactured in which, when viewed from the first surface A1 side, the external electrode 3 has a first region Q1 and a second region Q2 located around the first region Q1, and the thickness of the surface plating layer 31 at the outer periphery of the first region Q1 is thicker than the thickness of the surface plating layer 31 in the internal region surrounded by the outer periphery.

[0057] Unlike the embodiment, in the case of a multilayer ceramic capacitor 1 that does not have the first region Q1, it is likely to roll when stored in a storage container and transported, and it may become tilted inside the storage container and get caught on the inner surface of the container, making it difficult to remove, or it may tilt or roll during installation or transportation, increasing the possibility of problems occurring.

[0058] However, the multilayer ceramic capacitor 1 of the embodiment has a first region Q in which the thickness of the surface plating layer 31 at the outer periphery is thicker than the thickness of the surface plating layer 31 inside surrounded by the outer periphery, and the protrusion of the base electrode layer 30 is offset by the surface plating layer 31.

[0059] Therefore, even if the multilayer ceramic capacitor 1 of the embodiment is small in size, it is possible to prevent it from rolling during mounting or transportation.

[0060] Furthermore, in the first region Q1, the protruding portions of the outer surface plating layer 31b on the first surface A1 and the second surface A2 are removed, so the size of the external electrode 3 becomes smaller than before removal. Therefore, the ratio of the external electrode 3 to the laminate 2 can be made relatively small.

[0061] (Verification of Effects of Multilayer Ceramic Capacitor 1 of the Embodiment) Next, the results of verifying the effects of the multilayer ceramic capacitor 1 of the embodiment will be described.

[0062] A plurality of multilayer ceramic capacitors having the following dimensions were prepared after the plating layer forming step S6 was completed: Height dimension: 0.08 mm, First dimension: 0.16 mm, Second dimension: 0.08 mm

[0063] Then, for these multilayer ceramic capacitors, by changing the magnitude of pressure and the holding time in the first region forming step S7, 100 multilayer ceramic capacitors 1 of each embodiment were prepared in which the value of D1 / (D1+D2) was 33.50%, 39.10%, 42.90%, and 57.70%, where D1 is the area of ​​the first region Q1 and D2 is the area of ​​the second region Q2.

[0064] As a comparative example, 100 multilayer ceramic capacitors were also prepared in which the first region forming step S7 was not performed, i.e., the first region Q1 was not present and D1 / (D1+D2) was zero.

[0065] The multilayer ceramic capacitors were housed in containers of the following dimensions: Height: 0.10 mm, First direction: 0.18 mm, Second direction: 0.09 mm

[0066] The multilayer ceramic capacitors housed in the container were vibrated in the second direction for one hour, and the number of multilayer ceramic capacitors that rotated within the container and became pinched in the container (NG number) was counted.

[0067] FIG. 7 is a table showing the results. As shown in the table, in the case of the multilayer ceramic capacitor of the comparative example, the number of NG samples was 10 out of 100. In the case of the multilayer ceramic capacitor 1 of the embodiment in which the value of D1 / (D1+D2) was 33.50%, the number of NG samples was 4 out of 100. In the case of the multilayer ceramic capacitor 1 of the embodiment in which the value of D1 / (D1+D2) was 39.10%, the number of NG samples was 4 out of 100. In the case of the multilayer ceramic capacitor 1 of the embodiment in which the value of D1 / (D1+D2) was 42.90%, the number of NG samples was 2 out of 100. In the case of the multilayer ceramic capacitor 1 of the embodiment in which the value of D1 / (D1+D2) was 47.30%, the number of NG samples was 1 out of 100. In the case of the multilayer ceramic capacitor 1 of the embodiment in which the value of D1 / (D1+D2) was 57.70%, the number of NG samples was 0 out of 100.

[0068] As described above, in the multilayer ceramic capacitor of the comparative example, the number of NG samples was 10 out of 100, but in the multilayer ceramic capacitor 1 of the embodiment, when the value of D1 / (D1+D2) was 33.50% or more, the number of NG samples was 4 or less out of 100, proving that the multilayer ceramic capacitor of the embodiment is highly stable.

[0069] In the multilayer ceramic capacitor 1 of the embodiment in which the value of D1 / (D1+D2) is 42.90% or more, the number of NG samples was 2 or less out of 100 samples, further proving high stability.

[0070] In the multilayer ceramic capacitor 1 of the embodiment in which the value of D1 / (D1+D2) is 50% or more, ie, 57.70% or more, the number of NG capacitors was 0 or less out of 100, proving that the capacitor has higher stability.

[0071] Although the preferred embodiment of the present invention has been described above, the present invention is not limited to this and various modifications are possible.

[0072] A1 First surface A2 Second surface B1 Fifth surface B2 Sixth surface C1 Third surface C2 Fourth surface Q1 First region Q2 Second region 1 Multilayer ceramic capacitor 2 Laminate 3 External electrode 3A First external electrode 3B Second external electrode 30 Base electrode layer 30A First base electrode layer 30B Second base electrode layer 31 Surface plating layer 31A First surface plating layer 31Aa First inner surface plating layer 31Ab First outer surface plating layer 31B Second surface plating layer 31Ba Second inner surface plating layer 31Bb Second outer surface plating layer 31a Inner surface plating layer 31b Outer surface plating layer

Claims

a first surface and a second surface facing each other in a height direction; a third surface and a fourth surface facing each other in a first direction intersecting the height direction; a laminate having a fifth surface and a sixth surface facing each other in a second direction intersecting the height direction and the first direction; a first external electrode disposed on the third surface, the first surface, and the second surface; second external electrodes disposed on the fourth surface, the first surface, and the second surface; the first external electrode has a first base electrode layer and a first surface plating layer, the second external electrode has a second base electrode layer and a second surface plating layer, The dimension in the height direction is 0.08 mm or less, The dimension in the first direction is 0.16 mm or less, The dimension in the second direction is 0.08 mm or less, When viewed from the first surface side, the first external electrode has a first region and a second region located around the first region, the first region is a region in which the thickness of the first surface plating layer at the outer periphery of the first region is thicker than the thickness of the first surface plating layer in an internal region surrounded by the outer periphery, The area of ​​the first region is 33.50% or more of the area of ​​the second region. Multilayer ceramic capacitor. 　 The area of ​​the first region is 42.90% or more of the area of ​​the second region. The multilayer ceramic capacitor according to claim 1 . 　 The dimension of the multilayer ceramic capacitor in the height direction is smaller than the dimension in the second direction.

3. The multilayer ceramic capacitor according to claim 1. 　 The thickness of the first surface plating layer in the first region is 1.2 μm or more. The multilayer ceramic capacitor according to any one of claims 1 to 3. 　 The variation in the thickness of the outer periphery of the first region is 1.0 μm or less. The multilayer ceramic capacitor according to any one of claims 1 to 4. 　 a central portion of the first surface of the laminated body protrudes in the height direction more than an edge portion thereof in the first direction or the second direction; The multilayer ceramic capacitor according to any one of claims 1 to 5.

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