Nitride semiconductor device

Abstract

A nitride semiconductor device (1) comprises: a substrate (10); an n-type drift layer (12) provided above the substrate (10); a p-type block layer (14) provided above the drift layer (12); a nitride semiconductor layer (21) provided above the block layer (14); a p-type semiconductor layer (29) provided so as to be in contact with the block layer (14) in an opening (25) that penetrates the nitride semiconductor layer (21) and reaches the block layer (14); and an ohmic electrode (36) electrically connected to the p-type semiconductor layer (29).

Description

Nitride Semiconductor Devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Nitride semiconductors, such as GaN and AlGaN, have a larger band gap and a higher breakdown field and saturated drift velocity than compound semiconductor materials such as Si semiconductors or GaAs, and are therefore being applied to electronic devices such as high-voltage power devices and high-speed, high-output transistors.

[0003] Patent Document 1 discloses a vertical FET (Field Effect Transistor) formed using a GaN-based semiconductor material. The vertical FET disclosed in Patent Document 1 includes a drift layer made of n-type GaN and a current blocking layer made of p-type GaN between a source electrode and a drain electrode.

[0004] Patent No. 6511645

[0005] The device disclosed in Patent Document 1 has a problem in that the resistance increases during operation.

[0006] Therefore, the present disclosure provides a nitride semiconductor device that can suppress an increase in resistance during operation.

[0007] A nitride semiconductor device according to one aspect of the present disclosure includes a substrate, an n-type first nitride semiconductor layer provided above the substrate, a p-type second nitride semiconductor layer provided above the first nitride semiconductor layer, a third nitride semiconductor layer provided above the second nitride semiconductor layer, a p-type fourth nitride semiconductor layer provided in a first opening that penetrates the third nitride semiconductor layer and reaches the second nitride semiconductor layer so as to be in contact with the second nitride semiconductor layer, and a first electrode electrically connected to the fourth nitride semiconductor layer.

[0008] According to the present disclosure, an increase in resistance during operation can be suppressed.

[0009] FIG. 1 is a cross-sectional view of a nitride semiconductor device according to an embodiment. FIG. 2A is a cross-sectional view illustrating a step of a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 2B is a cross-sectional view illustrating a step of a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 2C is a cross-sectional view illustrating a step of a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 2D is a cross-sectional view illustrating a step of a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 2E is a cross-sectional view illustrating a step of a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 2F is a cross-sectional view illustrating a step of a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 2G is a cross-sectional view illustrating a step of a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view of a nitride semiconductor device according to a first modification of the embodiment. FIG. 4 is a cross-sectional view of a nitride semiconductor device according to a second modification of the embodiment. FIG. 5 is a cross-sectional view of a nitride semiconductor device according to a third modification of the embodiment. FIG. 6 is a cross-sectional view of a nitride semiconductor device according to a fourth modification of the embodiment. FIG. 7 is a plan view of a nitride semiconductor device according to the embodiment and each modification. FIG. 8 is a cross-sectional view of a nitride semiconductor device taken along line VIII-VIII of FIG. 7. FIG. 9 is a cross-sectional view of the nitride semiconductor device taken along line IX-IX in FIG.

[0010] (Findings that Form the Basis of the Present Disclosure) The present inventors have found that the following problems arise with the conventional devices described in the "Background Art" section.

[0011] The device disclosed in Patent Document 1 utilizes, as a channel, a two-dimensional electron gas (2DEG) generated by the polarization effect near the AlGaN / GaN heterointerface. Specifically, the 2DEG is generated by supplying a predetermined potential to the gate electrode so that a voltage equal to or greater than the threshold voltage is applied between the gate and source. This opens the channel, establishing electrical continuity between the drain electrode and the source electrode, allowing current to flow.

[0012] In the device disclosed in Patent Document 1, charges can accumulate in deep levels formed by impurities in the current blocking layer when the device is off. When charges accumulate in the current blocking layer, a sufficient amount of 2DEG cannot be generated near the heterointerface when the device is on, and the channel does not open completely, resulting in an increase in on-resistance.

[0013] In contrast, in the device disclosed in Patent Document 1, the source electrode is connected to the current blocking layer, so it is expected that the charge accumulated in the current blocking layer when the device is off will be extracted when the device is on. However, in order to connect the current blocking layer to the source electrode, the current blocking layer must be exposed by etching. Etching damage remains on the surface of the current blocking layer, and even if the source electrode and current blocking layer are connected, a good ohmic connection cannot be obtained. As a result, the charge accumulated in the current blocking layer cannot be extracted efficiently, and resistance increases during operation.

[0014] Therefore, an object of the present disclosure is to provide a nitride semiconductor device that can suppress an increase in resistance during operation.

[0015] A nitride semiconductor device according to a first aspect of the present disclosure comprises a substrate, an n-type first nitride semiconductor layer provided above the substrate, a p-type second nitride semiconductor layer provided above the first nitride semiconductor layer, a third nitride semiconductor layer provided above the second nitride semiconductor layer, a p-type fourth nitride semiconductor layer provided in a first opening that passes through the third nitride semiconductor layer and reaches the second nitride semiconductor layer so as to be in contact with the second nitride semiconductor layer, and a first electrode electrically connected to the fourth nitride semiconductor layer.

[0016] In this way, the first electrode is in contact with the p-type fourth nitride semiconductor layer, rather than the p-type second nitride semiconductor layer, which may be subject to etching damage. This reduces contact resistance compared to contact with the second nitride semiconductor layer, allowing charges accumulated in the second nitride semiconductor layer to be efficiently extracted to the first electrode via the fourth nitride semiconductor layer. This makes it possible to suppress an increase in resistance during operation of the nitride semiconductor device according to this aspect.

[0017] A nitride semiconductor device according to a second aspect of the present disclosure is the nitride semiconductor device according to the first aspect, further comprising a gate electrode provided above the third nitride semiconductor layer, a source electrode provided above the substrate and electrically connected to the third nitride semiconductor layer, and a drain electrode provided below the substrate, wherein the first electrode is electrically connected to the source electrode.

[0018] This results in a pn diode including the first electrode as an anode electrode and the drain electrode as a cathode electrode, and having pn junctions between the p-type second nitride semiconductor layer, the p-type fourth nitride semiconductor layer, and the n-type first nitride semiconductor layer. During freewheeling operation, in which current flows from the source electrode to the drain electrode, a current can flow through the pn diode. Since the drive voltage during freewheeling operation can be lowered, loss can be reduced.

[0019] A nitride semiconductor device according to a third aspect of the present disclosure is the nitride semiconductor device according to the second aspect, wherein the third nitride semiconductor layer is provided so as to cover an inner surface of a second opening that penetrates the second nitride semiconductor layer at a position away from the first opening and reaches the first nitride semiconductor layer, and an upper portion of the second nitride semiconductor layer.

[0020] This allows the third nitride semiconductor layer including the channel to come into contact with the n-type first nitride semiconductor layer at the bottom of the second opening, thereby reducing the on-resistance.

[0021] A nitride semiconductor device according to a fourth aspect of the present disclosure is the nitride semiconductor device according to the third aspect, further comprising a p-type fifth nitride semiconductor layer provided between the gate electrode and the third nitride semiconductor layer and electrically isolated from the fourth nitride semiconductor layer.

[0022] This increases the potential at the conduction band edge of the channel, thereby increasing the threshold voltage and realizing a normally-off FET.

[0023] A nitride semiconductor device according to a fifth aspect of the present disclosure is the nitride semiconductor device according to the fourth aspect, wherein the gate electrode and the fifth nitride semiconductor layer are provided at positions overlapping the second opening in a planar view of the substrate.

[0024] As a result, the channel in the third nitride semiconductor layer along the side surface of the second opening is controlled by the potential applied to the gate electrode. Because the side surface of the second opening includes the end face of the second nitride semiconductor layer, the influence of remaining charges on the channel is significant. Therefore, the effect of suppressing an increase in on-resistance by efficiently extracting charges is useful.

[0025] A nitride semiconductor device according to a sixth aspect of the present disclosure is the nitride semiconductor device according to the fourth aspect, wherein the gate electrode and the fifth nitride semiconductor layer are provided at positions that overlap the second nitride semiconductor layer but do not overlap the second opening in a planar view of the substrate.

[0026] This increases the distance between the gate electrode and the drain electrode, reducing the gate-drain parasitic capacitance Cgd, thereby enabling faster switching of the FET.

[0027] A nitride semiconductor device according to a seventh aspect of the present disclosure is the nitride semiconductor device according to the sixth aspect, further comprising: a second electrode set to the same potential as the source electrode, provided at a position overlapping a bottom surface of the second opening in a planar view of the substrate; and a p-type sixth nitride semiconductor layer provided between the second electrode and the third nitride semiconductor layer and electrically isolated from the fifth nitride semiconductor layer.

[0028] This allows the electric field lines extending from the drain electrode to terminate at the sixth nitride semiconductor layer and the second nitride semiconductor layer, thereby reducing the gate-drain parasitic capacitance Cgd and enabling faster switching of the FET.

[0029] A nitride semiconductor device according to an eighth aspect of the present disclosure is the nitride semiconductor device according to any one of the second to seventh aspects, wherein the third nitride semiconductor layer includes an electron transit layer and an electron supply layer provided above the electron transit layer and having a band gap larger than that of the electron transit layer.

[0030] This makes it possible to utilize the high electron mobility of the 2DEG generated in the vicinity of the heterointerface between the electron transit layer and the electron supply layer, thereby enabling the switching speed of the FET to be increased.

[0031] A nitride semiconductor device according to a ninth aspect of the present disclosure is the nitride semiconductor device according to the eighth aspect, wherein the source electrode is in contact with the electron transit layer within a third opening that penetrates the electron supply layer and reaches the electron transit layer.

[0032] This allows the source electrode to come into direct contact with the 2DEG, reducing the contact resistance of the source electrode and the on-resistance.

[0033] A nitride semiconductor device according to a tenth aspect of the present disclosure is the nitride semiconductor device according to the ninth aspect, wherein the third opening does not penetrate the electron transit layer and does not reach the second nitride semiconductor layer.

[0034] This reduces the depth of the opening, thereby shortening the dry etching time, reducing dry etching damage to the 2DEG, and reducing the contact resistance of the source electrode, thereby reducing the on-resistance.

[0035] A nitride semiconductor device according to an eleventh aspect of the present disclosure is the nitride semiconductor device according to any one of the third to seventh aspects, further comprising a high-resistance layer provided between the first nitride semiconductor layer and the second nitride semiconductor layer, the high-resistance layer having a higher resistance than both the first nitride semiconductor layer and the second nitride semiconductor layer, and the second opening penetrates the high-resistance layer to reach the first nitride semiconductor layer.

[0036] As a result, the high resistance layer is provided, and the breakdown voltage between the source and drain can be increased.

[0037] A nitride semiconductor device according to a twelfth aspect of the present disclosure is the nitride semiconductor device according to any one of the second to eleventh aspects, wherein the first electrode contains, as a main component, the same material as the material contained as a main component of the gate electrode.

[0038] This allows the gate electrode and the first electrode to be formed in the same process, thereby preventing the manufacturing process from becoming complicated.

[0039] A nitride semiconductor device according to a thirteenth aspect of the present disclosure is the nitride semiconductor device according to the fourth or fifth aspect, wherein the distance between the fifth nitride semiconductor layer and the substrate is shorter than the distance between the second nitride semiconductor layer and the substrate.

[0040] This allows the electric field to be dispersed to the lower surface of the fifth nitride semiconductor layer as well, making it possible to suppress electric field concentration at the lower end of the second nitride semiconductor layer and increasing the breakdown voltage.

[0041] A nitride semiconductor device according to a fourteenth aspect of the present disclosure is the nitride semiconductor device according to any one of the second to thirteenth aspects, comprising a plurality of the source electrodes and a plurality of the first electrodes, and when the substrate is divided into a first region and a second region located outside the first region in a plan view of the substrate, the plurality of source electrodes and the plurality of the first electrodes are provided in the first region.

[0042] This allows the charges accumulated in the second nitride semiconductor layer to be extracted within the device region. Because the extraction path for the charges is shortened, the charges can be extracted efficiently, enabling faster switching of the FET.

[0043] A nitride semiconductor device according to a fifteenth aspect of the present disclosure is the nitride semiconductor device according to any one of the second to thirteenth aspects, comprising a plurality of source electrodes, and when the substrate is divided into a first region and a second region located outside the first region in a plan view of the substrate, the plurality of source electrodes are provided in the first region, and the first electrode is provided in the second region.

[0044] This allows a large-area pn diode to be formed outside the device region, so that the operating voltage for freewheeling can be lowered and loss can be reduced.

[0045] A nitride semiconductor device according to a sixteenth aspect of the present disclosure is the nitride semiconductor device according to the fifteenth aspect, further comprising a source pad provided in the second region and receiving a potential supplied to the plurality of source electrodes.

[0046] This allows the region below the source pad to be effectively used as a pn diode, thereby realizing miniaturization of the nitride semiconductor device.

[0047] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0048] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0049] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0050] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or orthogonal, terms indicating the shape of elements, such as rectangular or trapezoidal, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0051] In this specification, the "thickness direction" of a substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may be referred to as the "lateral direction." A "vertical" device refers to a device in which the main path of a main current, such as a drain current or a forward current, is vertical, i.e., a device in which the main current passes vertically through the substrate. A "lateral" semiconductor device refers to a device in which the main path of a main current, such as a drain current or a forward current, is horizontal, i.e., a device in which the main current does not pass through the substrate.

[0052] Furthermore, the side on which the heterostructure is provided with respect to the substrate is considered to be "upper" or "upper side," and the opposite side is considered to be "lower" or "lower side." In this specification, the terms "upper" and "lower" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Furthermore, the terms "upper" and "lower" are used not only when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged in close contact with each other and the two components are in contact.

[0053] In this specification, unless otherwise specified, the term "plan view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, a view of the main surface of the substrate from the front.

[0054] In addition, in this specification, "A and B overlap in a plan view" means that at least a part of A overlaps with at least a part of B. In other words, this includes cases where only a part of A overlaps with only a part of B, where all of A overlaps with B, where all of B overlaps with A, and where A and B completely overlap with each other.

[0055] In this specification, AlGaN refers to a ternary mixed crystal Al ｘ Ga １－ｘHereinafter, multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, such as AlInN, GaInN, etc. For example, AlInN, which is an example of a nitride semiconductor, ｘ Ga １－ｘ－ｙ In ｙ N (0<x<1, 0<y<1, and 0<x+y<1) is abbreviated as AlGaInN, where x, 1-xy, and y represent the composition ratios of Al, Ga, and In, respectively.

[0056] Furthermore, n-type and p-type indicate the conductivity types of semiconductors, and are conductivity types of opposite polarity. ＋ The n-type indicates a state in which a semiconductor is doped with a high concentration of n-type dopants, i.e., a heavily doped semiconductor. － The term "type" refers to a state in which a semiconductor is doped with a low concentration of n-type dopant, i.e., a so-called lightly doped state. ＋ Type and n － Both types are examples of n-type, and may be referred to as n-type without distinction. ＋ Type and p － The same is true for types.

[0057] Furthermore, "A contains B as a main component" means that B has the highest composition ratio among the elements constituting A. Furthermore, a layer made of A and a layer constituted by A mean that the layer contains substantially only A. However, the layer may contain other elements as impurities, such as elements that are unavoidable in the manufacturing process, at a rate of 1 at % or less.

[0058] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0059] (Embodiment) [Configuration] First, the configuration of a nitride semiconductor device according to an embodiment will be described with reference to FIG.

[0060] Fig. 1 is a cross-sectional view of a nitride semiconductor device 1 according to an embodiment. In Fig. 1, components such as semiconductor layers, insulating layers, and electrodes other than an electron transit layer 22 are shaded with diagonal lines to indicate a cross section. This is also true for Fig. 2A and subsequent cross-sectional views.

[0061] The nitride semiconductor device 1 includes a normally-off vertical FET. In the nitride semiconductor device 1, for example, the source electrode 34 is grounded, and a positive potential is applied to the drain electrode 38. The potential applied to the drain electrode 38 is, for example, not limited to, 100 V or more and 1200 V or less. The nitride semiconductor device 1 performs modulation according to the potential applied to the gate electrode 32. For example, when 0 V or a negative potential (e.g., −5 V) is applied to the gate electrode 32, no current flows between the drain electrode 38 and the source electrode 34. In other words, the nitride semiconductor device 1 is in a non-conductive state (off). When a positive potential (e.g., +5 V) is applied to the gate electrode 32, a current flows from the drain electrode 38 to the source electrode 34. In other words, the nitride semiconductor device 1 is in a conductive state (on). The current flowing from the drain electrode 38 to the source electrode 34 when the device is on is called a drain current. The drain current flows through the substrate 10 in its thickness direction (i.e., vertical direction).

[0062] 1 , the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a block layer 14, a nitride semiconductor layer 21, a threshold adjustment layer 28, a p-type semiconductor layer 29, a gate electrode 32, a source electrode 34, an ohmic electrode 36, and a drain electrode 38. The nitride semiconductor layer 21 includes an electron transit layer 22, an electron supply layer 23, and a 2DEG 24. The nitride semiconductor device 1 further includes an insulating layer 40 and a source wiring 50. The nitride semiconductor device 1 also includes a vertical conduction opening 20, an opening 25, and a source opening 30.

[0063] The nitride semiconductor device 1 is a device in which a semiconductor layer including a channel contains a nitride semiconductor as a main component. Specifically, the drift layer 12, the block layer 14, the electron transit layer 22, the electron supply layer 23, the threshold adjustment layer 28, and the p-type semiconductor layer 29 each contain a nitride semiconductor as a main component.

[0064] Each of the components of the nitride semiconductor device 1 will be described in detail below.

[0065] The substrate 10 is made of a nitride semiconductor and has a rectangular shape in plan view, for example, but is not limited to this.

[0066] The substrate 10 has a thickness of, for example, 300 μm and a carrier concentration of 5×10 １８ cm －３ n ＋ The substrate is made of GaN.

[0067] The substrate 10 does not have to be a nitride semiconductor substrate, but may be, for example, a Si substrate, a SiC substrate, or a ZnO substrate.

[0068] The drift layer 12 is an example of an n-type first nitride semiconductor layer provided above the substrate 10. The drift layer 12 is, for example, an n-type first nitride semiconductor layer having a thickness of 8 μm. － The drift layer 12 is a film made of GaN of the type. The donor concentration of the drift layer 12 is, for example, 1×10 １５ cm －３ 1x10 or more １７ cm －３ As an example, １６ cm －３ The carbon concentration (C concentration) of the drift layer 12 is, for example, 1×10 １５ cm －３ 5x10 or more １６ cm －３ The drift layer 12 is provided in contact with, for example, the upper surface (main surface) of the substrate 10 .

[0069] The block layer 14 is an example of a p-type second nitride semiconductor layer provided above the drift layer 12. The block layer 14 has a thickness of 400 nm and a carrier concentration of 1×10 １７ cm －３ The block layer 14 is a film made of p-type GaN, where P is a GaN film. The block layer 14 is provided in contact with the upper surface of the drift layer 12.

[0070] A vertical conduction opening 20 is provided in the block layer 14. The vertical conduction opening 20 is an example of a second opening that penetrates the block layer 14 at a position away from the opening 25 and reaches the drift layer 12. A bottom surface 20a of the vertical conduction opening 20 is part of the upper surface of the drift layer 12. As shown in FIG. 1 , the bottom surface 20a is located below the lower surface of the block layer 14. The lower surface of the block layer 14 corresponds to the interface between the block layer 14 and the drift layer 12. The bottom surface 20a is, for example, parallel to the major surface of the substrate 10. When the nitride semiconductor device 1 is on, a drain current flows between the drain electrode 38 and the source electrode 34 through the bottom surface 20a of the vertical conduction opening 20.

[0071] In this embodiment, the vertical conductive opening 20 is formed so that the opening area increases as it becomes farther from the substrate 10. Specifically, the side surface 20b of the vertical conductive opening 20 is inclined obliquely. As shown in FIG. 1 , the cross-sectional shape of the vertical conductive opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0072] The inclination angle of the side surface 20b with respect to the bottom surface 20a is, for example, 20° to 80°, but may be 30° to 45°. The smaller the inclination angle, the closer the side surface 20b is to the c-plane, thereby improving the film quality of the electron transit layer 22 and other layers formed along the side surface 20b by crystal regrowth. On the other hand, the larger the inclination angle, the more effectively the vertical conduction opening 20 is prevented from becoming too large, thereby realizing a more compact nitride semiconductor device 1. The side surface 20b may be perpendicular to the bottom surface 20a.

[0073] The electron transit layer 22 is an example of a first regrowth layer provided to cover the inner surface of the vertical conduction opening 20 and the upper part of the block layer 14. Specifically, a part of the electron transit layer 22 is provided along the bottom surface 20 a and the side surface 20 b of the vertical conduction opening 20, and another part of the electron transit layer 22 is provided on the upper surface of the block layer 14. The electron transit layer 22 is, for example, a film made of undoped GaN with a thickness of 150 nm. Note that although the electron transit layer 22 is assumed to be undoped, a part of it may be made n-type by, for example, doping with Si.

[0074] The electron transit layer 22 is in contact with the drift layer 12 at the bottom surface 20 a and the side surface 20 b of the vertical conduction opening 20. The electron transit layer 22 is in contact with the block layer 14 at the side surface 20 b of the vertical conduction opening 20. The electron transit layer 22 is in contact with the top surface of the block layer 14.

[0075] The electron transit layer 22 has a channel region. Specifically, a 2DEG 24, which serves as a channel, is generated near the interface between the electron transit layer 22 and the electron supply layer 23. The 2DEG 24 is bent along the interface between the electron transit layer 22 and the electron supply layer 23, i.e., along the inner surface of the vertical conduction opening 20.

[0076] 1, an AlN layer having a thickness of about 1 nm is provided as a second regrown layer between the electron transit layer 22 and the electron supply layer 23. This suppresses alloy scattering, improves channel mobility, and makes it possible to reduce on-resistance. However, the AlN layer is not necessarily required.

[0077] The electron supply layer 23 is an example of a third regrowth layer provided above the electron transit layer 22. Specifically, the electron supply layer 23 is provided so as to cover the inner surface of the vertical conduction opening 20 and the upper side of the block layer 14. Specifically, the electron supply layer 23 is provided along the upper surface of the electron transit layer 22 so as to overlap the bottom surface 20 a and side surface 20 b of the vertical conduction opening 20 and the upper surface of the block layer 14 in a planar view of the substrate 10. The electron supply layer 23 is, for example, a film made of undoped AlGaN with a thickness of 20 nm. The electron supply layer 23 is formed to a shape that conforms to the upper surface of the electron transit layer 22 and to a substantially uniform thickness.

[0078] The electron supply layer 23 has a larger band gap than the electron transit layer 22. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 23 and the electron transit layer 22. The electron supply layer 23 supplies electrons to a channel region (2DEG 24) formed in the electron transit layer 22.

[0079] The electron transit layer 22 and the electron supply layer 23 are both layers included in the nitride semiconductor layer 21 provided in the nitride semiconductor device 1. The nitride semiconductor layer 21 is an example of a third nitride semiconductor layer provided above the block layer 14. Note that "provided above" means that at least a portion of the nitride semiconductor layer 21 is located above the block layer 14. In other words, at least a portion of the nitride semiconductor layer 21 is located above the block layer 14. In this embodiment, the nitride semiconductor layer 21 is provided so as to cover the inner surface of the vertical conduction opening 20 and the upper portion of the block layer 14.

[0080] An opening 25 is provided in the nitride semiconductor layer 21. The opening 25 is an example of a first opening that penetrates the nitride semiconductor layer 21 and reaches the block layer 14. Specifically, the opening 25 penetrates the electron supply layer 23 and the electron transit layer 22 and reaches the block layer 14. A bottom surface 25 a of the opening 25 is part of the upper surface of the block layer 14. As shown in FIG. 1 , the bottom surface 25 a is located below the lower surface of the electron transit layer 22. The lower surface of the electron transit layer 22 corresponds to the interface between the electron transit layer 22 and the block layer 14. The bottom surface 25 a is, for example, parallel to the major surface of the substrate 10. In this embodiment, the side surface 25 b of the opening 25 is perpendicular to the bottom surface 25 a, but may be inclined with respect to the bottom surface 25 a.

[0081] The p-type semiconductor layer 29 is an example of a p-type fourth nitride semiconductor layer provided in the opening 25 so as to be in contact with the block layer 14. Specifically, the p-type semiconductor layer 29 covers and is in contact with the bottom surface 25 a and the side surface 25 b of the opening 25, and is in contact with the block layer 14 at the bottom surface 25 a and parts of the side surface 25 b. The p-type semiconductor layer 29 also covers the upper surface of the nitride semiconductor layer 21. Specifically, the p-type semiconductor layer 29 overlaps the electron supply layer 23 in a plan view and covers and is in contact with part of the upper surface of the electron supply layer 23. More specifically, the p-type semiconductor layer 29 covers and is in contact with a part of the upper surface of the electron supply layer 23 that is located between the opening 25 and the source opening 30, of the upper surface of the electron supply layer 23.

[0082] The p-type semiconductor layer 29 has a thickness of 200 nm and a carrier concentration of 5×10 １７ cm －３The p-type semiconductor layer 29 is a film made of p-type GaN, which has the same composition and carrier concentration as the threshold adjustment layer 28. Note that the thickness and carrier concentration of the p-type semiconductor layer 29 are merely examples and can be changed as appropriate.

[0083] The threshold adjustment layer 28 is an example of a p-type fifth nitride semiconductor layer provided between the gate electrode 32 and the nitride semiconductor layer 21. Specifically, the threshold adjustment layer 28 is provided between the upper surface of the electron supply layer 23 and the lower surface of the gate electrode 32 in contact with each other.

[0084] In the present embodiment, the threshold adjustment layer 28 is provided at a position overlapping each of the vertical conductive opening 20 and the block layer 14 in a plan view of the substrate 10. Specifically, the threshold adjustment layer 28 overlaps the bottom surface 20a and the side surface 20b of the vertical conductive opening 20 and the upper surface of the block layer 14 in a plan view of the substrate 10. The threshold adjustment layer 28 is electrically isolated from the p-type semiconductor layer 29. Furthermore, the threshold adjustment layer 28 is disposed at a distance from the source electrode 34 and the ohmic electrode 36, and is electrically isolated from them.

[0085] The threshold adjustment layer 28 has a thickness of 200 nm and a carrier concentration of 5×10 １７ cm －３ The thickness and carrier concentration of the threshold adjustment layer 28 are merely examples and can be changed as appropriate.

[0086] The provision of the threshold adjustment layer 28 raises the potential of the conduction band edge in the channel portion. This reduces the carrier concentration directly below the gate electrode 32, shifting the threshold voltage of the transistor to the positive side. This makes it easy to realize the nitride semiconductor device 1 as a normally-off FET. The threshold adjustment layer 28 may be a film made of p-type AlGaN.

[0087] The source opening 30 is an example of a third opening that penetrates the electron supply layer 23 and reaches the electron transit layer 22 outside the vertical conduction opening 20 in a plan view of the substrate 10. In the present embodiment, the source opening 30 does not penetrate the electron transit layer 22 and does not reach the block layer 14. That is, the source opening 30 is an opening that is shallower than the opening 25. The source opening 30 is provided at a position away from both the gate electrode 32 and the threshold adjustment layer 28 in a plan view of the substrate 10. Specifically, the source opening 30 is provided between the threshold adjustment layer 28 and the opening 25 in a plan view of the substrate 10.

[0088] A bottom surface 30a of the source opening 30 is part of the upper surface of the electron transit layer 22. The bottom surface 30a is parallel to, for example, the main surface of the substrate 10. In the example shown in FIG. 1 , the bottom surface 30a is located lower than the lower surface of the electron supply layer 23. The lower surface of the electron supply layer 23 corresponds to the heterointerface between the electron supply layer 23 and the electron transit layer 22. The bottom surface 30a is located lower than the 2DEG 24 generated near the heterointerface. In other words, the 2DEG 24 is exposed on the side surface 30b of the source opening 30.

[0089] As shown in FIG. 1 , the source opening 30 is formed so that the opening area increases with increasing distance from the substrate 10. Specifically, the side surface 30 b of the source opening 30 is obliquely inclined. For example, the cross-sectional shape of the source opening 30 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid. In this case, the inclination angle of the side surface 30 b relative to the bottom surface 30 a is, for example, in the range of 30° to 60°. The oblique inclination of the side surface 30 b increases the contact area between the source electrode 34 and the 2DEG 24, facilitating ohmic contact. The 2DEG 24 is exposed on the side surface 30 b of the source opening 30 and connected to the source electrode 34 at the exposed portion. The side surface 30 b may also be perpendicular to the bottom surface 30 a.

[0090] The provision of the source opening 30 can reduce the ohmic contact resistance between the 2DEG 24 functioning as a channel and the source electrode 34. That is, the on-resistance of the nitride semiconductor device 1 can be reduced.

[0091] The gate electrode 32 is provided above the nitride semiconductor layer 21. Specifically, the gate electrode 32 is provided on the upper surface of the threshold adjustment layer 28 and is electrically connected to the threshold adjustment layer 28. In the present embodiment, the gate electrode 32 is provided at a position overlapping each of the vertical conductive opening 20 and the block layer 14 in a plan view of the substrate 10. Specifically, the gate electrode 32 overlaps the bottom surface 20 a and the side surface 20 b of the vertical conductive opening 20 and the upper surface of the block layer 14 in a plan view of the substrate 10. The gate electrode 32 is disposed apart from the source electrode 34 and the ohmic electrode 36 and is electrically isolated from them.

[0092] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 may be formed using a material that forms an ohmic contact with a p-type nitride semiconductor such as p-type GaN, but is not limited thereto and may also be formed using a material that forms a Schottky contact with the p-type nitride semiconductor. For example, the gate electrode 32 may be formed using Pd, a Ni-based material, WSi, Au, or the like.

[0093] The source electrode 34 is provided above the substrate 10 and electrically connected to the nitride semiconductor layer 21. In this embodiment, the source electrode 34 is in contact with the electron transit layer 22 within the source opening 30. Specifically, the source electrode 34 is provided in contact with the bottom surface 30a and the side surface 30b of the source opening 30. The source electrode 34 is in direct contact with the 2DEG 24 at the side surface 30b of the source opening 30. This reduces the contact resistance between the source electrode 34 and the 2DEG 24, thereby reducing the on-resistance of the nitride semiconductor device 1.

[0094] The source electrode 34 is formed using a conductive material such as a metal. Examples of the material for the source electrode 34 include Ti / Al (a laminated structure of a Ti layer and an Al layer), which can be ohmically connected to an n-type nitride semiconductor such as n-type GaN by heat treatment.

[0095] The ohmic electrode 36 is an example of a first electrode electrically connected to the p-type semiconductor layer 29. The ohmic electrode 36 is also electrically connected to the source electrode 34. In this embodiment, the ohmic electrode 36 is in contact with and covers the upper surface of the p-type semiconductor layer 29 and the upper surface of the source electrode 34.

[0096] The ohmic electrode 36 may be made of a material that forms an ohmic contact with a p-type nitride semiconductor such as p-type GaN. For example, the ohmic electrode 36 may be made of Pd, a Ni-based material, WSi, Au, or the like.

[0097] The drain electrode 38 is provided below the substrate 10. Specifically, the drain electrode 38 is provided in contact with the lower surface of the substrate 10.

[0098] The drain electrode 38 is formed using a conductive material such as a metal. As with the material of the source electrode 34, the material of the drain electrode 38 may be, for example, Ti / Al, which is a material that forms an ohmic contact with an n-type nitride semiconductor such as n-type GaN.

[0099] The insulating layer 40 is provided above the gate electrode 32. Specifically, the insulating layer 40 is provided so as to cover the gate electrode 32, the threshold adjustment layer 28, the electron supply layer 23, the source electrode 34, and the ohmic electrode 36. The insulating layer 40 has a laminated structure of a plurality of insulating films. The plurality of insulating films may be made of, for example, SiN, SiO ２ , SiON, Al ２ O ３ The insulating layer 40 may have a single layer structure of one insulating film.

[0100] The source wiring 50 is provided above the insulating layer 40 and is connected to the source electrode 34 through an opening provided in the insulating layer 40. Specifically, the source wiring 50 is electrically connected to the source electrode 34 through an ohmic electrode 36. The source wiring 50 is formed using a conductive material such as a metal. For example, the source wiring 50 is a plated film made of Au.

[0101] 1 , the opening 25, the source opening 30, the p-type semiconductor layer 29, the source electrode 34, and the ohmic electrode 36 are provided on both sides in the lateral direction of the vertical conductive opening 20, the threshold adjustment layer 28, and the gate electrode 32, but this is not limiting. The opening 25, the source opening 30, the p-type semiconductor layer 29, the source electrode 34, and the ohmic electrode 36 may be provided on only one side of the vertical conductive opening 20, the threshold adjustment layer 28, and the gate electrode 32.

[0102] [Manufacturing Method] Next, a method for manufacturing the nitride semiconductor device 1 according to this embodiment will be described with reference to Figures 2A to 2G. Figures 2A to 2G are cross-sectional views for explaining a step in the method for manufacturing the nitride semiconductor device 1 according to this embodiment. The cross-sectional configuration of the device during manufacturing changes in the order of Figures 2A to 2G.

[0103] First, as shown in FIG. 2A , a drift layer 12 and a block layer 14 are formed in this order by crystal growth above a substrate 10. Specifically, a nitride semiconductor is crystal-grown on the main surface of the substrate 10 by epitaxial growth, such as MOCVD (Metal Oxide Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy). By adjusting growth conditions, such as raw materials, growth temperature, and growth time, the composition, film thickness, impurity concentration, and the like, can be adjusted to values ​​appropriate for each layer. For example, n-type GaN is crystal-grown as the drift layer 12, and then p-type GaN is crystal-grown as the block layer 14. Si, for example, is used as the n-type impurity, and Mg, for example, is used as the p-type impurity. For example, the drift layer 12 and the block layer 14 are formed consecutively in the same growth furnace without being exposed to the atmosphere during the process. Although the block layer 14 is formed by crystal growth, it may also be formed by, for example, implanting Mg into a deposited i-GaN film.

[0104] Next, as shown in FIG. 2B , a vertical conductive opening 20 is formed through the block layer 14. For example, a photosensitive photoresist is applied to the upper surface of the block layer 14 and patterned into a predetermined shape by photolithography. The patterned photosensitive photoresist (i.e., a resist mask) has an opening at a position corresponding to the vertical conductive opening 20, exposing the upper surface of the block layer 14. At this time, the side surface of the resist mask opening can be sloped by adjusting baking conditions such as the baking temperature of the resist mask. Then, the vertical conductive opening 20 is formed by removing a portion of the block layer 14 and the drift layer 12 in an area not covered by the resist mask by dry etching or the like. The side surface 20b of the vertical conductive opening 20 is inclined according to the slope of the side surface of the resist mask opening. After the vertical conductive opening 20 is formed, the resist mask is peeled off.

[0105] 2C , an electron transit layer 22 and an electron supply layer 23 are formed in this order by crystal growth (second crystal growth) so as to cover the vertical conduction opening 20 and the block layer 14. For example, undoped GaN is epitaxially grown as the electron transit layer 22 so as to entirely cover the bottom surface 20 a and side surface 20 b of the vertical conduction opening 20 and the upper surface of the block layer 14, and then undoped AlGaN is successively grown as the electron supply layer 23. After forming the undoped GaN, undoped AlN may be formed before forming the undoped AlGaN.

[0106] 2D , an opening 25 is formed that penetrates the electron supply layer 23 and the electron transit layer 22. Specifically, similar to the formation of the vertical conduction opening 20, the opening 25 is formed by forming a resist mask by photolithography and then performing dry etching to expose a part of the block layer 14.

[0107] 2E , a p-type semiconductor layer 28A is formed by crystal growth (third crystal growth) so as to cover the opening 25. For example, p-type GaN is grown as the p-type semiconductor layer 28A by epitaxial growth so as to entirely cover the bottom surface 25a and side surface 25b of the opening 25 and the upper surface of the electron supply layer 23. As a result, the bottom surface 25a, which may be damaged by dry etching, is covered by the p-type semiconductor layer 28A. The p-type semiconductor layer 28A is a semiconductor film that serves as the basis for the threshold adjustment layer 28 and the p-type semiconductor layer 29.

[0108] Next, as shown in FIG. 2F , a portion of the p-type semiconductor layer 28A is removed to separate the p-type semiconductor layer 28A into the threshold adjustment layer 28 and the p-type semiconductor layer 29. Furthermore, a source opening 30 is formed through the electron supply layer 23. Removal of the portion of the p-type semiconductor layer 28A and formation of the source opening 30 are performed in two steps, similar to the formation of the vertical conduction opening 20, by forming a resist mask by photolithography and then dry etching. The source opening 30 is formed after separation into the threshold adjustment layer 28 and the p-type semiconductor layer 29, but this is not limited thereto. For example, after forming the source opening 30, a portion of the p-type semiconductor layer 28A in the range from the opening edge of the source opening 30 to the opening edge of the vertical conduction opening 20 may be removed. For example, the end face of the p-type semiconductor layer 29 on the source opening 30 side is an inclined surface flush with the side surface 30b of the source opening 30, but this is not limited thereto. A step may be formed between the end face of the p-type semiconductor layer 29 on the source opening 30 side and the side surface 30 b of the source opening 30 .

[0109] Next, as shown in FIG. 2G , the gate electrode 32, the source electrode 34, and the ohmic electrode 36 are formed. For example, a metal film is formed by sputtering or EB (Electron Beam) deposition using a metal material that can be ohmic-contacted to an n-type nitride semiconductor, and then the source electrode 34 is formed in a predetermined shape by etching or lift-off. Next, a metal film is formed by sputtering or EB deposition using a metal material that can be ohmic-contacted to a p-type nitride semiconductor, and then the gate electrode 32 and the ohmic electrode 36 are formed in a predetermined shape by etching or lift-off. In other words, the gate electrode 32 and the ohmic electrode 36 can be formed in the same process using the same material. This simplifies the manufacturing process. Note that the gate electrode 32 and the ohmic electrode 36 may be formed in different processes using different materials.

[0110] Next, the nitride semiconductor device 1 shown in FIG. 1 is manufactured by forming an insulating layer 40, a source wiring 50, and a drain electrode 38. For example, first, the insulating layer 40 is formed by plasma CVD, atomic layer deposition (ALD), or the like so as to cover the gate electrode 32, the source electrode 34, the ohmic electrode 36, and the like. Then, an opening exposing at least a portion of the ohmic electrode 36 and / or the source electrode 34 is formed in the insulating layer 40 by dry etching or the like. Next, the source wiring 50 is formed by plating or the like so as to contact the ohmic electrode 36 and / or the source electrode 34 in the formed opening. Also, although not shown, a gate wiring, a source pad, a gate pad, and the like connected to the gate electrode 32 are also formed. Finally, the drain electrode 38 is formed on the lower surface of the substrate 10 by sputtering, EB evaporation, or the like.

[0111] Through the above steps, the nitride semiconductor device 1 shown in Fig. 1 is manufactured. Note that the above-described manufacturing method is merely an example, and the order of steps and specific processing can be changed as appropriate.

[0112] [Characteristic Configuration] Next, the main characteristic configuration of the nitride semiconductor device 1 according to this embodiment will be described. Specifically, the connection relationship between the block layer 14 and the ohmic electrode 36 will be described.

[0113] Because the opening 25 for exposing the block layer 14 is formed by dry etching, etching damage may remain on the upper surface of the block layer 14 exposed as the bottom surface 25 a of the opening 25. For this reason, even if the ohmic electrode 36 is formed so as to be in direct contact with the block layer 14, it is difficult to achieve an ohmic connection to the block layer 14.

[0114] In contrast, in this embodiment, the ohmic electrode 36 is electrically connected to the block layer 14 via the p-type semiconductor layer 29. The surface of the p-type semiconductor layer 29 is formed by epitaxial growth and is free from etching damage. This allows for good ohmic contact between the ohmic electrode 36 and the p-type semiconductor layer 29, thereby reducing contact resistance. Furthermore, because the p-type semiconductor layer 29 and the block layer 14 are layers made of the same p-type nitride semiconductor, charge transfer is smooth.

[0115] Therefore, when the FET is turned on, charges accumulated in the block layer 14 near the side surface 20b of the vertical conductive opening 20 can be efficiently extracted to the ohmic electrode 36 via the p-type semiconductor layer 29. Simply put, the potential of the block layer 14 is likely to return to a normal value (e.g., 0 V) ​​immediately after switching from off to on. This makes it possible to suppress a decrease in the concentration of the 2DEG 24 when the FET is turned on, and to suppress an increase in on-resistance. A highly reliable nitride semiconductor device 1 can be realized, with on / off switching being performed appropriately and with high switching accuracy.

[0116] In this embodiment, a pn junction is formed between the p-type semiconductor layer 29 and the p-type block layer 14 and the n-type drift layer 12, thereby forming a pn diode with the ohmic electrode 36 as the anode electrode and the drain electrode 38 as the cathode electrode. The FET may perform a free-wheeling operation, i.e., the source electrode may be at a higher potential than the drain electrode, causing a current (called a free-wheeling current) to flow from the source electrode to the drain electrode. The free-wheeling current may flow through a first path through the 2DEG 24 and a second path through the pn diode. The free-wheeling current is more likely to flow through the path with the lower resistance of the first or second path.

[0117] If the p-type semiconductor layer 29 is not provided and the source electrode 34 or the ohmic electrode 36 is in contact with the block layer 14, a good ohmic connection cannot be achieved, resulting in high contact resistance. For this reason, the main path for the return current is the first path. However, when the return current is caused to flow through the first path, the drive voltage applied between the drain and source also increases. This is because, in the case of return operation, a negative bias must be applied to the gate electrode 32 to suppress malfunction, and a drain voltage that is smaller (with a larger absolute value) than the negative bias is applied.

[0118] In contrast, in this embodiment, the contact resistance between the ohmic electrode 36 and the p-type semiconductor layer 29 is low, so the return current is more likely to flow through the second path. The second path is not affected by the negative bias applied to the gate electrode 32, and the drive voltage applied between the drain and source only needs to exceed the turn-on voltage of the pn diode, which is smaller than when the current flows through the first path. Therefore, the drive voltage can be reduced, and loss can be reduced.

[0119] [Modifications] Next, several modifications of the embodiment will be described. In the following description, differences from the nitride semiconductor device 1 according to the embodiment will be mainly described, and descriptions of commonalities will be omitted or simplified.

[0120] <Modification 1> Fig. 3 is a cross-sectional view of a nitride semiconductor device 2 according to Modification 1. The nitride semiconductor device 2 shown in Fig. 3 differs from the nitride semiconductor device 1 in that it further includes a high-resistance layer 13.

[0121] The high-resistance layer 13 is an example of a nitride semiconductor layer provided between the drift layer 12 and the block layer 14. The high-resistance layer 13 is, for example, a 100 nm thick film made of carbon-doped GaN (C—GaN). The carbon concentration of the high-resistance layer 13 is, for example, 3×10 １７ cm －３ That's all, but 1 x 10 １８ cm －３ The high-resistance layer 13 is provided in contact with each of the drift layer 12 and the block layer 14. The high-resistance layer 13 may contain n-type impurities such as Si. The concentration of the n-type impurities contained in the high-resistance layer 13 is lower than the carbon concentration and oxygen concentration of the high-resistance layer 13, and may be, for example, 5×10 １６ cm －３ or less than or equal to 2×10 １６ cm －３ It may be the following:

[0122] In this modification, the vertical conducting opening 20 penetrates not only the block layer 14 but also the high-resistance layer 13 to reach the drift layer 12. Since the high-resistance layer 13 is not located on the path of the drain current when the FET is on, an increase in on-resistance can be suppressed.

[0123] In this modification, the provision of the high-resistance layer 13 can suppress punch-through and increase the breakdown voltage of the nitride semiconductor device 2 .

[0124] 4 is a cross-sectional view of a nitride semiconductor device 3 according to Modification 2. In the nitride semiconductor device 3 shown in Fig. 4, the vertical conducting opening 20 is formed deeper than in the nitride semiconductor device 1. That is, the bottom surface 20a of the vertical conducting opening 20 is located closer to the substrate 10.

[0125] Specifically, a distance D1 between the threshold adjustment layer 28 and the substrate 10 is shorter than a distance D2 between the block layer 14 and the substrate 10. The distance D1 is the shortest distance between the threshold adjustment layer 28 and the substrate 10, and specifically, the distance between the upper surface of the substrate 10 and a portion of the lower surface of the threshold adjustment layer 28 that overlaps with the bottom surface 20a of the vertical conductive opening 20 in a plan view of the substrate 10. The distance D2 is the distance between the lower surface of the block layer 14 and the upper surface of the substrate 10.

[0126] Since the distance D1 is shorter than the distance D2, the electric field between the drain and the source can be dispersed also to the lower surface of the threshold adjustment layer 28. This makes it possible to suppress the electric field concentration at the lower end of the block layer 14, thereby increasing the breakdown voltage of the FET.

[0127] The nitride semiconductor device 3 according to this modification may be provided with the high resistance layer 13 shown in FIG.

[0128] 5 is a cross-sectional view of a nitride semiconductor device 4 according to Modification 3. The nitride semiconductor device 4 shown in Fig. 5 differs from the nitride semiconductor device 1 in that it includes a threshold adjustment layer 128 and a gate electrode 132 instead of the threshold adjustment layer 28 and the gate electrode 32. In this modification, a recess 120 is provided in the electron supply layer 23.

[0129] The threshold adjustment layer 128 and the gate electrode 132 correspond to the threshold adjustment layer 28 and the gate electrode 32, respectively, but are provided at different positions. Specifically, the threshold adjustment layer 128 and the gate electrode 132 are provided at positions that do not overlap the vertical conductive opening 20 but overlap the block layer 14 in a planar view of the substrate 10. More specifically, the threshold adjustment layer 128 and the gate electrode 132 are provided at positions that overlap the upper surface of the block layer 14 in a planar view of the substrate 10. That is, the threshold adjustment layer 128 and the gate electrode 132 are provided outside the vertical conductive opening 20. Note that the threshold adjustment layer 128 and the gate electrode 132 may be provided at positions that overlap the inclined end face of the block layer 14 on the vertical conductive opening 20 side in a planar view of the substrate 10.

[0130] The recess 120 is provided at a position overlapping the gate electrode 132 in a plan view of the substrate 10. The recess 120 is formed, for example, by removing a part of the electron supply layer 23 by dry etching or the like. A threshold adjustment layer 128 is provided so as to contact and cover the bottom and side surfaces of the recess 120. Note that the side surfaces of the recess 120 are perpendicular to the bottom surface of the recess 120, but may be inclined at an angle.

[0131] In a plan view, the recessed portion 120 is provided in an area narrower than the threshold adjustment layer 128. Specifically, the entire recessed portion 120 is covered with the threshold adjustment layer 128. The threshold adjustment layer 128 is also in contact with a region of the electron supply layer 23 outside the recessed portion 120.

[0132] As shown in Fig. 2C, the recess 120 is formed by dry etching or the like after the electron transit layer 22 and the electron supply layer 23 are formed by crystal growth and before the p-type semiconductor layer 28A shown in Fig. 2E is formed. The recess 120 may be formed after or before the opening 25 is formed.

[0133] According to this modification, the carrier concentration directly below the gate electrode 132 can be reduced, and the threshold voltage of the FET can be further shifted to the positive side. Therefore, the nitride semiconductor device 4 can be most easily realized as a normally-off FET.

[0134] As shown in FIG. 5, the nitride semiconductor device 4 according to this modification further includes a p-type semiconductor layer 129 and an ohmic electrode 136 .

[0135] The p-type semiconductor layer 129 is an example of a p-type sixth nitride semiconductor layer provided between the ohmic electrode 136 and the nitride semiconductor layer 21. Specifically, the p-type semiconductor layer 129 is provided between the upper surface of the electron supply layer 23 and the lower surface of the ohmic electrode 136 in contact with each other.

[0136] The p-type semiconductor layer 129 is provided at a position overlapping the vertical conductive opening 20 in a plan view of the substrate 10. Specifically, the p-type semiconductor layer 129 overlaps each of the bottom surface 20a and the side surface 20b of the vertical conductive opening 20 in a plan view of the substrate 10. Note that the p-type semiconductor layer 129 may overlap only the bottom surface 20a of the vertical conductive opening 20 and not overlap the side surface 20b in a plan view of the substrate 10. Alternatively, the p-type semiconductor layer 129 may overlap not only the vertical conductive opening 20 but also the upper surface of the block layer 14 in a plan view of the substrate 10.

[0137] The p-type semiconductor layer 129 is electrically isolated from the threshold adjustment layer 128. A source potential is supplied to the p-type semiconductor layer 129 via an ohmic electrode 136. The p-type semiconductor layer 129 has a thickness of 200 nm and a carrier concentration of 1×10 １９ cm －３ The p-type semiconductor layer 129 is a film made of p-type GaN, where p-type semiconductor layer 129 is a p-type GaN film. The thickness and carrier concentration of the p-type semiconductor layer 129 are merely examples and can be changed as appropriate. The p-type semiconductor layer 129 is formed, for example, in the same process as the p-type semiconductor layer 29 and the threshold adjustment layer 128.

[0138] The ohmic electrode 136 is an example of a second electrode provided at a position overlapping the bottom surface 20a of the vertical conductive opening 20 in a plan view of the substrate 10. The ohmic electrode 136 is provided on the upper surface of the p-type semiconductor layer 129.

[0139] The ohmic electrode 136 is formed using a conductive material such as a metal. For example, the ohmic electrode 136 can be formed using a material that forms an ohmic connection with a p-type nitride semiconductor such as p-type GaN. For example, Pd, a Ni-based material, WSi, Au, etc. can be used as the material for forming the ohmic electrode 136. The ohmic electrode 136 is formed using the same material and in the same process as the gate electrode 132 and the ohmic electrode 36, for example.

[0140] The ohmic electrode 136 is set to the same potential as the source electrode 34. Specifically, the source wiring 50 is connected to the ohmic electrode 136 through an opening provided in the insulating layer 40, as shown in FIG.

[0141] In this way, by providing the p-type semiconductor layer 129, the electric field lines extending from the drain electrode 38 can be terminated at the p-type semiconductor layer 129 and the block layer 14, thereby reducing the parasitic capacitance Cgd between the gate and the drain, thereby enabling faster switching of the FET.

[0142] The nitride semiconductor device 4 according to this modification may be provided with the high-resistance layer 13 shown in Fig. 3. Furthermore, the nitride semiconductor device 4 according to this modification may have the vertical conduction opening 20 formed deeper, as in the nitride semiconductor device 3 shown in Fig. 4. That is, in the nitride semiconductor device 4, the distance between the p-type semiconductor layer 129 and the substrate 10 may be shorter than the distance between the block layer 14 and the substrate 10.

[0143] 5 , the recess 120, the threshold adjustment layer 128, the gate electrode 132, the opening 25, the source opening 30, the p-type semiconductor layer 29, the source electrode 34, and the ohmic electrode 36 are provided on both sides in the lateral direction of the vertical conductive opening 20, the p-type semiconductor layer 129, and the ohmic electrode 136. However, this is not limitative. The recess 120, the threshold adjustment layer 128, the gate electrode 132, the opening 25, the source opening 30, the p-type semiconductor layer 29, the source electrode 34, and the ohmic electrode 36 may be provided on only one side of the vertical conductive opening 20, the p-type semiconductor layer 129, and the ohmic electrode 136.

[0144] 6 is a cross-sectional view of a nitride semiconductor device 5 according to Modification 4. The nitride semiconductor device 5 shown in Fig. 6 differs from the nitride semiconductor device 1 in that it does not include a threshold adjustment layer 28. Since the threshold adjustment layer 28 is not provided, the gate electrode 32 is in contact with the upper surface of the electron supply layer 23.

[0145] In this modification, the threshold adjustment layer 28 is not provided, and therefore the FET included in the nitride semiconductor device 5 can be a normally-on type FET.

[0146] An insulating layer may be provided between the gate electrode 32 and the electron supply layer 23. The insulating layer may be made of, for example, SiO ２, SiN, SiON or Al ２ O ３ The nitride semiconductor device 5 has a single layer or multilayer structure of insulating films such as those mentioned above. That is, the FET included in the nitride semiconductor device 5 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0147] 3 may be provided in the nitride semiconductor device 5 according to this modification. Furthermore, the vertical conductive opening 20 may be formed deeper in the nitride semiconductor device 5 according to this modification, as in the nitride semiconductor device 3 shown in FIG. 4. That is, in the nitride semiconductor device 5, the distance between the gate electrode 32 and the substrate 10 may be shorter than the distance between the block layer 14 and the substrate 10. Furthermore, in the nitride semiconductor device 5, the gate electrode 32 may be provided at a position overlapping the block layer 14 but not overlapping the vertical conductive opening 20 in a plan view of the substrate 10, as in the nitride semiconductor device 4 shown in FIG. 5.

[0148] <Others> In the nitride semiconductor devices 1, 2, 3, 4, and 5 according to the embodiment and each modification, a high-resistance layer having a higher resistance than the block layer 14 may be provided between the block layer 14 and the electron transit layer 22. For example, the high-resistance layer is an undoped GaN film with a thickness of 200 nm, but it may also be a carbon-doped GaN film. The high-resistance layer is formed by crystal growth continuously from the formation of the block layer 14. When the high-resistance layer is formed, both the vertical conduction opening 20 and the opening 25 penetrate the high-resistance layer. The provision of the high-resistance layer prevents the formation of an npn parasitic transistor formed by the 2DEG 24, the p-type block layer 14, and the n-type drift layer 12, thereby suppressing malfunction of the nitride semiconductor devices 1, 2, 3, 4, and 5.

[0149] The source opening 30 may penetrate the electron transit layer 22 or reach the blocking layer 14. The source opening 30 may be formed integrally with the opening 25. That is, the bottom surface 30a of the source opening 30 may be continuous with the bottom surface 25a of the opening 25. When the source opening 30 is shallower than the opening 25, the edge of the bottom surface 30a of the source opening 30 may coincide with the upper end of the side surface 25b of the opening 25. The source opening 30 may not be provided. In this case, the source electrode 34 is provided on the upper surface of the electron supply layer 23.

[0150] The ohmic electrode 36 and the source electrode 34 do not need to be in direct contact with each other, and may be electrically connected via a via, a wiring, etc. Alternatively, the ohmic electrode 36 and the source electrode 34 may be integrally formed using the same material.

[0151] [Planar Layout] Next, an example of the planar layout of the nitride semiconductor devices 1, 2, 3, 4, and 5 according to the above-described embodiment and each modification will be described. Since the planar layouts of the nitride semiconductor devices 1, 2, 3, 4, and 5 are the same, the planar layout of the nitride semiconductor device 1 will be described as a representative example.

[0152] Fig. 7 is a plan view of the nitride semiconductor device 1 according to the embodiment. Fig. 8 is a cross-sectional view of the nitride semiconductor device 1 taken along line VIII-VIII in Fig. 7. Fig. 9 is a cross-sectional view of the nitride semiconductor device 1 taken along line IX-IX in Fig. 7.

[0153] The nitride semiconductor device 1 can be divided into an active region 1A and a peripheral region 1B located outside the active region 1A in a plan view of the substrate 10. For example, the peripheral region 1B is provided so as to surround the active region 1A.

[0154] The active region 1A is an example of a first region, and is a region provided with the nitride semiconductor layer 21 including the 2DEG 24, the gate electrode 32, and the source electrode 34. When the nitride semiconductor device 1 is on, a drain current flows mainly through the active region 1A. The active region 1A is also called a device region.

[0155] The active region 1A includes a plurality of unit cells 200 of the nitride semiconductor device 1. Each unit cell 200 is a structural unit operable as a FET, and specifically corresponds to the cross-sectional structure shown in FIG. 1 . As shown in FIG. 8 , each unit cell 200 includes a nitride semiconductor layer 21 including an electron transit layer 22 and an electron supply layer 23, a gate electrode 32, a threshold adjustment layer 28, and source electrodes 34 disposed on both sides of the nitride semiconductor layer 21. The drain electrode 38, the substrate 10, the drift layer 12, and the block layer 14 are continuously provided across the plurality of unit cells 200. The gate electrodes 32 included in each unit cell 200 may be connected to each other and integrated in at least one of the direction into and out of the plane of FIG. 8 . The same applies to the threshold adjustment layer 28, the electron supply layer 23, the electron transit layer 22, and the insulating layer 40.

[0156] In the active region 1A, the p-type semiconductor layer 29 and the ohmic electrode 36 are provided so as to be shared by adjacent unit cells 200. That is, in the active region 1A, the p-type semiconductor layer 29 and the ohmic electrode 36 are provided for each unit cell 200. In other words, a pn diode formed between the ohmic electrode 36 and the drain electrode 38 is provided in the active region 1A.

[0157] In this way, by providing the ohmic electrode 36 in the active region 1A, the charges accumulated in the block layer 14 can be extracted within the active region 1A. Since the extraction path of the charges is shortened, the charges can be extracted efficiently, and the switching speed of the FET can be increased.

[0158] The peripheral region 1B is an example of a second region provided outside the active region 1A. As shown in FIG. 7 , a gate pad 50G and a source pad 50S are provided in the peripheral region 1B. For this reason, the peripheral region 1B is also referred to as a pad region. Alternatively, the peripheral region 1B may be referred to as a non-active region, a non-device region, or an element isolation region. In FIG. 7 , the peripheral region 1B is provided in a rectangular ring shape surrounding the entire periphery of the active region 1A, but this is not limited thereto. The peripheral region 1B may be a rectangular region provided along one side of the rectangular active region 1A, or an L-shaped region provided along two adjacent sides of the active region 1A. Alternatively, the peripheral region 1B may be provided along three sides of the active region 1A, or may be provided separately in two locations along two opposing sides of the active region 1A.

[0159] The gate pad 50G and the source pad 50S are pads that receive a gate potential and a source potential, respectively, from outside the nitride semiconductor device 1. The gate pad 50G and the source pad 50S are electrically connected to an external substrate, die frame, or the like by wire bonding or the like. The gate pad 50G is electrically connected to the gate electrode 32 of each unit cell 200 provided in the active region 1A via a gate wiring (not shown), and can supply an externally supplied gate potential to the gate electrode 32. The source pad 50S is electrically connected to the source electrode 34 and the ohmic electrode 36 of each unit cell 200 provided in the active region 1A via a source wiring 50, and can supply an externally supplied gate potential to the source electrode 34 and the ohmic electrode 36.

[0160] 9, in the peripheral region 1B, the p-type semiconductor layer 29 is provided continuously from the active region 1A. Also, in the peripheral region 1B, an ohmic electrode 236 that electrically connects the source pad 50S and the p-type semiconductor layer 29 is provided.

[0161] The ohmic electrode 236 is an example of a first electrode electrically connected to the p-type semiconductor layer 29. The ohmic electrode 236 is also electrically connected to the source electrode 34 via the source pad 50S and the source wiring 50. In this embodiment, the ohmic electrode 236 contacts and covers the upper surface of the p-type semiconductor layer 29 in the peripheral region 1B.

[0162] The ohmic electrode 236 can be made of a material that forms an ohmic connection with the p-type GaN layer. For example, Pd, Ni-based materials, WSi, Au, etc. can be used as the material for forming the ohmic electrode 236. The ohmic electrode 236 can be formed in the same process as the ohmic electrode 36 in the active region 1A.

[0163] In this way, the peripheral region 1B can be used to form a large-area ohmic electrode 236. The contact resistance between the ohmic electrode 236 and the p-type semiconductor layer 29 can be further reduced, so that charges can be extracted efficiently. As a result, an increase in on-resistance can be suppressed.

[0164] Furthermore, since a large-area pn diode can be formed in the peripheral region 1B, the operating voltage of the freewheeling operation can be lowered, thereby reducing loss. Furthermore, since the region below the source pad 50S can be effectively used as a pn diode, the nitride semiconductor device 1 can be made smaller.

[0165] 9, an insulating layer 42 is provided to separate the ohmic electrode 36 from the ohmic electrode 236, but the insulating layer 42 may not be provided. Also, an insulating layer 44 is provided between the source pad 50S and the p-type semiconductor layer 29, but the insulating layer 44 may not be provided either. The insulating layer 42 and the insulating layer 44 may be made of, for example, SiN, SiO, etc., similar to the insulating layer 40. ２ , SiON, Al ２ O ３ The insulating film may have a single layer or a multilayer structure such as, but is not limited to, the insulating film.

[0166] Although the example shown here shows the ohmic electrode 236 and the p-type semiconductor layer 29 provided at a position overlapping the source pad 50S in a plan view of the substrate 10, the present invention is not limited to this. The ohmic electrode 236 and the p-type semiconductor layer 29 may be provided at a position overlapping the gate pad 50G in a plan view of the substrate 10. In this case, an insulating layer is provided between the ohmic electrode 236 and the gate pad 50G to prevent electrical conduction between them. The ohmic electrode 236 and the p-type semiconductor layer 29 may also be provided in a portion where neither the gate pad 50G nor the source pad 50S is provided.

[0167] Furthermore, when the ohmic electrode 36 and the p-type semiconductor layer 29 are provided in the active region 1A, the ohmic electrode 236 and the p-type semiconductor layer 29 may not be provided in the peripheral region 1B. Furthermore, when the ohmic electrode 236 and the p-type semiconductor layer 29 are provided in the peripheral region 1B, the ohmic electrode 36 and the p-type semiconductor layer 29 may not be provided in the active region 1A.

[0168] While nitride semiconductor devices according to one or more aspects have been described above based on embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0169] For example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) gradually decreases from the substrate 10 side to the block layer 14 side. The donor concentration may be controlled by Si, which acts as a donor, or by carbon, which acts as an acceptor that compensates for Si. Alternatively, the drift layer 12 may have a stacked structure of multiple nitride semiconductor layers with different impurity concentrations. Specifically, the drift layer may be two-layered, with a layer with a low donor concentration disposed below the block layer and a layer with a high donor concentration disposed on the substrate side. By providing a vertical conductive opening 20 that penetrates the layer with a low donor concentration, current flows through the layer with a high donor concentration through the vertical conductive opening 20 when the transistor is on, thereby reducing the on-resistance. Conversely, when the transistor is off, a high electric field is maintained by the layer with a low donor concentration, thereby achieving both low on-resistance and high breakdown voltage.

[0170] Furthermore, for example, the example in which the unit cells 200 are elongated in one direction in plan view and arranged side by side in the short direction has been shown, but this is not limiting. The unit cells 200 may be arranged so that their planar shapes are regular hexagons that fill a plane. Furthermore, for example, the number of unit cells 200 included in the nitride semiconductor device according to the present disclosure may be only one.

[0171] Furthermore, for example, the nitride semiconductor device according to the present disclosure may include a pn diode instead of or in addition to the FET. The pn diode has a pn junction between a p-type fourth nitride semiconductor layer and a p-type second nitride semiconductor layer and an n-type first nitride semiconductor layer. In this case, the nitride semiconductor device includes a first electrode that is an anode electrode and a cathode electrode ohmically connected to the first nitride semiconductor layer. Alternatively, the pn diode may have a pn junction between the p-type fourth nitride semiconductor layer and a p-type second nitride semiconductor layer and a 2DEG generated in the third nitride semiconductor layer. The pn diode may be a lateral diode or a vertical diode.

[0172] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0173] The nitride semiconductor device according to the present disclosure is useful as a power device used in, for example, power supply circuits of electrical equipment, inverter circuits, etc.

[0174] 1, 2, 3, 4, 5 Nitride semiconductor device 1A Active region 1B Peripheral region 10 Substrate 12 Drift layer 13 High resistance layer 14 Block layer 20 Vertical conduction opening 20a, 25a, 30a Bottom surface 20b, 25b, 30b Side surface 21 Nitride semiconductor layer 22 Electron transit layer 23 Electron supply layer 24 2DEG 25 Opening 28, 128 Threshold adjustment layer 28A, 29, 129 P-type semiconductor layer 30 Source opening 32, 132 Gate electrode 34 Source electrode 36, 136, 236 Ohmic electrode 38 Drain electrode 40, 42, 44 Insulating layer 50 Source wiring 50G Gate pad 50S Source pad 120 Recessed portion 200 Unit cell

Claims

1. A nitride semiconductor device comprising: a substrate; a first n-type nitride semiconductor layer provided above the substrate; a second p-type nitride semiconductor layer provided above the first nitride semiconductor layer; a third nitride semiconductor layer provided above the second nitride semiconductor layer; a fourth p-type nitride semiconductor layer provided in a first opening that passes through the third nitride semiconductor layer and reaches the second nitride semiconductor layer, so as to be in contact with the second nitride semiconductor layer; and a first electrode electrically connected to the fourth nitride semiconductor layer.

2. The nitride semiconductor device according to claim 1, further comprising: a gate electrode provided above the third nitride semiconductor layer; a source electrode provided above the substrate and electrically connected to the third nitride semiconductor layer; and a drain electrode provided below the substrate, wherein the first electrode is electrically connected to the source electrode.

3. The nitride semiconductor device according to claim 2, wherein the third nitride semiconductor layer is provided so as to cover an inner surface of a second opening that penetrates the second nitride semiconductor layer at a position away from the first opening and reaches the first nitride semiconductor layer, and an upper portion of the second nitride semiconductor layer.

4. The nitride semiconductor device according to claim 3, further comprising a p-type fifth nitride semiconductor layer provided between said gate electrode and said third nitride semiconductor layer and electrically isolated from said fourth nitride semiconductor layer.

5. The nitride semiconductor device according to claim 4, wherein the gate electrode and the fifth nitride semiconductor layer are provided at positions overlapping the second opening in a plan view of the substrate.

6. The nitride semiconductor device according to claim 4, wherein the gate electrode and the fifth nitride semiconductor layer are provided at positions that overlap the second nitride semiconductor layer but do not overlap the second opening in a plan view of the substrate.

7. The nitride semiconductor device according to claim 6, further comprising: a second electrode set to the same potential as said source electrode, provided at a position overlapping a bottom surface of said second opening in a plan view of said substrate; and a p-type sixth nitride semiconductor layer provided between said second electrode and said third nitride semiconductor layer and electrically isolated from said fifth nitride semiconductor layer.

8. The nitride semiconductor device according to any one of claims 2 to 7, wherein the third nitride semiconductor layer includes: an electron transit layer; and an electron supply layer provided above the electron transit layer and having a band gap larger than that of the electron transit layer.

9. The nitride semiconductor device according to claim 8, wherein the source electrode is in contact with the electron transit layer within a third opening that penetrates the electron supply layer and reaches the electron transit layer.

10. The nitride semiconductor device according to claim 9, wherein the third opening does not penetrate the electron transit layer and does not reach the second nitride semiconductor layer.

11. The nitride semiconductor device according to any one of claims 3 to 7, further comprising a high-resistance layer provided between the first nitride semiconductor layer and the second nitride semiconductor layer, the high-resistance layer having a higher resistance than both the first nitride semiconductor layer and the second nitride semiconductor layer, and the second opening penetrates the high-resistance layer to reach the first nitride semiconductor layer.

12. The nitride semiconductor device according to any one of claims 2 to 7, wherein the first electrode contains, as a main component, the same material as the main component of the gate electrode.

13. The nitride semiconductor device according to claim 4 or 5, wherein the distance between the fifth nitride semiconductor layer and the substrate is shorter than the distance between the second nitride semiconductor layer and the substrate.

14. The nitride semiconductor device according to any one of claims 2 to 7, comprising a plurality of each of the source electrodes and the first electrodes, and wherein, when the substrate is divided into a first region and a second region located outside the first region in a plan view of the substrate, the plurality of source electrodes and the plurality of first electrodes are provided in the first region.

15. The nitride semiconductor device according to any one of claims 2 to 7, comprising a plurality of source electrodes, wherein when the substrate is divided into a first region and a second region located outside the first region in a plan view of the substrate, the plurality of source electrodes are provided in the first region, and the first electrode is provided in the second region.

16. The nitride semiconductor device according to claim 15, further comprising a source pad provided in the second region for receiving a potential supplied to the plurality of source electrodes.

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