Semiconductor element

Abstract

The present invention reduces recovery loss. This semiconductor element comprises a semiconductor substrate, a tungsten upper electrode layer, and a lower electrode layer. A plurality of trenches extending along a first direction are provided on an upper surface, and the plurality of trenches are arranged at intervals in a second direction. A plurality of inter-trench semiconductor regions, which are each a semiconductor region sandwiched between the plurality of trenches, are arranged in each of an IGBT region and a diode region. In a predetermined cross section perpendicular to the first direction, the plurality of inter-trench semiconductor regions are exposed along the second direction. At least some of the plurality of inter-trench semiconductor regions exposed in the predetermined cross section each include a pillar region. The pillar region is a region that extends from a barrier region to the upper electrode layer and that is in Schottky contact with the tungsten upper electrode layer. In the diode region, the pillar regions are repeatedly arranged in the second direction in accordance with predetermined regularity.

Description

semiconductor elements

[0001] (Cross-reference to related applications) This application is a related application of Japanese Patent Application No. 2024-146791 filed on August 28, 2024, and claims priority based on this Japanese patent application, the entire contents of which are incorporated herein by reference.

[0002] The technology disclosed in this specification relates to a semiconductor device.

[0003] Conventionally, semiconductor elements having an RC-IGBT (abbreviation for Reverse-Conducting IGBT) structure in which a diode region is provided together with an IGBT region on a single chip have been proposed as switching elements for inverters and the like. Japanese Patent Application Laid-Open Publication No. 2013-48230 also discloses a technology in which a pillar region is provided in the diode region to obtain a hole injection suppression effect. The pillar region is an n-type region that extends from an n-type barrier region that contacts the body region from below to the upper electrode layer. The pillar region is in Schottky contact with the upper electrode layer. The provision of the pillar region suppresses hole injection from the body region to the drift region when the diode is turned on. Therefore, the recovery current is suppressed when the diode performs recovery operation.

[0004] Conventionally, AlSi alloys have been used as the top electrode layer. However, when using AlSi alloys, the Si in the alloy diffuses and grows into grains, which can precipitate as Si nodules at the Schottky contact interface with the pillar region. This can result in unstable Schottky barrier heights. This is problematic because it can lead to increased variations in threshold voltage and increased leakage current.

[0005] The semiconductor device (10) disclosed in this specification includes a semiconductor substrate (12), an upper electrode layer (69) in contact with the upper surface of the semiconductor substrate, and a lower electrode layer (72) in contact with the lower surface of the semiconductor substrate. The upper electrode layer is made of tungsten. The semiconductor substrate includes a p-type collector region (20) in contact with the lower electrode layer and an n-type cathode region (22) in contact with the lower electrode layer. When the semiconductor substrate is viewed along the thickness direction, the area overlapping with the collector region is an IGBT region (15), and the area overlapping with the cathode region is a diode region (16). When the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as a first direction (x) and the direction from the IGBT region toward the diode region on the upper surface is defined as a second direction (y), a plurality of trenches (60) extending along the first direction are provided on the upper surface, and the plurality of trenches are arranged at intervals in the second direction. The inner surface of each trench is covered with a trench insulating film (62). A trench electrode (64) is disposed within each trench. A plurality of inter-trench semiconductor regions (TA), which are semiconductor regions sandwiched between a plurality of trenches, are disposed in each of the IGBT region and the diode region. Each inter-trench semiconductor region in the IGBT region and the diode region has a p-type body region (34) in contact with the upper electrode layer and the trench insulating film, and an n-type barrier region (30) in contact with the body region from below. At least a portion of the inter-trench semiconductor region in the IGBT region has an n-type emitter region (32) in contact with the upper electrode layer and the trench insulating film above the body region. A semiconductor substrate is distributed across the IGBT region and the diode region and has an n-type drift region (24a) disposed below the body region. In a predetermined cross section (CS) perpendicular to the first direction, the plurality of inter-trench semiconductor regions are exposed along the second direction. At least some of the inter-trench semiconductor regions exposed in the predetermined cross section include pillar regions (26). The pillar regions extend from the barrier region to the upper electrode layer and are in Schottky contact with the tungsten upper electrode layer. Within the diode region, the pillar regions are repeatedly arranged in the second direction according to a predetermined regularity.

[0006] According to the above structure, tungsten (W) is used as the upper electrode layer. This prevents the precipitation of Si nodules at the contact interface with the pillar region, thereby stabilizing the Schottky barrier height. It is possible to suppress increases in threshold voltage variation and leakage current. However, when a diode region having a tungsten upper electrode layer and a diode region having an AlSi alloy upper electrode layer are operated under the same conditions, the diode region having a tungsten upper electrode layer exhibits a greater hole injection suppression effect due to the pillar region. This is because the Schottky barrier height of tungsten (0.68 eV) is lower than the Schottky barrier height of AlSi alloy (0.72 to 0.82 eV). If the hole injection suppression effect becomes unnecessarily high, snapback and an increase in forward voltage may occur. Therefore, the technology described herein includes a structure in which pillar regions are repeatedly arranged in a second direction according to a predetermined regularity within the diode region. That is, the structure includes a structure in which the pillar regions are thinned out according to a predetermined regularity. This makes it possible to appropriately suppress the hole injection suppression effect in the diode region using tungsten for the upper electrode layer, thereby preventing the occurrence of snapback and an increase in forward voltage.

[0007] The predetermined regularity is a concept that does not include a case where the pillar regions are randomly arranged in the second direction, a case where all inter-trench semiconductor regions in the diode region include pillar regions, or a case where all inter-trench semiconductor regions in the diode region do not include pillar regions.

[0008] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

[0009] 2. It is a top view of the semiconductor substrate 12. It is an enlarged perspective view of the semiconductor substrate 12 in the region RII of FIG. 1. It is a cross-sectional view at the predetermined cross section CS1 of FIG. 2. It is a top view of the semiconductor substrate 12. It is a graph of the simulation result. It is an enlarged perspective view of the semiconductor substrate 12 according to Example 2.

[0010] (Configuration of semiconductor element 10) Hereinafter, embodiments according to the technology of the present specification will be described with reference to the drawings. In the following embodiments, parts that are identical or equivalent to each other will be described by using the same reference numerals.

[0011] As shown in FIG. 1 , the semiconductor device 10 of the first embodiment has a semiconductor substrate 12 made of silicon. When viewed from above as shown in FIG. 1 , the semiconductor substrate 12 is partitioned into an element portion 14 and an outer peripheral portion 17. The element portion 14 is also partitioned into a plurality of IGBT regions 15 and a plurality of diode regions 16. Note that in FIG. 1 , the plurality of diode regions 16 are indicated by gray fill. An IGBT is provided in the IGBT region 15, and a diode is provided in the diode region 16. Each of the IGBT region 15 and the diode region 16 has a rectangular shape that is long in the x direction. The IGBT regions 15 and the diode regions 16 are alternately arranged in the y direction.

[0012] Although not shown, a voltage-resistant structure such as a guard ring is provided on the outer peripheral portion 17. Furthermore, signal electrode pads 18 are provided on the outer peripheral portion 17. One of the signal electrode pads 18 is a gate pad that controls the gate voltage of the IGBT.

[0013] Figure 2 shows an enlarged perspective view of the semiconductor substrate 12 in region RII in Figure 1. Note that the interlayer insulating film 68, upper electrode layer 69, and emitter electrode 70 are omitted from Figure 2. Also, in Figure 2, multiple pillar regions 26 are indicated by being filled in gray. Also, Figure 3 shows a cross-sectional view at a predetermined cross section CS1 in Figure 2. Note that the predetermined cross section will be described later.

[0014] A p-type collector region 20 and an n-type cathode region 22 are arranged in a range including the lower surface 12b of the semiconductor substrate 12. The collector region 20 is provided in the IGBT region 15, and the cathode region 22 is provided in the diode region 16. In other words, when the semiconductor substrate 12 is viewed along the thickness direction, the region overlapping with the collector region 20 is the IGBT region 15, and the region overlapping with the cathode region 22 is the diode region 16.

[0015] A plurality of trenches 60 are provided in the upper surface 12a of the semiconductor substrate 12. The plurality of trenches 60 are arranged in each of the IGBT region 15 and the diode region 16. The plurality of trenches 60 extend longitudinally along the x direction. The plurality of trenches 60 are also arranged at intervals in the y direction. The inner surface of each trench 60 is covered with a trench insulating film 62. A trench electrode 64 is arranged inside each trench 60. The trench electrode 64 is insulated from the semiconductor substrate 12 by the trench insulating film 62.

[0016] In this specification, among the semiconductor regions in the semiconductor substrate 12, a region sandwiched between two trenches 60 is referred to as an inter-trench semiconductor region TA. A plurality of inter-trench semiconductor regions TA are provided in each of the IGBT region 15 and the diode region 16.

[0017] 3 , an interlayer insulating film 68, an upper electrode layer 69, and an emitter electrode 70 are provided on the upper portion of the semiconductor substrate 12. The interlayer insulating film 68 covers the upper surfaces of the trench electrodes 64. In the region between the interlayer insulating films 68, an upper electrode layer 69 contacts the upper surface of the inter-trench semiconductor region TA. The upper electrode layer 69 is made of tungsten (W). The emitter electrode 70 is made of a metal (e.g., an AlSi alloy). The emitter electrode 70 is provided across the IGBT region 15 and the diode region 16, and covers the upper surfaces of the upper electrode layer 69 and the interlayer insulating film 68. As a result, a tungsten plug structure is formed by the upper electrode layer 69.

[0018] The trench electrode 64 in the IGBT region 15 is insulated from the emitter electrode 70 by an interlayer insulating film 68. The trench electrode 64 in the IGBT region 15 is connected to a gate pad by wiring (not shown). The trench electrode 64 in the IGBT region 15 is a gate electrode 64a whose potential can be changed by the gate pad. The trench electrode 64 in the diode region 16 is connected to the emitter electrode 70 by wiring (not shown). The trench electrode 64 in the diode region 16 is a dummy electrode 64b whose potential is fixed to the same potential as the emitter electrode 70.

[0019] A collector electrode 72 is provided on the lower part of the semiconductor substrate 12. The collector electrode 72 is provided across the IGBT region 15 and the diode region 16, and covers the lower surface 12b. The collector region 20 and the cathode region 22 are in ohmic contact with the collector electrode 72.

[0020] Each inter-trench semiconductor region TA in the IGBT region 15 and the diode region 16 has a p-type upper body region 34. The upper body region 34 is in contact with the emitter electrode 70 and is in contact with the trench insulating film 62 on the side surface of the trench 60. The upper body region 34 has a contact region 34a and a low-concentration region 34b. The contact region 34a is located at a position including the upper surface 12a and is in ohmic contact with the emitter electrode 70. The low-concentration region 34b has a lower p-type impurity concentration than the contact region 34a and is in contact with the contact region 34a from below. The low-concentration region 34b is in contact with the trench insulating film 62 on the side surface of the trench 60.

[0021] Each inter-trench semiconductor region TA in the IGBT region 15 has an n-type emitter region 32. Each emitter region 32 is disposed at a position including the upper surface 12a and is in ohmic contact with the emitter electrode 70. Each emitter region 32 is in contact with the trench insulating film 62 on the side surface of the trench 60. The low-concentration region 34b is in contact with each emitter region 32 from below. Each emitter region 32 is in contact with the trench insulating film 62 above the low-concentration region 34b. Although no emitter region 32 is provided in the diode region 16 in this embodiment, there is no problem if an emitter region 32 is provided in the diode region 16.

[0022] Each inter-trench semiconductor region TA in the IGBT region 15 and the diode region 16 has an n-type barrier region 30. The n-type impurity concentration of the barrier region 30 is lower than the n-type impurity concentration of the emitter region 32. The barrier region 30 is disposed below the low-concentration region 34b. The barrier region 30 contacts the trench insulating film 62 on the side surface of the trench 60.

[0023] Each inter-trench semiconductor region TA in the IGBT region 15 and the diode region 16 has a p-type lower body region 28. The p-type impurity concentration of the lower body region 28 is lower than the p-type impurity concentration of the contact region 34a. The lower body region 28 is disposed below the barrier region 30. The lower body region 28 contacts the trench insulating film 62 on the side surface of the trench 60. The lower body region 28 is separated from the upper body region 34 by the barrier region 30. In other words, the barrier region 30 separates the p-type body region into the upper body region 34 and the lower body region 28.

[0024] As shown in FIG. 3 , a plurality of inter-trench semiconductor regions TA are arranged along the y direction. Within the diode region 16, at least some of the plurality of inter-trench semiconductor regions TA include pillar regions 26. The pillar regions 26 are n-type regions that extend from the barrier region 30 to the upper electrode layer 69. The pillar regions 26 are in Schottky contact with the tungsten upper electrode layer 69. The n-type impurity concentration of the pillar regions 26 is lower than the n-type impurity concentration of the emitter region 32. The barrier region 30 and the pillar regions 26 together form a hole injection suppression structure 31. The operation of the hole injection suppression structure 31 will be described later.

[0025] The semiconductor substrate 12 has an n-type intermediate region 24. The intermediate region 24 is distributed across the IGBT region 15 and the diode region 16. The intermediate region 24 has a drift region 24a and a buffer region 24b. The drift region 24a is an n-type region having a lower n-type impurity concentration than the barrier region 30 and the pillar region 26. The drift region 24a is distributed across the IGBT region 15 and the diode region 16. The drift region 24a is disposed below the upper body region 34, the barrier region 30, and the lower body region 28. The drift region 24a contacts the lower body region 28 from below. The drift region 24a also contacts the trench insulating film 62 at the lower end of each trench 60.

[0026] The buffer region 24b is an n-type region having an n-type impurity concentration higher than that of the drift region 24a and lower than that of the cathode region 22. The buffer region 24b is distributed across the IGBT region 15 and the diode region 16. The buffer region 24b contacts the drift region 24a from below. The buffer region 24b contacts the collector region 20 and the cathode region 22 from above.

[0027] (Operation of Semiconductor Element 10) An IGBT is formed in the IGBT region 15. The IGBT switches when a potential higher than that of the emitter electrode 70 is applied to the collector electrode 72. When a potential higher than the gate threshold is applied to the gate electrode 64a, a channel is formed in the upper body region 34 and the lower body region 28 in the area adjacent to the trench insulating film 62. This turns on the IGBT, and a current flows from the collector electrode 72 to the emitter electrode 70. When the potential of the gate electrode 64a is reduced to a potential lower than the gate threshold, the channel disappears and the IGBT turns off.

[0028] A diode is formed in the diode region 16. When a higher potential is applied to the emitter electrode 70 than to the collector electrode 72, holes are injected from the upper body region 34 into the drift region 24a in the diode region 16. This reduces the electrical resistance of the drift region 24a due to conductivity modulation. As a result, electrons flow from the collector electrode 72 to the emitter electrode 70 via the cathode region 22, buffer region 24b, drift region 24a, lower body region 28, barrier region 30, and upper body region 34. In other words, the diode is turned on.

[0029] The technology of the present specification makes it possible to suppress hole injection into the drift region 24a by the hole injection suppression structure 31. That is, in the region where the hole injection suppression structure 31 is arranged, the barrier region 30 is connected to the emitter electrode 70, which has a low potential, by the pillar regions 26, so the potential of the barrier region 30 is low. This suppresses hole injection from the upper body region 34 into the drift region 24a. Because the hole injection suppression structure 31 is provided in the diode region 16 and the IGBT region 15, hole injection into the drift region 24a is suppressed in the diode region 16 and the IGBT region 15.

[0030] When the potential applied to the emitter electrode 70 is switched to a potential lower than that of the collector electrode 72 while the diode is on, the diode performs a recovery operation. That is, holes present in the drift region 24a are discharged to the emitter electrode 70, causing a reverse current (so-called recovery current) to instantaneously flow through the diode. With the technology of this specification, when the diode is on, hole injection into the drift region 24a is suppressed in both the diode region 16 and the IGBT region 15. Therefore, during the recovery operation, few holes are discharged from the drift region 24a to the emitter electrode 70. Therefore, a recovery current is unlikely to occur.

[0031] 4 shows a top view of the upper surface 12a of the semiconductor substrate 12 as viewed vertically from above (i.e., as viewed from the +z direction). The interlayer insulating film 68, upper electrode layer 69, and emitter electrode 70 are omitted from FIG. 4. The trench 60 is also simply indicated by a single line.

[0032] Each of the plurality of inter-trench semiconductor regions TA includes a plurality of specific regions SA. In FIG. 4, each of the plurality of specific regions SA is indicated by a dotted-line rectangle. The specific regions SA are configured so that pillar regions 26 can be disposed therein. That is, some of the specific regions SA have pillar regions 26 disposed therein, while others do not. The plurality of specific regions SA are disposed at regular intervals D1 in the x direction in each of the plurality of inter-trench semiconductor regions TA. The plurality of specific regions SA are also disposed in a straight line aligned in the y direction.

[0033] Here, predetermined cross sections CS1 to CS5 are defined. The predetermined cross sections CS1 to CS5 are cross sections passing through a plurality of specific areas SA aligned in the y direction and perpendicular to the x direction. The predetermined cross sections CS1 to CS5 are arranged at a constant interval D1 in the x direction and are arranged parallel to one another.

[0034] The regularity of the arrangement of the pillar regions 26 in the diode region 16 will be explained. In each of the predetermined cross sections CS1 to CS5, the pillar regions 26 are repeatedly arranged in the y direction according to a predetermined regularity. In the example of FIG. 4, units UT having a predetermined regularity are repeatedly arranged. Each unit UT has a configuration in which five specific regions SA are arranged in the y direction. Within the unit UT, the pillar regions 26 are arranged in a pattern of "present, present, absent, present, absent" from the positive side to the negative side in the y direction.

[0035] Furthermore, within the diode region 16, there is a rule that no more than three specific regions SA including the pillar regions 26 are consecutive in the y direction, and no more than three specific regions SA not including the pillar regions 26 are consecutive in the y direction. This makes it possible to suppress uneven distribution of the pillar regions 26 in the y direction. This makes it possible to make the hole injection suppression effect work evenly in the y direction.

[0036] The units UT are also repeatedly arranged in the x direction. When the units UT are repeatedly arranged in the x direction, the specific regions SA that serve as starting points are shifted one by one (see arrow A1). As a result, the pillar regions 26 are arranged in the x direction in a "present, present, absent, present, absent" pattern. Therefore, within the diode region 16, there is a regularity that no more than three specific regions SA including pillar regions 26 are consecutive in the x direction, and no more than three specific regions SA not including pillar regions 26 are consecutive in the x direction. This makes it possible to suppress uneven distribution of the pillar regions 26 in the x direction. It is also possible to ensure that the hole injection suppression effect is uniform in the x direction.

[0037] On the other hand, in the IGBT region 15, all of the inter-trench semiconductor regions TA exposed in the predetermined cross sections CS1 to CS5 include the pillar regions 26. That is, in the IGBT region 15, the pillar regions 26 are arranged in all of the specific regions SA, and the pillar regions 26 are not thinned out. This makes it possible to suppress hole injection from the IGBT region 15 side into the diode region 16, thereby enabling a further reduction in recovery loss.

[0038] There may be various methods for forming the pillar regions 26 arranged with a predetermined regularity. For example, when forming the pillar regions 26 by ion implantation, an implantation mask in which openings for forming the pillar regions 26 are formed with a predetermined regularity may be prepared. This does not complicate the manufacturing process, as it is only necessary to change the reticle.

[0039] (Effects) Conventional RC-IGBT elements use an AlSi alloy as the upper electrode layer. However, when an AlSi alloy is used, the Si in the alloy diffuses and grows into grains, sometimes resulting in the precipitation of Si nodules at the Schottky contact interface with the pillar region 26. This can result in an unstable Schottky barrier height, increasing the threshold voltage variation and increasing the leakage current. Therefore, the technology of this specification uses tungsten (W) as the upper electrode layer 69. This prevents the precipitation of Si nodules at the contact interface with the pillar region 26, thereby stabilizing the Schottky barrier height. This makes it possible to suppress the increase in threshold voltage variation and leakage current.

[0040] When a diode region having a tungsten upper electrode layer and a diode region having an AlSi alloy upper electrode layer are operated under the same conditions, the hole injection suppression effect of the pillar regions 26 is greater in the diode region having a tungsten upper electrode layer. This is because the Schottky barrier height of tungsten (0.68 eV) is lower than the Schottky barrier height of AlSi alloys (0.72 to 0.82 eV). If the hole injection suppression effect is higher than necessary, snapback and an increase in forward voltage may occur. Therefore, in the technology described herein, the pillar regions 26 are repeatedly arranged in the y and x directions according to a predetermined regularity in the diode region 16 (see FIG. 4 ). That is, a structure in which the pillar regions 26 are thinned out according to a predetermined regularity is adopted. The hole injection suppression effect can be prevented in regions where the pillar regions 26 are not arranged. This allows the hole injection suppression effect to be appropriately suppressed even when tungsten is used for the upper electrode layer 69. It is possible to prevent the occurrence of snapback and an increase in forward voltage.

[0041] As the semiconductor element 10 becomes smaller and the width of the inter-trench semiconductor region TA becomes narrower, the upper electrode layer 69 becomes more likely to peel off. Therefore, the technology of this specification uses tungsten for the upper electrode layer 69. Tungsten has higher adhesion to semiconductors than an AlSi alloy. Therefore, by using a tungsten upper electrode layer, peeling can be suppressed more effectively than when an AlSi alloy upper electrode layer is used. This enables further miniaturization of the semiconductor element 10.

[0042] (Preferred Range of Predetermined Ratio of Pillar Regions 26) The predetermined ratio of the pillar regions 26 will be described. The total number of inter-trench semiconductor regions TA exposed in a predetermined cross section CS in the diode region 16 is defined as the total number of regions. The number of inter-trench semiconductor regions TA that do not include a pillar region 26 in the diode region 16 is defined as the predetermined number of regions. The ratio of the predetermined number of regions to the total number of regions is defined as the predetermined ratio. The lower the predetermined ratio, the lower the proportion of inter-trench semiconductor regions TA that do not include a pillar region 26 in the total number of inter-trench semiconductor regions TA. In other words, the lower the predetermined ratio, the lower the proportion of pillar regions 26 that are thinned out. Therefore, the lower the predetermined ratio, the greater the hole injection suppression effect of the pillar regions 26.

[0043] 4, the total number of regions is "5" and the predetermined number of regions is "2". Therefore, the predetermined ratio of the unit UT is "0.4". Since the plurality of units UT are repeatedly arranged in the diode region 16, the predetermined ratio of the entire diode region 16 is also "0.4". In other words, the pillar regions 26 are thinned out in 40% of the inter-trench semiconductor region TA in the diode region 16.

[0044] The preferred range of the predetermined ratio will be explained. The predetermined ratio is preferably greater than 0.17. The reason for this is explained below. The ratio of the Schottky barrier height of tungsten to the maximum Schottky barrier height of an AlSi alloy is calculated as 0.68 eV / 0.82 eV=0.83. That is, the Schottky barrier height of tungsten is up to 17% smaller than that of an AlSi alloy. It is generally known to those skilled in the art that the aforementioned "hole injection suppression effect of the pillar regions 26" increases as the Schottky barrier height decreases. That is, when operated under the same conditions, it can be seen that the hole injection suppression effect of the pillar regions 26 is approximately 17% greater in a diode region having a tungsten upper electrode layer than in a diode region having an AlSi alloy upper electrode layer.

[0045] Therefore, in the technology of this specification, the hole injection suppression effect, which is increased by using tungsten for the upper electrode layer 69, is appropriately reduced by thinning out the pillar regions 26. Then, by making the predetermined ratio greater than "0.17" (i.e., by making the proportion of the inter-trench semiconductor region TA where the pillar regions 26 are not disposed greater than 17%), the hole injection suppression effect when using a tungsten upper electrode layer 69 can be made equal to or less than the hole injection suppression effect when using an AlSi alloy upper electrode layer 69. This makes it possible to prevent snapback and an increase in forward voltage even when using tungsten for the upper electrode layer 69.

[0046] In the technology of the present specification, the hole injection suppression effect is controlled by controlling the thinning rate of the pillar regions 26 rather than the area (thickness) of the pillar regions 26. The reason for this is explained below. As described above, the hole injection suppression effect is achieved by controlling the potential of the barrier region 30. It is difficult to significantly change the potential of the barrier region 30 by changing the area (thickness) of the pillar regions 26. On the other hand, the potential of the barrier region 30 can be significantly changed depending on the presence or absence of the pillar regions 26. Therefore, in the technology of the present specification, the barrier region 30 is divided into multiple regions by multiple inter-trench semiconductor regions TA. The potential of each of the divided barrier regions 30 is controlled depending on the presence or absence of the pillar regions 26.

[0047] A simulation was performed for a preferred range of the predetermined ratio. FIG. 5 shows a graph of the simulation results. The horizontal axis represents the predetermined ratio. The vertical axis on the left represents the inverter loss when the semiconductor device 10 of this embodiment is incorporated into an inverter and operated. The inverter loss is the sum of the turn-on loss Eon and the reverse recovery loss Err. The inverter loss is dimensionless, with the value set to 1 when the predetermined ratio is "0.17." The vertical axis on the right represents the snapback voltage VF of the semiconductor device 10. The snapback voltage VF indicates the amount of increase in the forward voltage of the diode region 16 when the snapback phenomenon occurs. Graph G1, indicated by open circles, represents the inverter loss. Graph G2, indicated by filled circles, represents the snapback voltage VF.

[0048] Graph G2 shows that the snapback voltage VF increases exponentially as the predetermined ratio becomes smaller than 0.17 (see ratio R1 in FIG. 5). The simulation results confirmed that the above-mentioned numerical range, "preferably the predetermined ratio is greater than 0.17," is appropriate.

[0049] In addition, in FIG. 5, the limit value EL of the inverter loss is set to "1.1." In other words, the limit value EL is set to a value that is 10 percent greater than the inverter loss when the predetermined ratio is "0.17." The predetermined ratio corresponding to this limit value EL is "0.7" (see ratio R2 in FIG. 5). Therefore, it is possible to derive the relationship that "it is preferable that the predetermined ratio be smaller than 0.7."

[0050] Furthermore, it is more preferable that the predetermined ratio be "greater than 0.33 and less than 0.67." The reason for this will be explained. As explained using FIG. 4 , there is a rule that three or more specific regions SA including pillar regions 26 do not consecutively occur in the y direction. To minimize the predetermined ratio while maintaining this rule, the aforementioned units UT must have a pattern of "present, present, absent." This leads to the condition that "the predetermined ratio is greater than 0.33." Similarly, there is a rule that three or more specific regions SA not including pillar regions 26 do not consecutively occur in the y direction. To maximize the predetermined ratio while maintaining this rule, the aforementioned units UT must have a pattern of "absent, absent, present." This leads to the condition that "the predetermined ratio is less than 0.67."

[0051] Fig. 6 shows a semiconductor substrate 12 according to Example 2. Fig. 6 is a diagram similar to Fig. 2 of Example 1. Example 2 differs from Example 1 in that it includes a lifetime control region 201. Contents common to Example 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0052] In the technology of Example 2, a lifetime control region 201 is formed in at least one of the IGBT region 15 and the diode region 16. In the example of Fig. 6, a plurality of lifetime control regions 201 are formed in at least a portion of the IGBT region 15. In Fig. 6, the lifetime control regions 201 are indicated by crosses. The plurality of lifetime control regions 201 are arranged in a plane at a predetermined depth from the upper surface 12a in the drift region 24a.

[0053] The lifetime control region 201 is a region where a large number of crystal defects are formed, and serves as a carrier recombination center. The lifetime control region 201 can be formed by irradiating helium ions from the upper surface 12a of the semiconductor substrate 12. The crystal defect density peaks at a predetermined depth, and the lifetime control region 201 is formed. The technology described in this specification can also be applied to a structure including such a lifetime control region 201.

[0054] The range in which the lifetime control region 201 is formed may vary. For example, it may be formed only in the diode region 16, or it may be formed over the entire region of the IGBT region 15 and the diode region 16.

[0055] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility.

[0056] (Modification) The pillar regions 26 may be arranged in various ways in the IGBT region 15. For example, not all of the inter-trench semiconductor regions TA exposed in a predetermined cross section may include the pillar regions 26. That is, in the IGBT region 15, the pillar regions 26 may not be arranged in all of the specific regions SA.

[0057] The method for arranging the pillar regions 26 with a predetermined regularity is not limited to the method using an implantation mask. The method for thinning out the pillar regions 26 is not limited to the method not involving ion implantation. For example, a method for preventing Schottky contact between the pillar regions 26 and the upper electrode layer 69 may be used. Specifically, in the region where the pillar regions 26 are thinned out, a p-type layer may be selectively disposed between the pillar regions 26 and the upper electrode layer 69.

[0058] The predetermined regularity described in this specification is an example, and various regularities can be used. Furthermore, the predetermined cross sections CS1 to CS5 described in this specification are an example, and a greater number of predetermined cross sections can be provided.

[0059] The material of the semiconductor substrate 12 is not limited to silicon, but may be a wide-gap semiconductor (e.g., SiC, GaN, Ga ２ O ３ etc.) can be used.

[0060] The configurations of the techniques disclosed in this specification are listed below. [Configuration 1] A semiconductor device (10) comprising: a semiconductor substrate (12); an upper electrode layer (69) in contact with an upper surface of the semiconductor substrate; and a lower electrode layer (72) in contact with a lower surface of the semiconductor substrate, wherein the upper electrode layer is tungsten; and the semiconductor substrate comprises a p-type collector region (20) in contact with the lower electrode layer and an n-type cathode region (22) in contact with the lower electrode layer; when the semiconductor substrate is viewed along a thickness direction, a region overlapping with the collector region is an IGBT region (15), and a region overlapping with the cathode region is a diode region (16); when a direction along a boundary between the IGBT region and the diode region on the upper surface is defined as a first direction (x) and a direction from the IGBT region toward the diode region on the upper surface is defined as a second direction (y), a plurality of trenches (60) extending along the first direction are provided on the upper surface, and the plurality of trenches are arranged at intervals in the second direction; an n-type emitter region (32) in contact with the upper electrode layer and the trench insulating film above the body region; and an n-type drift region (24a) disposed below the body region. In a predetermined cross section (CS) perpendicular to the first direction, a plurality of the inter-trench semiconductor regions are exposed along the second direction, and at least some of the inter-trench semiconductor regions exposed in the predetermined cross section include pillar regions (26),A semiconductor element, wherein the pillar region extends from the barrier region to the upper electrode layer and is in Schottky contact with the upper electrode layer made of tungsten, and the pillar regions are repeatedly arranged in the second direction according to a predetermined regularity in the diode region. [Structure 2] The semiconductor element according to Structure 1, wherein, when the total number of the inter-trench semiconductor regions exposed in the predetermined cross section in the diode region is defined as the total number of regions, and the number of the inter-trench semiconductor regions in the diode region that do not have the pillar region is defined as the predetermined number of regions, a predetermined ratio that is a ratio of the predetermined number of regions to the total number of regions is greater than 0.17. [Structure 3] The semiconductor element according to Structure 2, wherein the predetermined ratio is less than 0.7. [Structure 4] The semiconductor element according to Structure 1, wherein, when the total number of the inter-trench semiconductor regions exposed in the predetermined cross section in the diode region is defined as the total number of regions, and the number of the inter-trench semiconductor regions in the diode region that do not include the pillar regions is defined as the predetermined number of regions, a predetermined ratio that is a ratio of the predetermined number of regions to the total number of regions is greater than 0.33 and smaller than 0.67. [Structure 5] The semiconductor element according to any one of Structures 1-4, wherein the predetermined regularity includes a regularity that three or more inter-trench semiconductor regions that include the pillar regions do not occur consecutively in the second direction, and a regularity that three or more inter-trench semiconductor regions that do not include the pillar regions do not occur consecutively in the second direction. [Structure 6] The semiconductor element according to any one of Structures 1 to 5, wherein, in a vertical top view of the top surface of the semiconductor substrate, each of the plurality of inter-trench semiconductor regions includes a plurality of specific regions (SA) that are regions configured to allow the pillar regions to be disposed therein, the plurality of specific regions are disposed at regular intervals in the first direction in each of the plurality of inter-trench semiconductor regions and are disposed in a straight line in the second direction, the predetermined cross section is a cross section passing through the plurality of specific regions that are disposed in a straight line in the second direction, and there are a plurality of the predetermined cross sections that are disposed in parallel to each other at regular intervals in the first direction. [Structure 7]The semiconductor element according to any one of Structures 1 to 7, wherein, in each of the plurality of inter-trench semiconductor regions, there is established a regularity that three or more of the specific regions in which the pillar regions are arranged do not consecutively occur in the first direction, and there is also established a regularity that three or more of the specific regions in which the pillar regions are not arranged do not consecutively occur in the first direction. [Structure 8] The semiconductor element according to any one of Structures 1 to 7, wherein, in the IGBT region, all of the plurality of inter-trench semiconductor regions exposed in the predetermined cross section include the pillar regions.

[0061] The lower the predetermined ratio, the lower the proportion of the inter-trench semiconductor region that does not include pillar regions, resulting in a higher hole injection suppression effect. If the hole injection suppression effect becomes higher than necessary, there is a risk of the snapback phenomenon occurring. According to configuration 2, the predetermined ratio can be appropriately increased, making it possible to appropriately suppress the occurrence of snapback.

[0062] The higher the predetermined ratio, the lower the hole injection suppression effect, resulting in a larger recovery loss. According to configuration 3, the predetermined ratio can be appropriately reduced, thereby making it possible to appropriately suppress the recovery loss.

[0063] According to the fourth configuration, it is possible to more appropriately suppress the occurrence of the snapback phenomenon and recovery loss.

[0064] According to the fifth configuration, it is possible to suppress uneven distribution of the pillar regions in the diode region, and it is possible to make the hole injection suppression effect work uniformly in the diode region.

[0065] According to the sixth aspect, the pillar regions can be repeatedly arranged according to a predetermined regularity in the second direction as well. The pillar regions can be arranged according to a predetermined regularity within the plane of the diode region.

[0066] According to the seventh aspect, it is possible to suppress the uneven distribution of the pillar regions in the second direction as well, and it is possible to make the hole injection suppression effect work uniformly within the plane of the diode region.

[0067] According to the configuration 8, hole injection from the IGBT region side can be suppressed, and therefore recovery loss can be further reduced.

Claims

1. A semiconductor device (10) comprising a semiconductor substrate (12), an upper electrode layer (69) in contact with an upper surface of the semiconductor substrate, and a lower electrode layer (72) in contact with a lower surface of the semiconductor substrate, wherein the upper electrode layer is tungsten, and the semiconductor substrate comprises a p-type collector region (20) in contact with the lower electrode layer and an n-type cathode region (22) in contact with the lower electrode layer, wherein, when the semiconductor substrate is viewed along a thickness direction, a region overlapping with the collector region is an IGBT region (15), and a region overlapping with the cathode region is a diode region (16), and when a direction along a boundary between the IGBT region and the diode region on the upper surface is defined as a first direction (x) and a direction from the IGBT region toward the diode region on the upper surface is defined as a second direction (y), a plurality of trenches (60) extending along the first direction are provided on the upper surface, and the plurality of trenches are arranged at intervals in the second direction, an n-type emitter region (32) in contact with the upper electrode layer and the trench insulating film above the body region; and an n-type drift region (24a) disposed below the body region. In a predetermined cross section (CS) perpendicular to the first direction, a plurality of the inter-trench semiconductor regions are exposed along the second direction, and at least some of the inter-trench semiconductor regions exposed in the predetermined cross section include pillar regions (26),a semiconductor element, wherein the pillar region extends from the barrier region to the upper electrode layer and is in Schottky contact with the upper electrode layer made of tungsten, and the pillar regions are repeatedly arranged in the second direction according to a predetermined regularity within the diode region.

2. The semiconductor element according to claim 1, wherein when the total number of the plurality of inter-trench semiconductor regions exposed in the specified cross section in the diode region is defined as the total number of regions, and the number of inter-trench semiconductor regions in the diode region that do not include the pillar regions is defined as the specified number of regions, the specified ratio, which is the ratio of the specified number of regions to the total number of regions, is greater than 0.

17.

3. The semiconductor device according to claim 2, wherein said predetermined ratio is less than 0.

7.

4. The semiconductor element according to claim 1, wherein when the total number of the plurality of inter-trench semiconductor regions exposed in the specified cross section in the diode region is defined as the total number of regions, and the number of inter-trench semiconductor regions in the diode region that do not include the pillar regions is defined as the specified number of regions, the specified ratio, which is the ratio of the specified number of regions to the total number of regions, is greater than 0.33 and less than 0.

67.

5. The semiconductor element according to claim 4, wherein the predetermined regularity includes a regularity such that three or more inter-trench semiconductor regions each having the pillar region do not consecutively occur in the second direction, and a regularity such that three or more inter-trench semiconductor regions each not having the pillar region do not consecutively occur in the second direction.

6. A semiconductor device according to any one of claims 1 to 5, wherein, in a vertical top view of the top surface of the semiconductor substrate, each of the plurality of inter-trench semiconductor regions comprises a plurality of specific regions (SA) which are regions configured to allow the placement of the pillar regions, and the plurality of specific regions are arranged at regular intervals in the first direction in each of the plurality of inter-trench semiconductor regions and are aligned in a straight line in the second direction, and the predetermined cross section is a cross section passing through the plurality of specific regions that are aligned in a straight line in the second direction, and there are a plurality of the predetermined cross sections, which are aligned in the first direction at regular intervals and are aligned parallel to one another.

7. The semiconductor element described in claim 6, wherein in each of the plurality of inter-trench semiconductor regions, there is a regularity that no more than three of the specific regions in which the pillar regions are arranged are consecutive in the first direction, and there is also a regularity that no more than three of the specific regions in which the pillar regions are not arranged are consecutive in the first direction.

8. The semiconductor device according to claim 1, wherein in the IGBT region, all of the plurality of inter-trench semiconductor regions exposed in the predetermined cross section include the pillar region.

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