Light-emitting device

Abstract

This light-emitting device comprises: a multilayer substrate (20) including a substrate front surface (21), a substrate rear surface on the side opposite the substrate front surface (21), a front surface conductive layer (30) provided on the substrate front surface (21), a rear surface conductive layer provided on the substrate rear surface, and a first power-supply through-hole electrically connected to the front surface conductive layer (30); and a light-emitting element electrically connected to the front surface conductive layer (30). The front surface conductive layer (30) includes first power-supply wiring (40) that electrically connects the first power-supply through-hole to the light-emitting element. The first power-supply wiring (40) includes a plurality of pad regions (46) for mounting elements. The multilayer substrate (20) includes a pad-use heat dissipation via (90) provided in the multilayer substrate (20). The pad-use heat dissipation via (90) is provided at a position overlapping both the pad region (46) and the rear surface conductive layer in plan view.

Description

Light-emitting device

[0001] The present disclosure relates to a light emitting device.

[0002] Japanese Patent Application Laid-Open No. 2003-124222 discloses a semiconductor light emitting device including a semiconductor light emitting element, a switching element for driving the semiconductor light emitting element, and a capacitor.

[0003] Japanese Patent Application Laid-Open No. 2022-137839

[0004] [Summary] In semiconductor light emitting devices, there is a demand for improved heat dissipation performance.

[0005] A light-emitting device according to one aspect of the present disclosure comprises a multilayer substrate including a substrate surface, a substrate back surface opposite the substrate surface, a surface conductive layer provided on the substrate surface, a back conductive layer provided on the substrate back surface, and a first power terminal electrically connected to the surface conductive layer; and a light-emitting element electrically connected to the surface conductive layer, wherein the surface conductive layer includes first power wiring electrically connecting the first power terminal and the light-emitting element, and the first power wiring includes a plurality of pad areas for mounting elements, and the multilayer substrate includes a pad heat dissipation via provided within the multilayer substrate, and the pad heat dissipation via is positioned so as to overlap both the pad area and the back conductive layer in a planar view.

[0006] FIG. 1 is a schematic plan view of an exemplary light-emitting device according to a first embodiment. FIG. 2 is a schematic cross-sectional view of the light-emitting device taken along line F2-F2 in FIG. 1. FIG. 3 is a schematic perspective view of a light-emitting module in the light-emitting device. FIG. 4 is a schematic plan view showing the internal structure of the light-emitting module of FIG. 3. FIG. 5 is a schematic bottom view of the light-emitting module of FIG. 3. FIG. 6 is a schematic cross-sectional view of the light-emitting module taken along line F6-F6 in FIG. 4. FIG. 7 is a schematic cross-sectional view of the light-emitting module taken along line F7-F7 in FIG. 4. FIG. 8 is a schematic plan view showing an enlarged view of the light-emitting module, drive circuit, and surrounding area of ​​FIG. 1. FIG. 9 is a schematic plan view of a multilayer substrate of the light-emitting device. FIG. 10 is a schematic plan view showing an enlarged view of the first power supply wiring and its surrounding area of ​​FIG. 9. FIG. 11 is a schematic plan view showing an enlarged view of the light-emitting module, drive circuit, and its surrounding area of ​​FIG. 9. FIG. 12 is a schematic plan view of the light-emitting device in which a current-limiting resistor, a protective diode, an auxiliary resistor, an input capacitor, and a first heat dissipation member are mounted on the surface conductive layer of FIG. 10. FIG. 13 is a schematic plan view of a light-emitting device in which a light-emitting module, a drive circuit, a gate driver, and a second heat dissipation member are mounted on the surface conductive layer of FIG. 11 . FIG. 14 is a schematic plan view of an intermediate conductive layer closest to the surface conductive layer. FIG. 15 is a schematic plan view of an intermediate conductive layer closer to the back conductive layer than the intermediate conductive layer of FIG. 14 . FIG. 16 is a schematic plan view of an intermediate conductive layer closer to the back conductive layer than the intermediate conductive layer of FIG. 15 . FIG. 17 is a schematic plan view of an intermediate conductive layer closest to the back conductive layer. FIG. 18 is a schematic bottom view of a multilayer substrate. FIG. 19 is a schematic circuit diagram of a light-emitting system including a light-emitting device. FIG. 20 is a schematic plan view of an enlarged portion of the intermediate conductive layer closest to the surface conductive layer. FIG. 21 is a schematic plan view of an enlarged portion of the surface conductive layer. FIG. 22 is a schematic cross-sectional view of the multilayer substrate taken along line F22-F22 of FIG. 21 . FIG. 23 is a schematic cross-sectional view of the multilayer substrate taken along line F23-F23 of FIG. 21 . Fig. 24 is a schematic cross-sectional view of the multilayer substrate taken along line F24-F24 in Fig. 21. Fig. 25 is a schematic plan view showing an enlargement of the first element placement region and its periphery in Fig. 9. Fig. 26 is a schematic plan view showing an enlargement of the intermediate wiring in the intermediate conductive layer closest to the surface conductive layer and its periphery. Fig. 27 is a schematic cross-sectional view of the multilayer substrate taken along line F27-F27 in Fig. 25.FIG. 28 is a schematic plan view enlarging the transistor and its periphery in FIG. 9. FIG. 29 is a schematic cross-sectional view of the multilayer substrate taken along line F29-F29 in FIG. 28. FIG. 30 is a schematic front view of a light-emitting device to which a heat sink is attached. FIG. 31 is a schematic cross-sectional view of the light-emitting device of FIG. 30 taken along a line corresponding to line F2-F2 in FIG. 1. FIG. 32 is a schematic cross-sectional view of the light-emitting device of FIG. 30 taken along a line corresponding to line F22-F22 in FIG. 21. FIG. 33 is a graph showing the relationship between the heat transfer coefficient and the temperature of the light-emitting element. FIG. 34 is a schematic plan view enlarging a portion of the light-emitting device of the second embodiment. FIG. 35 is a schematic circuit diagram of a light-emitting system including the light-emitting device of FIG. 34. FIG. 36 is a schematic cross-sectional view of a pad heat dissipation via in a light-emitting device of a modified example. FIG. 37 is a schematic cross-sectional view of a pad heat dissipation via in a light-emitting device of a modified example. FIG. 38 is a schematic cross-sectional view of a first heat dissipation via in a light-emitting device of a modified example. Fig. 39 is a schematic cross-sectional view of a first heat dissipation via in a light emitting device of a modified example. Fig. 40 is a schematic plan view enlarging a protection diode and its periphery in a light emitting device of a modified example. Fig. 41 is a schematic plan view enlarging a portion of an intermediate conductive layer in a light emitting device of a modified example. Fig. 42 is a schematic cross-sectional view of a pad heat dissipation via in a light emitting device of a modified example. Fig. 43 is a schematic cross-sectional view of a first element heat dissipation via in a light emitting device of a modified example. Fig. 44 is a schematic cross-sectional view of a pad heat dissipation via in a light emitting device of a modified example. Fig. 45 is a schematic plan view enlarging a portion of a light emitting device of a modified example. Fig. 46 is a schematic plan view enlarging a portion of a light emitting device of a modified example. Fig. 47 is a schematic plan view enlarging a portion of a light emitting device of a modified example. Fig. 48 is a schematic circuit diagram of a light emitting device of a modified example.

[0007] [Detailed Description] Hereinafter, several embodiments of the light emitting device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The terms "first," "second," "third," etc. used in this disclosure are merely used to label and are not necessarily intended to assign any order to their objects. The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" if the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (thickness, distance) of A are equal to the dimensions (thickness, distance) of B" or "the dimensions (thickness, distance) of A and the dimensions (thickness, distance) of B are equal to each other" also includes a relationship in which the difference between the dimensions (thickness, distance) of A and the dimensions (thickness, distance) of B is, for example, within 10% of the dimensions (thickness, distance) of A.

[0011] 1 and 2 , the overall configuration of a light-emitting device 10 according to a first embodiment will be described. The light-emitting device 10 can be used in a laser system such as LiDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging), which is an example of three-dimensional distance measurement. The light-emitting device 10 may also be used in a laser system for two-dimensional distance measurement.

[0012] Fig. 1 shows a schematic planar structure of a light-emitting device 10 of the first embodiment, and illustrates a multilayer substrate 20, a light-emitting module 100, and a drive circuit 200, which will be described later. Fig. 2 shows a schematic cross-sectional structure of the light-emitting device 10 taken along line F2-F2 in Fig. 1.

[0013] In this disclosure, components may be described based on mutually orthogonal X, Y, and Z axes shown in the drawings. Here, the direction along the X axis is referred to as the "X direction," the direction along the Y axis is referred to as the "Y direction," and the direction along the Z axis is referred to as the "Z direction." Furthermore, the term "planar view" used in this disclosure refers to viewing the light emitting device 10 in the Z direction. Here, the X direction is an example of the "second direction," and the Y direction is an example of the "first direction."

[0014] 1 , the light-emitting device 10 includes a multilayer substrate 20, a light-emitting module 100 mounted on the multilayer substrate 20, a drive circuit 200, a gate driver 230, a current-limiting resistor 300, a protection diode 310, an auxiliary resistor 313, and an input capacitor 320. In the light-emitting device 10 of the first embodiment, the light-emitting module 100 is driven by the gate driver 230 and the drive circuit 200. The light-emitting module 100 is protected by the current-limiting resistor 300, the protection diode 310, and the auxiliary resistor 313. The light-emitting device 10 also includes a plurality of (four in the first embodiment) first heat dissipation members 340 and a plurality of (two in the first embodiment) second heat dissipation members 350 mounted on the multilayer substrate 20.

[0015] The multilayer substrate 20 is flat and has a thickness direction in the Z direction. Therefore, the Z direction can be considered to be the thickness direction of the multilayer substrate 20. The multilayer substrate 20 has a rectangular shape in a plan view. Here, "plan view" is synonymous with viewing the light emitting device 10 in the thickness direction of the multilayer substrate 20. The multilayer substrate 20 includes a substrate front surface 21, a substrate back surface 22 (see FIG. 2 ) opposite the substrate front surface 21, and first to fourth substrate side surfaces 23A to 23D connecting the substrate front surface 21 and the substrate back surface 22. The substrate front surface 21 and the substrate back surface 22 constitute both surfaces of the multilayer substrate 20 in the Z direction. The first substrate side surface 23A and the second substrate side surface 23B constitute both end surfaces of the multilayer substrate 20 in the X direction. The third substrate side surface 23C and the fourth substrate side surface 23D constitute both end surfaces of the multilayer substrate 20 in the Y direction.

[0016] The multilayer substrate 20 includes a plurality of (four in the first embodiment) substrate mounting holes 24 and a plurality of (six in the first embodiment) heat sink mounting holes 25. Each of the substrate mounting holes 24 and each of the heat sink mounting holes 25 penetrates the multilayer substrate 20 in the Z direction.

[0017] The plurality of substrate mounting holes 24 are holes for mounting the multilayer substrate 20 (light emitting device 10) to other electronic components (not shown). The substrate mounting holes 24 are provided at the four corners of the multilayer substrate 20 in a plan view.

[0018] The plurality of heat sink mounting holes 25 are holes for mounting a heat sink 400 (described later) to the multilayer substrate 20. The heat sink mounting holes 25 include a plurality of (three in the first embodiment) first mounting holes 25A arranged closer to the first substrate side surface 23A than the center in the X direction of the substrate surface 21 of the multilayer substrate 20 in a plan view, and a plurality of (three in the first embodiment) second mounting holes 25B arranged closer to the second substrate side surface 23B than the center in the X direction of the substrate surface 21 in a plan view.

[0019] The first mounting holes 25A and the second mounting holes 25B are arranged biased in the Y direction toward the third substrate side surface 23C on the substrate surface 21 of the multilayer substrate 20 in a plan view. The first mounting holes 25A are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction. The second mounting holes 25B are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction. The number and arrangement of the first mounting holes 25A and the second mounting holes 25B can be changed as desired.

[0020] The light-emitting module 100, the drive circuit 200, and the gate driver 230 are disposed between the first mounting hole 25A and the second mounting hole 25B in the X direction in a planar view. The light-emitting module 100 and the drive circuit 200 are disposed on the substrate surface 21, biased in the Y direction toward the third substrate side surface 23C in a planar view. The light-emitting module 100 and the drive circuit 200 are disposed in the center of the substrate surface 21 in the X direction in a planar view. The light-emitting module 100 is disposed closer to the third substrate side surface 23C than the drive circuit 200. The light-emitting module 100 can also be said to be disposed adjacent to the third substrate side surface 23C in the Y direction in a planar view. The gate driver 230 is disposed closer to the first substrate side surface 23A and the fourth substrate side surface 23D than the drive circuit 200 in a planar view.

[0021] The current limiting resistor 300 is configured to limit the current flowing through the first power supply wiring 40 (described later). The current limiting resistor 300 is disposed closer to the second substrate side surface 23B than the light-emitting module 100 and the drive circuit 200 in a planar view. The current limiting resistor 300 is disposed closer to the first substrate side surface 23A than the plurality of second mounting holes 25B in a planar view. That is, the current limiting resistor 300 is disposed between the light-emitting module 100 and the drive circuit 200 and the plurality of second mounting holes 25B in the X direction in a planar view. The current limiting resistor 300 is disposed closer to the fourth substrate side surface 23D than the light-emitting module 100 and the drive circuit 200 in a planar view. A plurality of current limiting resistors 300 (three in the first embodiment) may be provided. The plurality of current limiting resistors 300 are disposed at the same position in the X direction and spaced apart from each other in the Y direction.

[0022] The protection diode 310 and the auxiliary resistor 313 are configured to protect a light-emitting element 150 (described later) of the light-emitting module 100. The protection diode 310 and the auxiliary resistor 313 are arranged closer to the second substrate side surface 23B than the light-emitting module 100 and the drive circuit 200 in a planar view. The protection diode 310 and the auxiliary resistor 313 are arranged closer to the first substrate side surface 23A than the multiple current-limiting resistors 300 in a planar view. The protection diode 310 and the auxiliary resistor 313 are arranged in a position overlapping with the light-emitting module 100 when viewed from the X direction. The auxiliary resistor 313 is arranged closer to the second substrate side surface 23B than the protection diode 310. The auxiliary resistor 313 is arranged in a position overlapping with the current-limiting resistor 300 when viewed from the Y direction.

[0023] The input capacitor 320 is arranged closer to the second substrate side surface 23B than the multiple current limiting resistors 300 in a plan view. The input capacitor 320 is arranged closer to the second substrate side surface 23B than the multiple second mounting holes 25B in a plan view. A plurality of input capacitors 320 (two in the first embodiment) may be provided. The multiple input capacitors 320 are arranged at the same positions as each other in the Y direction and next to each other in the X direction. The number of input capacitors 320 can be changed as desired. In one example, there may be only one input capacitor 320.

[0024] The light emitting device 10 includes a first power connector 331, a second power connector 332, and a signal input connector 333. In Fig. 1, the first power connector 331, the second power connector 332, and the signal input connector 333 are each indicated by a two-dot chain line.

[0025] The first power connector 331 is configured to supply a current to the first power wiring 40 for charging a capacitor 220 (described later) of the drive circuit 200. The first power connector 331 is disposed closer to the fourth substrate side surface 23D than the heat sink mounting hole 25 in a plan view. The first power connector 331 is disposed adjacent to the second substrate side surface 23B in a plan view. The first power connector 331 includes a terminal that is electrically connected to an external DC power supply (not shown in FIG. 1 ).

[0026] The multilayer substrate 20 includes a first power supply through hole 26 to which the first power supply connector 331 is connected. The first power supply through hole 26 penetrates the multilayer substrate 20 in the Z direction. The first power supply through hole 26 is electrically connected to the surface conductive layer 30. Therefore, the first power supply through hole 26 is an example of a "first power supply terminal."

[0027] The first power supply through holes 26 include a first through hole 26A and a second through hole 26B. The first through hole 26A and the second through hole 26B are located at the same position in the X direction and spaced apart from each other in the Y direction. The first through hole 26A is a terminal electrically connected to the positive electrode of the DC power supply. The second through hole 26B is a terminal electrically connected to the negative electrode of the DC power supply. A first terminal and a second terminal of the first power supply connector 331 are inserted into both the first through hole 26A and the second through hole 26B. This electrically connects the first through hole 26A to the first terminal of the first power supply connector 331, and electrically connects the second through hole 26B to the second terminal of the first power supply connector 331.

[0028] The second power supply connector 332 is configured to supply operating current to the gate driver 230. The second power supply connector 332 includes a terminal electrically connected to an external control power supply (not shown in FIG. 1 ). The control power supply supplies operating current to the gate driver 230 through the second power supply connector 332. The second power supply connector 332 is disposed closer to the fourth substrate side surface 23D than the heat sink mounting hole 25 in a plan view. The second power supply connector 332 is disposed adjacent to the first substrate side surface 23A in a plan view.

[0029] The multilayer substrate 20 includes second power supply through holes 27 to which the second power supply connector 332 is connected. The second power supply through holes 27 penetrate the multilayer substrate 20 in the Z direction. The second power supply through holes 27 include a first through hole 27A and a second through hole 27B. The first through hole 27A and the second through hole 27B are located at the same position in the X direction and spaced apart from each other in the Y direction. The first through hole 27A is a terminal electrically connected to the positive electrode of the control power supply. The second through hole 27B is a terminal electrically connected to the negative electrode of the control power supply. The first and second terminals of the second power supply connector 332 are inserted into both the first through hole 27A and the second through hole 27B. This electrically connects the first through hole 27A to the first terminal of the second power supply connector 332, and the second through hole 27B to the second terminal of the second power supply connector 332. Here, the second power supply through hole 27 is an example of a "second power supply terminal."

[0030] The signal input connector 333 is configured to supply a pulse signal from an external control device to the gate driver 230. The signal input connector 333 may be a high-frequency connector such as an SMB connector. The pulse signal is used to control a transistor 210 (described later) of the drive circuit 200. The signal input connector 333 includes a terminal electrically connected to the control device. The signal input connector 333 is disposed closer to the fourth substrate side surface 23D than the heat sink mounting hole 25 in a plan view. The signal input connector 333 is disposed closer to the fourth substrate side surface 23D than the first power connector 331 and the second power connector 332 in a plan view.

[0031] The multilayer substrate 20 includes a signal through hole 28 to which the signal input connector 333 is connected, and a plurality of (four in the first embodiment) connector mounting holes 29. Both the signal through hole 28 and each connector mounting hole 29 penetrate the multilayer substrate 20 in the Z direction. The signal through hole 28 is electrically connected to the control device. The plurality of connector mounting holes 29 are provided around the signal through hole 28 in a plan view. Mounting portions provided on the housing of the signal input connector 333 are inserted into the plurality of connector mounting holes 29, and terminals of the signal input connector 333 are inserted into the signal through hole 28. This electrically connects the signal through hole 28 and the terminal of the signal input connector 333. Here, the signal through hole 28 is an example of a "signal input terminal."

[0032] As shown in FIG. 2 , the multilayer substrate 20 may include four or more conductive layers. In the first embodiment, the multilayer substrate 20 includes six conductive layers. Specifically, the multilayer substrate 20 includes a front conductive layer 30, intermediate conductive layers 60A-60D, and a back conductive layer 70. The front conductive layer 30 is a conductive layer provided on the front surface 21 of the multilayer substrate 20. The back conductive layer 70 is a conductive layer provided on the back surface 22 of the multilayer substrate 20. The intermediate conductive layers 60A-60D are conductive layers provided within the multilayer substrate 20. The intermediate conductive layers 60A-60D are provided between the front conductive layer 30 and the back conductive layer 70 in the Z direction. The intermediate conductive layers 60A-60D are separated from both the front conductive layer 30 and the back conductive layer 70 in the Z direction. The intermediate conductive layers 60A-60D are separated from each other in the Z direction. Each of the surface conductive layer 30, the intermediate conductive layers 60A-60D, and the back conductive layer 70 may be composed of one or more materials selected from a group including, for example, Cu (copper), Al (aluminum), Ti (titanium), TiN (titanium nitride), Au (gold), Ag (silver), and W (tungsten). In one example, the surface conductive layer 30, the intermediate conductive layers 60A and 60D, and the back conductive layer 70 may be composed of a first conductive film composed of a material containing Cu, a second conductive film on the first conductive film, and a third conductive film on the second conductive film. The first conductive film may be, for example, copper foil, and both the second and third conductive films may be plated films. The second and third conductive films may be, for example, plated films containing Cu. The intermediate conductive layers 60B and 60C may be composed of a conductive film composed of a material containing Cu. The conductive film may be, for example, copper foil. Alternatively, the intermediate conductive layers 60B and 60C may be formed of a first conductive film made of a material containing Cu and a second conductive film on the first conductive film. In this case, the first conductive film may be made of, for example, copper foil, and the second conductive film may be, for example, a plated film.

[0033] The multilayer substrate 20 includes multiple substrate insulating layers 80. Each substrate insulating layer 80 is made of an insulating material. For example, glass epoxy resin may be used as the insulating material. The multiple substrate insulating layers 80 include a front-side substrate insulating layer 81 including the substrate front surface 21, a back-side substrate insulating layer 82 including the substrate back surface 22, and multiple intermediate substrate insulating layers 83A to 83C provided between the front-side substrate insulating layer 81 and the back-side substrate insulating layer 82 in the Z direction. The intermediate substrate insulating layer 83A is disposed closer to the front-side substrate insulating layer 81 in the Z direction than the intermediate substrate insulating layers 83B and 83C. The intermediate substrate insulating layer 83C is disposed closer to the back-side substrate insulating layer 82 in the Z direction than the intermediate substrate insulating layers 83A and 83B. In the first embodiment, the thicknesses of both the front-side substrate insulating layer 81 and the back-side substrate insulating layer 82 are thinner than the thicknesses of the intermediate substrate insulating layers 83A to 83C. In one example, the thicknesses of the intermediate substrate insulating layers 83A to 83C may be equal to one another. In the first embodiment, the thickness of the front-side substrate insulating layer 81 and the thickness of the back-side substrate insulating layer 82 are equal to one another. In one example, the thickness of the front-side substrate insulating layer 81 may be 0.1 mm or less. In one example, the thickness of the back-side substrate insulating layer 82 may be 0.1 mm or less.

[0034] The front conductive layer 30 is provided on a front substrate insulating layer 81. The back conductive layer 70 is provided on a back substrate insulating layer 82. The front substrate insulating layer 81 constitutes the front substrate surface 21 of the multilayer substrate 20, and the back substrate insulating layer 82 constitutes the back substrate surface 22 of the multilayer substrate 20.

[0035] The intermediate conductive layer 60A is sandwiched between the front-side substrate insulating layer 81 and the intermediate substrate insulating layer 83A. The intermediate conductive layer 60B is sandwiched between the intermediate substrate insulating layer 83A and the intermediate substrate insulating layer 83B. The intermediate conductive layer 60C is sandwiched between the intermediate substrate insulating layer 83B and the intermediate substrate insulating layer 83C. The intermediate conductive layer 60D is sandwiched between the intermediate substrate insulating layer 83C and the back-side substrate insulating layer 82. The intermediate conductive layer 60A contacts the surface of the front-side substrate insulating layer 81 opposite to the surface on which the front conductive layer 30 is provided. The intermediate conductive layer 60D contacts the surface of the back-side substrate insulating layer 82 opposite to the surface on which the back conductive layer 70 is provided. In this way, the intermediate conductive layers 60A to 60D can be said to be provided on the intermediate substrate insulating layers 83A to 83C. In one example, the intermediate conductive layers 60A to 60D are not exposed from the multilayer substrate 20.

[0036] The thickness of the intermediate conductive layer 60A is thinner than the thicknesses of the intermediate conductive layers 60B and 60C. The thickness of the intermediate conductive layer 60D is thinner than the thicknesses of the intermediate conductive layers 60B and 60C. In other words, the thickness of the intermediate conductive layer 60A closer to the surface conductive layer 30 and the thickness of the intermediate conductive layer 60D closer to the back conductive layer 70 among the intermediate conductive layers 60A to 60D are both thinner than the thicknesses of the intermediate conductive layers 60B and 60C disposed closer to the center in the thickness direction (Z direction) of the multilayer substrate 20 than the intermediate conductive layers 60A and 60D. The thickness of the intermediate conductive layer 60A is equal to the thickness of the intermediate conductive layer 60D. The thickness of the intermediate conductive layer 60B is equal to the thickness of the intermediate conductive layer 60C. The thickness of the intermediate conductive layer 60A is thinner than the thickness of the surface conductive layer 30. The thickness of the intermediate conductive layer 60D is thinner than the thickness of the back conductive layer 70. The thicknesses of the intermediate conductive layers 60C and 60D are thicker than the thickness of the surface conductive layer 30. The thickness of the intermediate conductive layers 60C and 60D is greater than the thickness of the back surface conductive layer 70.

[0037] The thicknesses of the multiple substrate insulating layers 80 can be changed as desired. In one example, the thickness of the front-side substrate insulating layer 81 may be equal to or greater than the thickness of any one of the intermediate substrate insulating layers 83A to 83C. In one example, the thickness of the back-side substrate insulating layer 82 may be equal to or greater than the thickness of any one of the intermediate substrate insulating layers 83A to 83C. In one example, the thicknesses of the intermediate substrate insulating layers 83A to 83C may be different from one another. In one example, the thickness of the front-side substrate insulating layer 81 may be greater than 0.1 mm. In one example, the thickness of the back-side substrate insulating layer 82 may be greater than 0.1 mm.

[0038] Furthermore, the thicknesses of the surface conductive layer 30, the intermediate conductive layers 60A to 60D, and the back surface conductive layer 70 can each be changed as desired. In one example, the thickness of the intermediate conductive layer 60A may be equal to or greater than the thickness of the surface conductive layer 30. In one example, the thickness of the intermediate conductive layer 60D may be equal to or greater than the thickness of the back surface conductive layer 70. In one example, the thicknesses of the intermediate conductive layers 60A and 60D may be equal to or greater than the thicknesses of the intermediate conductive layers 60B and 60C. In one example, the thicknesses of the intermediate conductive layers 60B and 60C may be equal to or less than the thickness of the surface conductive layer 30. In one example, the thicknesses of the intermediate conductive layers 60B and 60C may be equal to or less than the thickness of the back surface conductive layer 70.

[0039] 2, the multilayer substrate 20 may include a front-side insulating layer 84 that covers the front-side conductive layer 30 and a back-side insulating layer 85 that covers the back-side conductive layer 70. Both the front-side insulating layer 84 and the back-side insulating layer 85 may be made of, for example, solder resist.

[0040] The surface-side insulating layer 84 is provided over substantially the entire substrate surface 21 and surface conductive layer 30 shown in FIG. 1 . The surface-side insulating layer 84 may include a first opening exposing the substrate mounting hole 24, a second opening exposing the heat sink mounting hole 25, a third opening exposing the first power supply through hole 26, a fourth opening exposing the second power supply through hole 27, a fifth opening exposing the signal through hole 28, and a sixth opening exposing the connector mounting hole 29. The surface-side insulating layer 84 may include openings for forming pads for mounting elements. Note that, for convenience, the surface conductive layer 30 covered by the surface-side insulating layer 84 is shown by a solid line in FIG. 1 .

[0041] The back-side insulating layer 85 is provided over substantially the entire substrate back surface 22 and back-side conductive layer 70 shown in Fig. 2. The back-side insulating layer 85 may include a first opening exposing the substrate mounting hole 24 and a second opening exposing the heat sink mounting hole 25 shown in Fig. 1, a third opening exposing the first power supply through-hole 26, a fourth opening exposing the second power supply through-hole 27, a fifth opening exposing the signal through-hole 28, and a sixth opening exposing the connector mounting hole 29.

[0042] [Configuration of Light-Emitting Module] The configuration of the light-emitting module 100 will be described with reference to Figures 3 to 7. Figure 3 shows a schematic perspective structure of the light-emitting module 100. Figure 4 shows a schematic planar structure of the interior of the light-emitting module 100. Figure 5 shows a schematic bottom structure of the light-emitting module 100. Figure 6 shows a schematic cross-sectional structure of the light-emitting module 100 taken along line F6-F6 in Figure 4. Figure 7 shows a schematic cross-sectional structure of the light-emitting module 100 taken along line F7-F7 in Figure 4.

[0043] As shown in Figure 3, the light-emitting module 100 comprises a rectangular, flat substrate 110 with its thickness direction in the Z direction, a light-emitting element 150 (see Figure 4) provided on the substrate 110, and a case 170 provided on the substrate 110 and housing the light-emitting element 150.

[0044] In the first embodiment, the substrate 110 has a rectangular shape with its long sides in the X direction and its short sides in the Y direction in a plan view. The substrate 110 has a substrate front surface 111 and a substrate back surface 112 that constitute both sides in the Z direction, and first to fourth substrate side surfaces 113 to 116 that connect the substrate front surface 111 and the substrate back surface 112. The first substrate side surface 113 and the second substrate side surface 114 constitute both end surfaces of the substrate 110 in the X direction. The third substrate side surface 115 and the fourth substrate side surface 116 constitute both end surfaces of the substrate 110 in the Y direction. The substrate 110 may be made of, for example, glass epoxy resin. The substrate 110 may also be made of a material containing ceramic. Examples of materials containing ceramic include aluminum nitride (AlN) or alumina (Al ２ O ３When the substrate 110 is made of a material containing ceramic, the heat dissipation performance of the substrate 110 is improved, and therefore the temperature of the light emitting element 150 can be prevented from becoming excessively high.

[0045] As shown in FIG. 4 , the light-emitting element 150 functions as a light source for the light-emitting module 100, in other words, a light source for the light-emitting device 10. The light-emitting element 150 is, for example, an edge-emitting element configured to emit light in a direction intersecting the Z direction. The light-emitting element 150 is, for example, a laser diode that emits light in a predetermined wavelength band. That is, the light-emitting element 150 is an edge-emitting laser element. The configuration of the light-emitting element 150 as an edge-emitting laser element is not particularly limited, but in the first embodiment, a Fabry-Perot laser diode element is used. The light-emitting element 150 is configured to emit light toward the third substrate side surface 115 (the third substrate side surface 23C of the multilayer substrate 20 shown in FIG. 1 ) in a plan view.

[0046] As shown in FIG. 3 , the case 170 is box-shaped and opens in the Z direction toward the substrate 110. The case 170 has first to fourth side walls 171 to 174 configured in a rectangular frame shape in a plan view, and a top wall 175 that covers one end of the opening defined by the first to fourth side walls 171 to 174 in the Z direction. In one example, the first to fourth side walls 171 to 174 and the top wall 175 are integrally formed. The first side wall 171 and the second side wall 172 constitute side walls at both ends of the case 170 in the X direction. The first side wall 171 is disposed near the first substrate side surface 113 of the substrate 110 in a plan view, and the second side wall 172 is disposed near the second substrate side surface 114 of the substrate 110 in a plan view. The third side wall 173 and the fourth side wall 174 constitute side walls at both ends of the case 170 in the Y direction. The third side wall 173 is disposed near the third substrate side surface 115 of the substrate 110 in a plan view, and the fourth side wall 174 is disposed near the fourth substrate side surface 116 of the substrate 110 in a plan view. The first side wall 171, the second side wall 172, the fourth side wall 174, and the top wall 175 are translucent, and the third side wall 173 is transparent. Laser light from the light-emitting element 150 is emitted to the outside of the case 170 through the transparent third side wall 173. It is sufficient that at least the side wall of the case 170 in the emission direction of the light-emitting element 150 (i.e., the side wall through which the light from the light-emitting element 150 passes) is transparent. Therefore, at least one of the first side wall 171, the second side wall 172, the fourth side wall 174, and the top wall 175 may be transparent. The case 170 is made of, for example, a glass material. Instead of a glass material, the case 170 may be made of a transparent or translucent resin material. Examples of the resin material include acrylic resin, epoxy resin, etc. The configuration of the case 170 can be changed as desired. For example, of the first to fourth side walls 171 to 174, the side wall through which the laser light passes (the third side wall 173 in the first embodiment) may be omitted.

[0047] 4, the substrate 110 includes a plurality of surface conductive layers 120 (ten in the first embodiment) provided on a substrate surface 111 of the substrate 110. Each surface conductive layer 120 is made of, for example, copper foil. Note that the material of each surface conductive layer 120 is not limited to copper foil, and may include at least one of Al, Ni, palladium (Pd), Ag, and Au.

[0048] The multiple surface conductive layers 120 include multiple (eight in the first embodiment) wire connection electrodes 121 to which the wires WR described later are connected, a first mounting pattern 122 for mounting the light-emitting element 150, and a second mounting pattern 123 for mounting the case 170.

[0049] The first mounting pattern 122 is disposed on the substrate surface 111 in the Y direction closer to the third substrate side surface 115. The first mounting pattern 122 has a rectangular shape with its long side extending in the X direction and its short side extending in the Y direction in a plan view.

[0050] The multiple wire connection electrodes 121 are arranged to surround the first mounting pattern 122 from the first substrate side surface 113, the second substrate side surface 114, and the fourth substrate side surface 116 in a plan view. The multiple wire connection electrodes 121 are arranged to be in a line-symmetric relationship with respect to the center line CL. The multiple wire connection electrodes 121 have shapes that are line-symmetric with respect to the center line CL in a plan view. Here, the center line CL is located at the center of the substrate surface 21 in the X direction in a plan view and is a straight line extending along the Y direction. The arrangement and shape of the multiple wire connection electrodes 121 can be changed as desired.

[0051] The second mounting pattern 123 has a rectangular frame shape surrounding the first mounting pattern 122 and the multiple wire connection electrodes 121 in a plan view. The second mounting pattern 123 is not electrically connected to the light emitting element 150. In other words, the second mounting pattern 123 is in an electrically floating state. The material constituting the second mounting pattern 123 can be changed as desired. In one example, the second mounting pattern 123 may be made of an insulating material. In this case, the multiple surface conductive layers 120 do not include the second mounting pattern 123. It can be said that the second mounting pattern 123 surrounds the multiple surface conductive layers 120 in a plan view. The shape of the second mounting pattern 123 in a plan view can be changed as desired.

[0052] A surface resist 124 is provided on the substrate surface 21. In plan view, the surface resist 124 has a generally U-shape that surrounds the first mounting pattern 122 from the first substrate side surface 113, the second substrate side surface 114, and the fourth substrate side surface 116. In plan view, the surface resist 124 is disposed between the first mounting pattern 122 and the plurality of wire connection electrodes 121. The surface resist 124 is, for example, a solder resist. The solder resist is made of, for example, an insulating material. For example, an epoxy resin is used as the insulating material.

[0053] 5, the substrate 110 includes a plurality of (nine in the first embodiment) back surface conductive layers 130 provided on the substrate back surface 112 of the substrate 110. The plurality of back surface conductive layers 130 are arranged spaced apart from one another. The plurality of back surface conductive layers 130 are made of, for example, copper foil. Note that the plurality of back surface conductive layers 130 are not limited to copper foil, and may include at least one of Al, Ni, Pd, Ag, and Au.

[0054] The multiple back surface conductive layers 130 include multiple (eight in the first embodiment) first back surface conductive layers 131 and second back surface conductive layers 132. The multiple first back surface conductive layers 131 are provided corresponding to the multiple wire connection electrodes 121 (see FIG. 4 ). The multiple first back surface conductive layers 131 are electrically connected to the corresponding wire connection electrodes 121, respectively. The multiple first back surface conductive layers 131 include portions that overlap with the multiple wire connection electrodes 121 in a plan view. The multiple first back surface conductive layers 131 are arranged in a line-symmetric relationship with respect to the center line CL in a plan view. The multiple first back surface conductive layers 131 have shapes that are line-symmetric with respect to the center line CL in a plan view.

[0055] The second back surface conductive layer 132 is electrically connected to the first mounting pattern 122 (see FIG. 4 ). The second back surface conductive layer 132 is arranged closer to the third substrate side surface 115 than the multiple first back surface conductive layers 131. The second back surface conductive layer 132 is convex in plan view. More specifically, the second back surface conductive layer 132 includes a strip-shaped main body portion extending in the X direction and a protruding portion protruding from the center of the main body portion in the X direction toward the fourth substrate side surface 116. The protruding portion is rectangular in plan view with its long sides extending in the X direction and its short sides extending in the Y direction.

[0056] 4, 5, and 7, the substrate 110 includes a plurality of through electrodes 140 (nine in the first embodiment). The through electrodes 140 connect the front surface conductive layer 120 and the back surface conductive layer 130. The through electrodes 140 penetrate the substrate 110 in the Z direction. Each through electrode 140 is made of a material containing Cu, for example. Note that each through electrode 140 is not limited to Cu, and may contain at least one of Ti, W, and Al.

[0057] The plurality of through electrodes 140 includes a plurality of (eight in the first embodiment) first through electrodes 141 and second through electrodes 142. The plurality of first through electrodes 141 individually connect the plurality of wire connection electrodes 121 and the plurality of first back surface conductive layers 131. Each of the first through electrodes 141 has a columnar shape that fills a through hole provided in the substrate 110. The plurality of first through electrodes 141 have the same size. Each of the first through electrodes 141 has an oval shape in a planar view. The plurality of first through electrodes 141 are arranged so as to be line-symmetrical with respect to the center line CL in a planar view. The plurality of first through electrodes 141 have a shape that is line-symmetrical with respect to the center line CL in a planar view. The shape of each of the first through electrodes 141 in a planar view can be arbitrarily changed. Each of the first through electrodes 141 may have a circular shape, an elliptical shape, a polygonal shape, or the like in a planar view.

[0058] The second through electrode 142 connects the first mounting pattern 122 and the second back surface conductive layer 132. The second through electrode 142 has a rectangular shape with its long sides in the X direction and its short sides in the Y direction in plan view.

[0059] As shown in FIG. 5 , a back surface resist 133 is provided on the back surface 112 of the substrate, covering the plurality of back surface conductive layers 130. The back surface resist 133 is, for example, a solder resist. The solder resist is made of, for example, an insulating material. For example, an epoxy resin is used as the insulating material. In one example, the back surface resist 133 may be made of the same material as the front surface resist 124 (see FIG. 4 ). Note that in FIG. 5 , the portions of the plurality of back surface conductive layers 130 that overlap with the back surface resist 133 are indicated by dashed lines.

[0060] The rear surface resist 133 covers most of the substrate rear surface 112. The rear surface resist 133 includes a plurality of openings corresponding to the plurality of first rear surface conductive layers 131 and the plurality of second rear surface conductive layers 132. The rear surface resist 133 includes a plurality of (eight in the first embodiment) first openings 134 and a plurality of (six in the first embodiment) second openings 135. The plurality of first openings 134 are provided so as to individually expose the plurality of first rear surface conductive layers 131. Each of the plurality of second openings 135 is provided so as to expose the second rear surface conductive layer 132.

[0061] 4 , the light-emitting module 100 includes a submount 160 that supports the light-emitting element 150. The submount 160 is mounted on the first mounting pattern 122. In one example, the submount 160 is die-bonded to the first mounting pattern 122. Note that the first mounting pattern 122 may be integrated with the submount 160.

[0062] The surface resist 124 allows the die bonding material (not shown) used to die bond the submount 160 to the first mounting pattern 122 to remain on the first mounting pattern 122. Examples of the die bonding material include conductive bonding materials such as solder paste, Ag paste, Au paste, and Cu paste. In this way, the surface resist 124 is provided between the first mounting pattern 122 and the plurality of wire connection electrodes 121, so that the first mounting pattern 122 and the plurality of wire connection electrodes 121 can be prevented from being electrically connected by the conductive bonding material.

[0063] The submount 160 has a flat plate shape with its thickness direction aligned in the Z direction. The submount 160 has a rectangular shape with its long sides aligned in the X direction and its short sides aligned in the Y direction in plan view. In one example, the submount 160 is slightly smaller than the first mounting pattern 122 in plan view.

[0064] The submount 160 is made of, for example, a material containing silicon (Si). The submount 160 may be made of a material containing ceramic. The submount 160 may also be made of a conductive material. Examples of conductive materials include Cu and Al. When the submount 160 is made of ceramic or a conductive material, the heat dissipation performance of the submount 160 is improved. This makes it easier for heat from the light-emitting element 150 to transfer to the substrate 110 through the submount 160. This makes it possible to prevent the temperature of the light-emitting element 150 from becoming excessively high.

[0065] 6 and 7, the thickness of the submount 160 is greater than the thickness of the substrate 110. The thickness of the submount 160 can be changed as desired. The thickness of the submount 160 may be equal to or less than the thickness of the substrate 110.

[0066] The submount 160 has a front surface 161 and a back surface 162 that form both surfaces in the Z direction. In one example, the light emitting element 150 is mounted on the front surface 161 of the submount 160. The light emitting element 150 is die-bonded to the front surface 161 of the submount 160.

[0067] The submount 160 includes a through electrode 163 penetrating through the submount 160 in its thickness direction. The through electrode 163 is made of a material containing Cu, for example. Note that the through electrode 163 is not limited to Cu and may contain at least one of Ti, W, and Al. In the first embodiment, there is one through electrode 163, but multiple through electrodes 163 may be provided. In one example, the number of through electrodes 163 may be the same as the number of element electrodes 153 (eight in the first embodiment) of the light-emitting element 150, which will be described later. Note that if the submount 160 is made of a conductive material, the through electrode 163 may be omitted. The through electrode 163 is electrically connected to the first mounting pattern 122 by a conductive bonding material.

[0068] As shown in Figures 2, 6, and 7, the light-emitting element 150 mounted on the surface 161 of the submount 160 is flat and has a thickness in the Z direction. As shown in Figure 4, the light-emitting element 150 is rectangular in shape with its long sides in the X direction and its short sides in the Y direction in a plan view. In one example, the light-emitting element 150 is slightly smaller than the submount 160 in a plan view. The light-emitting element 150 is disposed at the center of the substrate 110 in the X direction in a plan view. Therefore, it can be said that the center line CL is located at the center of the light-emitting element 150 in the X direction.

[0069] As shown in FIGS. 6 and 7, the light emitting element 150 includes an element front surface 151 and an element back surface 152 which constitute both surfaces in the Z direction, and a plurality of element electrodes 153 provided on the element front surface 151.

[0070] The plurality of element electrodes 153 are arranged in a line in the X direction. Each element electrode 153 is made of, for example, Au. Note that each element electrode 153 is not limited to Au and may contain at least one of Al, Ni, Pd, Ag, and Cu. In the first embodiment, each element electrode 153 constitutes an anode of the light-emitting element 150.

[0071] 4, the light-emitting element 150 includes a plurality of light-emitting portions 154 corresponding to a plurality of element electrodes 153. Therefore, in the first embodiment, the light-emitting element 150 includes eight light-emitting portions 154. The plurality of light-emitting portions 154 are arranged in a row in the X direction. Four of the eight light-emitting portions 154 are arranged closer to the first substrate side surface 113 than the center line CL, and the remaining four light-emitting portions 154 are arranged closer to the second substrate side surface 114 than the center line CL. Each light-emitting portion 154 is configured to emit laser light toward the third substrate side surface 115 in a plan view.

[0072] 6 and 7 , the light-emitting element 150 includes a back surface conductive layer 155 provided on the element back surface 152. In one example, the back surface conductive layer 155 is provided over the entire element back surface 152. The back surface conductive layer 155 is made of, for example, Au. Note that the back surface conductive layer 155 is not limited to Au, and may contain at least one of Al, Ni, Pd, Ag, and Cu. In the first embodiment, the back surface conductive layer 155 forms the cathode of the light-emitting element 150.

[0073] The light-emitting element 150 is mounted on the submount 160 by a conductive bonding material (not shown). Therefore, the back surface conductive layer 155 is electrically connected to the submount 160 (through electrode 163) by the conductive bonding material. Examples of the conductive bonding material include solder paste, Ag paste, Au paste, and Cu paste. The second back surface conductive layer 132 electrically connected to the through electrode 163 of the submount 160 constitutes a cathode terminal.

[0074] 4, the light-emitting module 100 includes a plurality of wires WR that individually and electrically connect the light-emitting elements 150 to a plurality of wire-connecting electrodes 121. Each light-emitting section 154 is connected to the wire-connecting electrode 121 electrically connected to the light-emitting section 154 by a plurality of wires WR (four in the first embodiment). The number of wires WR can be changed as desired. A plurality of first back surface conductive layers 131 electrically connected to the plurality of wire-connecting electrodes 121 constitute anode terminals.

[0075] [Configuration of the Drive Circuit] The configuration of the drive circuit 200 will be described with reference to Fig. 2 and Fig. 8. Fig. 8 shows a schematic planar structure of the light-emitting module 100, the drive circuit 200, and the surrounding area in an enlarged scale in Fig. 1 .

[0076] 8 , the drive circuit 200 is configured to drive the light emitting module 100. The drive circuit 200 is configured to drive the light emitting element 150 of the light emitting module 100. The drive circuit 200 is connected to the surface conductive layer 30.

[0077] The drive circuit 200 includes a transistor 210 and one or more capacitors 220. The transistor 210 is configured to control driving of the light-emitting element 150. The capacitor 220 is configured to supply current to the light-emitting element 150. In one example, the drive circuit 200 may include six or more capacitors 220. In the first embodiment, the drive circuit 200 includes twelve capacitors 220. The capacitors 220 are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The number of capacitors 220 may be changed as appropriate, for example, depending on the light-emitting element 150 of the light-emitting module 100. When viewed from the Y direction, some of the multiple capacitors 220 are arranged further outward in the X direction than the transistor 210. In the first embodiment, some of the multiple capacitors 220 are arranged closer to the first substrate side surface 23A than the transistor 210. Another part of the multiple capacitors 220 are arranged closer to the second substrate side surface 23B than the transistor 210. In the first embodiment, some of the capacitors 220 are arranged closer to the first substrate side surface 23A than the light-emitting module 100. Another part of the capacitors 220 are arranged closer to the second substrate side surface 23B than the light-emitting module 100.

[0078] The light-emitting module 100, the transistor 210, and the capacitor 220 are arranged spaced apart from one another in the Y direction in a plan view. The capacitor 220 is arranged between the light-emitting module 100 and the transistor 210 in the Y direction. Therefore, it can also be said that the capacitor 220 is arranged between the light-emitting element 150 and the transistor 210 in the Y direction.

[0079] The transistor 210 has a quadrangular shape in a plan view. In one example, the transistor 210 has a rectangular shape with the dimension in the X direction longer than the dimension in the Y direction. The transistor 210 includes, for example, a lateral transistor. The lateral transistor may include, for example, a nitride semiconductor. The lateral transistor may be, for example, a high electron mobility transistor (HEMT) made of a nitride semiconductor such as gallium nitride (GaN). The lateral transistor may also be a metal-oxide-semiconductor field-effect transistor (MOSFET). Note that the shape of the transistor 210 in a plan view can be changed as desired.

[0080] 2 , the transistor 210 includes a first element surface 211 and a second element surface 212 opposite the first element surface 211. The transistor 210 includes a source electrode 213, a drain electrode 214, and a gate electrode 215 (all of which are shown in FIG. 8 ) provided on the first element surface 211. The transistor 210 is mounted with the first element surface 211 facing the multilayer substrate 20. Therefore, the first element surface 211 is the surface facing the surface conductive layer 30. The first element surface 211 is disposed closer to the surface conductive layer 30 than the second element surface 212.

[0081] 8 , a plurality of source electrodes 213 and a plurality of drain electrodes 214 (three of each in the first embodiment) are provided. The plurality of source electrodes 213 and the plurality of drain electrodes 214 are alternately arranged one by one in the X direction. The gate electrodes 215 are provided at corner portions of the first element surface 211 in a plan view.

[0082] Each capacitor 220 may be, for example, a ceramic capacitor. Each capacitor 220 has a rectangular shape in a plan view. Each capacitor 220 has two long sides along the Y direction and two short sides along the X direction. Each capacitor 220 includes a first electrode 221 and a second electrode 222. The first electrode 221 is provided at one end of the capacitor 220 in the Y direction, and the second electrode 222 is provided at the other end of the capacitor 220 in the Y direction.

[0083] [Electrode Configuration of Multilayer Substrate] The electrode configuration of the multilayer substrate 20 will be described with reference to FIGS. 9 to 18. FIG. 9 shows a schematic planar structure of the surface conductive layer 30 in FIG. 1. FIG. 10 shows an enlarged schematic planar structure of the first power supply wiring 40 (described later) and its periphery in FIG. 9. FIG. 11 shows an enlarged schematic planar structure of the light-emitting module 100 and its periphery in FIG. 9. FIG. 12 shows an enlarged schematic planar structure of the first power supply wiring 40 and its periphery in FIG. 1. FIG. 13 shows an enlarged schematic planar structure of the light-emitting module 100 and its periphery in FIG. 1. FIGS. 14 to 17 show the schematic planar structures of the intermediate conductive layers 60A to 60D. FIG. 18 shows the schematic planar structure of the back surface conductive layer 70. Note that elements mounted on the first power supply wiring 40 are omitted in FIG. 9. Elements mounted on the surface conductive layer 30 (described later) are omitted in FIG. 10. FIG. 18 is a perspective view.

[0084] 9 , the surface conductive layer 30 is provided so as to avoid both the substrate mounting hole 24 and the heat sink mounting hole 25 in a plan view. The surface conductive layer 30 is provided over most of the substrate surface 21 of the multilayer substrate 20. The surface conductive layer 30 includes a first power supply wiring 40, a second power supply wiring 47, and a third power supply wiring 50.

[0085] As shown in FIG. 10 , the first power supply wiring 40 is connected to the first through hole 26A of the first power supply through hole 26. That is, the first power supply wiring 40 is a wiring to which current is supplied from a DC power supply through the first through hole 26A of the first power supply through hole 26. The first power supply wiring 40 is a wiring for supplying a drive current for driving the light emitting element 150 from the first power supply through hole 26 to the light emitting element 150. The first power supply wiring 40 has a stepped shape in a plan view. The first power supply wiring 40 includes a first wiring portion 41, a second wiring portion 42, a third wiring portion 43, a fourth wiring portion 44, and a fifth wiring portion 45. The first to fifth wiring portions 41 to 45 are arranged spaced apart from one another.

[0086] The first wiring portion 41 is a wiring portion of the first power supply wiring 40 to which the first power supply connector 331 (see FIG. 1) is connected. The first wiring portion 41 is arranged closer to the fourth board side surface 23D than the multiple second mounting holes 25B of the heat sink mounting hole 25. The first wiring portion 41 extends in the X direction from the first through hole 26A of the first power supply through hole 26 toward the first board side surface 23A (see FIG. 9). The first wiring portion 41 includes a portion arranged closer to the first board side surface 23A than the second mounting holes 25B.

[0087] The first wiring portion 41 can be divided into a first portion 41A, a second portion 41B, and a third portion 41C. The first portion 41A is connected to the first through-hole 26A and extends in the X direction. The second portion 41B is a portion of the first portion 41A that extends from an end of the first portion 41A closer to the first substrate side surface 23A toward the fourth substrate side surface 23D (see FIG. 9). The third portion 41C is a portion that extends in the X direction from the second portion 41B toward the first substrate side surface 23A. Therefore, the first wiring portion 41 includes a recessed portion 41D. The recessed portion 41D is positioned closer to the first substrate side surface 23A than the second mounting hole 25B.

[0088] The second wiring portion 42 is a wiring portion that is partially disposed in the recessed portion 41D of the first wiring portion 41. Therefore, the second wiring portion 42 is disposed closer to the first substrate side surface 23A than the second mounting hole 25B. The second wiring portion 42 includes a portion that protrudes closer to the third substrate side surface 23C than the first portion 41A of the first wiring portion 41. The second wiring portion 42 is rectangular in plan view.

[0089] The third wiring portion 43 is a wiring portion that is arranged closer to the third substrate side surface 23C than the second wiring portion 42. The second wiring portion 42 and the third wiring portion 43 are arranged at the same position in the X direction and spaced apart from each other in the Y direction. The third wiring portion 43 has a quadrangular shape in a plan view. The size of the third wiring portion 43 is the same as the size of the second wiring portion 42.

[0090] The fourth wiring portion 44 is disposed closer to the third substrate side surface 23C than the third wiring portion 43. The fourth wiring portion 44 is L-shaped in a plan view. The fourth wiring portion 44 includes a first portion 44A extending in the Y direction and a second portion 44B extending in the X direction.

[0091] The first portion 44A is disposed closer to the third substrate side surface 23C than the third wiring portion 43. The first portion 44A and the third wiring portion 43 are disposed at the same position in the X direction and spaced apart from each other in the Y direction. In one example, the dimension of the first portion 44A in the Y direction is greater than the dimension of the third wiring portion 43 in the Y direction.

[0092] The second portion 44B extends in the X direction from an end of the first portion 44A closer to the third substrate side surface 23C toward the first substrate side surface 23A. As shown in Fig. 9, the second portion 44B is strip-shaped with a larger dimension in the X direction than in the Y direction in a plan view. The tip of the second portion 44B in the X direction includes an inclined portion that slopes toward the fourth substrate side surface 23D as it approaches the first substrate side surface 23A.

[0093] 10 , the fifth wiring portion 45 is disposed closer to the third substrate side surface 23C than the first portion 44A of the fourth wiring portion 44. The fifth wiring portion 45 is strip-shaped and has a larger dimension in the X direction than the dimension in the Y direction in a plan view. In one example, the dimension in the Y direction of the fifth wiring portion 45 is smaller than the dimension in the Y direction of the second portion 44B of the fourth wiring portion 44.

[0094] The first power supply wiring 40 includes a plurality of pad regions 46 for mounting elements. Each pad region 46 is an opening region configured to expose the first power supply wiring 40 from the front-side insulating layer 84 (see FIG. 2).

[0095] The multiple pad regions 46 include resistor pad regions 46A to 46C, a diode pad region 46D, and an auxiliary resistor pad region 46E. The resistor pad regions 46A to 46C are regions of the first power supply wiring 40 where a current limiting resistor 300 (see FIG. 12) is mounted. The diode pad region 46D is a region where a protection diode 310 (see FIG. 12) is mounted. The auxiliary resistor pad region 46E is a region where an auxiliary resistor 313 (see FIG. 12) is mounted. In this way, the multiple pad regions 46 are regions where the current limiting resistor 300, the protection diode 310, and the auxiliary resistor 313 are mounted as elements.

[0096] The resistor pad regions 46A are provided in both the third portion 41C of the first wiring portion 41 and the second wiring portion 42. The resistor pad regions 46A are provided at one of the Y-direction end portions of the second wiring portion 42 that is closer to the third portion 41C. In this way, the resistor pad regions 46A are provided at the same position in the X-direction and spaced apart in the Y-direction. Each resistor pad region 46A is strip-shaped with a dimension in the X-direction greater than its dimension in the Y-direction.

[0097] The resistor pad regions 46B are provided in both the second wiring portion 42 and the third wiring portion 43. More specifically, the resistor pad regions 46B are provided in both of the Y-direction ends of the second wiring portion 42 that are closer to the third wiring portion 43 and in both of the Y-direction ends of the third wiring portion 43 that are closer to the second wiring portion 42. In this manner, the resistor pad regions 46B are provided at the same position in the X-direction and spaced apart in the Y-direction. Each resistor pad region 46B is strip-shaped, with its dimension in the X-direction greater than its dimension in the Y-direction. The size of each resistor pad region 46B is the same as the size of each resistor pad region 46A.

[0098] The resistor pad regions 46C are provided in both the third wiring portion 43 and the fourth wiring portion 44. More specifically, the resistor pad regions 46C are provided in both of the Y-direction ends of the third wiring portion 43 that are closer to the fourth wiring portion 44, and in both of the Y-direction ends of the first portion 44A of the fourth wiring portion 44 that are closer to the third wiring portion 43. In this manner, the resistor pad regions 46C are provided at the same position in the X-direction and spaced apart in the Y-direction. Each resistor pad region 46C is strip-shaped, with its dimension in the X-direction greater than its dimension in the Y-direction. The size of each resistor pad region 46C is the same as the size of each resistor pad region 46A. The resistor pad regions 46A to 46C are arranged at the same position in the X-direction and spaced apart from each other in the Y-direction.

[0099] The diode pad region 46D is provided in the fifth wiring portion 45. The diode pad region 46D is provided at one of both ends of the fifth wiring portion 45 in the X direction that is closer to the second power supply wiring 47. The diode pad region 46D has a rectangular shape in a plan view. The size of the diode pad region 46D is smaller than the size of each resistor pad region 46A, for example.

[0100] The auxiliary resistor pad region 46E is provided in both the fourth wiring portion 44 and the fifth wiring portion 45. More specifically, one of the auxiliary resistor pad regions 46E is provided at one of the Y-direction ends of the first portion 44A of the fourth wiring portion 44 that is closer to the fifth wiring portion 45. The other auxiliary resistor pad region 46E is provided at a position in the fifth wiring portion 45 adjacent to the diode pad region 46D in the X-direction.

[0101] The pad regions 46 may include an input capacitor pad region 46F. The input capacitor pad region 46F is a region where an input capacitor 320 is mounted as an element. The input capacitor pad region 46F is provided in the first portion 41A of the first wiring part 41.

[0102] 11 , the multiple pad regions 46 may include a light-emitting element pad region 46G. The light-emitting element pad region 46G is a region where a light-emitting module 100 is mounted as an element. The light-emitting element pad region 46G is provided in the second portion 44B of the fourth wiring part 44.

[0103] The multiple pad regions 46 may include a capacitor pad region 46H. The capacitor pad region 46H is a region where a capacitor 220 (see FIG. 13 ) of the drive circuit 200 is mounted as an element. The capacitor pad region 46H is provided in the second portion 44B of the fourth wiring section 44. The capacitor pad region 46H is provided closer to the fourth substrate side surface 23D than the light-emitting element pad region 46G. A plurality of capacitor pad regions 46H (12 in the first embodiment) are provided spaced apart in the X direction. Each capacitor pad region 46H is provided at one of both Y-direction ends of the second portion 44B, the end closest to the fourth substrate side surface 23D (see FIG. 9 ).

[0104] As shown in FIG. 10 , the multiple pad regions 46 may include a heat dissipation member pad region 46J. The heat dissipation member pad region 46J is a region where a first heat dissipation member 340 (see FIG. 12 ), which will be described later as an element, is mounted. The heat dissipation member pad region 46J is provided in each of the first to fourth wiring portions 41 to 44. One of the heat dissipation member pad regions 46J is provided adjacent to the resistor pad region 46A provided in the first wiring portion 41 in the Y direction. Another of the heat dissipation member pad regions 46J is provided adjacent to the resistor pad regions 46A and 46B provided in the second wiring portion 42 in the X direction. Yet another of the heat dissipation member pad regions 46J is provided adjacent to the resistor pad regions 46B and 46C provided in the third wiring portion 43 in the X direction. The remaining one of the heat dissipation member pad regions 46J is provided at a position adjacent to the resistor pad region 46C provided in the fourth wiring portion 44 in the X direction.

[0105] 10 and 11 , the second power supply wiring 47 is disposed adjacent to both the second portion 44B and the fifth wiring portion 45 of the fourth wiring portion 44 of the first power supply wiring 40. The second power supply wiring 47 is disposed adjacent to the third substrate side surface 23C. The second power supply wiring 47 is a wiring through which a drive current flows from the light emitting element 150. The second power supply wiring 47 includes a narrow portion 48A and a wide portion 48B.

[0106] The narrow width portion 48A is disposed adjacent to the second portion 44B of the fourth wiring portion 44 in the Y direction and adjacent to the fifth wiring portion 45 in the X direction. The narrow width portion 48A extends in the X direction. The width of the narrow width portion 48A is narrower than the width of the second portion 44B. Here, the width of the narrow width portion 48A is the dimension in the direction (Y direction) perpendicular to the direction in which the narrow width portion 48A extends (X direction) in a planar view. The width of the second portion 44B is the dimension in the direction (Y direction) perpendicular to the direction in which the second portion 44B extends (X direction) in a planar view.

[0107] As shown in FIG. 11 , the wide portion 48B is a portion of the second power supply wiring 47 that is wider than the narrow portion 48A. The wide portion 48B is disposed closer to the first substrate side surface 23A (see FIG. 9 ) than the narrow portion 48A. The wide portion 48B extends in the X direction. The wide portion 48B includes an inclined portion whose width increases along the inclined portion at the tip of the second portion 44B. Here, the width of the wide portion 48B is the dimension in the direction (Y direction) perpendicular to the direction in which the wide portion 48B extends (X direction) in a plan view.

[0108] The narrow width portion 48A includes a protrusion 48C that protrudes toward the fourth substrate side surface 23D (see FIG. 9 ). The second portion 44B of the fourth wiring portion 44 includes a recess 44C that is provided corresponding to the protrusion 48C. A portion of the protrusion 48C is disposed within the recess 44C. The plurality of light-emitting element pad regions 46G provided in the second portion 44B are disposed so as to surround the recess 44C in a plan view. In other words, the plurality of light-emitting element pad regions 46G are disposed so as to surround the protrusion 48C in a plan view.

[0109] The second power supply wiring 47 includes a plurality of (six in the first embodiment) light-emitting element pad regions 49A. The light-emitting element pad regions 49A are regions where the second power supply wiring 47 is exposed through openings in the front-side insulating layer 84. The light-emitting element pad regions 49A are regions where the light-emitting modules 100 are mounted.

[0110] The multiple light emitting element pad regions 49A are spaced apart in the X direction in a plan view. The light emitting element pad regions 49A are provided on the protruding portion 48C of the narrow width portion 48A and its periphery. The light emitting element pad regions 49A are located adjacent to the light emitting element pad region 46G of the first power supply wiring 40 in the Y direction. Therefore, the light emitting element pad region 46G of the first power supply wiring 40 is located on the recessed portion 44C of the second portion 44B and its periphery. In the example shown in FIG. 11 , the Y direction dimension of the four light emitting element pad regions 49A provided on the protruding portion 48C is larger than the Y direction dimension of two light emitting element pad regions 49A provided at positions other than the protruding portion 48C.

[0111] As shown in FIG. 9 , the second power supply wiring 47 includes a heat dissipation member pad region 49B. The heat dissipation member pad region 49B is a region where the second power supply wiring 47 is exposed through an opening in the front-side insulating layer 84. The heat dissipation member pad region 49B is a region where the second heat dissipation member 350 (see FIG. 13 ) is mounted. The heat dissipation member pad region 49B is provided in the wide portion 48B. In other words, the heat dissipation member pad region 49B is provided closer to the first substrate side surface 23A than the light-emitting element pad region 49A. Multiple heat dissipation member pad regions 49B (two in the first embodiment) are provided, spaced apart in the X direction.

[0112] 10 , the second power supply wiring 47 includes a diode pad region 49C. The diode pad region 49C is a region where the second power supply wiring 47 is exposed through an opening in the front-side insulating layer 84. The diode pad region 49C is a region where a protection diode 310 (see FIG. 12 ) is mounted. The diode pad region 49C is provided in the narrow width portion 48A. The diode pad region 49C is provided at one of both ends of the narrow width portion 48A in the X direction that is closer to the fifth wiring portion 45.

[0113] As shown in FIG. 9 , the third power supply wiring 50 is connected to the second through hole 26B of the first power supply through hole 26 and the second through hole 27B of the second power supply through hole 27. The third power supply wiring 50 is electrically connected to the back surface conductive layer 70 (see FIG. 18 ). The third power supply wiring 50 is disposed at a distance from the first power supply wiring 40 and the second power supply wiring 47. The third power supply wiring 50 is disposed adjacent to the first power supply wiring 40 in the X direction and the Y direction. The third power supply wiring 50 is disposed adjacent to the wide portion 48B of the second power supply wiring 47 in the Y direction. The third power supply wiring 50 includes a portion disposed on the opposite side of the first power supply wiring 40 from the second mounting hole 25B. The third power supply wiring 50 is disposed adjacent to all of the four substrate mounting holes 24 except for the substrate mounting hole 24 disposed at the corner defined by the second substrate side surface 23B and the third substrate side surface 23C. The third power supply wiring 50 is provided so as to surround the two first mounting holes 25A near the fourth substrate side surface 23D in plan view.

[0114] The third power supply wiring 50 includes a capacitor pad region 51A, an input capacitor pad region 51B, a heat dissipation member pad region 51C, a transistor pad region 51D, a driver pad region 51E, a pull-down resistor pad region 51F, and a capacitor pad region 51G. These pad regions 51A to 51G are regions where the third power supply wiring 50 is exposed through openings in the front-side insulating layer 84.

[0115] The capacitor pad region 51A is a region where the capacitor 220 of the drive circuit 200 is mounted. The capacitor pad region 51A is provided in a portion of the third power supply wiring 50 adjacent to the second portion 44B of the fourth wiring portion 44 of the first power supply wiring 40 in the Y direction. The capacitor pad region 51A is provided in a position adjacent to the capacitor pad region 46H of the first power supply wiring 40 in the Y direction. A plurality of capacitor pad regions 51A (12 in the first embodiment) are provided spaced apart in the X direction. The capacitor pad region 51A is provided in a position adjacent to the capacitor pad region 46H of the first power supply wiring 40 in the Y direction.

[0116] The input capacitor pad region 51B is a region where the input capacitor 320 is mounted. The input capacitor pad region 51B is provided in a portion of the third power supply wiring 50 adjacent to the first portion 41A of the first wiring part 41 of the first power supply wiring 40 in the Y direction. The input capacitor pad region 51B is provided at a position adjacent to the input capacitor pad region 46F of the first power supply wiring 40 in the Y direction.

[0117] The heat dissipation member pad region 51C is a region where the first heat dissipation member 340 (see FIG. 12) and the second heat dissipation member 350 (see FIG. 13) are mounted. A plurality of heat dissipation member pad regions 51C are provided. The plurality of heat dissipation member pad regions 51C are provided in positions adjacent to the first to fourth wiring portions 41 to 44 of the third power supply wiring 50 and in a position adjacent to the wide portion 48B of the second power supply wiring 47. The heat dissipation member pad region 51C is provided in a position adjacent to the heat dissipation member pad region 46J and in a position adjacent to the heat dissipation member pad region 49B.

[0118] 11 , the transistor pad region 51D is a region where the transistor 210 of the drive circuit 200 is mounted, and more specifically, a region where the source electrode 213 (see FIG. 13 ) of the transistor 210 is bonded. A plurality of transistor pad regions 51D (three in the first embodiment) are provided. The plurality of transistor pad regions 51D are spaced apart in the X direction. The plurality of transistor pad regions 51D and the plurality of drain openings 52 are alternately arranged one by one in the X direction.

[0119] The driver pad region 51E is a region where the gate driver 230 (see FIG. 13) is mounted. A plurality of driver pad regions 51E (two in the first embodiment) are provided. The plurality of driver pad regions 51E are arranged, for example, spaced apart in the Y direction.

[0120] The pull-down resistor pad region 51F is a region where the pull-down resistor 231 (see FIG. 13) is mounted. The pull-down resistor pad region 51F is disposed closer to the first substrate side surface 23A and the fourth substrate side surface 23D (see FIG. 9) than the driver pad region 51E.

[0121] The capacitor pad region 51G is a region where the capacitor 232 (see FIG. 13) is mounted. The capacitor pad region 51G is disposed closer to the second substrate side surface 23B and the fourth substrate side surface 23D (see FIG. 9) than the driver pad region 51E.

[0122] The surface conductive layer 30 includes a drain wiring 55, a first gate wiring 56, a second gate wiring 57, and a third gate wiring 58. The drain wiring 55 is a wiring electrically connected to the drain of the transistor 210 (see FIG. 13 ). The drain wiring 55 is provided in a position adjacent to the capacitor pad region 51A of the third power supply wiring 50 in the Y direction. A plurality of drain wirings 55 (three in the first embodiment) are provided spaced apart from each other in the X direction. Each drain wiring 55 has a strip shape extending in the Y direction in a plan view. The plurality of drain wirings 55 are provided in a plurality of drain openings 52 provided in the third power supply wiring 50. Therefore, each drain wiring 55 is spaced apart from the third power supply wiring 50. Each drain wiring 55 includes a transistor pad region 55A. The transistor pad region 55A is a region of each drain wiring 55 on which the transistor 210 is mounted, and more specifically, a region to which the drain electrode 214 (see FIG. 13) of the transistor 210 is bonded.

[0123] The first gate wiring 56 is a wiring that electrically connects the gate of the transistor 210 and the gate driver 230 (see FIG. 13 ). The first gate wiring 56 is provided within a first gate slit 53A provided in the third power supply wiring 50. Therefore, the first gate wiring 56 is separated from the third power supply wiring 50. The first gate slit 53A communicates with one of the multiple drain openings 52 that is closer to the first substrate side surface 23A.

[0124] The first gate wiring 56 includes a transistor pad region 56 A and a driver pad region 56 B. The transistor pad region 56 A and the driver pad region 56 B are regions where the first gate wiring 56 is exposed through an opening in the front-side insulating layer 84 .

[0125] The transistor pad region 56A is a region where the transistor 210 is mounted, and more specifically, a region where the gate electrode 215 (see FIG. 13 ) of the transistor 210 is bonded. The transistor pad region 56A is provided at the end of the first gate wiring 56 that is closer to the transistor 210. The transistor pad region 56A is located adjacent in the X direction to the driver pad region 51E of the third power supply wiring 50 that is closer to the third substrate side surface 23C.

[0126] The driver pad region 56B is a region where the gate driver 230 is mounted. A plurality of driver pad regions 56B (two in the first embodiment) are provided. The plurality of driver pad regions 56B are provided at the end of the first gate wiring 56 that is closer to the gate driver 230. The plurality of driver pad regions 56B are arranged at intervals in the X direction.

[0127] The second gate wiring 57 is a wiring that electrically connects the gate driver 230 and the signal through-hole 28. The second gate wiring 57 is arranged closer to the fourth substrate side surface 23D than the first gate wiring 56. The second gate wiring 57 extends toward the fourth substrate side surface 23D. The second gate wiring 57 is provided within the second gate slit 53B provided in the third power supply wiring 50. Therefore, the second gate wiring 57 is separated from the third power supply wiring 50.

[0128] The second gate wiring 57 includes a driver pad region 57 A and a pull-down resistor pad region 57 B. The driver pad region 57 A and the pull-down resistor pad region 57 B are regions where the second gate wiring 57 is exposed through the opening of the front-side insulating layer 84.

[0129] The driver pad region 57A is a region where the gate driver 230 is mounted. The driver pad region 57A is provided at the end of the second gate wiring 57 that is closer to the gate driver 230. The driver pad region 57A is located adjacent to the driver pad region 51E of the third power supply wiring 50 that is closer to the fourth substrate side surface 23D, and closer to the first substrate side surface 23A in the X direction.

[0130] The pull-down resistor pad region 57B is a region where the pull-down resistor 231 is mounted. The pull-down resistor pad region 57B is disposed closer to the fourth substrate side surface 23D than the driver pad region 57A.

[0131] The third gate wiring 58 is electrically connected to the gate driver 230. The third gate wiring 58 is provided within a third gate slit 53C provided in the third power supply wiring 50. Therefore, the third gate wiring 58 is separated from the third power supply wiring 50.

[0132] The third gate wiring 58 includes a driver pad region 58 A and a capacitor pad region 58 B. The driver pad region 58 A and the capacitor pad region 58 B are regions where the third gate wiring 58 is exposed through the opening of the front-side insulating layer 84 .

[0133] The driver pad region 58A is a region where the gate driver 230 is mounted. The driver pad region 58A is provided at the end of the third gate wiring 58 that is closer to the gate driver 230. The driver pad region 58A is located adjacent to the driver pad region 51E of the third power supply wiring 50 that is closer to the fourth substrate side surface 23D, and closer to the second substrate side surface 23B in the X direction.

[0134] The capacitor pad region 58B is a region where the capacitor 232 is mounted. The capacitor pad region 58B is disposed closer to the fourth substrate side surface 23D than the driver pad region 58A.

[0135] As shown in FIG. 12 , a plurality of current limiting resistors 300 are mounted on the first power supply wiring 40. Each current limiting resistor 300 includes a first terminal 301 and a second terminal 302. One current limiting resistor 300 is arranged to straddle the first wiring portion 41 and the second wiring portion 42 of the first power supply wiring 40 in the Y direction. One current limiting resistor 300 is mounted on a resistor pad area 46A. In one example, the first terminal 301 of the current limiting resistor 300 is mounted on the resistor pad area 46A of the first wiring portion 41, and the second terminal 302 is mounted on the resistor pad area 46A of the second wiring portion 42. As a result, the first terminal 301 of the current limiting resistor 300 is electrically connected to the first wiring portion 41, and the second terminal 302 is electrically connected to the second wiring portion 42.

[0136] Another current limiting resistor 300 is arranged to straddle the second wiring portion 42 and the third wiring portion 43 in the Y direction. The other current limiting resistor 300 is mounted on the resistor pad region 46B. In one example, a first terminal 301 of the current limiting resistor 300 is mounted on the resistor pad region 46B of the second wiring portion 42, and a second terminal 302 is mounted on the resistor pad region 46B of the third wiring portion 43. As a result, the first terminal 301 of the current limiting resistor 300 is electrically connected to the second wiring portion 42, and the second terminal 302 is electrically connected to the third wiring portion 43.

[0137] The remaining current limiting resistor 300 is disposed so as to straddle the third wiring portion 43 and the fourth wiring portion 44 in the Y direction. The remaining current limiting resistor 300 is mounted on the resistor pad region 46C. In one example, the first terminal 301 of the current limiting resistor 300 is mounted on the resistor pad region 46C of the third wiring portion 43, and the second terminal 302 is mounted on the resistor pad region 46C of the fourth wiring portion 44. As a result, the first terminal 301 of the current limiting resistor 300 is electrically connected to the third wiring portion 43, and the second terminal 302 is electrically connected to the fourth wiring portion 44. In this way, a plurality of current limiting resistors 300 are provided corresponding to the plurality of resistor pad regions 46A to 46C. The plurality of current limiting resistors 300 are connected in series.

[0138] An auxiliary resistor 313 is mounted on the first power supply wiring 40. The auxiliary resistor 313 is arranged to straddle the first portion 44A of the fourth wiring portion 44 and the fifth wiring portion 45 in the Y direction. The auxiliary resistor 313 is mounted on an auxiliary resistor pad region 46E. The auxiliary resistor 313 includes a first terminal 314 and a second terminal 315. The first terminal 314 is mounted on the auxiliary resistor pad region 46E of the fourth wiring portion 44, and the second terminal 315 is mounted on the auxiliary resistor pad region 46E of the fifth wiring portion 45. As a result, the first terminal 314 is electrically connected to the fourth wiring portion 44, and the second terminal 315 is electrically connected to the fifth wiring portion 45.

[0139] A protection diode 310 is mounted on the first power supply wiring 40 and the second power supply wiring 47. The protection diode 310 is arranged to straddle the fifth wiring portion 45 of the first power supply wiring 40 and the narrow portion 48A of the second power supply wiring 47 in the X direction. The protection diode 310 is mounted on the diode pad regions 46D and 49C. In one example, the cathode electrode 312 of the protection diode 310 is mounted on the diode pad region 46D, and the anode electrode 311 of the protection diode 310 is mounted on the diode pad region 49C. As a result, the cathode electrode 312 is electrically connected to the first power supply wiring 40, and the anode electrode 311 is electrically connected to the second power supply wiring 47.

[0140] An input capacitor 320, a first heat dissipation member 340, and a second heat dissipation member 350 (see FIG. 13 ) are mounted on the first power supply wiring 40 and the third power supply wiring 50. The input capacitor 320 is disposed so as to straddle the first portion 41A of the first wiring section 41 and the third power supply wiring 50 in the Y direction. The input capacitor 320 is mounted on the input capacitor pad areas 46F and 51B. In one example, a first electrode of the input capacitor 320 is mounted on the input capacitor pad area 46F, and a second electrode of the input capacitor 320 is mounted on the input capacitor pad area 51B. As a result, the first electrode of the input capacitor 320 is electrically connected to the first power supply wiring 40, and the second electrode of the input capacitor 320 is electrically connected to the third power supply wiring 50.

[0141] The first heat dissipation member 340 is individually mounted on the first to fourth wiring portions 41 to 44. In one example, the first heat dissipation member 340 is configured to have a thermal conductivity of 100 W / m / K or higher. The first heat dissipation member 340 includes a first terminal 341, a second terminal 342, and a heat dissipation body 343. The first terminal 341 and the second terminal 342 are made of, for example, a metal material. The heat dissipation body 343 is made of, for example, an insulating material. Therefore, the first terminal 341 and the second terminal 342 are electrically insulated by the heat dissipation body 343. The metal material may be at least one of Cu, Al, Au, Ag, and Ni. The insulating material may be at least one of AlN and beryllium oxide (BeO).

[0142] The first heat dissipation member 340 is mounted on the heat dissipation member pad areas 46J and 51C. In one example, the first terminal 341 is mounted on the heat dissipation member pad area 46J, and the second terminal 342 is mounted on the heat dissipation member pad area 51C. Therefore, the first heat dissipation member 340 is connected to the first power supply wiring 40 and the third power supply wiring 50. Meanwhile, the first terminal 341 and the second terminal 342 are insulated by the heat dissipation body 343, and therefore the first power supply wiring 40 and the third power supply wiring 50 are physically and thermally connected by the first heat dissipation member 340 but electrically insulated.

[0143] The first heat dissipation member 340 is disposed adjacent to the plurality of pad regions 46 in a plan view. More specifically, the first heat dissipation member 340 is disposed adjacent to the resistor pad regions 46A to 46C in a plan view.

[0144] The first heat dissipation member 340 mounted on the first wiring portion 41 and the third power supply wiring 50 is disposed adjacent to the resistor pad region 46A in the Y direction. The first heat dissipation member 340 is disposed at a position adjacent to the current limiting resistor 300 mounted in the resistor pad region 46A in the Y direction. The first heat dissipation member 340 is disposed in an orientation such that the first terminal 341 and the second terminal 342 are arranged at a distance in the Y direction.

[0145] The first heat dissipation member 340 mounted on the second wiring portion 42 and the third power supply wiring 50 is disposed adjacent to both the resistor pad region 46A and the resistor pad region 46B. The first heat dissipation member 340 is disposed adjacent to both the current limiting resistor 300 mounted in the resistor pad region 46A and the current limiting resistor 300 mounted in the resistor pad region 46B. When viewed from the X direction, the first heat dissipation member 340 includes portions overlapping with both the current limiting resistor 300 mounted in the resistor pad region 46A and the current limiting resistor 300 mounted in the resistor pad region 46B. In other words, the first heat dissipation member 340 is disposed adjacent to both the current limiting resistor 300 mounted in the resistor pad region 46A and the current limiting resistor 300 mounted in the resistor pad region 46B in the X direction. The first heat dissipation member 340 is disposed in such a position that the first terminal 341 and the second terminal 342 are arranged apart from each other in the X direction.

[0146] The first heat dissipation member 340 mounted on the third wiring portion 43 and the third power supply wiring 50 is disposed adjacent to both the resistor pad region 46B and the resistor pad region 46C. The first heat dissipation member 340 is disposed adjacent to both the current limiting resistor 300 mounted in the resistor pad region 46B and the current limiting resistor 300 mounted in the resistor pad region 46C. When viewed from the X direction, the first heat dissipation member 340 includes portions overlapping with both the current limiting resistor 300 mounted in the resistor pad region 46B and the current limiting resistor 300 mounted in the resistor pad region 46C. In other words, the first heat dissipation member 340 is disposed adjacent to both the current limiting resistor 300 mounted in the resistor pad region 46B and the current limiting resistor 300 mounted in the resistor pad region 46C in the X direction. The first heat dissipation member 340 is disposed in such a position that the first terminal 341 and the second terminal 342 are arranged apart from each other in the X direction.

[0147] The first heat dissipation member 340 mounted on the fourth wiring portion 44 and the third power supply wiring 50 is disposed adjacent to the resistor pad region 46C in the X direction. The first heat dissipation member 340 is disposed in a position adjacent to the current limiting resistor 300 mounted in the resistor pad region 46C in the X direction. The first heat dissipation member 340 is mounted on the first portion 44A of the fourth wiring portion 44, and is disposed closer to the fourth substrate side surface 23D than the second portion 44B. The first heat dissipation member 340 is disposed in an orientation in which the first terminal 341 and the second terminal 342 are arranged and spaced apart in the X direction.

[0148] As described above, the first heat dissipation member 340 is disposed adjacent to the resistor pad regions 46A to 46C, and is disposed in a position different from the resistor pad regions 46A to 46C in a plan view. For this reason, it can be said that the pad heat dissipation vias 90, which are provided in positions overlapping with the resistor pad regions 46A to 46C in a plan view, are disposed in a position different from the first heat dissipation member 340 in a plan view.

[0149] As shown in FIG. 13 , the second heat dissipation member 350 is disposed so as to straddle the second power wiring 47 and the third power wiring 50 in the Y direction. More specifically, the second heat dissipation member 350 is disposed so as to straddle the wide portion 48B of the second power wiring 47 and the third power wiring 50 adjacent to the wide portion 48B in the Y direction. The second heat dissipation member 350 is disposed adjacent to the light-emitting module 100 (light-emitting element 150). The second heat dissipation member 350 is disposed closer to the first substrate side surface 23A (see FIG. 9 ) than the light-emitting module 100. The second heat dissipation member 350 can also be said to be disposed adjacent to the capacitor 220 of the drive circuit 200. The second heat dissipation member 350 is disposed closer to the first substrate side surface 23A than the capacitor 220. In one example, the second heat dissipation member 350 is configured to have a thermal conductivity of 100 W / m / K or higher.

[0150] The second heat dissipation member 350 includes a first terminal 351, a second terminal 352, and a heat dissipation body 353. The configuration and size of the second heat dissipation member 350 are the same as those of the first heat dissipation member 340. The second heat dissipation member 350 is mounted on the heat dissipation member pad areas 49B and 51C. In one example, the first terminal 351 is mounted on the heat dissipation member pad area 49B, and the second terminal 352 is mounted on the heat dissipation member pad area 51C. Therefore, the second heat dissipation member 350 is connected to the second power supply wiring 47 and the third power supply wiring 50. Meanwhile, because the first terminal 351 and the second terminal 352 are insulated by the heat dissipation body 353, the second power supply wiring 47 and the third power supply wiring 50 are physically and thermally connected by the second heat dissipation member 350 but are electrically insulated.

[0151] As shown in FIG. 13 , a light-emitting module 100 is mounted on the first power supply wiring 40 and the second power supply wiring 47. The light-emitting module 100 is disposed so as to straddle in the Y direction between the second portion 44B of the fourth wiring portion 44 of the first power supply wiring 40 and the narrow portion 48A of the second power supply wiring 47. The first back surface conductive layer 131 (see FIG. 5 ) of the light-emitting module 100 is mounted on the light-emitting element pad region 46G (see FIG. 11 ) of the first power supply wiring 40, and the second back surface conductive layer 132 (see FIG. 5 ) is mounted on the light-emitting element pad region 49A (see FIG. 11 ) of the second power supply wiring 47. As a result, the first back surface conductive layer 131 is electrically connected to the first power supply wiring 40, and the second back surface conductive layer 132 is electrically connected to the second power supply wiring 47. In other words, the anode of the light-emitting element 150 is electrically connected to the first power supply wiring 40, and the cathode of the light-emitting element 150 is electrically connected to the second power supply wiring 47. In this manner, the light emitting element 150 is electrically connected to the surface conductive layer 30 .

[0152] A plurality of capacitors 220 of the drive circuit 200 are mounted on the first power supply wiring 40 and the third power supply wiring 50. Each capacitor 220 is arranged to straddle the second portion 44B of the fourth wiring section 44 of the first power supply wiring 40 and the third power supply wiring 50 adjacent to the second portion 44B in the Y direction. A first electrode 221 of each capacitor 220 is mounted on the capacitor pad region 46H of the first power supply wiring 40, and a second electrode 222 of each capacitor 220 is mounted on the capacitor pad region 51A of the third power supply wiring 50.

[0153] A transistor 210 of the drive circuit 200 is mounted on the third power supply wiring 50, the drain wiring 55, and the first gate wiring 56. A source electrode 213 of the transistor 210 is mounted on the third power supply wiring 50, a drain electrode 214 is mounted on the drain wiring 55, and a gate electrode 215 is mounted on the first gate wiring 56. As a result, the source electrode 213 is electrically connected to the third power supply wiring 50, the drain electrode 214 is electrically connected to the drain wiring 55, and the gate electrode 215 is electrically connected to the first gate wiring 56.

[0154] A gate driver 230 is mounted on the third power supply wiring 50, the first gate wiring 56, the second gate wiring 57, and the third gate wiring 58. The gate driver 230 is electrically connected to the third power supply wiring 50, the first gate wiring 56, the second gate wiring 57, and the third gate wiring 58. The gate driver 230 is electrically connected to the gate electrode 215 of the transistor 210 through the first gate wiring 56. The gate driver 230 is electrically connected to the signal input connector 333 (see FIG. 1) through the second gate wiring 57. The gate driver 230 is configured to control the transistor 210. Specifically, the gate driver 230 generates a gate drive signal from a control signal input through the signal input connector 333. The gate driver 230 then supplies the gate drive signal to the gate electrode 215 of the transistor 210 through the first gate wiring 56.

[0155] A pull-down resistor 231 is mounted on the third power supply wiring 50 and the second gate wiring 57. A first terminal of the pull-down resistor 231 is mounted on the second gate wiring 57, and a second terminal of the pull-down resistor 231 is mounted on the third power supply wiring 50.

[0156] A capacitor 232 is mounted on the third power supply wiring 50 and the third gate wiring 58. A first electrode of the capacitor 232 is mounted on the third gate wiring 58, and a second electrode of the capacitor 232 is mounted on the third power supply wiring 50.

[0157] 14, the intermediate conductive layer 60A is provided over most of the intermediate substrate insulating layer 83A in plan view. The intermediate conductive layer 60A is provided so as to overlap most of the surface conductive layer 30 (see FIG. 9) in plan view. In plan view, the area of ​​the intermediate conductive layer 60A is larger than the area of ​​the surface conductive layer 30.

[0158] The intermediate conductive layer 60A includes an intermediate wiring 61A and a ground wiring 62A. The intermediate wiring 61A and the ground wiring 62A are arranged spaced apart from each other. The intermediate wiring 61A is provided at a position overlapping both the light-emitting module 100 and the drive circuit 200 (see FIG. 13 for both) in a planar view. The intermediate wiring 61A is arranged at a position overlapping both the second portion 44B of the fourth wiring portion 44 of the first power supply wiring 40 and the narrow portion 48A of the second power supply wiring 47 (see FIG. 13 for both) in a planar view. The intermediate wiring 61A is arranged at a position separated from the gate driver 230 (see FIG. 13) in a planar view. The intermediate wiring 61A has a rectangular shape with its long sides extending in the Y direction and its short sides extending in the X direction in a planar view.

[0159] The ground wiring 62A is provided so as to surround the intermediate wiring 61A in a plan view. More specifically, the ground wiring 62A includes a recess 62AA that opens to the third substrate side surface 23C in a plan view. The recess 62AA has a rectangular recessed shape in a plan view. The intermediate wiring 61A is disposed within the recess 62AA in a plan view.

[0160] The ground wiring 62A includes a first opening 62AB for isolating it from the first through hole 26A of the first power supply through hole 26, a second opening 62AC for isolating it from the signal through hole 28, and a wiring opening 62AD extending from the gate driver 230 toward the first through hole 27A of the second power supply through hole 27. The ground wiring 62A is separated from the first through hole 27A of the second power supply through hole 27 by the wiring opening 62AD. Therefore, the ground wiring 62A is insulated from the first through hole 26A of the first power supply through hole 26, the first through hole 27A of the second power supply through hole 27, and the signal through hole 28. Meanwhile, the ground wiring 62A is electrically connected to both the second through hole 26B of the first power supply through hole 26 and the second through hole 27B of the second power supply through hole 27.

[0161] The intermediate conductive layer 60A includes a control power supply wiring 63A disposed in the wiring opening 62AD. The control power supply wiring 63A is a wiring that electrically connects the gate driver 230 and the first through-hole 27A of the second power supply through-hole 27. The control power supply wiring 63A is spaced apart from the ground wiring 62A. Therefore, the control power supply wiring 63A is insulated from the ground wiring 62A. The control power supply wiring 63A is provided spaced apart from the intermediate wiring 61A.

[0162] 15 to 17, the intermediate conductive layers 60B to 60D have substantially the same configuration as the intermediate conductive layer 60A, but the intermediate conductive layers 60B to 60D do not have the control power supply wiring 63A and the wiring opening 62AD.

[0163] As shown in FIG. 15 , the intermediate conductive layer 60B includes an intermediate wiring 61B and a ground wiring 62B. The ground wiring 62B includes a recess 62BA, a first opening 62BB, a second opening 62BC, and a third opening 62BD. The intermediate wiring 61B is disposed within the recess 62BA in a plan view. The intermediate wiring 61B is disposed at a position overlapping the intermediate wiring 61A (see FIG. 14 ) in a plan view. The dimensions of the intermediate wiring 61B in the X and Y directions are equal to the dimensions of the intermediate wiring 61A in the X and Y directions. The ground wiring 62B is separated from the first through hole 26A of the first power supply through hole 26 by the first opening 62BB, from the signal through hole 28 by the second opening 62BC, and from the first through hole 27A of the second power supply through hole 27 by the third opening 62BD. Therefore, the ground wiring 62B is insulated from the first through hole 26A of the first power supply through hole 26, the first through hole 27A of the second power supply through hole 27, and the signal through hole 28. On the other hand, the ground wiring 62B is electrically connected to both the second through hole 26B of the first power supply through hole 26 and the second through hole 27B of the second power supply through hole 27.

[0164] As shown in FIG. 16 , the intermediate conductive layer 60C includes an intermediate wiring 61C and a ground wiring 62C. The ground wiring 62C includes a recess 62CA, a first opening 62CB, a second opening 62CC, and a third opening 62CD. The intermediate wiring 61C is disposed within the recess 62CA in a plan view. The intermediate wiring 61C is disposed at a position overlapping the intermediate wiring 61B (see FIG. 15 ) in a plan view. The dimensions of the intermediate wiring 61C in the X and Y directions are equal to the dimensions of the intermediate wiring 61B in the X and Y directions. The ground wiring 62C is separated from the first through hole 26A of the first power supply through hole 26 by the first opening 62CB, separated from the signal through hole 28 by the second opening 62CC, and separated from the first through hole 27A of the second power supply through hole 27 by the third opening 62CD. Therefore, the ground wiring 62C is insulated from the first through hole 26A of the first power supply through hole 26, the first through hole 27A of the second power supply through hole 27, and the signal through hole 28. On the other hand, the ground wiring 62C is electrically connected to both the second through hole 26B of the first power supply through hole 26 and the second through hole 27B of the second power supply through hole 27.

[0165] As shown in FIG. 17 , the intermediate conductive layer 60D includes an intermediate wiring 61D and a ground wiring 62D. The ground wiring 62D includes a recess 62DA, a first opening 62DB, a second opening 62DC, and a third opening 62DD. The intermediate wiring 61D is disposed within the recess 62DA in a plan view. The intermediate wiring 61D is disposed at a position overlapping the intermediate wiring 61C (see FIG. 16 ) in a plan view. The dimensions of the intermediate wiring 61D in the X and Y directions are equal to the dimensions of the intermediate wiring 61C in the X and Y directions. The ground wiring 62D is separated from the first through hole 26A of the first power supply through hole 26 by the first opening 62DB, from the signal through hole 28 by the second opening 62DC, and from the first through hole 27A of the second power supply through hole 27 by the third opening 62DD. For this reason, the ground wiring 62D is insulated from the first through hole 26A of the first power supply through hole 26, the first through hole 27A of the second power supply through hole 27, and the signal through hole 28. On the other hand, the ground wiring 62D is electrically connected to both the second through hole 26B of the first power supply through hole 26 and the second through hole 27B of the second power supply through hole 27. Here, the intermediate wiring 61D is an example of a back-side intermediate wiring that contacts the surface of the back-side substrate insulating layer 82 opposite to the surface on which the back-side conductive layer 70 is provided.

[0166] The intermediate wiring 61D is provided at a position overlapping the back surface conductive layer 70 in a plan view. In one example, the intermediate wiring 61D is provided so that the entire intermediate wiring 61D overlaps the back surface conductive layer 70 in a plan view. In a plan view, the area of ​​the intermediate wiring 61D is 1 / 2 times the output capacitance C ＯＳＳ In the first embodiment, the area of ​​the intermediate wiring 61D in a plan view is set so that the parasitic capacitance between the intermediate wiring 61D and the back surface conductive layer 70 is 70 pF or less.

[0167] 18 , the back surface conductive layer 70 is provided over most of the back surface 22 of the substrate in a plan view. The back surface conductive layer 70 is provided so as to overlap most of the intermediate conductive layer 60D in a plan view. In a plan view, the area of ​​the back surface conductive layer 70 is larger than the area of ​​the intermediate conductive layer 60D. Here, in FIG. 18 , for convenience, the back surface conductive layer 70 covered with the back surface-side insulating layer 85 is shown by a solid line.

[0168] The back surface conductive layer 70 includes corner notches 71 provided to avoid each board mounting hole 24, a first opening 72 for isolating the first through hole 26A of the first power supply through hole 26, a second opening 73 for isolating the signal through hole 28, and a third opening 74 for isolating the first through hole 27A of the second power supply through hole 27. Therefore, the back surface conductive layer 70 is insulated from the first through hole 26A of the first power supply through hole 26, the first through hole 27A of the second power supply through hole 27, and the signal through hole 28. On the other hand, the back surface conductive layer 70 is electrically connected to both the second through hole 26B of the first power supply through hole 26 and the second through hole 27B of the second power supply through hole 27.

[0169] An electrode opening 85A is provided in the back-side insulating layer 85. The electrode opening 85A exposes the back-side conductive layer 70. More specifically, the electrode opening 85A is provided in a portion of the back-side insulating layer 85 closer to the third substrate side surface 23C. That is, the electrode opening 85A exposes a portion of the back-side conductive layer 70 closer to the third substrate side surface 23C. The electrode opening 85A is provided to overlap the light-emitting module 100, drive circuit 200, and gate driver 230 shown in FIG. 13 in a plan view. The electrode opening 85A is provided to overlap a portion of the current-limiting resistors 300, the protection diode 310, the auxiliary resistor 313, a portion of the first heat dissipation members 340 shown in FIG. 12, and the second heat dissipation members 350 shown in FIG. 13. The electrode opening 85A is also provided to overlap the heat sink mounting hole 25 in a plan view. The electrode opening 85A has a rectangular shape with its long sides extending in the X direction and its short sides extending in the Y direction in plan view.

[0170] 11 and 14 , the multilayer substrate 20 includes a plurality of first element connection vias 86, a plurality of second element connection vias 87, and a third element connection via 88. Each of the first element connection vias 86, the second element connection vias 87, and the third element connection vias 88 may be made of one or more materials selected from the group including, for example, Cu, Al, Ti, TiN, Au, Ag, and W. In one example, each of the first element connection vias 86, the second element connection vias 87, and the third element connection vias 88 is made of a material including Cu. Furthermore, each of the first element connection vias 86, the second element connection vias 87, and the third element connection vias 88 may be made of a conductive material filled in a hole formed by, for example, laser processing.

[0171] The multiple first element connection vias 86 are provided in a region overlapping both the light-emitting module 100 and the intermediate wiring 61A in a planar view. The multiple first element connection vias 86 are provided in a position overlapping the second power supply wiring 47 in a planar view. Each first element connection via 86 connects the second power supply wiring 47 of the surface conductive layer 30 to the intermediate conductive layer 60A. More specifically, each first element connection via 86 electrically connects the second power supply wiring 47 to the intermediate wiring 61A. Therefore, the intermediate wiring 61A is electrically connected to the second power supply wiring 47 by the multiple first element connection vias 86. The multiple first element connection vias 86 are arranged in a matrix. In one example, the multiple first element connection vias 86 are arranged between the multiple light-emitting element pad regions 49A in the X direction in a planar view. The arrangement positions of the multiple first element connection vias 86 can be changed as desired. In one example, the multiple first element connecting vias 86 may be arranged at positions that overlap with at least one of the multiple light emitting element pad regions 49A in a plan view.

[0172] A plurality of second element connection vias 87 are provided in a plurality of drain wirings 55. More specifically, a second element connection via 87 is provided at both ends of each drain wiring 55 in the Y direction. Each second element connection via 87 electrically connects the drain wiring 55 to the intermediate wiring 61A. Each second element connection via 87 is electrically connected to the transistor 210 through the drain wiring 55. In other words, each second element connection via 87 electrically connects the intermediate wiring 61A to the transistor 210. The drain electrode 214 of the transistor 210 is electrically connected to the intermediate wiring 61A through each drain wiring 55 and each second element connection via 87.

[0173] In this way, in the light-emitting device 10, a loop-shaped path is formed through which a driving current flows in the following order: the first electrode 221 of the capacitor 220 of the driving circuit 200, the first power supply wiring 40, the first back surface conductive layer 131 (see FIG. 5 ) of the light-emitting module 100, the light-emitting element 150, the second back surface conductive layer 132 (see FIG. 5 ), the second power supply wiring 47, the first element connecting via 86, the intermediate wiring 61A, the second element connecting via 87, the drain wiring 55, the drain electrode 214 of the transistor 210, the source electrode 213, the third power supply wiring 50, and the second electrode 222 of the capacitor 220. Here, the driving current is a current that drives the light-emitting element 150.

[0174] The third element connecting via 88 is provided at a position overlapping both the third gate wiring 58 and the control power supply wiring 63A in plan view. The third element connecting via 88 electrically connects the third gate wiring 58 and the control power supply wiring 63A. In this way, an operating current is supplied to the gate driver 230 through the first through hole 27A of the second power supply through hole 27, the control power supply wiring 63A, the third element connecting via 88, and the third gate wiring 58.

[0175] [Circuit Configuration of Light-Emitting Device and Light-Emitting System] The circuit configuration of the light-emitting device 10 will be described with reference to Fig. 19. Fig. 19 shows a schematic circuit configuration of a light-emitting system 800 including the light-emitting device 10.

[0176] 19 , a light-emitting system 800 includes a light-emitting device 10, a DC power supply 801, a control power supply 802, and a pulse generator 803. The DC power supply 801, the input capacitor 320, and the current-limiting resistor 300 are configured to supply current to the light-emitting module 100 and the drive circuit 200. A first terminal 301 of the current-limiting resistor 300 closest to the DC power supply 801 among the multiple current-limiting resistors 300 is electrically connected to the positive electrode of the DC power supply 801 and the first electrode of the input capacitor 320. A second terminal 302 of the current-limiting resistor 300 closest to the light-emitting module 100 among the multiple current-limiting resistors 300 is electrically connected to the first back surface conductive layer 131 (anode electrode, see FIG. 5 ) of the light-emitting module 100 and the first electrode 221 of the capacitor 220 of the drive circuit 200.

[0177] The gate driver 230 is electrically connected to the gate electrode 215 of the transistor 210. The pulse generator 803, the control power supply 802, and the capacitor 232 are each electrically connected to the gate driver 230. The pulse generator 803 is electrically connected to the signal input connector 333 (see FIG. 1). The pulse generator 803 is configured to output a pulse signal to the gate driver 230 for controlling the transistor 210. The control power supply 802 is electrically connected to the second power supply connector 332 (see FIG. 1). The control power supply 802 is configured to supply an operating current to the gate driver 230 through the second power supply connector 332. The capacitor 232 is connected in parallel with the control power supply 802. The capacitor 232 is configured to reduce noise from the control power supply 802.

[0178] The negative electrode of the DC power supply 801, the second electrode of the input capacitor 320, the pulse generator 803, the second electrode 222 of the capacitor 220, the negative electrode of the control power supply 802, and the source electrode 213 of the transistor 210 are each electrically connected to the back surface conductive layer 70 (see Figure 18).

[0179] The drain electrode 214 of the transistor 210 is electrically connected to the second back surface conductive layer 132 (see FIG. 5 ) of the light-emitting module 100 and the anode electrode 311 of the protection diode 310. The cathode electrode 312 of the protection diode 310 is electrically connected to the auxiliary resistor 313. The auxiliary resistor 313 is electrically connected to the first back surface conductive layer 131 of the light-emitting module 100.

[0180] In the light-emitting device 10 configured as described above, when the transistor 210 of the drive circuit 200 is in an off state, the capacitor 220 is charged by the DC power supply 801. Then, when the transistor 210 switches from an off state to an on state, a drive current flows from the capacitor 220 to the light-emitting module 100. The drive current flows from the light-emitting element 150 to the second power supply wiring 47. When the transistor 210 is repeatedly turned on and off by a pulsed control signal supplied from the pulse generator 803, pulsed laser light is emitted from the light-emitting module 100. In this manner, the drive circuit 200 is configured to drive the light-emitting module 100.

[0181] [Heat Dissipation Structure] The heat dissipation structure of the light-emitting device 10 will be described with reference to FIGS. 9, 12, and 20 to 32. FIG. 20 shows a schematic planar structure in which a portion of the intermediate conductive layer 60A is enlarged. FIG. 21 shows a schematic planar structure in which the first power supply wiring 40 and its periphery are enlarged. Note that the current limiting resistor 300, the protection diode 310, and the auxiliary resistor 313 are omitted from FIG. 21. FIG. 22 shows a schematic cross-sectional structure of the multilayer substrate 20 taken along line F22-F22 in FIG. 21. FIG. 23 shows a schematic cross-sectional structure of the multilayer substrate 20 taken along line F23-F23 in FIG. 21. FIG. 24 shows a schematic cross-sectional structure of the multilayer substrate 20 taken along line F24-F24 in FIG. 21. FIG. 25 shows a schematic planar structure in which the light-emitting element pad region 46G and its periphery in FIG. 3 are enlarged. FIG. 26 shows a schematic planar structure in which the intermediate wiring 61A and its periphery are enlarged. Fig. 27 shows a schematic cross-sectional structure of the multilayer substrate 20 taken along line F27-F27 in Fig. 25. Fig. 28 shows a schematic planar structure of the drain wiring 55 and its surroundings in Fig. 3, enlarged. Fig. 29 shows a schematic cross-sectional structure of the multilayer substrate 20 taken along line F29-F29 in Fig. 28. Fig. 30 shows a schematic side structure of the light-emitting device 10 as viewed from the third substrate side surface 23C side. Figs. 31 and 32 show schematic cross-sectional structures of the multilayer substrate 20 and the heat sink 400.

[0182] (Through Vias) As shown in FIG. 9 , the multilayer substrate 20 includes a plurality of through vias 89. Each through via 89 penetrates the multilayer substrate 20 in the Z direction. The plurality of through vias 89 electrically connect the third power supply wiring 50 of the front surface conductive layer 30, the ground wirings 62A-62D of the intermediate conductive layers 60A-60D (see FIGS. 14-17), and the back surface conductive layer 70 (see FIG. 18). The plurality of through vias 89 are not provided in the first power supply wiring 40 or the second power supply wiring 47. The plurality of through vias 89 are not provided in the intermediate wirings 61A-61D (see FIGS. 14-17). Each through via 89 is cylindrical. The through vias 89 are provided at positions different from the control power supply wiring 63A (see FIG. 14) in a plan view. The plurality of through vias 89 are arranged, for example, in a matrix. The through vias 89 are provided, for example, on the side surfaces of through holes that penetrate the multilayer substrate 20 in the Z direction. The through via 89 has a cylindrical shape. In one example, the through via 89 has a cylindrical shape. The through via 89 may be made of one or more materials selected from the group including, for example, Cu, Al, Ti, TiN, Au, Ag, and W. In one example, the through via 89 is made of a material including Cu.

[0183] (Pad Heat Dissipation Vias and Inter-Pad Heat Dissipation Vias) As shown in FIG. 20 , the multilayer substrate 20 includes a plurality of pad heat dissipation vias 90. Each pad heat dissipation via 90 is provided within the multilayer substrate 20. Each pad heat dissipation via 90 is connected to the intermediate conductive layer 60A. More specifically, each pad heat dissipation via 90 is connected to the ground wiring 62A of the intermediate conductive layer 60A. The pad heat dissipation via 90 may be made of one or more materials selected from the group including, for example, Cu, Al, Ti, TiN, Au, Ag, and W. In one example, the pad heat dissipation via 90 is made of a material including Cu.

[0184] 21 , the plurality of pad heat dissipation vias 90 are provided at positions overlapping both the pad region 46 and the back surface conductive layer 70 (see FIG. 18 ) in a plan view. More specifically, the plurality of pad heat dissipation vias 90 are provided at positions overlapping both the resistor pad regions 46A to 46C and the back surface conductive layer 70 in a plan view. In one example, a plurality of pad heat dissipation vias 90 are provided corresponding to the plurality of resistor pad regions 46A to 46C. The plurality of pad heat dissipation vias 90 are provided at positions overlapping both the diode pad region 46D and the back surface conductive layer 70 in a plan view. The plurality of pad heat dissipation vias 90 are provided at positions overlapping both the auxiliary resistor pad region 46E and the back surface conductive layer 70 in a plan view. Hereinafter, among the multiple pad heat dissipation vias 90, the heat dissipation vias corresponding to the resistor pad regions 46A to 46C will be referred to as "resistor heat dissipation vias 91," the heat dissipation vias corresponding to the diode pad region 46D will be referred to as "diode heat dissipation vias 92," and the heat dissipation vias corresponding to the auxiliary resistor pad region 46E will be referred to as "auxiliary resistor heat dissipation vias 93." Note that when there is no need to distinguish between the resistor heat dissipation vias 91, diode heat dissipation vias 92, and auxiliary resistor heat dissipation vias 93, or when describing a common configuration, they will be referred to as "pad heat dissipation vias 90."

[0185] The plurality of resistor heat dissipation vias 91 are arranged in a matrix in plan view. The number of resistor heat dissipation vias 91 arranged in the X direction is greater than the number of resistor heat dissipation vias 91 arranged in the Y direction. The plurality of resistor heat dissipation vias 91 are provided at positions overlapping with each of the two resistor pad regions 46A in plan view. The plurality of resistor heat dissipation vias 91 are provided at positions overlapping with each of the two resistor pad regions 46B in plan view. The plurality of resistor heat dissipation vias 91 are provided at positions overlapping with each of the two resistor pad regions 46C in plan view.

[0186] The plurality of diode heat dissipation vias 92 are arranged in a row in the Y direction in a plan view. The plurality of auxiliary resistor heat dissipation vias 93 are arranged in a matrix in a plan view. The number of auxiliary resistor heat dissipation vias 93 arranged in the X direction is greater than the number of auxiliary resistor heat dissipation vias 93 arranged in the Y direction. The plurality of auxiliary resistor heat dissipation vias 93 are provided at positions overlapping with each of the two auxiliary resistor pad regions 46E in a plan view. In the example shown in FIG. 21 , the number of auxiliary resistor heat dissipation vias 93 arranged in the X direction is equal to the number of resistor heat dissipation vias 91 arranged in the X direction. The number of auxiliary resistor heat dissipation vias 93 arranged in the Y direction is equal to the number of resistor heat dissipation vias 91 arranged in the Y direction.

[0187] The multilayer substrate 20 includes a plurality of inter-pad heat dissipation vias 94 to 96. Each of the inter-pad heat dissipation vias 94 to 96 is connected to the intermediate conductive layer 60A. More specifically, each of the inter-pad heat dissipation vias 94 to 96 is connected to the ground wiring 62A of the intermediate conductive layer 60A.

[0188] The inter-pad heat dissipation vias 94-96 are provided between the pad regions 46. More specifically, the inter-pad heat dissipation vias 94 are provided between two resistor pad regions 46A adjacent to each other in the Y direction. The inter-pad heat dissipation vias 94 are provided between two resistor pad regions 46B adjacent to each other in the Y direction. The inter-pad heat dissipation vias 94 are provided between two resistor pad regions 46C adjacent to each other in the Y direction. In one example, the number of resistor heat dissipation vias 91 may be greater than the number of inter-pad heat dissipation vias 94. In one example, the arrangement pitch of the resistor heat dissipation vias 91 may be equal to the arrangement pitch of the inter-pad heat dissipation vias 94.

[0189] In this way, the plurality of resistor heat dissipation vias 91 and the plurality of inter-pad heat dissipation vias 94 can be said to be provided at positions that overlap with the current limiting resistor 300 (see FIG. 12 ) in a plan view. In other words, the multilayer substrate 20 can be said to include a first heat dissipation via provided in a first arrangement region, which is a region that overlaps with the current limiting resistor 300 in a plan view.

[0190] The plurality of inter-pad heat dissipation vias 95 are provided between the diode pad region 46D and the diode pad region 49C of the second power supply wiring 47, which are adjacent to each other in the X direction. The plurality of inter-pad heat dissipation vias 95 are arranged in a matrix in a plan view. In this manner, the plurality of diode heat dissipation vias 92 and the plurality of inter-pad heat dissipation vias 95 can be said to be provided at positions overlapping with the protection diodes 310 (see FIG. 12 ) in a plan view. In one example, the number of diode heat dissipation vias 92 may be less than the number of inter-pad heat dissipation vias 95. The plurality of inter-pad heat dissipation vias 95 are provided at positions overlapping with both the fifth wiring portion 45 and the narrow portion 48A of the second power supply wiring 47 in a plan view.

[0191] The plurality of diode heat dissipation vias 92, the plurality of inter-pad heat dissipation vias 95, and the plurality of diode heat dissipation vias 99 described below are located at positions overlapping the protection diodes 310 in a plan view. In other words, the multilayer substrate 20 includes second heat dissipation vias located in a second arrangement region that is a region overlapping the protection diodes 310 in a plan view.

[0192] The plurality of inter-pad heat dissipation vias 96 are provided between two auxiliary resistor pad regions 46E. The plurality of inter-pad heat dissipation vias 96 are arranged in a matrix in plan view. The number of inter-pad heat dissipation vias 96 arranged in the X direction is greater than the number of inter-pad heat dissipation vias 96 arranged in the Y direction. In this manner, the plurality of auxiliary resistor heat dissipation vias 93 and the plurality of inter-pad heat dissipation vias 96 can be said to be provided at positions overlapping with the auxiliary resistors 313 (see FIG. 12 ) in plan view. In one example, the number of auxiliary resistor heat dissipation vias 93 may be greater than the number of inter-pad heat dissipation vias 95.

[0193] In this way, the plurality of auxiliary resistor heat dissipation vias 93 and the plurality of inter-pad heat dissipation vias 96 can be said to be provided at positions that overlap the auxiliary resistors 313 in a plan view. In other words, the multilayer substrate 20 can be said to include a third heat dissipation via provided in a third arrangement region, which is a region that overlaps the auxiliary resistors 313 in a plan view.

[0194] (Cross-sectional Structure of Heat Dissipation Vias) As shown in FIG. 22 , the resistor heat dissipation vias 91 are disposed apart from the first power supply wiring 40 in the Z direction. That is, the resistor heat dissipation vias 91 are not electrically connected to the first power supply wiring 40. On the other hand, the resistor heat dissipation vias 91 are electrically connected to the intermediate conductive layer 60A. More specifically, the resistor heat dissipation vias 91 are electrically connected to the ground wiring 62A. The diode heat dissipation vias 92 shown in FIG. 23 and the auxiliary resistor heat dissipation vias 93 shown in FIG. 24 are also electrically connected to the ground wiring 62A. Note that, as shown in FIGS. 22 to 24 , the resistor heat dissipation vias 91, the diode heat dissipation vias 92, and the auxiliary resistor heat dissipation vias 93 have the same cross-sectional structure. For this reason, the following description will be given of the cross-sectional structure of the pad heat dissipation vias 90.

[0195] As shown in FIGS. 22 to 24 , each pad heat dissipation via 90 includes a front-side pad via 90A that is spaced apart from the first power supply wiring 40 and closer to the back surface conductive layer 70 in the Z direction, and a back surface pad via 90B that is closer to the back surface conductive layer 70 than the front-side pad via 90A in the Z direction. The back surface pad via 90B is connected to the back surface conductive layer 70. The front surface pad via 90A and the back surface pad via 90B are spaced apart from each other in the Z direction. The front surface pad via 90A and the back surface pad via 90B are individually provided. In this manner, each pad heat dissipation via 90 is connected to the multiple intermediate conductive layers 60A to 60D (ground wirings 62A to 62D) and the back surface conductive layer 70. Therefore, the ground wirings 62A to 62D and the back surface conductive layer 70 are electrically connected through each pad heat dissipation via 90.

[0196] The surface-side pad via 90A is connected to a plurality of intermediate conductive layers 60A-60D. It can also be said that the surface-side pad via 90A is connected to a plurality of ground wirings 62A-62D. The surface-side pad via 90A penetrates the intermediate substrate insulating layers 83A-83C and the intermediate conductive layers 60B, 60C in the Z direction. The surface-side pad via 90A is provided, for example, on the side of a through hole that penetrates the intermediate substrate insulating layers 83A-83C and the intermediate conductive layers 60B, 60C in the Z direction in the multilayer substrate 20. The surface-side pad via 90A is, for example, cylindrical. In one example, the diameter of the surface-side pad via 90A in a plan view is smaller than the diameter of the through via 89 in a plan view.

[0197] The back-side pad via 90B connects the back-side conductive layer 70 and the intermediate conductive layer 60D. Therefore, both the front-side pad via 90A and the back-side pad via 90B are connected to the intermediate conductive layer 60D. In other words, the front-side pad via 90A and the back-side pad via 90B are electrically connected through the intermediate conductive layer 60D. The back-side pad via 90B may be provided at a position different from the front-side pad via 90A in a plan view. The back-side pad via 90B may be formed by, for example, a conductive material filled in a hole formed by laser processing.

[0198] A plurality of front-side pad vias 90A and a plurality of back-side pad vias 90B are provided. In the example shown in FIG. 22 , the arrangement pitch P2 of the back-side pad vias 90B is smaller than the arrangement pitch P1 of the front-side pad vias 90A. These arrangement pitches P1 and P2 are smaller than the arrangement pitch PT of the plurality of through vias 89 (see FIG. 13 ). The number of back-side pad vias 90B is greater than the number of front-side pad vias 90A. Here, the arrangement pitch P1 of the front-side pad vias 90A can be defined by the center-to-center distance between the front-side pad vias 90A adjacent to each other in the X direction or the Y direction. The arrangement pitch P2 of the back-side pad vias 90B can be defined by the center-to-center distance between the back-side pad vias 90B adjacent to each other in the X direction or the Y direction. The arrangement pitch PT of the through vias 89 can be defined by the center-to-center distance between the through vias 89 adjacent to each other in the X direction or the Y direction.

[0199] The thickness TS of the front-side pad via 90A is greater than the thickness TR of the back-side pad via 90B. The distance D1 in the Z direction between the front-side pad via 90A and the substrate front surface 21 of the multilayer substrate 20 is equal to the distance D2 in the Z direction between the front-side pad via 90A and the substrate back surface 22 of the multilayer substrate 20.

[0200] The inter-pad heat dissipation vias 94 to 96 include front-side pad vias and back-side pad vias. The cross-sectional structures of the front-side pad vias and back-side pad vias of the inter-pad heat dissipation vias 94 to 96 are the same as the cross-sectional structure of the pad heat dissipation via 90, so detailed description thereof will be omitted.

[0201] (Diode Heat Dissipation Vias) As shown in FIG. 21 , the multilayer substrate 20 includes a plurality of diode heat dissipation vias 99. The plurality of diode heat dissipation vias 99 are provided within the multilayer substrate 20. The plurality of diode heat dissipation vias 99 are provided at positions overlapping both the diode pad region 49C of the second power supply wiring 47 and the back surface conductive layer 70 in a plan view. The plurality of diode heat dissipation vias 99 are arranged in a row in the Y direction in a plan view. The cross-sectional structure of the diode heat dissipation vias 99 is the same as the cross-sectional structure of the pad heat dissipation vias 90. The diode heat dissipation vias 99 may be made of one or more materials selected from a group including, for example, Cu, Al, Ti, TiN, Au, Ag, and W. In one example, the diode heat dissipation vias 99 are made of a material including Cu.

[0202] (First Element Heat Dissipation Vias) As shown in FIGS. 25 and 26 , the multilayer substrate 20 includes a plurality of first element heat dissipation vias 97. The plurality of first element heat dissipation vias 97 are provided within the multilayer substrate 20. The plurality of first element heat dissipation vias 97 are provided in positions overlapping both the first element arrangement region RA in which the light emitting module 100 is arranged and the back surface conductive layer 70 (see FIG. 18 ) in a planar view. Therefore, it can be said that the plurality of first element heat dissipation vias 97 are provided in positions overlapping both the region in which the light emitting element 150 is arranged and the back surface conductive layer 70 in a planar view. In FIG. 25 , the first element arrangement region RA is indicated by a rectangular frame defined by two-dot chain lines. The first element arrangement region RA is a region overlapping with the light emitting module 100 (see FIG. 13 ) in a planar view.

[0203] As shown in FIG. 25 , the multiple first element heat dissipation vias 97 are biased in the Y direction relative to the first element placement area RA. More specifically, the multiple first element heat dissipation vias 97 are arranged closer to the third substrate side surface 23C in the first element placement area RA. Therefore, the multiple first element heat dissipation vias 97 are mainly arranged in positions overlapping with the second power supply wiring 47 in a planar view. Some of the multiple first element heat dissipation vias 97 are arranged in positions overlapping with the second portion 44B of the fourth wiring portion 44 of the first power supply wiring 40 in a planar view. Also, as shown in FIG. 25 , the multiple first element heat dissipation vias 97 include those arranged in positions overlapping with the light emitting element pad areas 46G, 49A in a planar view and those arranged in positions different from the light emitting element pad areas 46G, 49A in a planar view. In the example shown in FIG. 25 , the area where the first element heat dissipation vias 97 are arranged in a planar view is wider than the area where the first element connection vias 86 are arranged in a planar view. The first element heat dissipation via 97 may be made of one or more materials selected from the group including, for example, Cu, Al, Ti, TiN, Au, Ag, and W. In one example, the first element heat dissipation via 97 is made of a material including Cu.

[0204] 26 , the multiple first element heat dissipation vias 97 are arranged at positions overlapping with the intermediate wiring 61A of the intermediate conductive layer 60A in a planar view. More specifically, the multiple first element heat dissipation vias 97 are arranged offset in the Y direction with respect to the intermediate wiring 61A in a planar view. Even more specifically, the multiple first element heat dissipation vias 97 are arranged closer to the third substrate side surface 23C of the intermediate wiring 61A in a planar view. Because the intermediate wirings 61B to 61D overlap with the intermediate wiring 61A in a planar view, it can also be said that the multiple first element heat dissipation vias 97 are arranged at positions overlapping with the intermediate wirings 61B to 61D in a planar view.

[0205] 27 , each first element heat dissipation via 97 is disposed at a distance from both the front surface conductive layer 30 and the back surface conductive layer 70 in the Z direction. Each first element heat dissipation via 97 and each first element connecting via 86 are disposed at a distance from each other in the Z direction. Each first element connecting via 86 is provided closer to the front surface conductive layer 30 than each first element heat dissipation via 97.

[0206] Each first element heat dissipation via 97, which is located closer to the back surface conductive layer 70 than each first element connection via 86, is connected to multiple intermediate conductive layers 60A-60D. More specifically, each first element heat dissipation via 97 is connected to multiple intermediate wirings 61A-61D. Each first element heat dissipation via 97 penetrates the intermediate substrate insulating layers 83A-83C and the intermediate conductive layers 60B, 60C in the Z direction. The first element heat dissipation via 97 is located, for example, on a side surface of the multilayer substrate 20 that constitutes a through hole penetrating the intermediate substrate insulating layers 83A-83C and the intermediate conductive layers 60B, 60C in the Z direction. The first element heat dissipation via 97 is, for example, cylindrical. In one example, the diameter of the first element heat dissipation via 97 in a plan view is smaller than the diameter of the through via 89 (see FIG. 26 ) in a plan view. In one example, the diameter of the first element heat dissipation via 97 in plan view is equal to the diameter of the front surface side pad via 90A (see FIG. 22) in plan view.

[0207] Since each first element connecting via 86 is connected to the intermediate conductive layer 60A, both each first element heat dissipation via 97 and each first element connecting via 86 are connected to the intermediate conductive layer 60A. More specifically, both each first element heat dissipation via 97 and each first element connecting via 86 are connected to the intermediate wiring 61A.

[0208] The thickness TT1 of the first element heat dissipation via 97 is thicker than the thickness TC of the first element connection via 86. The thickness TT1 may be equal to the thickness TS of the front-side pad via 90A (see FIG. 22 ). The thickness TC may be equal to the thickness TR of the back-side pad via 90B (see FIG. 22 ). A distance D3 between the first element heat dissipation via 97 and the substrate front surface 21 of the multilayer substrate 20 in the Z direction is equal to a distance D4 between the first element heat dissipation via 97 and the substrate back surface 22 of the multilayer substrate 20 in the Z direction. The distance D3 may be equal to the distance D1 between the front-side pad via 90A and the substrate front surface 21 of the multilayer substrate 20 in the Z direction (see FIG. 22 ). The distance D4 may be equal to the distance D2 between the front-side pad via 90A and the substrate back surface 22 of the multilayer substrate 20 in the Z direction (see FIG. 22 ).

[0209] In the example shown in FIG. 27 , the arrangement pitch P3 of the first element heat dissipation vias 97 is smaller than the arrangement pitch PT of the multiple through vias 89. Furthermore, the arrangement pitches P4 and P5 of the first element connection vias 86 are smaller than the arrangement pitch PT of the multiple through vias 89. The arrangement pitch P5 is smaller than the arrangement pitch P4. The arrangement pitches P4 and P5 of the first element connection vias 86 are different from the arrangement pitch P3 of the first element heat dissipation vias 97. In one example, the arrangement pitch P4 is larger than the arrangement pitch P3. The arrangement pitch P5 is smaller than the arrangement pitch P3. The number of first element connection vias 86 is smaller than the number of first element heat dissipation vias 97. Here, the arrangement pitch P3 of the first element heat dissipation vias 97 can be defined by the center-to-center distance between first element heat dissipation vias 97 adjacent to each other in the X direction or the Y direction. The arrangement pitches P4 and P5 of the first element connection vias 86 can be defined by the center-to-center distance between first element connection vias 86 adjacent to each other in the X direction. The arrangement pitch P5 of the first element heat dissipation vias 97 may be equal to the arrangement pitch P1 of the front surface-side pad vias 90A (see FIG. 22).

[0210] 25, the arrangement pitch P6 of the first element connection vias 86 may be equal to the arrangement pitch P5 shown in FIG. 27. Therefore, the arrangement pitch P6 is different from the arrangement pitch P3 (see FIG. 27) of the first element heat dissipation vias 97. The arrangement pitch P6 is smaller than the arrangement pitch P3. Here, the arrangement pitch P6 can be defined by the center-to-center distance between first element connection vias 86 adjacent to each other in the Y direction.

[0211] (Second Element Heat Dissipation Vias) As shown in FIGS. 26 and 28 , the multilayer substrate 20 includes a plurality of second element heat dissipation vias 98. The plurality of second element heat dissipation vias 98 are provided within the multilayer substrate 20. The plurality of second element heat dissipation vias 98 are provided in positions overlapping both the second element placement region RB, in which the transistor 210 of the drive circuit 200 (see FIG. 13 ) is arranged, and the back surface conductive layer 70 (see FIG. 18 ) in plan view. In FIG. 28 , the second element placement region RB is indicated by a rectangular frame defined by two-dot chain lines. The second element placement region RB is a region overlapping with the transistor 210 in plan view. In other words, the plurality of second element heat dissipation vias 98 are provided in positions overlapping both the second element placement region RB and the intermediate wiring 61B (see FIG. 26 ) in plan view.

[0212] Some of the multiple second element heat dissipation vias 98 are arranged in positions different from the second element placement region RB. More specifically, some of the multiple second element heat dissipation vias 98 are provided closer to the second substrate side surface 23B (see FIG. 9 ) than the second element placement region RB in a planar view. Some of the multiple second element heat dissipation vias 98 are provided in positions adjacent to the second element placement region RB in the X direction in a planar view. Some of the multiple second element heat dissipation vias 98 are provided in positions overlapping with the intermediate wiring 61A in a planar view.

[0213] The multiple second-element heat dissipation vias 98 are arranged in rows spaced apart in the X direction, aligned in the Y direction. In the example shown in FIG. 28 , two rows of second-element heat dissipation vias 98 adjacent in the X direction are arranged at positions overlapping one source electrode 213 (see FIG. 13 ) of the transistor 210 in a plan view. As shown in FIG. 26 , the rows of second-element heat dissipation vias 98 are arranged at two different pitches P7 and P8. In one example, the pitch P7 is the pitch between two rows of second-element heat dissipation vias 98 that are arranged at positions overlapping the source electrode 213. The pitch P8 is the pitch between the row of second-element heat dissipation vias 98 that is arranged at a position different from the position overlapping the source electrode 213 and the row of second-element heat dissipation vias 98 that is arranged at a position overlapping the source electrode 213. The pitch P7 is smaller than the pitch P8. The arrangement pitch P7 is smaller than the arrangement pitch PT of the plurality of through vias 89. The arrangement pitch P7 may be equal to the arrangement pitch P1 (see FIG. 22 ) of the surface-side pad vias 90A. The arrangement pitch P8 is smaller than the arrangement pitch PT of the plurality of through vias 89. The arrangement pitch P8 is larger than the arrangement pitch P1 of the surface-side pad vias 90A. The second element heat dissipation via 98 may be made of one or more materials selected from the group including, for example, Cu, Al, Ti, TiN, Au, Ag, and W. In one example, the second element heat dissipation via 98 is made of a material including Cu.

[0214] As shown in FIG. 29 , each second element heat dissipation via 98 is disposed at a distance from both the front surface conductive layer 30 and the back surface conductive layer 70 in the Z direction. Each second element heat dissipation via 98 is connected to a plurality of intermediate conductive layers 60A-60D. More specifically, each second element heat dissipation via 98 is connected to a plurality of intermediate wirings 61A-61D. Each second element heat dissipation via 98 penetrates the intermediate substrate insulating layers 83A-83C and the intermediate conductive layers 60B, 60C in the Z direction. The second element heat dissipation via 98 is provided, for example, on a side surface of the multilayer substrate 20 that constitutes a through hole that penetrates the intermediate substrate insulating layers 83A-83C and the intermediate conductive layers 60B, 60C in the Z direction. The second element heat dissipation via 98 is, for example, cylindrical. In one example, the diameter of the second element heat dissipation via 98 in a plan view is smaller than the diameter of the through via 89 in a plan view. In one example, the diameter of the second element heat dissipation via 98 in plan view is equal to the diameter of the front surface side pad via 90A in plan view.

[0215] The second element heat dissipation vias 98 and the second element connecting vias 87 (see FIG. 28 ) are arranged spaced apart from each other in the Z direction. The second element heat dissipation vias 98 are arranged closer to the back surface conductive layer 70 than the second element connecting vias 87 in the Z direction. The second element heat dissipation vias 98 and the second element connecting vias 87 are connected to the intermediate conductive layer 60A. More specifically, the second element heat dissipation vias 98 and the second element connecting vias 87 are connected to the intermediate wiring 61A.

[0216] The thickness TT2 of the second element heat dissipation via 98 is thicker than the thickness of the second element connection via 87. The thickness TT2 may be equal to the thickness TS of the front-side pad via 90A (see FIG. 22). The thickness of the second element connection via 87 may be equal to the thickness TR of the back-side pad via 90B (see FIG. 22). The thickness of the second element connection via 87 may be equal to the thickness TC of the first element connection via 86 (see FIG. 27). The distance D5 between the second element heat dissipation via 98 and the substrate front surface 21 of the multilayer substrate 20 in the Z direction and the distance D6 between the second element heat dissipation via 98 and the substrate back surface 22 of the multilayer substrate 20 in the Z direction are equal to each other. The distance D5 may be equal to the distance D1 between the front-side pad via 90A and the substrate front surface 21 of the multilayer substrate 20 in the Z direction (see FIG. 22). The distance D6 may be equal to the distance D2 (see FIG. 22) between the front surface-side pad via 90A and the rear surface 22 of the multilayer substrate 20 in the Z direction.

[0217] (Heat Sink) As shown in FIG. 30 , the light-emitting device 10 includes a heat sink 400. The heat sink 400 is located on the substrate rear surface 22 side of the multilayer substrate 20. The heat sink 400 is attached to the multilayer substrate 20 through heat sink mounting holes 25 (see FIG. 18 ) using bolts (not shown). The heat sink 400 is indirectly connected to the rear surface conductive layer 70 (see FIG. 18 ). More specifically, the light-emitting device 10 includes an intermediate heat dissipation material 410 connected to the rear surface conductive layer 70 through an electrode opening 85A (see FIG. 18 ) in the rear surface insulating layer 85. The heat sink 400 is connected to the intermediate heat dissipation material 410. The intermediate heat dissipation material 410 may be, for example, a grease or gel-like heat dissipation material, or a heat dissipation sheet. In one example, the intermediate heat dissipation material 410 may be, for example, a TIM (Thermal Interface Material). The TIM may be, for example, a sheet-like material made of silicone resin or epoxy resin filled with a highly thermally conductive filler.

[0218] The heat sink 400 includes a base 401 connected to an intermediate heat dissipation material 410, and a plurality of heat dissipation fins 402 extending radially from the base 401. In one example, the base 401 and the plurality of heat dissipation fins 402 are integrated together. The heat sink 400 is made of a material including at least one of Al and Cu, for example.

[0219] The heat sink 400 is disposed at a position overlapping the light-emitting module 100, the drive circuit 200, the current limiting resistor 300, the protection diode 310, the auxiliary resistor 313, the first heat dissipation member 340, and the second heat dissipation member 350 (all see FIG. 1) in plan view. The heat sink 400 is disposed so as to overlap the pad heat dissipation via 90, the inter-pad heat dissipation vias 94 to 96 (all see FIG. 21), the first element heat dissipation via 97, and the second element heat dissipation via 98 (all see FIG. 26) in plan view.

[0220] 31 , heat from the light emitting module 100 is transferred to the heat sink 400 through the first element heat dissipation vias 97. Heat from the transistor 210 of the drive circuit 200 is transferred to the heat sink 400 through the second element heat dissipation vias 98.

[0221] 32 , heat from the current limiting resistor 300 is transferred to the heat sink 400 through the pad heat dissipation vias 90 and the inter-pad heat dissipation vias 94 (see FIG. 21 ). Although not shown, heat from the protection diode 310 is transferred to the heat sink 400 through the diode heat dissipation vias 92 and the inter-pad heat dissipation vias 95. Heat from the auxiliary resistor 313 is transferred to the heat sink 400 through the auxiliary resistor heat dissipation vias 93 and the inter-pad heat dissipation vias 96.

[0222] [Operation of First Embodiment] The operation of the light emitting device 10 of the first embodiment will be described. Fig. 33 is a graph showing the relationship between the heat transfer coefficient and the temperature of the light emitting element. The graph with triangles in Fig. 33 shows the relationship between the heat transfer coefficient and the temperature of the light emitting element 150 in the light emitting device 10 of the first embodiment. The graph with circles in Fig. 33 shows the relationship between the heat transfer coefficient and the temperature of the light emitting element in a light emitting device of a comparative example. Compared to the light emitting device 10 of the first embodiment, the light emitting device of the comparative example has a configuration in which the pad heat dissipation via 90, the first element heat dissipation via 97, and the second element heat dissipation via 98 are omitted.

[0223] In the light emitting device 10 of the first embodiment, heat from each of the current limiting resistor 300, the protection diode 310, and the auxiliary resistor 313 moves to the back surface conductive layer 70 through the pad heat dissipation via 90. Heat from the light emitting module 100 moves to the back surface conductive layer 70 through the first element heat dissipation via 97. Heat from the transistor 210 moves to the back surface conductive layer 70 through the second element heat dissipation via 98. This reduces the temperature of the light emitting module 100 and its surroundings, so that, as shown in FIG. 33 , the temperature of the light emitting element 150 in the light emitting device 10 of the first embodiment becomes lower than the temperature of the light emitting element in the light emitting device of the comparative example.

[0224] [Effects of First Embodiment] The light-emitting device 10 of the first embodiment has the following effects. (1-1) The light-emitting device 10 includes a multilayer substrate 20 including a substrate surface 21, a substrate back surface 22 opposite the substrate surface 21, a surface conductive layer 30 provided on the substrate surface 21, a back surface conductive layer 70 provided on the substrate back surface 22, and a first power supply through-hole 26 serving as a first power supply terminal electrically connected to the surface conductive layer 30; and a light-emitting element 150 electrically connected to the surface conductive layer 30. The surface conductive layer 30 includes a first power supply wiring 40 for supplying a drive current for driving the light-emitting element 150 from the first power supply through-hole 26 to the light-emitting element 150. The first power supply wiring 40 includes a plurality of pad regions 46 for mounting elements. The multilayer substrate 20 includes a pad heat dissipation via 90 provided within the multilayer substrate 20. The pad heat dissipation via 90 is provided at a position overlapping both the pad region 46 and the back surface conductive layer 70 in a plan view.

[0225] With this configuration, heat from the elements mounted on the multiple pad regions 46 can be easily transferred to the back surface conductive layer 70 through the pad heat dissipation vias 90. This makes it easier to lower the temperature of the elements, thereby improving the heat dissipation performance of the light emitting device 10.

[0226] (1-2) The light emitting device 10 includes a current limiting resistor 300 that limits the current flowing through the first power supply wiring 40. The pad regions 46 include resistor pad regions 46A to 46C. The current limiting resistor 300 is mounted on the resistor pad regions 46A to 46C.

[0227] With this configuration, heat from the current limiting resistor 300 is more likely to move to the back surface conductive layer 70 through the pad heat dissipation vias 90 provided at positions that overlap the resistor pad regions 46A to 46C in a plan view. This makes it easier for the temperature of the current limiting resistor 300 to decrease, thereby improving the heat dissipation performance of the light emitting device 10.

[0228] (1-3) The light emitting device 10 includes a protection diode 310 that protects the light emitting element 150. The pad regions 46 include a diode pad region 46D. The protection diode 310 is mounted on the diode pad region 46D.

[0229] According to this configuration, heat from the protection diode 310 is more likely to move to the back surface conductive layer 70 through the pad heat dissipation via 90 provided at a position overlapping the diode pad region 46D in a plan view. This makes it easier for the temperature of the protection diode 310 to decrease, thereby improving the heat dissipation performance of the light emitting device 10.

[0230] (1-4) The pad heat dissipation via 90 includes a front-side pad via 90A arranged closer to the back surface conductive layer 70 than the first power supply wiring 40 in the Z direction and spaced apart, and a back-side pad via 90B provided closer to the back surface conductive layer 70 than the front-side pad via 90A in the Z direction and connected to the back surface conductive layer 70. The front-side pad via 90A and the back-side pad via 90B are provided separately. The number of back-side pad vias 90B is greater than the number of front-side pad vias 90A.

[0231] This configuration allows heat from the elements mounted on the multiple pad regions 46 to more easily move to the back surface conductive layer 70 through the pad heat dissipation vias 90. This makes it easier for the temperature of the elements to decrease, thereby further improving the heat dissipation performance of the light emitting device 10.

[0232] (1-5) The multilayer substrate 20 includes a plurality of intermediate conductive layers 60A to 60D spaced apart from one another in the Z direction. The front-side pad via 90A is connected to the plurality of intermediate conductive layers 60A to 60D.

[0233] With this configuration, heat transferred from the element to the front-side pad via 90A moves to the intermediate conductive layers 60A-60D and then to the back-side conductive layer 70. This increases the heat dissipation capacity within the multilayer substrate 20, thereby improving the heat dissipation performance of the light-emitting device 10.

[0234] (1-6) The multilayer substrate 20 includes a plurality of substrate insulating layers 80. The plurality of substrate insulating layers 80 include intermediate substrate insulating layers 83A-83C provided with intermediate conductive layers 60A-60D, and a front surface-side substrate insulating layer 81 provided with a surface conductive layer 30. The thickness of the front surface-side substrate insulating layer 81 is thinner than the thickness of the intermediate substrate insulating layers 83A-83C.

[0235] With this configuration, heat from elements mounted in the multiple pad regions 46 is more likely to move to the front-side pad vias 90A. Therefore, heat from the elements is more likely to move to the back-surface conductive layer 70 through the front-side pad vias 90A, improving the heat dissipation performance of the light-emitting device 10. In addition, the length of the loop-shaped path of the drive current flowing between the drive circuit 200 and the light-emitting module 100 through the intermediate wiring 61A can be shortened. Therefore, the inductance caused by the length of this path can be reduced.

[0236] (1-7) The thickness of the front-side substrate insulating layer 81 is 0.1 mm or less. With this configuration, the front-side substrate insulating layer 81 is thin, at 0.1 mm or less, so that heat from the elements mounted in the multiple pad regions 46 is easily transferred to the front-side pad vias 90A. This makes it easier for heat from the elements to transfer to the back surface conductive layer 70 through the front-side pad vias 90A, thereby improving the heat dissipation performance of the light-emitting device 10. In addition, the length of the loop-shaped path of the drive current flowing between the drive circuit 200 and the light-emitting module 100 through the intermediate wiring 61A can be further shortened. This further reduces the inductance caused by the length of this path.

[0237] (1-8) The distance D1 in the Z direction between the front-side pad via 90A and the substrate front surface 21 is equal to the distance D2 in the Z direction between the front-side pad via 90A and the substrate back surface 22. This configuration can prevent warping of the multilayer substrate 20 due to the front-side pad via 90A.

[0238] (1-9) The multilayer substrate 20 includes a first element heat dissipation via 97 provided within the multilayer substrate 20. The first element heat dissipation via 97 is provided at a position overlapping both the first element placement area RA in which the light emitting module 100 including the light emitting element 150 is placed and the back surface conductive layer 70 in plan view.

[0239] According to this configuration, heat from the light emitting element 150 is more likely to move to the back surface conductive layer 70 through the first element heat dissipation via 97. This makes it easier for the temperature of the light emitting element 150 to decrease, thereby improving the heat dissipation performance of the light emitting device 10.

[0240] (1-10) The multilayer substrate 20 includes a plurality of intermediate conductive layers 60A to 60D spaced apart from one another in the Z direction. The first element heat dissipation via 97 is connected to the plurality of intermediate conductive layers 60A to 60D.

[0241] With this configuration, heat transferred from the light emitting element 150 to the first element heat dissipation via 97 moves to the intermediate conductive layers 60A-60D and then to the back surface conductive layer 70. This increases the heat dissipation capacity within the multilayer substrate 20, thereby improving the heat dissipation performance of the light emitting device 10.

[0242] (1-11) The multilayer substrate 20 includes a plurality of substrate insulating layers 80. The plurality of substrate insulating layers 80 include intermediate substrate insulating layers 83A-83C provided with intermediate conductive layers 60A-60D, and a back surface side substrate insulating layer 82 provided with a back surface conductive layer 70. The thickness of the back surface side substrate insulating layer 82 is thinner than the thickness of the intermediate substrate insulating layers 83A-83C.

[0243] According to this configuration, heat transferred from the light emitting element 150 to the first element heat dissipation via 97 is more likely to move to the back surface conductive layer 70. Therefore, heat from the light emitting element 150 is more likely to move to the back surface conductive layer 70 through the first element heat dissipation via 97, thereby improving the heat dissipation performance of the light emitting device 10.

[0244] (1-12) The thickness of the back surface side substrate insulating layer 82 is 0.1 mm or less. With this configuration, the thickness of the back surface side substrate insulating layer 82 is as thin as 0.1 mm or less, so that heat from the first element heat dissipation via 97 can be easily transferred to the back surface conductive layer 70. Therefore, heat from the light emitting element 150 can be easily transferred to the back surface conductive layer 70 through the first element heat dissipation via 97, thereby improving the heat dissipation performance of the light emitting device 10.

[0245] (1-13) The distance D3 in the Z direction between the first element heat dissipation via 97 and the substrate front surface 21 is equal to the distance D4 in the Z direction between the first element heat dissipation via 97 and the substrate back surface 22. This configuration can prevent warping of the multilayer substrate 20 due to the first element heat dissipation via 97.

[0246] (1-14) The front surface conductive layer 30 includes a third power supply wiring 50 electrically connected to the back surface conductive layer 70. The light emitting device 10 includes a first heat dissipation member 340 connected to the first power supply wiring 40 and the third power supply wiring 50. The first heat dissipation member 340 is arranged adjacent to a plurality of pad regions 46 in a plan view.

[0247] According to this configuration, heat from an element (e.g., the current limiting resistor 300) mounted on the pad region 46 moves to the first heat dissipation member 340. Then, the heat from the first heat dissipation member 340 moves to the back surface conductive layer 70 through the third power wiring 50. This makes it easier to lower the temperature of the element, thereby improving the heat dissipation performance of the light emitting device 10.

[0248] (1-15) The first heat dissipation member 340 is configured to have a thermal conductivity of 100 W / m / K or more. This configuration makes it easier for heat from an element (e.g., the current-limiting resistor 300) mounted on the pad region 46 to move to the first heat dissipation member 340. This makes it easier for the temperature of the element to decrease, thereby improving the heat dissipation performance of the light emitting device 10.

[0249] (1-16) The front surface conductive layer 30 includes a second power supply wiring 47 through which a drive current flows from the light emitting element 150, and a third power supply wiring 50 electrically connected to the back surface conductive layer 70. The light emitting device 10 includes a second heat dissipation member 350 connected to the second power supply wiring 47 and the third power supply wiring 50. The second heat dissipation member 350 is disposed adjacent to the light emitting element 150.

[0250] According to this configuration, heat from the light emitting element 150 moves to the second heat dissipation member 350. Then, heat from the first heat dissipation member 340 moves to the back surface conductive layer 70 through the third power wiring 50. This makes it easier for the temperature of the light emitting element 150 to decrease, thereby improving the heat dissipation performance of the light emitting device 10.

[0251] (1-17) The second heat dissipation member 350 is configured to have a thermal conductivity of 100 W / m / K or more. This configuration makes it easier for heat from the light emitting element 150 to move to the second heat dissipation member 350. This makes it easier for the temperature of the light emitting element 150 to decrease, thereby improving the heat dissipation performance of the light emitting device 10.

[0252] (1-18) The multilayer substrate 20 includes a plurality of substrate insulating layers 80. The plurality of substrate insulating layers 80 includes a back-side substrate insulating layer 82 on which a back-side conductive layer 70 is provided. The plurality of intermediate wirings 61A to 61D includes an intermediate wiring 61D as a back-side intermediate wiring that contacts the surface of the back-side substrate insulating layer 82 opposite to the surface on which the back-side conductive layer 70 is provided. In a plan view, the area of ​​the intermediate wiring 61D is set to be 10% or less of the output capacitance of the transistor 210.

[0253] This configuration can reduce the parasitic capacitance between the intermediate wiring 61D and the back surface conductive layer 70. Therefore, adverse effects such as switching delays on the switching operation of the transistor 210 can be suppressed.

[0254] (1-19) The multilayer substrate 20 includes a second element heat dissipation via 98 provided within the multilayer substrate 20. The second element heat dissipation via 98 is provided at a position overlapping both the transistor 210 and the back surface conductive layer 70 in plan view.

[0255] According to this configuration, heat from the transistor 210 is more likely to move to the back surface conductive layer 70 through the second element heat dissipation via 98. This makes it easier for the temperature of the transistor 210 to decrease, thereby improving the heat dissipation performance of the light emitting device 10.

[0256] (1-20) The multilayer substrate 20 includes a plurality of intermediate conductive layers 60A to 60D spaced apart from one another in the Z direction. The second element heat dissipation via 98 is connected to the plurality of intermediate conductive layers 60A to 60D.

[0257] With this configuration, heat transferred from the transistor 210 to the second element heat dissipation via 98 moves to the intermediate conductive layers 60A-60D and then to the back surface conductive layer 70. This increases the heat dissipation capacity within the multilayer substrate 20, thereby improving the heat dissipation performance of the light emitting device 10.

[0258] (1-21) The distance D5 between the second element heat dissipation via 98 and the substrate front surface 21 in the Z direction is equal to the distance D6 between the second element heat dissipation via 98 and the substrate back surface 22 in the Z direction. This configuration can prevent warping of the multilayer substrate 20 due to the second element heat dissipation via 98.

[0259] (1-22) In plan view, the light emitting element 150, the transistor 210, and the capacitor 220 are arranged spaced apart from each other in the Y direction. The capacitor 220 is arranged between the light emitting element 150 and the transistor 210.

[0260] This configuration shortens the loop path of the drive current flowing through the light emitting element 150, the transistor 210, and the capacitor 220. This reduces the inductance caused by the length of this path.

[0261] (1-23) The drive circuit 200 includes a plurality of capacitors 220. The plurality of capacitors 220 are arranged in the X direction. This configuration can reduce the resistance and inductance in the loop path of the drive current flowing through the light-emitting element 150, the transistor 210, and the capacitor 220.

[0262] (1-24) The transistor 210 includes a lateral transistor. With this configuration, the transistor 210 can be flip-chip mounted on the surface conductive layer 30. This eliminates the need for wires to connect the surface conductive layer 30 and the transistor 210, thereby eliminating the inductance caused by the wires. This allows for a low inductance in the loop path of the drive current flowing through the light-emitting element 150, the transistor 210, and the capacitor 220.

[0263] (1-25) A plurality of current limiting resistors 300 are provided corresponding to the plurality of resistor pad regions 46A to 46C. The plurality of current limiting resistors 300 are connected in series. With this configuration, it is possible to reduce heat from the current limiting resistor 300 that is closest to the light emitting element 150 among the plurality of current limiting resistors 300. Therefore, it is possible to reduce the thermal effect on the light emitting element 150 caused by the current limiting resistor 300.

[0264] (1-26) The multilayer substrate 20 includes a back-side insulating layer 85 that is provided on the substrate back surface 22 and covers the back-side conductive layer 70. The back-side insulating layer 85 includes an electrode opening 85A that exposes the back-side conductive layer 70. The light-emitting device 10 includes an intermediate heat dissipation material 410 that is connected to the back-side conductive layer 70 through the electrode opening 85A, and a heat sink 400 that serves as a heat dissipation body that is connected to the intermediate heat dissipation material 410.

[0265] According to this configuration, heat from the elements mounted on the front surface conductive layer 30 is transferred to the heat sink 400 through the back surface conductive layer 70 and the intermediate heat dissipation material 410. This makes it easier to lower the temperature of the elements, thereby improving the heat dissipation performance of the light emitting device 10.

[0266] 34 and 35 , a light emitting device 10 according to a second embodiment will be described. The light emitting device 10 according to the second embodiment differs from the light emitting device 10 according to the first embodiment mainly in the configuration of the third power supply wiring 50 of the surface conductive layer 30. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0267] Fig. 34 shows a schematic enlarged planar structure of the light emitting module 100, the drive circuit 200, and the surrounding area in the light emitting device 10 of the second embodiment. Fig. 35 shows a schematic circuit configuration of the light emitting device 10 of the second embodiment.

[0268] 34 , in the second embodiment, the third power supply wiring 50 includes a drive wiring section 501, a first heat dissipation wiring section 502, and a second heat dissipation wiring section 503. The drive wiring section 501 is disposed adjacent to the first power supply wiring 40 in the Y direction. More specifically, the drive wiring section 501 is disposed adjacent to the second portion 44B of the fourth wiring section 44 of the first power supply wiring 40 in the Y direction. The drive wiring section 501 is provided with a plurality of capacitor pad regions 51A. The plurality of capacitors 220 of the drive circuit 200 are disposed so as to straddle the first power supply wiring 40 and the drive wiring section 501 in the Y direction.

[0269] The first heat dissipation wiring section 502 is provided at a position adjacent to the drive wiring section 501 in the X direction. The first heat dissipation wiring section 502 is arranged closer to the first substrate side surface 23A than the drive wiring section 501. The first heat dissipation wiring section 502 is a region of the third power supply wiring 50 in which a plurality of second heat dissipation members 350 are arranged. The first heat dissipation wiring section 502 is provided with a heat dissipation member pad region 51C corresponding to the second heat dissipation members 350.

[0270] The second heat dissipation wiring portion 503 is provided adjacent to the drive wiring portion 501 in the X direction. The second heat dissipation wiring portion 503 is disposed closer to the second substrate side surface 23B (see FIG. 9 ) than the drive wiring portion 501. In other words, the second heat dissipation wiring portion 503 is provided on the opposite side of the drive wiring portion 501 from the first heat dissipation wiring portion 502. The second heat dissipation wiring portion 503 includes a portion between the drive wiring portion 501 and the first portion 44A of the fourth wiring portion 44 of the first power supply wiring 40 in the X direction. The second heat dissipation wiring portion 503 includes a region of the third power supply wiring 50 where the first heat dissipation member 340 is disposed. The second heat dissipation wiring portion 503 is provided with a heat dissipation member pad region 51C corresponding to the first heat dissipation member 340.

[0271] The multilayer substrate 20 includes a first isolation region 510 that separates the drive wiring section 501 from the first heat dissipation wiring section 502 , and a second isolation region 520 that separates the drive wiring section 501 from the second heat dissipation wiring section 503 .

[0272] The first isolation region 510 is provided in a position adjacent to the capacitor 220 of the drive circuit 200 in the X direction. More specifically, the first isolation region 510 is provided closer to the first substrate side surface 23A than the capacitor 220 closest to the first substrate side surface 23A (see FIG. 9 ) among the multiple capacitors 220, and in a position adjacent to the capacitor 220 in the X direction. The first isolation region 510 can also be said to be provided between the capacitor 220 and the second heat dissipation member 350 in the X direction. The first isolation region 510 is provided so as to communicate with the first gate slit 53A. The first isolation region 510 extends along the Y direction in a plan view.

[0273] The first isolation region 510 prevents current from flowing directly from the drive wiring section 501 to the first heat dissipation wiring section 502. More specifically, the first isolation region 510 separates the drive wiring section 501 and the first heat dissipation wiring section 502. Therefore, when the transistor 210 is turned on, the current that flows to drive the light-emitting module 100 through the transistor 210 is less likely to flow to the first heat dissipation wiring section 502. The output terminal of the gate driver 230 that drives the transistor 210 is electrically connected to the gate electrode 215 of the transistor 210 by the first gate wiring 56. The source electrode 213 of the transistor 210 is electrically connected to the drive wiring section 501 of the third power supply wiring 50. Therefore, the first gate wiring 56 and the portion 501A of the drive wiring section 501 on the opposite side of the first gate wiring 56 from the first isolation region 510 form a ground path R1 connecting the source electrode 213 of the transistor 210 and the ground terminal of the gate driver 230.

[0274] The current that flows from the first gate wiring 56 to the gate electrode 215 of the transistor 210 flows from the source electrode 213 of the transistor 210 to the gate driver 230 through a path (ground path R1) that electrically connects the drive wiring unit 501 and the gate driver 230. The current for driving the light-emitting module 100 does not flow to the first heat dissipation wiring unit 502 due to the first isolation region 510. As a result, the signal path for the gate signal between the gate driver 230 and the transistor 210 is less susceptible to the influence of the drive current that drives the light-emitting module 100.

[0275] Furthermore, the drive wiring section 501 is separated from the first heat dissipation wiring section 502 by the first isolation region 510. Therefore, when the transistor 210 is turned on, the current flowing through the transistor 210 tends to flow from the transistor 210 toward the capacitor 220. This makes it possible to suppress a current drop in the current loop for the drive current including the light-emitting module 100. As a result, it is possible to increase the current flowing to drive the light-emitting module 100. This increase in current leads to an increase in the amount of light in the light-emitting module 100, which can reduce the pulse width of the emitted laser light.

[0276] The second isolation region 520 is provided on the opposite side of the capacitor 220 from the first isolation region 510 in the X direction. The second isolation region 520 is provided so as to surround the transistor 210 in a plan view. The second isolation region 520 includes a first isolation portion 521, a second isolation portion 522, a third isolation portion 523, and a fourth isolation portion 524.

[0277] The first separation portion 521 is provided in a position adjacent to the capacitor 220 in the X direction. More specifically, the first separation portion 521 is provided closer to the second substrate side surface 23B than the capacitor 220 closest to the second substrate side surface 23B among the multiple capacitors 220, and in a position adjacent to the capacitor 220 in the X direction. It can also be said that the first separation portion 521 is provided between the capacitor 220 and the first heat dissipation member 340 in the X direction. The first separation portion 521 extends along the Y direction in a plan view. The first separation portion 521 is provided closer to the second portion 44B of the fourth wiring portion 44 than the transistor 210 in the Y direction.

[0278] The second isolation portion 522 is provided at a position adjacent to the transistor 210 in the X direction. The second isolation portion 522 is provided closer to the second substrate side surface 23B than the transistor 210. The second isolation portion 522 extends along the Y direction in a plan view. The second isolation portion 522 extends closer to the fourth substrate side surface 23D (see FIG. 9 ) than the transistor 210.

[0279] The third isolation portion 523 connects the first isolation portion 521 and the second isolation portion 522. The third isolation portion 523 is provided between the first isolation portion 521 and the second isolation portion 522 in the X direction. The third isolation portion 523 extends in the X direction in a plan view. The third isolation portion 523 is provided at the same position as the end of the transistor 210 that is closer to the capacitor 220 in the Y direction.

[0280] The fourth isolation portion 524 is provided closer to the fourth substrate side surface 23D than the transistor 210 in the Y direction. The fourth isolation portion 524 is provided closer to the fourth substrate side surface 23D than the drain wiring 55 and the drain opening 52. The fourth isolation portion 524 is provided between the gate driver 230 and the transistor 210 in the Y direction. More specifically, the fourth isolation portion 524 is provided closer to the gate driver 230 than the transistor 210 in the Y direction.

[0281] The fourth isolation portion 524 extends from the second isolation portion 522 toward the gate driver 230. The fourth isolation portion 524 extends across the entire transistor 210 in the X direction. In the second embodiment, the fourth isolation portion 524 extends slightly closer to the first substrate side surface 23A than the transistor 210 in the X direction. Furthermore, the fourth isolation portion 524 is provided closer to the second substrate side surface 23B than the control power supply wiring 63A in plan view.

[0282] The second isolation region 520 prevents a current from flowing directly from the drive wiring unit 501 to the second heat dissipation wiring unit 503. More specifically, because the drive wiring unit 501 and the second heat dissipation wiring unit 503 are separated by the second isolation region 520, the drive wiring unit 501 and the second heat dissipation wiring unit 503 are electrically connected through a connection portion of the third power supply wiring 50 that is closer to the fourth substrate side surface 23D than the second isolation region 520 and closer to the second substrate side surface 23B than the gate driver 230. In other words, the source electrode 213 of the transistor 210 is electrically connected to the ground terminal of the gate driver 230 through a portion 501A between the fourth isolation region 524 and the first gate slit 53A that separates the first gate wiring 56. In other words, the drive signal loop formed by the output terminal of the gate driver 230, the gate electrode 215 of the transistor 210, the source electrode 213 of the transistor 210, and the ground terminal of the gate driver 230 is less susceptible to the influence of the drive current loop that flows when the transistor 210 is turned on, i.e., the loop formed by the first electrode 221 of the capacitor 220, the light-emitting module 100, the drain electrode 214 of the transistor 210, the source electrode 213 of the transistor 210, and the second electrode 222 of the capacitor 220. This makes it possible to suppress the influence of fluctuations in the gate-source voltage of the transistor 210. Therefore, it is possible to suppress fluctuations in the light output of the light-emitting element 150.

[0283] Furthermore, the drive wiring section 501 is separated from the second heat dissipation wiring section 503 by the second isolation region 520. Therefore, when the transistor 210 is turned on, the current flowing through the transistor 210 tends to flow from the transistor 210 toward the capacitor 220. This makes it possible to suppress a current drop in the current loop for the drive current including the light-emitting module 100. As a result, it is possible to increase the current flowing to drive the light-emitting module 100. This increase in current leads to an increase in the amount of light in the light-emitting module 100, which can reduce the pulse width of the emitted laser light.

[0284] As shown in FIG. 35 , by providing the third power supply wiring 50 with a first isolation region 510 and a second isolation region 520 (both see FIG. 34 ), the path electrically connecting the source of the transistor 210 and ground is separated into two ground paths R1 and R2. The ground path R1 is a path that includes the drive wiring unit 501 (see FIG. 34 ). The ground path R1 is a path that connects the source of the transistor 210 and the gate driver 230. In other words, the ground path R1 is a path that electrically connects the drive wiring unit 501 and the gate driver 230. The ground path R2 forms part of the path through which the drive current flows through the transistor 210 and the light-emitting module 100 shown in FIG. 35 . In other words, the ground path R2 does not include the portion 501A of the drive wiring section 501 between the fourth separation section 524 and the first gate slit 53A that separates the first gate wiring 56, nor the first heat dissipation wiring section 502 and the second heat dissipation wiring section 503 (both see Figure 34).

[0285] [Effects of Second Embodiment] The light-emitting device 10 of the second embodiment provides the following effects. (2-1) The light-emitting device 10 includes a multilayer substrate 20 including a substrate surface 21, a substrate back surface 22 opposite the substrate surface 21, a surface conductive layer 30 provided on the substrate surface 21, a back surface conductive layer 70 provided on the substrate back surface 22, and a first power supply through-hole 26 serving as a first power supply terminal electrically connected to the surface conductive layer 30; a light-emitting element 150 electrically connected to the surface conductive layer 30; a transistor 210 and a capacitor 220 connected to the surface conductive layer 30 and driving the light-emitting element 150; and a gate driver 230 controlling the transistor 210. The light-emitting element 150, the transistor 210, and the capacitor 220 are arranged in the Y direction in a plan view. The capacitor 220 is disposed between the light-emitting element 150 and the transistor 210 in the Y direction. The gate driver 230 is disposed apart from the transistor 210 in the X direction in a plan view and on the opposite side of the capacitor 220 from the transistor 210 in the Y direction. The front surface conductive layer 30 includes a first power supply wiring 40 and a second power supply wiring 47 on which the light emitting element 150 is mounted, a third power supply wiring 50 electrically connected to the back surface conductive layer 70, and a first gate wiring 56 electrically connecting the gate of the transistor 210 to the gate driver 230. The third power supply wiring 50 includes a drive wiring section 501 adjacent to the first power supply wiring 40 in the Y direction and a first heat dissipation wiring section 502 adjacent to the drive wiring section 501 in the X direction. The capacitor 220 is disposed so as to straddle the first power supply wiring 40 and the drive wiring section 501 in the Y direction. The multilayer substrate 20 includes a first isolation region 510 that separates the drive wiring section 501 and the first heat dissipation wiring section 502, and a first gate slit 53A that separates the first gate wiring 56 and the third power supply wiring 50. The first isolation region 510 is provided adjacent to the capacitor 220 in the X direction and communicates with the first gate slit 53A.

[0286] According to this configuration, the drive wiring section 501 and the first heat dissipation wiring section 502 are separated by the first isolation region 510, so that the drive current supplied to the light-emitting module 100 can be prevented from flowing into the first heat dissipation wiring section 502. This allows the path of the current flowing from the first gate wiring 56 to the gate of the transistor 210 to be separated. This prevents a decrease in the gate-source voltage when the transistor 210 is turned on, thereby improving the optical output of the light-emitting element 150. This also reduces the pulse width of the laser light emitted from the light-emitting module 100.

[0287] (2-2) The third power supply wiring 50 includes a second heat dissipation wiring section 503 provided on the opposite side of the drive wiring section 501 from the first heat dissipation wiring section 502. The multilayer substrate 20 includes a second isolation region 520 provided on the opposite side of the capacitor 220 in the Y direction from the first isolation region 510. The second isolation region 520 separates the drive wiring section 501 and the second heat dissipation wiring section 503. The second isolation region 520 is provided to surround the transistor 210 in a plan view.

[0288] According to this configuration, the drive wiring section 501 and the second heat dissipation wiring section 503 are separated by the second isolation region 520, so that the drive current supplied to the light-emitting module 100 can be prevented from flowing into the second heat dissipation wiring section 503. This allows the path of the current flowing from the first gate wiring 56 to the gate of the transistor 210 to be separated. Therefore, the decrease in the gate-source voltage when the transistor 210 is turned on can be suppressed, thereby improving the optical output of the light-emitting element 150. This can also reduce the pulse width of the laser light emitted from the light-emitting module 100.

[0289] <Modifications> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0290] In each embodiment, as shown in FIG. 36 , the cylindrical pad heat dissipation via 90 may be filled with an insulating member 600. The insulating member 600 may be made of a material (heat dissipation material) with excellent heat dissipation performance, such as AlN or BeO. This makes it easier for heat from the current limiting resistor 300 (see FIG. 12 ) to move to the heat sink 400 through the pad heat dissipation via 90. This makes it easier for the current limiting resistor 300 to dissipate heat via the heat sink 400. This reduces the temperature of the current limiting resistor 300. The insulating member 600 may be made of a resin material, such as epoxy resin. The inter-pad heat dissipation vias 94 to 96 can also be similarly modified.

[0291] In each embodiment, the pad heat dissipation vias 90 may be provided in a columnar shape, as shown in FIG. 37 . In one example, the pad heat dissipation vias 90 are cylindrical. This makes it easier for heat from the current limiting resistor 300 (see FIG. 12 ) to move to the back surface conductive layer 70 through the pad heat dissipation vias 90. This makes it easier for the current limiting resistor 300 to dissipate heat by the heat sink 400. This makes it possible to lower the temperature of the current limiting resistor 300. Note that the inter-pad heat dissipation vias 94 to 96 can also be similarly modified.

[0292] In each embodiment, as shown in FIG. 38 , the cylindrical first element heat dissipation via 97 may be filled with an insulating member 600. The insulating member 600 may be made of a material (heat dissipation material) with excellent heat dissipation performance, such as AlN or BeO. This makes it easier for heat from the light-emitting module 100 to move to the back surface conductive layer 70 through the first element heat dissipation via 97. This makes it easier for the light-emitting module 100 (see FIG. 13 ) to dissipate heat using the heat sink 400. This allows the temperature of the light-emitting module 100 to be reduced. The insulating member 600 may be made of a resin material, such as epoxy resin. The second element heat dissipation via 98 can also be modified in a similar manner.

[0293] In each embodiment, as shown in FIG. 39 , a cylindrical first element heat dissipation via 97 may be filled with a conductive material. The conductive material may be the same material as that constituting the first element heat dissipation via 97. In one example, the first element heat dissipation via 97 is cylindrical. This makes it easier for heat from the light emitting module 100 (see FIG. 13 ) to move to the back surface conductive layer 70 through the first element heat dissipation via 97. This makes it easier for the light emitting module 100 to dissipate heat using the heat sink 400. This allows the temperature of the light emitting module 100 to be reduced. Note that the second element heat dissipation via 98 can also be modified in a similar manner.

[0294] In each embodiment, the resistor heat dissipation via 91 may be provided across the entirety of each of the resistor pad regions 46A to 46C in plan view. In other words, the resistor heat dissipation via 91 may be provided at a position that protrudes from the current limiting resistor 300 in the Y direction in plan view.

[0295] In each embodiment, the resistor heat dissipation vias 91 may be provided in regions of different sizes relative to the resistor pad regions 46A to 46C. That is, the number of resistor heat dissipation vias 91 provided at positions overlapping the resistor pad regions 46A to 46C in a plan view may differ from one another. For example, the number of resistor heat dissipation vias 91 provided at positions overlapping the resistor pad region 46A in a plan view may be greater than the number of resistor heat dissipation vias 91 provided at positions overlapping the resistor pad region 46B in a plan view. For example, the number of resistor heat dissipation vias 91 provided at positions overlapping the resistor pad region 46A in a plan view may be greater than the number of resistor heat dissipation vias 91 provided at positions overlapping the resistor pad region 46C in a plan view. For example, the number of resistor heat dissipation vias 91 provided at positions overlapping the resistor pad region 46B in a plan view may be greater than the number of resistor heat dissipation vias 91 provided at positions overlapping the resistor pad region 46C in a plan view.

[0296] In each embodiment, the sizes of the resistor heat dissipation vias 91 provided at positions overlapping the resistor pad regions 46A to 46C in a plan view may be different from one another. For example, the size (diameter) in a plan view of the resistor heat dissipation via 91 provided at a position overlapping the resistor pad region 46A in a plan view may be larger than the size (diameter) in a plan view of the resistor heat dissipation via 91 provided at a position overlapping the resistor pad region 46B in a plan view. For example, the size (diameter) in a plan view of the resistor heat dissipation via 91 provided at a position overlapping the resistor pad region 46B in a plan view may be larger than the size (diameter) in a plan view of the resistor heat dissipation via 91 provided at a position overlapping the resistor pad region 46C in a plan view.

[0297] In each embodiment, the diode heat dissipation vias 92 may be provided in regions of different sizes relative to the diode pad regions 46D and 49C. That is, the number of diode heat dissipation vias 92 provided at positions overlapping the diode pad region 46D in plan view may be different from the number of diode heat dissipation vias 92 provided at positions overlapping the diode pad region 49C.

[0298] In each embodiment, the size (diameter) in a planar view of the diode heat dissipation via 92 provided at a position overlapping the diode pad region 46D in a planar view may be different from the size (diameter) in a planar view of the diode heat dissipation via 92 provided at a position overlapping the diode pad region 49C in a planar view.

[0299] In each embodiment, the auxiliary resistor heat dissipation vias 93 may be provided in areas of different sizes relative to the two auxiliary resistor pad areas 46 E. That is, the number of auxiliary resistor heat dissipation vias 93 provided at positions overlapping the auxiliary resistor pad areas 46 E of the fourth wiring part 44 in plan view may be different from the number of auxiliary resistor heat dissipation vias 93 provided at positions overlapping the auxiliary resistor pad areas 46 E of the fifth wiring part 45.

[0300] - In each embodiment, the size (diameter) in a planar view of the auxiliary resistor heat dissipation via 93 provided at a position overlapping with the auxiliary resistor pad region 46E of the fourth wiring part 44 in a planar view may be different from the size (diameter) in a planar view of the auxiliary resistor heat dissipation via 93 provided at a position overlapping with the auxiliary resistor pad region 46E of the fifth wiring part 45 in a planar view.

[0301] In each embodiment, it is possible to omit at least one of the inter-pad heat dissipation vias 94 to 96. In each embodiment, the area where the pad heat dissipation vias 90 are provided can be changed as desired.

[0302] In one example, the diode heat dissipation via 92 may be omitted from the pad heat dissipation via 90. In this case, the diode heat dissipation via 99 provided in the second power supply wiring 47 at a position overlapping the diode pad region 49C in plan view may also be omitted. In another example, the inter-pad heat dissipation via 95 provided between the diode heat dissipation via 92 and the diode heat dissipation via 99 in the X direction may also be omitted.

[0303] In one example, the auxiliary resistor heat dissipation vias 93 may be omitted from the pad heat dissipation vias 90. In one example, the auxiliary resistor heat dissipation vias 93 provided at positions overlapping the auxiliary resistor pad regions 46E of the fifth wiring portion 45 in a planar view may be omitted. In one example, the auxiliary resistor heat dissipation vias 93 provided at positions overlapping the auxiliary resistor pad regions 46E of the fourth wiring portion 44 in a planar view may be omitted. In one example, both the auxiliary resistor heat dissipation vias 93 provided at positions overlapping the auxiliary resistor pad regions 46E of the fifth wiring portion 45 in a planar view and the auxiliary resistor heat dissipation vias 93 provided at positions overlapping the auxiliary resistor pad regions 46E of the fourth wiring portion 44 in a planar view may be omitted. In another example, the inter-pad heat dissipation vias 96 provided between these auxiliary resistor heat dissipation vias 93 in the Y direction may also be omitted.

[0304] In one example, the resistor heat dissipation vias 91 may be omitted from the pad heat dissipation vias 90. In one example, the resistor heat dissipation vias 91 may be omitted at positions overlapping with the resistor pad regions 46A in a planar view. In one example, the inter-pad heat dissipation vias 94 may be omitted between the two resistor pad regions 46A in the Y direction. In one example, the resistor heat dissipation vias 91 may be omitted at positions overlapping with the resistor pad regions 46B in a planar view. In one example, the inter-pad heat dissipation vias 94 may be omitted between the two resistor pad regions 46B in the Y direction. In one example, the resistor heat dissipation vias 91 may be omitted at positions overlapping with the resistor pad region 46C in a planar view. In one example, the inter-pad heat dissipation vias 94 may be omitted between the two resistor pad regions 46C in the Y direction.

[0305] In one example, the pad heat dissipation via 90 may be provided at a position overlapping the first heat dissipation member 340 in a plan view. In other words, the pad heat dissipation via 90 may be provided at a position overlapping the heat dissipation member pad region 46J of the first power supply wiring 40 in a plan view.

[0306] In each embodiment, as shown in FIG. 40 , the auxiliary resistor 313 may be omitted. In this case, the protection diode 310 is disposed so as to straddle the fourth wiring portion 44 of the first power supply wiring 40 and the narrow portion 48A of the second power supply wiring 47 in the Y direction. A diode pad region 46D is provided in the fourth wiring portion 44, and a diode pad region 49C is provided in the narrow portion 48A. The anode electrode 311 of the protection diode 310 is mounted in the diode pad region 49C, and the cathode electrode 312 is mounted in the diode pad region 46D. As a result, the anode electrode 311 of the protection diode 310 is electrically connected to the second power supply wiring 47, and the cathode electrode 312 is electrically connected to the first power supply wiring 40. When the auxiliary resistor 313 is omitted, a diode having a forward voltage Vf higher than that of the protection diode 310 in each embodiment is used as the protection diode 310. In the modification shown in FIG. 40, the fifth wiring portion 45 may be omitted from the first power supply wiring 40.

[0307] As shown in FIG. 41 , the ground wiring 62A of the intermediate conductive layer 60A is provided with a diode heat dissipation via 92 and an inter-pad heat dissipation via 95. The diode heat dissipation via 92 is provided in a position overlapping the diode pad region 46D (see FIG. 40 ) in a plan view. The inter-pad heat dissipation via 95 is provided in a region between the diode pad region 46D and the diode pad region 49C in the Y direction. The diode heat dissipation via 99 is provided in a position overlapping the diode pad region 49C (see FIG. 40 ) in a plan view. In this manner, the diode heat dissipation vias 92, 99 and the inter-pad heat dissipation via 95 are provided in a region overlapping the protection diode 310 in a plan view. Note that the configurations of the diode heat dissipation vias 92, 99 and the inter-pad heat dissipation via 95 are the same as the configurations of the diode heat dissipation vias 92, 99 and the inter-pad heat dissipation via 95 in the above-described embodiments.

[0308] In each embodiment, the relationship between the arrangement pitch P1 of the front-side pad vias 90A and the arrangement pitch P2 of the back-side pad vias 90B of the pad heat dissipation vias 90 can be changed arbitrarily. In one example, as shown in FIG. 42 , the arrangement pitch P1 may be smaller than the arrangement pitch P2. Although not shown, the arrangement pitch P1 and the arrangement pitch P2 may be equal to each other. In one example, the number of front-side pad vias 90A may be equal to the number of back-side pad vias 90B, or the number of front-side pad vias 90A may be smaller than the number of back-side pad vias 90B. In another example, the arrangement pitch P1 may be equal to the arrangement pitch PT (see FIG. 13 ) of the through vias 89. In one example, the arrangement pitch P1 may be larger than the arrangement pitch PT. In one example, the arrangement pitch P2 may be equal to the arrangement pitch PT. In one example, the arrangement pitch P2 may be larger than the arrangement pitch PT. The same can be applied to the inter-pad heat dissipation vias 94 to 96.

[0309] In each embodiment, the first element heat dissipation via 97 is provided at a position overlapping both the first element arrangement area RA in which the light emitting module 100 is arranged and the back surface conductive layer 70 in plan view, but this is not limited to this. In one example, the first element heat dissipation via 97 may be provided at a position overlapping both the area in which the light emitting element 150 is arranged and the back surface conductive layer 70 in plan view. In another example, the first element heat dissipation via 97 may be provided throughout the entire first element arrangement area RA.

[0310] In each embodiment, the relationship between the arrangement pitch P3 of the first element heat dissipation vias 97 and the arrangement pitches P4, P5 of the first element connection vias 86 can be changed as desired. In one example, as shown in FIG. 43 , the multiple first element connection vias 86 may be arranged at an arrangement pitch P9 instead of the arrangement pitches P4, P5. That is, the multiple first element connection vias 86 may be arranged at the same arrangement pitch. In this case, the arrangement pitch P9 may be larger than the arrangement pitch P3. Although not shown, the arrangement pitch P9 and the arrangement pitch P3 may be equal to each other. In one example, the number of first element heat dissipation vias 97 may be equal to the number of first element connection vias 86, or the number of first element heat dissipation vias 97 may be smaller than the number of first element connection vias 86. In another example, the arrangement pitch P3 may be equal to the arrangement pitch PT of the through vias 89 (see FIG. 13 ). In one example, the arrangement pitch P3 may be larger than the arrangement pitch PT. In one example, the arrangement pitch P9 may be equal to the arrangement pitch PT. In one example, the arrangement pitch P9 may be larger than the arrangement pitch PT. The relationship between the arrangement pitch of the second element heat dissipation vias 98 and the arrangement pitch of the second element connection vias 87 can also be changed in a similar manner.

[0311] In each embodiment, the arrangement pitches P4 to P6 of the multiple first element connection vias 86 can be changed as desired. In one example, the arrangement pitch P4 may be equal to the arrangement pitch PT of the through vias 89. In one example, the arrangement pitch P4 may be larger than the arrangement pitch PT. In one example, the arrangement pitch P5 may be equal to the arrangement pitch PT. In one example, the arrangement pitch P5 may be larger than the arrangement pitch PT. In one example, the arrangement pitch P6 may be equal to the arrangement pitch PT. In one example, the arrangement pitch P6 may be larger than the arrangement pitch PT.

[0312] In each embodiment, the first element connection via 86 may be omitted. In this case, the first element heat dissipation via 97 that is provided at a position overlapping the second power supply wiring 47 in a plan view may be provided to connect to the second power supply wiring 47.

[0313] In each embodiment, the configuration of the pad heat dissipation vias 90 can be changed as desired. The inter-pad heat dissipation vias 94 to 96 can also be changed in the same way. In one example, the front-side pad vias 90A and the back-side pad vias 90B may be integrated. In this case, the arrangement pitch P1 of the front-side pad vias 90A and the arrangement pitch P2 of the back-side pad vias 90B are equal to each other.

[0314] In one example, as shown in FIG. 44 , the back-side pad via 90B may be omitted from the pad heat dissipation via 90. Note that the inter-pad heat dissipation vias 94 to 96 can also be modified in a similar manner. In one example, although not shown, the front-side pad via 90A may be spaced apart from the intermediate conductive layer 60D in the Z direction. In this case, the front-side pad via 90A may be provided so as to be connected to the intermediate conductive layers 60A to 60C. In another example, the front-side pad via 90A may be spaced apart from both the intermediate conductive layers 60A and 60D in the Z direction. In this case, the front-side pad via 90A may be provided so as to be connected to the intermediate conductive layers 60B and 60C.

[0315] In one example, although not shown, the surface-side pad via 90A may be spaced apart from both of the intermediate conductive layers 60C and 60D in the Z direction. In this case, the surface-side pad via 90A may be provided so as to be connected to the intermediate conductive layers 60A and 60B. In one example, the surface-side pad via 90A may be spaced apart from the intermediate conductive layers 60B to 60D in the Z direction. In this case, the surface-side pad via 90A may be provided so as to be connected to the intermediate conductive layer 60A.

[0316] In one example, although not shown, the thickness TS of the front-side pad via 90A may be equal to the thickness TR of the back-side pad via 90B. In one example, the thickness TS of the front-side pad via 90A may be thinner than the thickness TR of the back-side pad via 90B. In this case, the back-side pad via 90B may be connected to at least one of the intermediate conductive layers 60C, 60B, and 60A in addition to the intermediate conductive layer 60D.

[0317] In one example (not shown), the thickness TS of the front-side pad via 90A of the resistor heat dissipation via 91 may be different from the thickness TS of the front-side pad via 90A of the diode heat dissipation via 92. In one example, the thickness TS of the front-side pad via 90A of the resistor heat dissipation via 91 may be different from the thickness TS of the front-side pad via 90A of the auxiliary resistor heat dissipation via 93.

[0318] In one example (not shown), the thickness TR of the back-side pad via 90B of the resistor heat dissipation via 91 may be different from the thickness TR of the back-side pad via 90B of the diode heat dissipation via 92. In one example, the thickness TS of the back-side pad via 90B of the resistor heat dissipation via 91 may be different from the thickness TR of the back-side pad via 90B of the auxiliary resistor heat dissipation via 93.

[0319] In each embodiment, the configurations of the first element heat dissipation vias 97 and the first element connection vias 86 can be changed as desired. The second element heat dissipation vias 98 and the second element connection vias 87 can also be changed in the same manner.

[0320] In one example, the first element heat dissipation via 97 may be spaced apart from the intermediate conductive layer 60A (intermediate wiring 61A) in the Z direction. In this case, the first element heat dissipation via 97 may be provided so as to be connected to the intermediate conductive layers 60B to 60D (intermediate wirings 61B to 61D). In another example, the first element heat dissipation via 97 may be spaced apart from both the intermediate conductive layers 60A and 60D (intermediate wirings 61A and 61D) in the Z direction. In this case, the first element heat dissipation via 97 may be provided so as to be connected to the intermediate conductive layers 60B and 60C (intermediate wirings 61B and 61C).

[0321] In one example, the first element heat dissipation via 97 may be separated from both of the intermediate conductive layers 60A and 60B (intermediate wirings 61A and 61B) in the Z direction. In this case, the first element heat dissipation via 97 may be provided so as to be connected to the intermediate conductive layers 60C and 60D (intermediate wirings 61C and 61B). In one example, the first element heat dissipation via 97 may be separated from the intermediate conductive layers 60A to 60C (intermediate wirings 61A to 61C) in the Z direction. In this case, the first element heat dissipation via 97 may be provided so as to be connected to the intermediate conductive layer 60D (intermediate wiring 61D).

[0322] In one example, the thickness TT1 of the first element heat dissipation via 97 may be equal to the thickness TC of the first element connecting via 86. In one example, the thickness TT1 of the first element heat dissipation via 97 may be thinner than the thickness TC of the first element connecting via 86. In this case, the first element connecting via 86 may be connected to at least one of the intermediate conductive layers 60B to 60D (intermediate wirings 61B to 61D) in addition to the intermediate conductive layer 60A (intermediate wiring 61A).

[0323] In each embodiment, the distance D1 between the front-side pad via 90A of the pad heat dissipation via 90 and the substrate front surface 21 of the multilayer substrate 20 may be different from the distance D2 between the front-side pad via 90A and the substrate rear surface 22 of the multilayer substrate 20. Note that the inter-pad heat dissipation vias 94 to 96 can also be changed in the same way.

[0324] In each embodiment, the distance D3 between the first element heat dissipation via 97 and the substrate front surface 21 of the multilayer substrate 20 and the distance D3 between the first element heat dissipation via 97 and the substrate rear surface 22 of the multilayer substrate 20 may be different from each other. The second element heat dissipation via 98 can also be changed in the same way.

[0325] In each embodiment, the configuration of the multiple substrate insulating layers 80 of the multilayer substrate 20 can be changed as desired. In the second embodiment, the configuration of the second isolation region 520 can be changed as desired. For example, as shown in FIG. 45 , the third isolation portion 523 of the second isolation region 520 may be located adjacent to the second electrode 222 of the capacitor 220 closest to the second substrate side surface 23B among the multiple capacitors 220. As a result, the Y-direction dimension of the first isolation portion 521 of the second isolation region 520 shown in FIG. 45 is smaller than the Y-direction dimension of the first isolation portion 521 of the second embodiment. Meanwhile, the Y-direction dimension of the second isolation portion 522 of the second isolation region 520 shown in FIG. 45 is larger than the Y-direction dimension of the second isolation portion 522 of the second isolation region 520. The third isolation portion 523 shown in FIG. 45 is inclined toward the first substrate side surface 23A as it extends from the first isolation portion 521 toward the fourth substrate side surface 23D.

[0326] 45 is provided at the same position as the capacitor 220 closest to the second substrate side surface 23B in the X direction among the multiple capacitors 220. Therefore, the second isolation portion 522 is provided closer to the first heat dissipation member 340 than the transistor 210 in a plan view. As a result, the X direction dimension of the fourth isolation portion 524 of the second isolation region 520 shown in FIG. 45 is larger than the X direction dimension of the fourth isolation portion 524 of the second embodiment.

[0327] In yet another example, the second isolation region 520 may include a fifth isolation portion extending from the fourth isolation portion 524 along the Y direction. In one example, the fifth isolation portion may extend from the X-direction tip of the fourth isolation portion 524 toward the third substrate side surface 23C. In this case, the Y-direction tip of the fifth isolation portion is located closer to the fourth substrate side surface 23D than the transistor 210. In another example, the fifth isolation portion may extend from the X-direction tip of the fourth isolation portion 524 toward the fourth substrate side surface 23D. In this case, the Y-direction tip of the fifth isolation portion may be closer to the fourth substrate side surface 23D than the gate driver 230. In yet another example, the fourth isolation portion 524 may be omitted from the second isolation region 520.

[0328] 46 , the second isolation region 520 may be omitted. In this case, the third power supply wiring 50 includes a drive wiring portion 501 and a first heat dissipation wiring portion 502, but does not include a second heat dissipation wiring portion 503.

[0329] 47 , the first isolation region 510 may be omitted. In this case, the third power supply wiring 50 includes the drive wiring portion 501 and the second heat dissipation wiring portion 503, but does not include the first heat dissipation wiring portion 502.

[0330] In each embodiment, the area of ​​the intermediate wiring 61D in a plan view can be changed as desired. For example, the area of ​​the intermediate wiring 61D in a plan view may be set to be larger than 10% of the output capacitance of the transistor 210.

[0331] In each embodiment, it is possible to arbitrarily change the position of the first heat dissipation member 340. In one example, the first heat dissipation member 340 may be disposed closer to the second substrate side surface 23B than the resistor pad regions 46A to 46C.

[0332] In each embodiment, the first heat dissipation members 340 may have a thermal conductivity of less than 100 W / m / K. In each embodiment, at least one of the first heat dissipation members 340 may be omitted.

[0333] In each embodiment, the second heat dissipation member 350 may have a thermal conductivity of less than 100 W / m / K. In each embodiment, at least one of the second heat dissipation members 350 may be omitted.

[0334] In each embodiment, instead of the current limiting resistor 300, a wiring layer connecting the two resistor pad regions 46A may be provided. Instead of the current limiting resistor 300, a wiring layer connecting the two resistor pad regions 46B may be provided. Instead of the current limiting resistor 300, a wiring layer connecting the two resistor pad regions 46C may be provided. In another example, if the current limiting resistor 300 is omitted, the resistor pad regions 46A to 46C may also be omitted. In this case, the first to fourth wiring portions 41 to 44 may be integrated.

[0335] In each embodiment, the protection diode 310 may be omitted. In this case, the diode pad regions 46D, 49C may be omitted. In each embodiment, the arrangement of the transistor 210 and the capacitor 220 of the drive circuit 200 may be changed as desired. In one example, the capacitor 220 may be arranged on the opposite side of the transistor 210 from the light-emitting module 100.

[0336] In each embodiment, the capacitor 220 is not limited to a ceramic capacitor, and may be, for example, a silicon capacitor. In each embodiment, the arrangement of the plurality of capacitors 220 can be changed as desired. In one example, the plurality of capacitors 220 may be aligned in the Y direction.

[0337] In each embodiment, the number of capacitors 220 can be changed arbitrarily. For example, the number of capacitors 220 may be five or less. For example, the number of capacitors 220 may be one.

[0338] In each embodiment, the transistor 210 may be a lateral transistor other than a GaN HEMT, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). In one example, the transistor 210 is not limited to a lateral transistor, and may be a vertical transistor.

[0339] In each embodiment, one of the transistor 210 and the capacitor 220 may be omitted from the drive circuit 200. In each embodiment, the gate driver 230 may be omitted. In this case, the second gate wiring 57, the third gate wiring 58, and the control power supply wiring 63A may be omitted. The second power supply through-hole 27 and the signal through-hole 28 may also be omitted.

[0340] In each embodiment, the drive circuit 200 may be omitted. In this case, the drain wiring 55, the first to third gate wirings 56 to 58, the control power supply wiring 63A, and the intermediate wirings 61A to 61D may be omitted.

[0341] In each embodiment, the heat sink 400 may be omitted. In this case, the intermediate heat dissipation material 410 may also be omitted. In each embodiment, the light-emitting device 10 may be attached to a housing (not shown) instead of the heat sink 400. The housing may be made of a metal material such as Al. The housing may be, for example, box-shaped. The light-emitting device 10 is housed within the housing. In one example, the light-emitting device 10 is attached to a support member provided on the housing. The support member is in contact with the back surface conductive layer 70 of the light-emitting device 10. This allows heat from the light-emitting device 10 to be transferred to the support member and the housing. This makes it easier for the temperatures of the light-emitting element 150, the drive circuit 200, the current-limiting resistor 300, the protection diode 310, and the auxiliary resistor 313 to decrease, thereby improving the heat dissipation performance of the light-emitting device 10.

[0342] In each embodiment, the circuit configuration of the light-emitting system 800 can be changed as desired. For example, as shown in FIG. 48 , the source electrode 213 of the transistor 210 in the drive circuit 200 may be electrically connected to the first back surface conductive layer 131 (anode electrode) of the light-emitting element 150. The drain electrode 214 of the transistor 210 is electrically connected to the current-limiting resistor 300 and the capacitor 220 in the drive circuit 200. In this manner, the light-emitting system 800 may employ a high-side drive method for driving the light-emitting element 150, in which the transistor 210 is provided on the high side of the light-emitting element 150.

[0343] In each embodiment, the configuration of the light-emitting element 150 can be changed as desired. The number of light-emitting portions 154 of the light-emitting element 150 may be eight or less, or nine or more. Furthermore, a surface-emitting laser element may be used as the light-emitting element 150 instead of an edge-emitting element. An example of a surface-emitting laser element may be a photonic-crystal surface-emitting laser (PCSEL) element or a vertical-cavity surface-emitting laser (VCSEL) element.

[0344] In each embodiment, the configuration of the light-emitting module 100 can be changed as desired. For example, the case 170 may be omitted from the light-emitting module 100. The submount 160 may be omitted from the light-emitting module 100. The substrate 110 may be omitted from the light-emitting module 100. In other words, the light-emitting element 150 may be directly joined to the second power supply wiring 47.

[0345] One or more of the various examples described in this disclosure can be combined to the extent that they are not technically inconsistent. The term "on" used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be in contact with the second element and disposed directly on the second element, but in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0346] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0347] <Supplementary Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the supplementary notes are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0348] [Supplementary Note 1] A multilayer substrate (20) including a substrate surface (21), a substrate back surface (22) opposite to the substrate surface (21), a surface conductive layer (30) provided on the substrate surface (21), a back surface conductive layer (70) provided on the substrate back surface (22), and a first power supply terminal (26) electrically connected to the surface conductive layer (30); and a light-emitting element (150) electrically connected to the surface conductive layer (30), wherein the surface conductive layer (30) includes first power supply wiring (40) electrically connecting the first power supply terminal (26) and the light-emitting element (150), the first power supply wiring (40) including a plurality of pad regions (46) for mounting elements, and the multilayer substrate (20) including pad heat dissipation vias (90) provided in the multilayer substrate (20), The light emitting device (10) is configured such that the pad heat dissipation via (90) is provided at a position overlapping both the pad region (46) and the back surface conductive layer (70) in a plan view.

[0349] [Appendix 2] The light-emitting device according to Appendix 1, further comprising a current-limiting resistor (300) that limits a current flowing through the first power supply wiring (40), wherein the plurality of pad regions (46) include resistor pad regions (46A to 46C), and the current-limiting resistor (300) is mounted in the resistor pad (46A to 46C) region.

[0350] [Supplementary Note 3] The light-emitting device according to Supplementary Note 1 or 2, further comprising a protection diode (310) for protecting the light-emitting element (150), wherein the plurality of pad regions (46) includes a diode pad region (46D), and the protection diode (310) is mounted on the diode pad region (46D).

[0351] [Appendix 4] The light-emitting device according to any one of Appendices 1 to 3, wherein the pad heat dissipation via (90) is arranged at a distance from the first power wiring (40) in the thickness direction (Z) of the multilayer substrate (20).

[0352] [Appendix 5] The light-emitting device according to Appendix 4, wherein the pad heat dissipation via (90) includes: a front-side pad via (90A) arranged at a distance from the first power supply wiring (40) closer to the back surface conductive layer (70) in the thickness direction (Z) of the multilayer substrate (20); and a back-side pad via (90B) arranged closer to the back surface conductive layer (70) than the front-side pad via (90A) in the thickness direction (Z), and connected to the back surface conductive layer (70), wherein the front-side pad via (90A) and the back surface pad via (90B) are individually arranged.

[0353] [Appendix 6] The light-emitting device according to Appendix 5, wherein a plurality of the front-side pad vias (90A) and a plurality of the back-side pad vias (90B) are provided, and an arrangement pitch (P2) of the plurality of back-side pad vias (90B) is smaller than an arrangement pitch (P1) of the plurality of the front-side pad vias (90A).

[0354] [Supplementary Note 7] The light emitting device according to Supplementary Note 6, wherein the number of the rear surface side pad vias (90B) is greater than the number of the front surface side pad vias (90A).

[0355] [Appendix 8] The light-emitting device according to any one of Appendices 5 to 7, wherein the multilayer substrate (20) includes an intermediate conductive layer (60A-60D) provided between the surface conductive layer (30) and the back surface conductive layer (70) in a thickness direction (Z) of the multilayer substrate (20), the surface side pad via (90A) and the back surface side pad via (90B) are spaced apart in the thickness direction (Z), and both the surface side pad via (90A) and the back surface side pad via (90B) are connected to the intermediate conductive layer (60D).

[0356] [Appendix 9] The light-emitting device according to appendix 8, wherein the intermediate conductive layers (60A to 60D) are provided at intervals in the thickness direction (Z) of the multilayer substrate (20), and the surface-side pad via (90A) is connected to the intermediate conductive layers (60A to 60D).

[0357] [Appendix 10] The light-emitting device according to appendix 9, wherein the multilayer substrate (20) includes a plurality of substrate insulating layers (80), the plurality of substrate insulating layers (80) include a back-side substrate insulating layer (82) on which the back-side conductive layer (70) is provided, and one intermediate conductive layer (60D) of the plurality of intermediate conductive layers (60A to 60D) is in contact with a surface of the back-side substrate insulating layer (82) opposite to a surface on which the back-side conductive layer (70) is provided.

[0358] [Appendix 11] The light-emitting device according to appendix 10, wherein the multilayer substrate (20) includes a plurality of substrate insulating layers (80), and the plurality of substrate insulating layers (80) include intermediate substrate insulating layers (83A to 83D) on which the intermediate conductive layers (60A to 60D) are provided, and a surface-side substrate insulating layer (81) on which the surface conductive layer (30) is provided, and the thickness of the surface-side substrate insulating layer (81) is thinner than the thickness of the intermediate substrate insulating layers (83A to 83D).

[0359] [Appendix 12] The light-emitting device according to appendix 11, wherein the thickness of the front-side substrate insulating layer (81) is 0.1 mm or less.

[0360] [Appendix 13] The light emitting device according to any one of appendices 8 to 12, wherein the thickness (TS) of the front surface side pad via (90A) is greater than the thickness (TR) of the back surface side pad via (90B).

[0361] [Appendix 14] The light-emitting device according to any one of Appendices 5 to 13, wherein a distance (D1) between the surface-side pad via (90A) and the substrate surface (21) in the thickness direction (Z) of the multilayer substrate (20) and a distance (D2) between the surface-side pad via (90A) and the substrate back surface (22) in the thickness direction (Z) are equal to each other.

[0362] [Appendix 15] The light-emitting device according to any one of Appendices 1 to 14, wherein the multilayer substrate (20) includes a first element heat dissipation via (97) provided within the multilayer substrate (20), and the first element heat dissipation via (97) is provided in a position that overlaps both the area in which the light-emitting element (150) is arranged and the back surface conductive layer (70) in a planar view.

[0363] [Appendix 16] The light-emitting device described in Appendix 15, wherein the first element heat dissipation via (97) is arranged at a distance from both the surface conductive layer (30) and the back conductive layer (70) in the thickness direction (Z) of the multilayer substrate (20).

[0364] [Appendix 17] The light-emitting device according to appendix 15 or 16, wherein the multilayer substrate (20) includes an intermediate conductive layer (60A-60D) provided between the surface conductive layer (30) and the back conductive layer (70) in the thickness direction (Z) of the multilayer substrate (20), the surface conductive layer (30) includes a second power supply wiring (47) provided at a distance from the first power supply wiring (40) and electrically connected to the light-emitting element (150), and a first element connection via (86) provided closer to the surface conductive layer (30) than the first element heat dissipation via (97) in the thickness direction (Z) of the multilayer substrate (20), connecting the second power supply wiring (47) and the intermediate conductive layer (60A).

[0365] [Appendix 18] The light-emitting device according to Appendix 17, wherein a plurality of the first element heat dissipation vias (97) and a plurality of the first element connection vias (86) are provided, and the arrangement pitch (P4 to P6) of the plurality of first element connection vias (86) is different from the arrangement pitch (P3) of the plurality of first element heat dissipation vias (97).

[0366] [Appendix 19] A light-emitting device as described in Appendix 17 or 18, wherein the first element heat dissipation via (97) and the first element connection via (86) are spaced apart from each other in the thickness direction (Z), and both the first element heat dissipation via (97) and the first element connection via (86) are connected to the intermediate conductive layer (60A).

[0367] [Appendix 20] The light-emitting device according to appendix 19, wherein the intermediate conductive layers (60A to 60D) are provided in a plurality spaced apart relation to each other in the thickness direction (Z) of the multilayer substrate (20), and the first element heat dissipation via (97) is connected to the plurality of intermediate conductive layers (60A to 60D).

[0368] [Supplementary Note 21] The light emitting device according to Supplementary Note 19 or 20, wherein a thickness (TT1) of the first element heat dissipation via (97) is greater than a thickness (TC) of the first element connection via (86).

[0369] [Appendix 22] The light-emitting device according to any one of Appendices 19 to 21, wherein the multilayer substrate (20) includes a plurality of substrate insulating layers (80), and the plurality of substrate insulating layers (80) include intermediate substrate insulating layers (83A to 83D) on which the intermediate conductive layers (60A to 60D) are provided, and a back surface side substrate insulating layer (82) on which the back surface conductive layer (70) is provided, and the thickness of the back surface side substrate insulating layer (82) is thinner than the thickness of the intermediate substrate insulating layers (83A to 83D).

[0370] [Appendix 23] The light emitting device according to appendix 22, wherein the rear substrate insulating layer (82) has a thickness of 0.1 mm or less.

[0371] [Appendix 24] A light-emitting device according to any one of Appendices 16 to 23, wherein the distance (D3) between the first element heat dissipation via (97) and the substrate surface (21) in the thickness direction (Z) of the multilayer substrate (20) and the distance (D4) between the first element heat dissipation via (97) and the substrate back surface (22) in the thickness direction (Z) are equal to each other.

[0372] [Appendix 25] The light-emitting device according to any one of Appendices 1 to 24, wherein the surface conductive layer (30) includes a third power supply wiring (50) electrically connected to the back surface conductive layer (70), and the light-emitting device is provided with a first heat dissipation member (340) connected to the first power supply wiring (40) and the third power supply wiring (50), and the first heat dissipation member (340) is arranged adjacent to the plurality of pad regions (46) in a planar view.

[0373] [Supplementary Note 26] The light emitting device according to Supplementary Note 25, wherein the first heat dissipation member (340) is configured to have a thermal conductivity of 100 W / m / K or more.

[0374] [Supplementary Note 27] The light emitting device according to Supplementary Note 25 or 26, wherein the pad heat dissipation via (90) is provided at a position different from that of the first heat dissipation member (340) in a plan view.

[0375] [Appendix 28] The light-emitting device according to any one of Appendices 1 to 24, wherein the surface conductive layer (30) includes: a second power supply wiring (47) that is provided at a distance from the first power supply wiring (40) and electrically connected to the light-emitting element (150); and a third power supply wiring (50) that is electrically connected to the back surface conductive layer (70), and further includes a second heat dissipation member (350) that is connected to the second power supply wiring (47) and the third power supply wiring (50), and the second heat dissipation member (350) is disposed in a position adjacent to the light-emitting element (150).

[0376] [Supplementary Note 29] The light emitting device according to Supplementary Note 28, wherein the second heat dissipation member (350) is configured to have a thermal conductivity of 100 W / m / K or more.

[0377] [Supplementary Note 30] The light-emitting device according to any one of Supplementary Notes 1 to 29, further comprising a driving circuit (200) connected to the surface conductive layer (30) and configured to drive the light-emitting element (150).

[0378] [Supplementary Note 31] The light-emitting device according to Supplementary Note 30, wherein the driving circuit (200) includes: a transistor (210) configured to control driving of the light-emitting element (150); and a capacitor (220) configured to supply current to the light-emitting element (150).

[0379] [Supplementary Note 32] The surface conductive layer (30) includes a second power supply wiring (47) provided at a distance from the first power supply wiring (40) and electrically connected to the light emitting element (150), and the multilayer substrate (20) includes: intermediate conductive layers (60A-60D) provided between the surface conductive layer (30) and the back surface conductive layer (70) in the thickness direction (Z) of the multilayer substrate (20), and first element connection vias (86) provided at positions overlapping both the second power supply wiring (47) and the back surface conductive layer (70) in a planar view, the intermediate conductive layers (60A-60D) include intermediate wirings (61A-61D) provided at positions overlapping both the light emitting element (150) and the drive circuit (200) in a planar view, and the intermediate wirings (61A-61D) are electrically connected to the second power supply wiring (47) by the first element connection vias (86), 32. The light-emitting device according to claim 31, further comprising a second element connection via (87) that electrically connects the intermediate wiring (61A) and the transistor (210).

[0380] [Appendix 33] The light-emitting device according to Appendix 32, wherein a plurality of the intermediate conductive layers (60A to 60D) are provided at intervals in the thickness direction (Z), a plurality of the intermediate wirings (61A to 61D) are provided at intervals in the thickness direction (Z), the plurality of intermediate wirings (61A to 61D) are arranged in positions where they overlap each other in a planar view, the multilayer substrate (20) includes a first element heat dissipation via (97) provided in the multilayer substrate (20), and the first element heat dissipation via (97) is provided in a position where it overlaps both an area where the light-emitting element (150) is arranged and the back surface conductive layer (70) in a planar view, and connects the plurality of the intermediate wirings (61A to 61D).

[0381] [Supplementary Note 34] The light-emitting device according to Supplementary Note 33, wherein the multilayer substrate (20) includes a plurality of substrate insulating layers (80), the plurality of substrate insulating layers (80) include a back-side substrate insulating layer (82) on which the back-side conductive layer (70) is provided, the plurality of intermediate wirings (61A to 61D) include a back-side intermediate wiring (61D) in contact with a surface of the back-side substrate insulating layer (82) opposite to a surface on which the back-side conductive layer (70) is provided, and the area of ​​the back-side intermediate wiring (61D) is set to be 10% or less of the output capacitance of the transistor (210) in a plan view.

[0382] [Appendix 35] The light-emitting device according to any one of Appendices 32 to 34, wherein the surface conductive layer (30) comprises: a third power supply wiring (50) electrically connected to the back surface conductive layer (70); and a drain wiring (55) provided at a distance from the third power supply wiring (50) and electrically connected to a drain (214) of the transistor (210), wherein a source (213) of the transistor (210) is electrically connected to the third power supply wiring (50), and the second element connection via (87) connects the drain wiring (55) and the intermediate wiring (61A).

[0383] [Appendix 36] The light-emitting device according to any one of Appendices 32 to 35, wherein the multilayer substrate (20) includes a second element heat dissipation via (98) provided within the multilayer substrate (20), and the second element heat dissipation via (98) is provided at a position that overlaps both a region (RB) in which the transistor (210) is arranged and the back surface conductive layer (70) in a planar view.

[0384] [Supplementary Note 37] The light emitting device according to Supplementary Note 36, wherein both the second element connection via (87) and the second element heat dissipation via (98) are connected to the intermediate conductive layer (60A).

[0385] [Appendix 38] The light-emitting device according to Appendix 37, wherein the intermediate conductive layers (60A to 60D) are provided in a plurality spaced apart relation to each other in the thickness direction (Z) of the multilayer substrate (20), and the second element heat dissipation via (98) is connected to the plurality of intermediate conductive layers (60A to 60D).

[0386] [Appendix 39] A light-emitting device according to any one of Appendices 36 to 38, wherein the distance (D5) between the second element heat dissipation via (98) and the substrate surface (21) in the thickness direction (Z) of the multilayer substrate (20) and the distance (D6) between the second element heat dissipation via (98) and the substrate back surface (22) in the thickness direction (Z) are equal to each other.

[0387] [Appendix 40] The light-emitting device according to Appendix 31, wherein, in a plan view, the light-emitting element (150), the transistor (210), and the capacitor (220) are arranged spaced apart from each other in a first direction (Y), and the capacitor (220) is arranged between the light-emitting element (150) and the transistor (210).

[0388] [Supplementary Note 41] The light-emitting device according to Supplementary Note 40, wherein a plurality of the capacitors (210) are provided, and the plurality of capacitors (210) are arranged in a second direction (X) perpendicular to the first direction (Y) in a planar view.

[0389] [Supplementary Note 42] The light-emitting device according to Supplementary Note 41, wherein the number of the capacitors (220) is six or more.

[0390] [Appendix 43] The light-emitting device according to any one of Appendices 40 to 42, wherein the capacitor (220) is a ceramic capacitor.

[0391] [Supplementary Note 44] The light-emitting device according to Supplementary Note 31, wherein the transistor (210) comprises a lateral transistor.

[0392] [Supplementary Note 45] The light-emitting device according to Supplementary Note 44, wherein the lateral transistor (210) includes a nitride semiconductor.

[0393] [Supplementary Note 46] The light-emitting device according to Supplementary Note 31, further comprising a gate driver (230) mounted on the surface conductive layer (30) and controlling the transistor (210).

[0394] [Supplementary Note 47] The light-emitting device according to Supplementary Note 46, further comprising a signal input terminal (28) electrically connected to the gate driver (230), wherein the surface conductive layer (30) includes: a first gate wiring (56) electrically connecting the gate (215) of the transistor (210) and the gate driver (230); and a second gate wiring (57) electrically connecting the gate driver (230) and the signal input terminal (28).

[0395] [Appendix 48] The multilayer substrate (20) comprises intermediate conductive layers (60A-60D) provided between the surface conductive layer (30) and the back surface conductive layer (70) in the thickness direction (Z) of the multilayer substrate (20), and a second power supply terminal (27) electrically connected to the gate driver (230), wherein the surface conductive layer (30) includes: a third power supply wiring (50) electrically connected to the back surface conductive layer (70); and a drain wiring (55) provided at a distance from the third power supply wiring (50) and electrically connected to a drain (214) of the transistor (210), wherein a source (213) of the transistor (210) is electrically connected to the third power supply wiring (50), and the intermediate conductive layer (60A) includes: an intermediate wiring (61A) provided at a position overlapping both the light-emitting element (150) and the drive circuit (200) in a plan view, and a control power supply wiring (63A) provided at a distance from the intermediate wiring (61A) and electrically connected to the second power supply terminal (27).

[0396] [Appendix 49] The light-emitting device according to any one of Appendices 5 to 14, wherein the surface conductive layer (30) includes a third power supply wiring (50) electrically connected to the back surface conductive layer (70), the multilayer substrate (20) includes a plurality of through vias (89) connecting the third power supply wiring (50) and the back surface conductive layer (70), and the arrangement pitch (P1) of the surface-side pad vias (90A) is smaller than the arrangement pitch (PT) of the through vias (89).

[0397] [Appendix 50] The light-emitting device according to any one of Appendices 15 to 24, wherein the surface conductive layer (30) includes a third power supply wiring (50) electrically connected to the back surface conductive layer (70), the multilayer substrate (20) includes a plurality of through vias (89) connecting the third power supply wiring (50) and the back surface conductive layer (70), and the arrangement pitch (P4 to P6) of the first element heat dissipation vias (97) is smaller than the arrangement pitch (PT) of the through vias (89).

[0398] [Appendix 51] The light-emitting device according to Appendix 2, wherein a plurality of the resistor pad regions (46A to 46D) are provided at a distance from each other, a plurality of the current limiting resistors (300) are provided corresponding to the plurality of resistor pad regions (46A to 46D), and the plurality of current limiting resistors (300) are connected in series.

[0399] [Supplementary Note 52] The light emitting device according to Supplementary Note 51, wherein a plurality of the pad heat dissipation vias (90) are provided corresponding to a plurality of the resistor pad regions (46).

[0400] [Appendix 53] The light-emitting device according to any one of Appendices 1 to 52, wherein the multilayer substrate (20) includes a back-side insulating layer (85) provided on the back surface (22) of the substrate and covering the back-side conductive layer (70), the back-side insulating layer (85) includes an electrode opening (85A) that exposes the back-side conductive layer (70), an intermediate heat dissipation material (410) connected to the back-side conductive layer (80) through the electrode opening (85A), and a heat sink (400) connected to the intermediate heat dissipation material (410).

[0401] [Supplementary Note 54] A multilayer substrate (20) including a substrate surface (21), a substrate back surface (22) opposite to the substrate surface (21), a surface conductive layer (30) provided on the substrate surface (21), and a back conductive layer (70) provided on the substrate back surface (22); a light-emitting element (150) electrically connected to the surface conductive layer (30); a transistor (210) and a capacitor (220) connected to the surface conductive layer (30) for driving the light-emitting element (150); and a gate driver (230) for controlling the transistor (210), wherein the light-emitting element (150), the transistor (210), and the capacitor (220) are arranged in a first direction (Y) in a plan view, and the capacitor (220) is disposed between the light-emitting element (150) and the transistor (210) in the first direction (Y), the gate driver (230) is spaced apart from the transistor (210) in a second direction (X) perpendicular to the first direction (Y) in a plan view and is disposed on the opposite side of the transistor (210) from the capacitor (220) in the first direction (Y); the surface conductive layer (30) includes: first power supply wiring (40) and second power supply wiring (47) on which the light-emitting element (150) is mounted; third power supply wiring (50) electrically connected to the back surface conductive layer (70); and first gate wiring (56) electrically connecting a gate (215) of the transistor (210) and the gate driver (200); the third power supply wiring (50) includes: a drive wiring section (501) adjacent to the first power supply wiring (40) in the first direction (Y); and a first heat dissipation wiring section (502) adjacent to the drive wiring section (501) in the second direction (X); the capacitor (220) is arranged so as to straddle the first power supply wiring (40) and the drive wiring section (501) in the first direction (Y), and the multilayer substrate (20) includes: a first isolation region (510) that isolates the drive wiring section (501) and the first heat dissipation wiring section (502); and a first gate slit (53A) that isolates the first gate wiring (56) and the third power supply wiring (50),The light-emitting device (10) is provided so that the first isolation region (510) is adjacent to the capacitor (220) in the second direction (X) and communicates with the first gate slit (53A).

[0402] [Summary of Supplementary Note 54] The drive current flowing from the drive circuit to the light emitting element may affect the current loop passing through the gate driver and the gate of the transistor.

[0403] In this regard, according to Appendix 54, the first isolation region can prevent current from flowing from the drive wiring section to the first heat dissipation wiring section, thereby preventing the drive current flowing from the drive circuit to the light-emitting element from affecting the current loop passing through the gate driver and the gate of the transistor.

[0404] [Appendix 55] The light-emitting device according to Appendix 54, wherein the third power supply wiring (50) includes a second heat dissipation wiring section (503) provided on the opposite side of the drive wiring section (501) from the first heat dissipation wiring section (502), and further includes a second isolation region (520) provided on the opposite side of the capacitor (220) from the first isolation region (510) in the second direction (X) and separating the drive wiring section (501) from the second heat dissipation wiring section (503), and the second isolation region (520) is provided so as to surround the transistor (210) in a planar view.

[0405] [Appendix 56] The light-emitting device according to Appendix 55, wherein the capacitors (220) are arranged in a line in the second direction (X), and some of the capacitors (220) are arranged outward in the second direction (X) from the transistor (210) as viewed from the first direction (Y), and the second separation region (520) includes: a first separation portion (521) arranged adjacent to the capacitor (220) in the second direction (X) and extending in the first direction (Y), a second separation portion (522) arranged adjacent to the transistor (210) in the second direction (X) and extending in the first direction (Y), and a third separation portion (523) extending in the second direction (X) and connecting the first separation portion (521) and the second separation portion (522).

[0406] [Appendix 57] The light-emitting device described in Appendix 56, wherein the third separation portion (523) is provided at the same position as the end of the transistor (210) that is closer to the capacitor (220) in the first direction (Y).

[0407] [Supplementary Note 58] The light-emitting device according to Supplementary Note 56 or 57, wherein the second isolation region (520) includes a fourth isolation portion (524) extending from the second isolation portion (522) toward the gate driver (230).

[0408] [Supplementary Note 59] The light-emitting device according to Supplementary Note 58, wherein the fourth isolation portion (524) extends across the entirety of the transistor (210) in the second direction (X).

[0409] [Appendix 60] A multilayer substrate (20) including a substrate surface (21), a substrate back surface (22) opposite to the substrate surface (21), a surface conductive layer (30) provided on the substrate surface (21), and a back surface conductive layer (70) provided on the substrate back surface (22); a light-emitting element (150) connected to the surface conductive layer (30); and a transistor (210) and a capacitor (22) connected to the surface conductive layer (30) and driving the light-emitting element (150), wherein the light-emitting element (150), the transistor (210), and the capacitor (220) are arranged in a first direction (Y) in a plan view, and the capacitor (220) is disposed between the light-emitting element (150) and the transistor (210) in the first direction (Y), and the surface conductive layer (30) is connected to a first power wiring (40) and a second power wiring (47) on which the light-emitting element (150) is mounted, a third power supply wiring (50) electrically connected to the back surface conductive layer (70), wherein the third power supply wiring (50) includes: a drive wiring section (501) adjacent to the first power supply wiring (40) in the first direction (Y); and a second heat dissipation wiring section (503) adjacent to the drive wiring section (501) in a second direction (Z) perpendicular to the first direction (Y) in a planar view, wherein the capacitor (220) is arranged so as to straddle the first power supply wiring (40) and the drive wiring section (501) in the first direction (Y), and includes a second isolation region (520) separating the drive wiring section (501) and the second heat dissipation wiring section (503), wherein the second isolation region (520) is adjacent to the capacitor (220) in the second direction (X) and is provided so as to surround the transistor (210) in a planar view.

[0410] [Summary of Supplementary Note 60] The drive current flowing from the drive circuit to the light emitting element may affect the current loop passing through the gate driver and the gate of the transistor.

[0411] In this regard, according to Supplementary Note 60, the isolation region can prevent current from flowing from the drive wiring section to the heat dissipation wiring section, thereby preventing the drive current flowing from the drive circuit to the light-emitting element from affecting the current loop passing through the gate driver and the gate of the transistor.

[0412] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0413] 10...light emitting device, 20...multilayer substrate, 21...substrate surface, 22...substrate back surface, 23A-23D...first to fourth substrate side surfaces, 24...substrate mounting hole, 25...heat sink mounting hole, 25A...first mounting hole, 25B...second mounting hole, 26...first power supply through hole, 26A...first through hole, 26B...second through hole, 27...second power supply through hole, 27A...first through hole, 27B...second through hole, 28...signal through hole, 29...connector mounting hole, 30...surface conductive layer, 40...first power supply wiring, 41...first wiring portion, 41A-41C...first to third portions, 41D...recess wiring portion, 42...second wiring portion, 43...third wiring portion, 44...fourth wiring portion, 44A...first portion, 44B...second portion, 44C...recess, 45...fifth wiring portion, 46...pad area, 46A to 46C...resistor pad area, 46D...diode pad area, 46E...auxiliary resistor pad area, 46F...input capacitor pad area, 46G...light-emitting element pad area, 46H...capacitor pad area, 46J...heat dissipation member pad area, 47...second power supply wiring, 48A...narrow portion, 48B...wide portion, 48C...protruding portion, 49A...light-emitting element pad area, 49B...heat dissipation member pad area , 49C...diode pad region, 50...third power supply wiring, 51A...capacitor pad region, 51B...input capacitor pad region, 51C...heat dissipation member pad region, 51D...transistor pad region, 51E...driver pad region, 51F...pull-down resistor pad region, 51G...capacitor pad region, 52...drain opening, 53A...first gate slit, 53B...second gate slit, 53C...third gate slit, 55...drain wiring, 55A...transistor pad region, 56...first gate wiring, 56A...transistor pad region, 56B... driver pad region, 57... second gate wiring, 57A... driver pad region, 57B... pull-down resistor pad region, 58... third gate wiring, 58A... driver pad region, 58B... capacitor pad region, 60A to 60D... intermediate conductive layer, 61A to 61D... intermediate wiring, 62A to 62D... ground wiring, 62AA, 62BA, 62CA, 62DA... recess, 62AB, 62BB, 62CB, 62DB... first opening, 62AC, 62BC, 62CC, 62DC... second opening, 62AD... wiring opening, 62BD, 62DD... third opening,63A...control power supply wiring, 70...back surface conductive layer, 71...corner notch, 72...first opening, 73...second opening, 74...third opening, 80...substrate insulating layer, 81...front surface side substrate insulating layer, 82...rear surface side substrate insulating layer, 83A to 83C...intermediate substrate insulating layer, 84...front surface side insulating layer, 85...rear surface side insulating layer, 85A...electrode opening, 86...first element connecting via, 87...second element connecting via, 88...third element connecting via, 89...through via, 90...heat dissipation via for pad, 90A...front surface side pad via, 90B...rear surface side pad via, 91...heat dissipation via for resistor, 92...heat dissipation via for diode, 93...auxiliary resistor Heat dissipation vias for the diode, 94 to 96... heat dissipation vias between pads, 97... first element heat dissipation vias, 98... second element heat dissipation vias, 99... heat dissipation vias for diode, 100... light emitting module, 110... substrate, 111... substrate front surface, 112... substrate rear surface, 113 to 116... first to fourth substrate side surfaces, 120... surface conductive layer, 121... wire connection electrode, 122... first mounting pattern, 123... second mounting pattern, 124... front surface resist, 130... rear surface conductive layer, 131... first rear surface conductive layer, 132... second rear surface conductive layer, 133... rear surface resist, 134... first opening, 135... second opening, 140... through electrode, 1 41...first through electrode, 142...second through electrode, 150...light-emitting element, 151...element surface, 152...element back surface, 153...element electrode, 154...light-emitting portion, 155...back surface conductive layer, 160...submount, 161...surface, 162...back surface, 163...through electrode, 170...case, 171 to 174...first to fourth side walls, 175...upper wall, 200...drive circuit, 210...transistor, 211...element surface, 212...element back surface, 213...source electrode, 214...drain electrode, 215...gate electrode, 220...capacitor, 221...first electrode, 222...second electrode, 230...gate driver, 231...pull-down resistor, 232...capacitor, 300...current limiting resistor, 301...first terminal, 302...second terminal, 310...protection diode, 311...anode electrode, 312...cathode electrode, 313...auxiliary resistor, 314...first terminal, 315...second terminal, 320...input capacitor, 331...first power connector, 332...second power connector, 333...signal input connector, 340...first heat dissipation member, 341...first terminal, 342...second terminal, 343...heat dissipation body, 350...second heat dissipation member, 351...first terminal, 352...second terminal, 353...heat dissipation body, 400...heat sink,401...base, 402...heat dissipation fin, 410...intermediate heat dissipation material, 501...drive wiring section, 502...first heat dissipation wiring section, 503...second heat dissipation wiring section, 510...first isolation region, 520...second isolation region, 521...first isolation section, 522...second isolation section, 523...third isolation section, 524...fourth isolation section, 600...insulating member, 800...light emitting system, 801...DC power supply, 802...control power supply, 803...pulse generator, R1, R2...ground path, RA...first element arrangement area, RB...second element arrangement area, CL...center line, D1...distance between the surface side pad via of the pad heat dissipation via and the substrate surface of the multilayer substrate, D2...distance between the surface side pad via of the pad heat dissipation via and the substrate back surface of the multilayer substrate, D3...distance between the first element heat dissipation via and the Distance between the substrate surface, D4...distance between the first element heat dissipation via and the substrate back surface of the multilayer substrate, D5...distance between the second element heat dissipation via and the substrate surface of the multilayer substrate, D6...distance between the second element heat dissipation via and the substrate back surface of the multilayer substrate, P1...arrangement pitch of surface side pad vias for pad heat dissipation vias, P2...arrangement pitch of back side pad vias for pad heat dissipation vias, P3...arrangement pitch of first element heat dissipation vias, P4 to P6, P9...arrangement pitch of first element connection vias, P7, P8...arrangement pitch of second element heat dissipation vias, PT...arrangement pitch of through vias, TS...thickness of surface side pad vias, TR...thickness of back side pad vias, TT1...thickness of first element heat dissipation vias, TT2...thickness of second element heat dissipation vias, TC...thickness of first element connection vias, WR...wire.

Claims

1. A light-emitting device comprising: a multilayer substrate including a substrate surface, a substrate back surface opposite the substrate surface, a surface conductive layer provided on the substrate surface, a back conductive layer provided on the substrate back surface, and a first power supply terminal electrically connected to the surface conductive layer; and a light-emitting element electrically connected to the surface conductive layer, wherein the surface conductive layer includes first power supply wiring electrically connecting the first power supply terminal and the light-emitting element, the first power supply wiring including a plurality of pad areas for mounting elements, the multilayer substrate including pad heat dissipation vias provided within the multilayer substrate, and the pad heat dissipation vias are provided in a position overlapping both the pad area and the back conductive layer in a planar view.

2. The light emitting device according to claim 1, further comprising a current limiting resistor that limits the current flowing through the first power supply wiring, wherein the plurality of pad areas include a resistor pad area, and wherein the current limiting resistor is mounted on the resistor pad area.

3. The light emitting device according to claim 1 or 2, further comprising a protection diode for protecting the light emitting element, wherein the plurality of pad regions include a diode pad region, and the protection diode is mounted on the diode pad region.

4. The light emitting device according to any one of claims 1 to 3, wherein the pad heat dissipation via is disposed at a distance from the first power supply wiring in the thickness direction of the multilayer substrate.

5. A light-emitting device as described in claim 4, wherein the pad heat dissipation via includes a front-side pad via arranged at a distance from the first power supply wiring and closer to the back surface conductive layer in the thickness direction of the multilayer substrate, and a back-side pad via arranged closer to the back surface conductive layer than the front-side pad via in the thickness direction and connected to the back surface conductive layer, and the front-side pad via and the back-side pad via are arranged separately.

6. The light emitting device according to claim 5, wherein a plurality of the front surface side pad vias and a plurality of the back surface side pad vias are provided, and the arrangement pitch of the plurality of back surface side pad vias is smaller than the arrangement pitch of the plurality of the front surface side pad vias.

7. The light emitting device according to claim 6, wherein the number of the rear surface side pad vias is greater than the number of the front surface side pad vias.

8. A light-emitting device described in any one of claims 5 to 7, wherein the multilayer substrate includes an intermediate conductive layer provided between the front conductive layer and the back conductive layer in the thickness direction of the multilayer substrate, the front side pad via and the back side pad via are spaced apart in the thickness direction, and both the front side pad via and the back side pad via are connected to the intermediate conductive layer.

9. The light emitting device according to claim 8, wherein a plurality of the intermediate conductive layers are provided spaced apart from each other in the thickness direction of the multilayer substrate, and the surface side pad via is connected to a plurality of the intermediate conductive layers.

10. A light-emitting device as described in claim 9, wherein the multilayer substrate includes a plurality of substrate insulating layers, the plurality of substrate insulating layers including a back-side substrate insulating layer on which the back-side conductive layer is provided, and one of the plurality of intermediate conductive layers is in contact with the surface of the back-side substrate insulating layer opposite to the surface on which the back-side conductive layer is provided.

11. A light-emitting device as described in claim 10, wherein the plurality of substrate insulating layers include an intermediate substrate insulating layer provided with the intermediate conductive layer, and a surface-side substrate insulating layer provided with the surface conductive layer, and the thickness of the surface-side substrate insulating layer is thinner than the thickness of the intermediate substrate insulating layer.

12. The light emitting device according to claim 11, wherein the thickness of the front substrate insulating layer is 0.1 mm or less.

13. The light emitting device according to any one of claims 8 to 12, wherein the thickness of the front surface side pad via is greater than the thickness of the rear surface side pad via.

14. A light-emitting device described in any one of claims 5 to 13, wherein the distance between the surface-side pad via and the surface of the substrate in the thickness direction of the multilayer substrate is equal to the distance between the surface-side pad via and the back surface of the substrate in the thickness direction.

15. A light-emitting device according to any one of claims 1 to 14, wherein the multilayer substrate includes a first element heat dissipation via provided within the multilayer substrate, and the first element heat dissipation via is provided in a position that overlaps both the area in which the light-emitting element is arranged and the back surface conductive layer in a planar view.

16. The light emitting device according to claim 15, wherein the first element heat dissipation via is disposed apart from both the front surface conductive layer and the back surface conductive layer in the thickness direction of the multilayer substrate.

17. A light-emitting device as described in claim 15 or 16, wherein the multilayer substrate includes an intermediate conductive layer provided between the front surface conductive layer and the back surface conductive layer in the thickness direction of the multilayer substrate, the front surface conductive layer includes a second power supply wiring provided at a distance from the first power supply wiring and electrically connected to the light-emitting element, and a first element connection via provided closer to the front surface conductive layer than the first element heat dissipation via in the thickness direction of the multilayer substrate, connecting the second power supply wiring and the intermediate conductive layer.

18. A light emitting device as described in claim 17, wherein a plurality of the first element heat dissipation vias and a plurality of the first element connection vias are provided, and the arrangement pitch of the plurality of the first element connection vias is different from the arrangement pitch of the plurality of the first element heat dissipation vias.

19. A light-emitting device as described in claim 17 or 18, wherein the first element heat dissipation via and the first element connection via are spaced apart from each other in the thickness direction, and both the first element heat dissipation via and the first element connection via are connected to the intermediate conductive layer.

20. A light-emitting device as described in claim 19, wherein a plurality of the intermediate conductive layers are provided spaced apart from each other in the thickness direction of the multilayer substrate, and the first element heat dissipation via is connected to a plurality of the intermediate conductive layers.

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