Processor architecture for accelerating neural network feedforward calculation

Abstract

The present technical solution relates generally to the field of computing, and more particularly to computing device architectures. A processor architecture for accelerating artificial neural network feedforward calculation comprises at least one control device capable of transmitting control flows to executing devices and controlling pipeline task execution dependencies; at least one array processor which contains two read ports and is capable of providing an uninterrupted data flow to a matrix multiplication module; at least one vector processor capable of performing operations on two-dimensional tensor slices, including data decimation and depthwise separable convolution; and at least one device for directly accessing an external memory, said device being capable of writing and reading data. The technical result achieved in solving the technical problem of interest is that of increasing scalability, reducing response time, improving the efficiency of hardware utilization for different neural network graphs, and reducing the local memory required and the number of external memory requests, thus leading to a reduction in energy consumption and external memory access rate requirements.

Description

PROCESSOR ARCHITECTURE FOR ACCELERATION OF FORWARD-LOOKING CALCULATORS OF NEURAL NETWORKS AREA OF TECHNOLOGY

[0001] This technical solution generally relates to the field of computing, and in particular to the architecture of computing devices. LEVEL OF TECHNOLOGY

[0002] Artificial intelligence is currently being challenged by the ever-growing volume of data and the high demands on the speed of response. Modern AI services, such as voice-activated assistance, email spam filters, and engines for generating movie and product recommendations, are becoming increasingly complex. The neural networks they power require 10 times more computation than they did just a year ago. Modern central processors are unable to respond quickly to AI service requests, which negatively impacts the user experience. ESSENCE OF THE INVENTION

[0003] This technical solution for accelerating the forward calculation of artificial neural networks provides the performance, energy efficiency, and response time required for next-generation artificial intelligence products and services in cloud storage, data centers, onboard vehicles, and other end-user devices.

[0004] The technical task or technical problem solved in this technical solution is the efficient implementation of a hardware accelerator for calculating the forward path of convolutional and recurrent neural networks, with greater efficiency (hardware utilization) and energy efficiency than graphic processing units (GPUs).

[0005] The technical result achieved by solving the above technical problem is an improvement in scalability, response time and efficiency of using the processor's computing cores for various neural network graphs, a reduction in the required local memory and the number of accesses to external memory, which leads to a reduction in energy consumption and requirements for access speed to external memory.

[0006] The specified technical result is achieved by implementing a processor architecture for accelerating the calculation of the forward progress of artificial neural networks, which contains at least one control device configured to transmit control flows to executive devices and control the dependencies of the execution of tasks by conveyors; at least one matrix processor, which contains two reading ports, configured to provide an uninterrupted data flow to the matrix multiplication module; at least one vector processor configured to perform operations working with sections of tensors in two dimensions, which include data thinning and convolution with division by depth; at least one device for direct access to external memory, configured to write and read data.

[0007] In some embodiments of the invention, the control device comprises a control core and conveyor control modules.

[0008] In some embodiments of the invention, the control core contains a set of configuration registers accessible through a memory access interface and necessary for controlling the device.

[0009] In some embodiments of the invention, the shared memory is implemented in the form of a multi-port multi-bank memory (hereinafter referred to as shared memory) with software-based resolution of memory access conflicts.

[0010] In some embodiments of the invention, all computing devices have equal access to all cells of the shared memory.

[0011] In some embodiments of the invention, the shared memory has N banks of equal depth and width, Nr read ports, Nw write ports of equal width with fixed latency.

[0012] In some embodiments of the invention, reading / writing to the same bank at different addresses from different read / write ports in the same cycle is prohibited in the shared memory.

[0013] In some embodiments of the invention, the memory banks are made dual-port (independent read and write ports in one memory bank) and / or single-port (multiplexed read / write port).

[0014] In some embodiments of the invention, some actuators comprise tensor sampling units configured to transpose the tensor, sampling columns for the convolution operation from the entire tensor or a portion thereof.

[0015] In some embodiments of the invention, the block is used to form columns for a convolution operation.

[0016] In some embodiments of the invention, the ports of the matrix processor are configured by specifying a base address and a read algorithm template.

[0017] In some embodiments of the invention, the matrix processor comprises a matrix multiplier unit, which is a systolic array of elementary computing devices. BRIEF DESCRIPTION OF DRAWINGS

[0018] The features and advantages of this technical solution will become apparent from the following detailed description and the accompanying drawings, in which:

[0019] Fig. 1 shows a simplified structure of the processor.

[0020] Fig. 2 shows the architecture of the universal tensor sampling block.

[0021] Fig. 3 shows an embodiment of a device for loading and unloading tensors.

[0022] Fig. 4 shows an embodiment of a matrix processor.

[0023] Fig. 5 shows an example of the implementation of an elementary computing device of a systolic array.

[0024] Fig. 6 shows a simplified implementation of a systolic array of N by N calculators.

[0025] Fig. 7 shows an embodiment of the control and management device.

[0026] Fig. 8 shows an embodiment of a vector processor. DETAILED DESCRIPTION

[0027] This technical solution can be implemented in a separate microcircuit together with a computer or other data processing device in the form of a computing device architecture.

[0028] The technical solution can be implemented in a distributed computer system (centralized or decentralized), the components of which are cloud or local servers.

[0029] This technical solution can be implemented in a system-on-chip (SoC) in the form of a computing module architecture.

[0030] In this solution, the term “system” refers to a computer system or automated system (AS), a computer (electronic computer), a numerical control (CNC), a PLC (programmable logic controller), a FPGA (programmable logic integrated circuit), a VLSI (very large-scale integrated circuit), a computerized control system, and any other devices capable of performing a given, clearly defined sequence of computing operations (actions, instructions).

[0031] A control device is an electronic unit or integrated circuit (microprocessor) that executes machine instructions (programs).

[0032] The command processing unit reads and executes machine instructions (programs) from one or more storage devices.

[0033] A program is a sequence of instructions intended for execution by various executive devices, and the control unit delivers this program from memory to the executive devices. devices, checks readiness and monitors the order of command execution.

[0034] This processor architecture enables multithreaded data processing using multiple execution units (EUs). Control of the command execution sequence is then moved to the program compilation stage for the unit. In an exemplary implementation, the processor architecture may contain the following set of execution units (EUs): - at least one matrix processor; - at least one vector processor; - direct access devices to external memory (abbr. DAD).

[0035] However, this list of UI is not exhaustive, since the processor architecture allows for the inclusion of other UI that correspond to the operating principles of the device described below.

[0036] Data exchange between the EDs is accomplished by writing / reading data to / from shared memory via a coordinated data exchange interface. In this particular implementation, the shared memory is implemented as a multi-port, multi-bank memory with software-based memory access conflict resolution. However, other implementations of this memory are also possible, as is obvious to those skilled in the art. This memory is described in more detail below.

[0037] The configuration of the ED is carried out using the control unit. The processor consists of several pipelines that perform data processing. Before transmitting the processed data to the pipeline input, all of its execution units (e.g., a matrix processor, a vector processor, etc.) must be configured, i.e., switched to the required mode. This setup is performed using a control flow - a program transmitted to the port of the execution unit as a sequence of configuration words. The set of control flows required to configure all the units of a single pipeline to process a fixed-size data stream is called a task. Tasks can be dependent on one another, i.e., have dependencies (e.g., (Before one task unloads data from memory, another task must ensure that the data is written to memory.) The control unit is designed to transmit control flows to the execution units and to monitor the dependencies of task execution on the conveyors.

[0038] A simplified structural diagram of the technical solution for a processor to accelerate the calculation of the forward motion of artificial neural networks is shown in Fig. 1. It consists of the following blocks:

[0039] A control device (101) that ensures the coordinated operation of all other processor units during the execution of the program for calculating the forward motion of an artificial neural network.

[0040] The core of the service microcontroller (102), which configures, manages and controls complex functional blocks included in the technical solution.

[0041] JTAG Debug Interface (103)

[0042] Matrix multiplier (104) based on a systolic array of elementary calculators.

[0043] Scalar processor (105) used to accumulate partial sums.

[0044] A planar processor (106) that performs subsampling, normalization, reduction and other operations on two-dimensional matrices

[0045] Element-by-element processor (107) that performs element-by-element operations - activations.

[0046] Data transfer unit (108) used to transfer data between the RAM and the built-in multi-port memory of the device.

[0047] System bus switch (109)

[0048] External interfaces: SPI (110), UART (111), PC1e (112) and others.

[0049] Shared memory block (113).

[0050] DDR (114) RAM Controller

[0051] Matrix Processor Block (115)

[0052] Vector processor block (116).

[0053] To calculate the forward motion of artificial neural networks, it is necessary to have a sufficient number of on-chip Memory for storing operands and computation results. There are different types of operands (features, convolution weights, DWS weights, biases, multipliers, partial sums) that must be simultaneously fed to the computing units (weights and features for convolution), transferred between computing units during processing, and loaded and unloaded into external memory. Depending on the task (neural network layer), the ratio of the number of different operand types may vary. Therefore, in a specific implementation, shared memory (113) is used as an on-chip buffer, where each computing unit can continuously access any memory cell.

[0054] The memory has N memory banks of equal depth and width, Nr read ports, and Nw write ports of equal width with fixed latency. In general, N != Nw != Nr, meaning it can take on any value.

[0055] Fig. 1 shows a variant of the module implementation with N = 8, Nr = 2, Nw = 2. The three most significant bits of the address specify the path along the switching tree from each port to the memory banks. Since it is assumed that only one port has access to a memory bank at each clock cycle, a logical OR operation can be applied to requests from all ports to a specific memory bank. Each read or write port has continuous access to the entire memory array. Memory access is organized such that reading from / writing to the same bank at different addresses is prohibited from different read / write ports during a single clock cycle. Resolution of such access conflicts is performed at the control level of devices using the on-chip memory unit. This memory architecture reduces the hardware overhead of its implementation due to the possibility of using single-port memory macroblocks.

[0056] Memory banks can be implemented as either dual-port (independent read and write ports in a single memory bank) or single-port (multiplexed read / write port). The multi-port architecture of the on-chip memory device effectively solves the problem of distributing memory between computing modules, operands within one computing module, as well as data transfer between modules.

[0057] Computational modules require different traversal orders for the input tensor from shared memory. Therefore, each computational module includes a universal tensor loader / unloader, as shown in Fig. 2. This unit can be used to perform tensor transposition and select columns for the convolution operation from the entire tensor or a portion of it.

[0058] In this particular case, the tensor loader / unloader is used to form columns for the 20-fold and depth-separated convolution operations. During tensor sampling, the specified axes are padded. The required sampling algorithms can be represented as several nested address generation loops.

[0059] Fig. 2 shows a block diagram of a device for tensor sampling from shared memory, which consists of the following functional blocks.

[0060] Six-dimensional tensor index calculator (201), padding detector (202), base address calculator (203), tensor element address calculator (204).

[0061] The shared memory tensor fetcher is used to transform the shape and size of a multidimensional tensor when reading and writing the tensor from and to shared memory.

[0062] The input accepts tuples of the following values: Shape, number of elements, alternation (205). Indent shape (206). Step of address change along the dimensions of the multidimensional tensor (207), address of the filling value (208).

[0063] Fig. 3 shows a block diagram of a variant of the tensor loading and unloading device. This device consists of the following blocks:

[0064] DRAM Write Address Generator (301).

[0065] RAM Read Address Generator (302).

[0066] Direct Access Memory (DAM) Controller (303).

[0067] On-chip memory write address generator (304)

[0068] Shared Memory Read Address Generator (305).

[0069] FIFO buffer for data read from shared memory (306).

[0070] The operating algorithm of the tensor load / unload device in the tensor loading mode from RAM: the tensor attributes (shape, size, base address in RAM, padding and fill shape) are fed to the shared memory read address generator (305), which in turn generates a sequence of addresses and task settings for the PDP controller (303), which in turn fetches data from the bidirectional RAM access bus (315) mapped into the shared address space. At the same time, the attributes of the recipient tensor (309) in shared memory are fed to the shared memory write address generator (304), which in turn generates a sequence of addresses in shared memory (312). Data transfer for shared memory (314) is synchronized with the address sequence (312).

[0071] The operating algorithm of the tensor load / unload unit in the tensor unloading mode into RAM: the attributes of the tensor (its mapping in RAM) (307) are fed to the write address generator (301), which in turn generates a sequence of addresses and task settings for the PMA controller (303), which in turn loads the data into the bidirectional RAM access bus (315) mapped into the shared address space. Read addresses from the shared memory (311) are generated based on the attributes of the original tensor (310) by the read address generator (305). To match the bandwidths of the shared and RAM memories, a FIFO buffer (305) is used in the data transmission channel from the shared memory to the PMA controller (313). The tensor load / unload unit (LSU) is designed to load tensors from external memory into the shared memory and to unload them. During the process of transferring tensors, transposition can be applied to them.It is also possible to multiply tensors.

[0072] The shared memory access speed is more than twice the DRAM access bandwidth, so it is possible to multiplex two DRAM channels using only one shared memory port.

[0073] There are two possible multiplexing scenarios: • The LSU types a word to be written to memory over two clock cycles. Memory port accesses alternate between the two LSUs each clock cycle, allowing writing to multiple shared memory banks simultaneously. • The two LSUs are synchronized to produce one data word each clock cycle, utilizing the entire external DRAM bus bandwidth.

[0074] The unit receives all necessary parameters, such as address generation algorithms, aggregation of LSU modules and base addresses, in the form of a microcommand from the control device.

[0075] Fig. 4 shows an embodiment of a matrix processor, which consists of the following blocks:

[0076] The matrix processor control device (401) carries out coordinated control of all functional blocks of the matrix processor.

[0077] The matrix multiplication block (410), which in turn consists of: a systolic array (402) of elementary calculators, a data type conversion block (403), a time shift alignment block (404), data feeders (407) from the general memory (409), and blocks for forming a ladder delay of data (406).

[0078] A scalar operations block (411), which in turn consists of: a scalar processor (405) performing element-by-element multiplication / addition of the result of matrix multiplication by the scaling and offset coefficients, as well as a feeder (407) from the common memory (409) and a recording block (408) into the common memory (409).

[0079] Fig. 5 shows the structural diagram of an elementary calculator that performs a multiplication and accumulation operation. The input latch register block (501) latches the input operand "B" (504). The input operand "A" (502) is fed to the multiplier and, through a one-cycle delay cell, to the output (503), usually connected to the input "A" of the next elementary calculator in the series. The partial sum input (505) is connected to the adder, the output of which, with the result of the sum of the partial sum input and the result of the multiplication of operand “A” and operand “B”, goes through a delay cell for one clock cycle to the partial sum output y (507), which in turn is usually connected to the partial sum input of the next elementary calculator in the column.

[0080] The operating principle of the systolic array of elementary calculators is demonstrated in Figure 6. In the first phase, the "B" operands are loaded into the latch registers of the corresponding elementary calculators. In the second phase, the "A" operand is loaded with step-by-step multiplication and addition, propagation of partial sums, and the resulting operation is unloaded at the column outputs.

[0081] Fig. 7 shows a structural diagram of a possible control unit organization. The example shown demonstrates a general structure with a core and one execution pipeline for two execution units (EU) (there may be many such execution pipelines, including those with different numbers of execution units).

[0082] The control device in the exemplary embodiment consists of a control core (701) and several (corresponding to the number of controlled conveyors) conveyor control modules (702). The control core contains a set of configuration registers accessible through the memory access interface (716) and necessary for device control. This core enables device operation in two modes: • direct control flow write mode, i.e. when data written to one of the configuration registers is interpreted as a control flow and transmitted to the corresponding conveyor control module; • the mode of reading the control flow from the memory, i.e. when the control core, through the memory access interface (706), ensures the loading of data from the memory, after which this data is interpreted as a control flow, which is transmitted to the corresponding pipeline control module.

[0083] In the direct control flow recording mode, the control device operates as follows: • the control module (705) is switched to the direct recording mode of the control flow; li • the control module sets the appropriate settings for the 2x1 (707) and 1xN (709) stream multiplexers; • the value written to the corresponding register of the control module is interpreted as a control flow word and is transferred to the FIFO buffer (708) via the 2x1 flow multiplexer; • from the FIFO buffer (708) through the 1xN flow multiplexer (709) the control flow is transmitted to the corresponding conveyor control module (702).

[0084] In general, the control module performs the following functions: • provides decoding of memory access interface transactions (716) and access to configuration registers; • transmits commands to the data transfer module (706) in the mode of reading the control stream from the memory; • transmits the control stream through the 2x1 stream multiplexer (701) to the input of the FIFO buffer module (708) in the direct control stream recording mode; • sets the corresponding operating mode of the flow multiplexers (modules (707) and (709)).

[0085] In the mode of reading the control flow from the memory, the control device operates as follows: • the control module is switched to the mode of reading the control flow from memory; • the control module sets the corresponding settings for the flow multiplexers (707) and (709); • the control module transmits a command to the data transfer module (706) to read data from the memory; • data read from memory is interpreted as a control stream, which is transmitted through the stream multiplexer (707) to the FIFO buffer (708); • from the FIFO buffer (708) through the flow multiplexer (709) the control flow is transmitted to the corresponding conveyor control module.

[0086] In general, the data transfer module (708) performs the following functions: • receives commands from the control module to unload data from memory; • forms control streams from the downloaded data, transmitted through the 2x1 stream multiplexer to the input of the FIFO buffer module; • in direct recording mode the control flow is not used.

[0087] One of the outputs of the flow multiplexer (709) is connected to the input of the FIFO module of the command buffer (704) of the control device, which makes it possible to use the control flow read from the memory to generate commands for the data transfer module (706).

[0088] The conveyor control module (702) can operate in three main states:

[0089] the control flow is transmitted through the FIFO buffer (710) to the address of one of the executive devices of the UI conveyor (703);

[0090] The control flow is blocked until all dependencies of the current task are resolved. The control flow is blocked by the pipeline manager module (711) after the current control flow being transmitted is identified as task dependency information. In this case, this flow is passed through the multiplexer (712) to the dependency resolution module (714), and the blocking signal is asserted.

[0091] The control flow is permitted after confirmation that all dependencies of the current task are satisfied. The basis for unblocking is the identity of the status information of tasks completed by all pipelines (712) and the dependency information of the pending task (714).

[0092] The UI pipeline (702) consists of one or more UIs (713)(714) and is characterized by the sequential passage of input data (717) to the output (718).

[0093] The completion signal generation logic (715) generates a status signal for the executed commands of the control unit pipeline.

[0094] The instruction flow must be halted if a shared memory address conflict occurs: one DI (1) has delayed its execution and has not yet retrieved data from shared memory, while another DI (2) is ready to write data to that address. In such situations, DI (2) is prevented from executing the task until DI (1) completes the task. To avoid constant pipeline stalls, at least a double buffer is allocated for each module.

[0095] The following mechanism is provided to resolve dependencies:

[0096] The ED informs the control unit of the task completion by setting the ready flag and increments the task counter (task identifier) ​​of the corresponding ED by one value. In some implementations, the task counter may have a numeric format. The control block contains a queue of command execution dependencies for each ED: a. Dependency mask (k bits), where k is the number of EDs; b. Task identifiers (task_id[0], task_id[1], ...), after the execution of which the corresponding new task can be launched. To save memory, task identifiers are transmitted only for those EDs on which the execution of the task depends.

[0097] If for each task identifier (for example, the task can be loading a data array; performing mathematical operations; unloading data, etc.) from the dependency list the condition is met: the current task identifier is greater than the one specified in the dependency list, then the command is submitted to the command queue for the corresponding control unit.

[0098] Dependencies are determined by the compiler during the neural network graph analysis phase and form an integral part of the microprocessor program. The graph is a user-generated description of the neural network. It is not used in the processor; instead, the compiler uses it to generate a set of commands and dependencies that control the microprocessor's operation. Commands are sent to the appropriate control units via the streaming interface. The criterion for initiating a command transmission is the control unit's approval for its execution.

[0099] The CUs support two types of commands: configuration commands (cfg), which contain general parameters for a series of calculations, and task commands (task), which contain parameters for a specific task. This reduces the amount of memory required to store the processor program.

[0100] The block diagram of the vector processor is shown in Fig. 8. Microinstructions from the control unit are sent to the Planar (803) and Element-by-Element (804) processor units. The Planar Processor unit (803) performs downsampling and channel-by-channel convolution operations on two-dimensional tensors: each of the incoming two-dimensional tensors is divided into sections of the same size (windows). A series of operations are performed on the numbers that fall within the window, and the result of these operations yields one number of the output tensor (for each of the windows of the input tensor). The Element-by-Element Processor unit (804) performs post-processing of the data generated by the Planar Processor unit. The Element-by-Element processor performs element-by-element calculations of the following operations: addition, subtraction, max values, multiplication, as well as a variety of nonlinear activation functions and a variety of different reduction operations.An operating mode is possible where data passes through the Planar Processor block unchanged (bypass mode), and all processing is performed by the Element-Based Processor block. The tensor loading (805)(806) and unloading (807) blocks respectively read the source data and write the processing results to shared memory (802).

[0101] The vector processor is designed to perform operations on sections of tensors in two dimensions, which include: • data thinning; • channel-wise convolution (depth-wise separable convolution); • a set of element-by-element operations on data. • data reduction (including calculation of maximums, minimums, root mean square, etc.)

[0102] The elements of the proposed technical solution are functionally interconnected, and their combined use leads to the creation of a new and unique technical solution. Thus, all blocks are functionally interconnected.

[0103] All blocks used in the system can be implemented using electronic components used to create digital integrated circuits, which is obvious to a person skilled in the art. This includes, but is not limited to, microcircuits whose operating logic is determined during manufacture, or programmable logic integrated circuits (FPGAs), whose operating logic is specified through programming. For programming, programmers and debugging environments are used, allowing the desired structure of the digital device to be specified in the form of a circuit diagram or a program in specialized hardware description languages: Verilog, VHDL, AHDL, etc. Alternatives to FPGAs include programmable logic controllers (PLCs), basic matrix chips (BMCs), which require a factory production process for programming; ASICs - specialized custom large-scale integrated circuits (LSI), which are significantly more expensive for small-scale and individual production.

[0104] Typically, the FPGA chip itself consists of the following components: • configurable logic blocks that implement the required logical function; • programmable electronic connections between configurable logical blocks; • programmable input / output blocks that provide communication between the external output of the microcircuit and the internal logic.

[0105] Blocks can also be implemented using read-only memory devices.

[0106] Thus, the implementation of all used blocks is achieved by standard means based on classical principles of implementing the fundamentals of computing technology.

[0107] Aspects of the present technical solution may be implemented as a system, method, or computer software product. Accordingly, various aspects of the present technical solution may be implemented solely as hardware, as software (including application software), or as a computer program. software, etc.) or as an embodiment combining software and hardware aspects, which may generally be referred to as a "module," "system," or "architecture." Furthermore, aspects of the present technical solution may take the form of a computer software product implemented on one or more machine-readable media having machine-readable program code implemented thereon.

[0108] Any combination of one or more machine-readable media may also be used. A machine-readable storage medium may be, without limitation, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or any suitable combination thereof. Specifically, non-exhaustive examples of machine-readable storage media include: an electrical connection via one or more wires, a portable computer diskette; a hard disk drive, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), fiber optic connection, compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any combination of the foregoing.In the context of the present description, a machine-readable storage medium may be any flexible storage medium that can contain or store a program for use by or in connection with a system, device, apparatus.

[0109] The program code embedded in the machine-readable medium may be transmitted via any medium, including, without limitation, wireless, wired, fiber optic, infrared, and any other suitable network or combination thereof.

[0110] The computer program code for performing the operations for the steps of the present technical solution may be written in any programming language or combination of programming languages, including an object-oriented programming language such as Java, Smalltalk, C++, etc., and conventional procedural languages. Programming languages, such as the C programming language or similar programming languages, can be used. The program code can be executed on the user's computer, in whole or in part, or as a separate software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN), a wide area network (WAN), or a connection to an external computer (e.g., via the Internet using Internet service providers).

[0111] Aspects of the present technical solution have been described in detail with reference to block diagrams, circuit diagrams, and / or diagrams of methods, devices (systems), and computer program products in accordance with embodiments of the present technical solution. It should be borne in mind that each block of the block diagram and / or diagrams, as well as combinations of blocks of the block diagram and / or diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, or another data processing device to create a procedure, such that the instructions executed by the computer processor or other programmable data processing device create means for implementing the functions / actions indicated in the block or blocks of the block diagram and / or diagram.

[0112] These computer program instructions may also be stored on a machine-readable medium that can control a computer other than a programmable data processing device or other than devices that operate in a specific manner, such that the instructions stored on the machine-readable medium create a device that includes instructions that perform the functions / actions indicated in the block of the flowchart and / or diagram.

Claims

FORMULA 1. A processor architecture for accelerating the calculation of the forward motion of artificial neural networks, containing: • at least one control device configured to transmit control flows to executive devices and control the dependencies of task execution by conveyors; • at least one matrix processor that contains two read ports, configured to provide an uninterrupted data flow to the matrix multiplication module; • at least one vector processor configured to perform operations operating on sections of tensors in two dimensions, which include data decimation and depth-wise convolution; • at least one device for direct access to external memory, configured to write and read data.

2. The processor architecture according to paragraph 1, characterized in that the control device contains a control core and conveyor control modules.

3. The processor architecture according to paragraph 2, characterized in that the control core contains a set of configuration registers accessible through the memory access interface and necessary for controlling the device.

4. The processor architecture according to paragraph 1, characterized in that the shared memory is implemented in the form of a multi-port multi-bank (shared) memory with software resolution of memory access conflicts.

5. The processor architecture according to paragraph 5, characterized in that all computing devices have equal access to all cells of the shared memory.

6. The processor architecture according to paragraph 5, characterized in that the shared memory has N banks of the same depth and width, Nr read ports, Nw write ports of the same width with a fixed latency.

7. The processor architecture according to paragraph 5, characterized by the fact that in the shared memory, in one cycle, reading / writing to the same bank at different addresses from different read / write ports is prohibited.

8. The processor architecture according to paragraph 7, characterized in that the memory banks are made dual-port (independent read and write ports in one memory bank) and / or single-port (multiplexed read / write port).

9. The processor architecture according to paragraph 5, characterized in that some executive devices contain tensor sampling units configured to transpose the tensor, sampling columns for the convolution operation from the entire tensor or part of it.

10. The processor architecture according to claim 10, characterized in that the block is used to form columns for the convolution operation.

11. The processor architecture according to paragraph 1, characterized in that the ports of the matrix processor are configured by setting a base address and a reading algorithm template.

12. The processor architecture according to paragraph 1, characterized in that the matrix processor contains a matrix multiplier block, which is a systolic array of elementary computing devices.

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