Power converter and control circuit applied to power converter

Abstract

The present application provides a power converter and a control circuit applied to a power converter. In the power converter, a first switch and a second switch are connected in series and then connected to an input end of the power converter, and two ends of the second switch are connected to an output end of the power converter. In the control circuit of the power converter, a first input end and a second input end of an operational amplifier circuit are used for receiving a reference voltage and a ripple voltage of the output end of the power converter, respectively. A first output end and a second output end of the operational amplifier circuit are connected to a first input end and a second input end of a voltage-controlled delay circuit, respectively, and a third input end of the voltage-controlled delay circuit is used for receiving a clock signal. A first output end and a second output end of the voltage-controlled delay circuit are connected to a first input end and a second input end of a flip-flop circuit, respectively, and a first output end and a second output end of the flip-flop circuit are connected to the first switch and the second switch, respectively. On the basis of the present application, the delay time of the control circuit can be reduced.

Description

Power converter and control circuit applied to power converter

[0001] The present application claims priority to the Chinese patent application No. 202411258969.9, filed on September 9, 2024, with the State Intellectual Property Office of China, and the Chinese patent application No. 202411258969.9 has the title of "Power converter and control circuit applied to power converter", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of power supply circuit, in particular to a power converter and a control circuit applied to the power converter. BACKGROUND

[0003] With the rapid development of electronic information technology, power converters are widely used in electronic devices and systems due to their high efficiency and compact design, and provide stable voltage for electronic devices and systems to make them run normally. At present, the power converter includes a switch and a control circuit. In the case of using a traditional proportion integral differential (PID) control method, the control circuit mainly controls the duty cycle signal of the switch through a comparator and a resistor-capacitance (RC) compensation circuit, thereby converting the input voltage of the power circuit into the output voltage required by the electronic device or system. However, when the power converter is a high-frequency high-speed power converter, the performance limitation of the comparator will cause logic errors and duty cycle limitations, thereby causing the delay time of the control circuit to be too long. SUMMARY

[0004] The present application provides a power converter and a control circuit applied to the power converter, which can reduce the delay time of the control circuit and improve the transient response speed of the control circuit, and has strong applicability.

[0005] In a first aspect, an embodiment of the present application provides a power converter, which comprises an input end, a first switch, a second switch, an output end and a control circuit. The input end of the power converter is configured to be connected to a power supply. The first switch and the second switch are connected in series and connected to the input end of the power converter. The second switch is connected (e.g., directly or indirectly) to the output end of the power converter. The output end of the power converter is configured to be connected to a load. The control circuit comprises an operational amplifier circuit, a voltage-controlled delay circuit and a flip-flop circuit. The first input end of the operational amplifier circuit is configured to receive a reference voltage. The second input end of the operational amplifier circuit is configured to receive a ripple voltage of the output end of the power converter. The first output end of the operational amplifier circuit is connected to the first input end of the voltage-controlled delay circuit. The second output end of the operational amplifier circuit is connected to the second input end of the voltage-controlled delay circuit. The third input end of the voltage-controlled delay circuit is configured to receive a clock signal. The first output end of the voltage-controlled delay circuit is connected to the first input end of the flip-flop circuit. The second output end of the voltage-controlled delay circuit is connected to the second input end of the flip-flop circuit. The first output end of the flip-flop circuit is connected to the first switch. The second output end of the flip-flop circuit is connected to the second switch. By using the voltage-controlled delay circuit to replace the comparator to delay the signal, the logic error and the limited duty cycle caused by using the comparator to delay the signal can be avoided, the delay time of the control circuit is reduced, and the transient response speed of the control circuit is improved. In addition, the complex RC compensation circuit in the control circuit can be avoided, the structure of the control circuit is simplified, the circuit area is reduced, the structure of the power converter is further simplified, and the circuit area is further reduced. The applicability is strong.

[0006] In a possible implementation, the operational amplifier circuit comprises a first operational amplifier and a second operational amplifier. The non-inverting input end of the first operational amplifier and the inverting input end of the second operational amplifier are connected to the first input end of the operational amplifier circuit to receive the reference voltage. The inverting input end of the first operational amplifier and the non-inverting input end of the second operational amplifier are connected to the second input end of the operational amplifier circuit to receive the ripple voltage of the output end of the power converter. The output end of the first operational amplifier is connected to the first output end of the operational amplifier circuit. The output end of the second operational amplifier is connected to the second output end of the operational amplifier circuit. The first operational amplifier is configured to output a first control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage. The second operational amplifier is configured to output a second control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage. The first control signal and the second control signal are both configured to control the delay time of the voltage-controlled delay circuit. According to the difference between the reference voltage and the ripple voltage, the first control signal and the second control signal can be adjusted in real time, so that the delay time of the voltage-controlled delay circuit can be controlled in real time. The control flexibility of the delay time is stronger.

[0007] In a possible implementation, the voltage-controlled delay circuit includes a first voltage-controlled delay line and a second voltage-controlled delay line. The first input terminal of the first voltage-controlled delay line is connected to the first input terminal of the voltage-controlled delay circuit to receive the first control signal output by the first operational amplifier. The first input terminal of the second voltage-controlled delay line is connected to the second input terminal of the voltage-controlled delay circuit to receive the second control signal output by the second operational amplifier. The second input terminal of the first voltage-controlled delay line is connected to the third input terminal of the voltage-controlled delay circuit to receive the clock signal. The output terminal of the first voltage-controlled delay line is connected to the second input terminal of the second voltage-controlled delay line and the first output terminal of the voltage-controlled delay circuit, and the output terminal of the second voltage-controlled delay line is connected to the second output terminal of the voltage-controlled delay circuit. The first voltage-controlled delay line is configured to delay the clock signal based on the first control signal and output a first delay signal to the second voltage-controlled delay line and the flip-flop circuit. The second voltage-controlled delay line is configured to delay the first delay signal based on the second control signal and output a second delay signal to the flip-flop circuit. By using the first voltage-controlled delay line and the second voltage-controlled delay line to replace the comparator to delay the signal, the logic error and the limited duty cycle caused by using the comparator to delay the signal can be avoided, the delay time of the control circuit is reduced, and the transient response speed of the control circuit is improved.

[0008] In a possible implementation, the flip-flop circuit includes a flip-flop and an inverter. The first input terminal of the flip-flop is connected to the first input terminal of the flip-flop circuit to receive the first delay signal output by the first voltage-controlled delay line. The second input terminal of the flip-flop is connected to the second input terminal of the flip-flop circuit to receive the second delay signal output by the second voltage-controlled delay line. The output terminal of the flip-flop is connected to the first output terminal of the flip-flop circuit and the input terminal of the inverter, and the output terminal of the inverter is connected to the second output terminal of the flip-flop circuit. The flip-flop is configured to output a duty cycle signal to the first switch and output an inverted duty cycle signal to the second switch through the inverter based on the first delay signal and the second delay signal, so that the difference between the output voltage of the power converter and the voltage of the load is less than the preset threshold. According to the duty cycle signal and the inverted duty cycle signal, the first switch and the second switch can be controlled to be turned on or turned off in real time, so that the output voltage of the power converter can be quickly adjusted to meet the voltage demand of the load.

[0009] In a possible implementation, the delay time between the first delay signal and the clock signal is positively correlated with the absolute value of the difference between the reference voltage and the ripple voltage. According to the absolute value of the difference, the length of the delay time between the first delay signal and the clock signal can be adjusted in real time, and the control flexibility of the delay time is higher.

[0010] In a possible implementation, the delay time between the second delay signal and the first delay signal is positively correlated with the absolute value of the difference between the reference voltage and the ripple voltage. By implementing the embodiment of the application, the length of the delay time between the second delay signal and the first delay signal can be adjusted in real time according to the absolute value of the difference, and the control flexibility of the delay time is stronger.

[0011] In a possible implementation, the control circuit further includes a voltage-controlled oscillation circuit, wherein an input end of the voltage-controlled oscillation circuit is connected to the output end of the power converter, and an output end of the voltage-controlled oscillation circuit is connected to the third input end of the voltage-controlled delay circuit. The voltage-controlled oscillation circuit is configured to output a clock signal to the voltage-controlled delay circuit based on the sampled output voltage of the power converter. By implementing the embodiment of the application, the oscillation frequency of the clock signal can be changed in real time according to the sampled output voltage, so that a high-precision high-frequency clock signal is output, and the control flexibility and the precision of the clock signal are stronger and higher.

[0012] In a possible implementation, the power converter further includes an inductor, wherein the inductor is connected between the series connection point of the first switch and the second switch and the output end of the power converter. The control circuit further includes a current sampling circuit, wherein an input end of the current sampling circuit is connected between the series connection point of the first switch and the second switch and the inductor, and an output end of the current sampling circuit is connected to the second input end of the operational amplifier circuit. The current sampling circuit is configured to collect the current flowing through the inductor, and output the ripple voltage to the operational amplifier circuit based on the current flowing through the inductor. By implementing the embodiment of the application, the size of the ripple voltage can be detected in real time according to the current flowing through the inductor, so as to meet different voltage requirements of the load.

[0013] In a second aspect, the embodiments of the present application provide a control circuit for a power converter. The control circuit comprises an operational amplifier circuit, a voltage-controlled delay circuit, and a flip-flop circuit. The power converter comprises an input terminal, a first switch, a second switch, and an output terminal. The first switch and the second switch are connected in series and connected to the input terminal of the power converter. The second switch is connected to the output terminal of the power converter. The first input terminal of the operational amplifier circuit is configured to receive a reference voltage. The second input terminal of the operational amplifier circuit is configured to receive a ripple voltage of the output terminal of the power converter. The first output terminal of the operational amplifier circuit is connected to the first input terminal of the voltage-controlled delay circuit. The second output terminal of the operational amplifier circuit is connected to the second input terminal of the voltage-controlled delay circuit. The third input terminal of the voltage-controlled delay circuit is configured to receive a clock signal. The first output terminal of the voltage-controlled delay circuit is connected to the first input terminal of the flip-flop circuit. The second output terminal of the voltage-controlled delay circuit is connected to the second input terminal of the flip-flop circuit. The first output terminal of the flip-flop circuit is configured to be connected to the first switch. The second output terminal of the flip-flop circuit is configured to be connected to the second switch. By using the voltage-controlled delay circuit to replace the comparator to delay the signal, the logic error and the limited duty cycle caused by using the comparator to delay the signal can be avoided, the delay time of the control circuit is reduced, and the transient response speed of the control circuit is improved. In addition, the complex RC compensation circuit in the control circuit can be avoided, the structure of the control circuit is simplified, the circuit area is smaller, the structure of the power converter is further simplified, and the circuit area is smaller. The applicability is strong.

[0014] In a possible implementation, the operational amplifier circuit comprises a first operational amplifier and a second operational amplifier. The non-inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier are connected to the first input terminal of the operational amplifier circuit to receive the reference voltage. The inverting input terminal of the first operational amplifier and the non-inverting input terminal of the second operational amplifier are connected to the second input terminal of the operational amplifier circuit to receive the ripple voltage of the output terminal of the power converter. The output terminal of the first operational amplifier is connected to the first output terminal of the operational amplifier circuit, and the output terminal of the second operational amplifier is connected to the second output terminal of the operational amplifier circuit. The first operational amplifier is configured to output a first control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage. The second operational amplifier is configured to output a second control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage. The first control signal and the second control signal are both configured to control the delay time of the voltage-controlled delay circuit. According to the difference between the reference voltage and the ripple voltage, the first control signal and the second control signal can be adjusted in real time, so that the delay time of the voltage-controlled delay circuit can be controlled in real time, and the control flexibility of the delay time is stronger.

[0015] In a possible implementation, the voltage-controlled delay circuit includes a first voltage-controlled delay line and a second voltage-controlled delay line. The first input terminal of the first voltage-controlled delay line is connected to the first input terminal of the voltage-controlled delay circuit to receive the first control signal output by the first operational amplifier. The first input terminal of the second voltage-controlled delay line is connected to the second input terminal of the voltage-controlled delay circuit to receive the second control signal output by the second operational amplifier. The second input terminal of the first voltage-controlled delay line is connected to the third input terminal of the voltage-controlled delay circuit to receive the clock signal. The output terminal of the first voltage-controlled delay line is connected to the second input terminal of the second voltage-controlled delay line and the first output terminal of the voltage-controlled delay circuit, and the output terminal of the second voltage-controlled delay line is connected to the second output terminal of the voltage-controlled delay circuit. The first voltage-controlled delay line is configured to delay the clock signal based on the first control signal and output a first delay signal to the second voltage-controlled delay line and the flip-flop circuit. The second voltage-controlled delay line is configured to delay the first delay signal based on the second control signal and output a second delay signal to the flip-flop circuit. By using the first voltage-controlled delay line and the second voltage-controlled delay line to replace the comparator to delay the signal, the logic error and the limited duty cycle caused by using the comparator to delay the signal can be avoided, the delay time of the control circuit is reduced, and the transient response speed of the control circuit is improved.

[0016] In a possible implementation, the flip-flop circuit includes a flip-flop and an inverter. The first input terminal of the flip-flop is connected to the first input terminal of the flip-flop circuit to receive the first delay signal output by the first voltage-controlled delay line. The second input terminal of the flip-flop is connected to the second input terminal of the flip-flop circuit to receive the second delay signal output by the second voltage-controlled delay line. The output terminal of the flip-flop is connected to the first output terminal of the flip-flop circuit and the input terminal of the inverter, and the output terminal of the inverter is connected to the second output terminal of the flip-flop circuit. The flip-flop is configured to output a duty cycle signal to the first switch and output an inverted duty cycle signal to the second switch through the inverter based on the first delay signal and the second delay signal, so that the difference between the output voltage of the power converter and the voltage of the load is less than the preset threshold. According to the duty cycle signal and the inverted duty cycle signal, the first switch and the second switch can be controlled to be turned on or turned off in real time, so that the output voltage of the power converter can be quickly adjusted to meet the voltage demand of the load.

[0017] In a possible implementation, the delay time between the first delay signal and the clock signal is positively correlated with the absolute value of the difference between the reference voltage and the ripple voltage. According to the absolute value of the difference, the length of the delay time between the first delay signal and the clock signal can be adjusted in real time, and the control flexibility of the delay time is higher.

[0018] In a possible implementation, the delay time between the second delay signal and the first delay signal is positively correlated with the absolute value of the difference between the reference voltage and the ripple voltage. By implementing the embodiment of the present application, the length of the delay time between the second delay signal and the first delay signal can be adjusted in real time according to the absolute value of the difference, and the control flexibility of the delay time is stronger.

[0019] In a possible implementation, the control circuit further includes a voltage-controlled oscillation circuit, an input end of the voltage-controlled oscillation circuit is connected to the output end of the power converter, and an output end of the voltage-controlled oscillation circuit is connected to the third input end of the voltage-controlled delay circuit. The voltage-controlled oscillation circuit is configured to output a clock signal to the voltage-controlled delay circuit based on the sampled output voltage of the power converter. By implementing the embodiment of the present application, the oscillation frequency of the clock signal can be changed in real time according to the sampled output voltage, so that a high-precision high-frequency clock signal is output, and the control flexibility and the precision of the clock signal are stronger and higher.

[0020] In a possible implementation, the control circuit further includes a current sampling circuit, and the power converter further includes an inductor. An input end of the current sampling circuit is connected between the series connection point of the first switch and the second switch and the inductor, and an output end of the current sampling circuit is connected to the second input end of the operational amplifier circuit. The current sampling circuit is configured to collect the current flowing through the inductor, and output the ripple voltage to the operational amplifier circuit based on the current flowing through the inductor. By implementing the embodiment of the present application, the size of the ripple voltage can be detected in real time according to the current flowing through the inductor, so as to meet different voltage requirements of the load.

[0021] It should be understood that the implementation and beneficial effects of the above aspects of the present application can be mutually referred to. BRIEF DESCRIPTION OF DRAWINGS

[0022] FIG. 1 is a circuit schematic diagram of a power converter provided by an embodiment of the present application;

[0023] FIG. 2 is another circuit schematic diagram of a power converter provided by an embodiment of the present application;

[0024] FIG. 3 is another circuit schematic diagram of a power converter provided by an embodiment of the present application;

[0025] FIG. 4 is another circuit schematic diagram of a power converter provided by an embodiment of the present application;

[0026] FIG. 5 is a waveform schematic diagram of a clock signal, a first delay signal, a second delay signal, and a duty cycle signal provided by an embodiment of the present application;

[0027] FIG. 6 is another circuit schematic diagram of a power converter provided by an embodiment of the present application;

[0028] Fig. 7A is a waveform diagram of output voltage of the power converter when the control circuit adopts a conventional PID control mode;

[0029] Fig. 7B is a waveform diagram of output voltage of the power converter when the control circuit adopts a time-domain information based hysteresis control mode according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0031] The embodiments of the technical solutions of the present application will be further described in detail below with reference to the drawings.

[0032] Referring to Fig. 1, Fig. 1 is a circuit schematic diagram of a power converter according to an embodiment of the present application. As shown in Fig. 1, the power converter 2 is used to be connected between a power supply 1 and a load 3 for voltage conversion. In a specific implementation, the power converter 2 converts the voltage provided by the power supply 1 into a target voltage and supplies power to the load 3, so as to meet the voltage requirement of the load 3. Exemplarily, the power converter 2 can be a high-frequency high-speed power converter or a low-speed power converter, which is not limited herein.

[0033] The power converter 2 includes an input terminal in, a first switch S1, a second switch S2, an output terminal out and a control circuit 21. The input terminal in of the power converter 2 is used to be connected to the power supply 1 to receive the voltage provided by the power supply 1. The first switch S1 and the second switch S2 are connected in series and connected to the input terminal in of the power converter 2. The two ends of the second switch S2 are connected (such as directly connected or indirectly connected) to the output terminal out of the power converter 2. The output terminal out of the power converter 2 is used to be connected to the load 3 to output the target voltage to the load 3 for power supply.

[0034] The control circuit 21 comprises an operational amplifier circuit 211, a voltage-controlled delay circuit 212, and a flip-flop circuit 213. The first input terminal of the operational amplifier circuit 211 is configured to receive a reference voltage Vref, and the second input terminal of the operational amplifier circuit 211 is configured to receive a ripple voltage Vramp of the output terminal of the power converter 2. The ripple voltage Vramp is an AC component of the output voltage of the power converter 2. The first output terminal of the operational amplifier circuit 211 is connected to the first input terminal of the voltage-controlled delay circuit 212, the second output terminal of the operational amplifier circuit 211 is connected to the second input terminal of the voltage-controlled delay circuit 212, and the third input terminal of the voltage-controlled delay circuit 212 is configured to receive a clock signal CLK. The first output terminal of the voltage-controlled delay circuit 212 is connected (e.g., directly or indirectly) to the first input terminal of the flip-flop circuit 213, and the second output terminal of the voltage-controlled delay circuit 212 is connected (e.g., directly or indirectly) to the second input terminal of the flip-flop circuit 213. The first output terminal of the flip-flop circuit 213 is connected (e.g., directly or indirectly) to the first switch S1, and the second output terminal of the flip-flop circuit 213 is connected (e.g., directly or indirectly) to the second switch S2.

[0035] By implementing the embodiments of the present application, the voltage-controlled delay circuit 212 is used to replace the comparator to delay the signal, thereby avoiding the logical error and the limited duty cycle caused by using the comparator to delay the signal, and further reducing the delay time of the control circuit 21 and improving the transient response speed of the control circuit 21. In addition, the complex RC compensation circuit in the control circuit 21 can be avoided, the structure of the control circuit 21 is simplified, and a smaller circuit area is achieved, and the structure of the power converter 2 is further simplified and a smaller circuit area is achieved, which has strong applicability.

[0036] It can be understood that the control circuit 21 can be implemented by a chip-level full integration, that is, all functional circuits of the control circuit 21 are integrated on a system on chip (SoC), at this time, the complex RC compensation circuit in the control circuit 21 can be avoided to save the chip area, and the cost is lower. Alternatively, the combination of discrete devices in all functional circuits of the control circuit 21 can also be implemented by a board level, that is, the discrete devices in all functional circuits are arranged on a printed circuit board (PCB) according to their circuit connection mode.

[0037] The control circuit 21 can be integrated inside the power converter 2. Alternatively, the control circuit 21 can also be arranged outside the power converter 2 and exist independently, and the specific position of the control circuit 21 is not limited in the embodiments of the present application.

[0038] For example, when the power converter 2 is a direct current (DC) / DC converter, the power source 1 is a DC power source and the load 3 is a DC load. When the power converter 2 is an alternating current (AC) / DC converter, the power source 1 is an AC power source and the load 3 is a DC load. When the power converter 2 is an AC / AC converter, the power source 1 is an AC power source and the load 3 is an AC load.

[0039] For example, each of the first switch S1 and the second switch S2 can be any one of a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), a silicon controlled rectifier (SCR), a gate turn-off thyristor (GTO), a MOS controlled gyrator (MCT), a static induction transistor (SIT), and a metal oxide semiconductor (MOS). The above are only examples, and embodiments of the present application do not limit the specific type of each switch.

[0040] In the case where the current of the load 3 jumps to cause a change in the voltage of the load 3, i.e., a transient occurs, the control circuit 21 is configured to control the output voltage of the power converter 2 to increase or decrease by controlling each of the first switch S1 and the second switch S2 to be turned on or turned off, so as to meet the voltage requirement of the load 3. For example, when the voltage of the load 3 increases as the current of the load 3 decreases, the control circuit 21 controls the output voltage of the power converter 2 to increase, and when the voltage of the load 3 decreases as the current of the load 3 increases, the control circuit 21 controls the output voltage of the power converter 2 to decrease.

[0041] The specific implementation process of the control circuit 21 controlling the output voltage of the power converter 2 can be illustrated by combining FIGS. 2 to 6 below.

[0042] When the power converter 2 is a switching inductance type converter, such as a buck converter, a circuit structure of the power converter 2 can be as shown in FIG. 2. The power converter 2 shown in FIG. 1 further includes an inductor L and a capacitor C1. The inductor L is connected between a series connection point of the first switch S1 and the second switch S2 and an output terminal out of the power converter 2. The capacitor C1 is connected across the output terminal out of the power converter 2, for filtering the target voltage and outputting the filtered target voltage to the load 3 for power supply. The control circuit 21 shown in FIG. 1 further includes a current sampling circuit 214. The current sampling circuit 214 can be a current sensor or a current sampling resistor, which are merely examples and the circuit structure of the current sampling circuit 214 is not limited in the embodiments of the present application. The input terminal of the current sampling circuit 214 is connected between the series connection point of the first switch S1 and the second switch S2 and the inductor L, and the output terminal of the current sampling circuit 214 is connected to the second input terminal of the operational amplifier circuit 211. The current sampling circuit 214 is configured to sample the current I flowing through the inductor L and output a ripple voltage Vramp to the operational amplifier circuit 211 based on the current I flowing through the inductor L. According to the embodiments of the present application, the size of the ripple voltage Vramp can be detected in real time according to the current I flowing through the inductor L, so as to meet different voltage requirements of the load 3.

[0043] As shown in FIG. 2, the control circuit 21 further includes a voltage controlled oscillation circuit 215. The voltage controlled oscillation circuit 215 can be one of an inductor-capacitor (LC) voltage controlled oscillator (VCO), an RC voltage controlled oscillator and a crystal voltage controlled oscillator. The input terminal of the voltage controlled oscillation circuit 215 is connected to the output terminal of the power converter 2, and the output terminal of the voltage controlled oscillation circuit 215 is connected to the third input terminal of the voltage controlled delay circuit 212. The voltage controlled oscillation circuit 215 is configured to output a clock signal CLK to the voltage controlled delay circuit 212 based on a sampling output voltage Vo of the power converter 2. The sampling output voltage Vo can be directly sampled by the voltage controlled oscillation circuit 215, or output by an external voltage sampling circuit to the voltage controlled oscillation circuit 215. According to the embodiments of the present application, the oscillation frequency (i.e., frequency conversion) of the clock signal CLK can be changed in real time according to the sampling output voltage Vo, so as to output a high-precision high-frequency clock signal CLK, and the control flexibility and accuracy of the clock signal CLK are higher.

[0044] Referring to FIG. 3, FIG. 3 is another circuit schematic diagram of the power converter provided by the embodiments of the present application. As shown in FIG. 3, the operational amplifier circuit 211 shown in FIG. 2 includes a first operational amplifier OPA1 and a second operational amplifier OPA2. Exemplarily, each of the first operational amplifier OPA1 and the second operational amplifier OPA2 can be an operational transconductance amplifier (OTA) or a differential amplifier, which are merely examples and the embodiments of the present application do not limit the specific type of each operational amplifier. The non-inverting input terminal of the first operational amplifier OPA1 and the inverting input terminal of the second operational amplifier OPA2 are connected to the first input terminal of the operational amplifier circuit 211 to receive the reference voltage Vref. The inverting input terminal of the first operational amplifier OPA1 and the non-inverting input terminal of the second operational amplifier OPA2 are connected to the second input terminal of the operational amplifier circuit 211 to receive the ripple voltage Vramp of the output terminal of the power converter 2. The output terminal of the first operational amplifier OPA1 is connected to the first output terminal of the operational amplifier circuit 211, and the output terminal of the second operational amplifier OPA2 is connected to the second output terminal of the operational amplifier circuit 211. Optionally, the output terminal of the first operational amplifier OPA1 is further connected to the reference ground through a capacitor C2, and the second operational amplifier OPA2 is further connected to the reference ground through a capacitor C3.

[0045] The first operational amplifier OPA1 is configured to output a first control signal CS1 to the voltage-controlled delay circuit 212 based on the reference voltage Vref and the ripple voltage Vramp. The second operational amplifier OPA2 is configured to output a second control signal CS2 to the voltage-controlled delay circuit 212 based on the reference voltage Vref and the ripple voltage Vramp. The first control signal CS1 and the second control signal CS2 are both configured to control the delay time of the voltage-controlled delay circuit 212. Exemplarily, when each operational amplifier is an operational transconductance amplifier, each operational amplifier is configured to convert the difference between the reference voltage Vref and the ripple voltage Vramp into a current signal and output the current signal as a control signal (such as the first control signal CS1 or the second control signal CS2) to the voltage-controlled delay circuit 212. Optionally, when each operational amplifier is a differential amplifier, each operational amplifier is configured to amplify the difference between the reference voltage Vref and the ripple voltage Vramp to obtain a voltage signal and output the voltage signal as a control signal to the voltage-controlled delay circuit 212. By implementing the embodiments of the present application, the first control signal CS1 and the second control signal CS2 can be adjusted in real time according to the difference between the reference voltage Vref and the ripple voltage Vramp, so as to control the delay time of the voltage-controlled delay circuit 212 in real time, and the control flexibility of the delay time is stronger.

[0046] It can be understood that the first operational amplifier OPA1 and the second operational amplifier OPA2 can be two independent devices. Alternatively, the first operational amplifier OPA1 and the second operational amplifier OPA2 can also be integrated into an integrated structure.

[0047] Referring to FIG. 4, FIG. 4 is another circuit schematic diagram of the power converter provided by the embodiments of the present application. As shown in FIG. 4, the voltage controlled delay circuit 212 shown in FIG. 3 includes a first voltage controlled delay line VCDL1 and a second voltage controlled delay line VCDL2. Exemplarily, each voltage controlled delay line (VCDL) in the first voltage controlled delay line VCDL1 and the second voltage controlled delay line VCDL2 can be implemented by a plurality of inverters connected in series, or by a plurality of capacitors connected in parallel, which are only examples and are not limited herein. The first input end of the first voltage controlled delay line VCDL1 is connected to the first input end of the voltage controlled delay circuit 212 to receive the first control signal CS1 output by the first operational amplifier OPA1. The first input end of the second voltage controlled delay line VCDL2 is connected to the second input end of the voltage controlled delay circuit 212 to receive the second control signal CS2 output by the second operational amplifier OPA2. The second input end of the first voltage controlled delay line VCDL1 is connected to the third input end of the voltage controlled delay circuit 212 to receive the clock signal CLK output by the voltage controlled oscillator circuit 215. The output end of the first voltage controlled delay line VCDL1 is connected to the second input end of the second voltage controlled delay line VCDL2 and the first output end of the voltage controlled delay circuit 212, and the output end of the second voltage controlled delay line VCDL2 is connected to the second output end of the voltage controlled delay circuit 212.

[0048] The first voltage-controlled delay line VCDL1 is configured to delay the clock signal CLK based on the first control signal CS1, and output a first delay signal SET to the second voltage-controlled delay line VCDL2 and the flip-flop circuit 213. The delay time between the first delay signal SET and the clock signal CLK is positively correlated with the absolute value of the difference between the reference voltage Vref and the ramp voltage Vramp. The second voltage-controlled delay line VCDL2 is configured to delay the first delay signal SET based on the second control signal CS2, and output a second delay signal RESET to the flip-flop circuit 213. The delay time between the second delay signal RESET and the first delay signal SET is positively correlated with the absolute value of the difference between the reference voltage Vref and the ramp voltage Vramp. For example, the waveforms of the clock signal CLK, the first delay signal SET and the second delay signal RESET can be as shown in FIG. 5. The delay time Td1 between the first delay signal SET and the clock signal CLK is the time interval between the rising edge of the first delay signal SET and the rising edge of the clock signal CLK, and the delay time Td1 is positively correlated with the phase difference between the rising edge of the first delay signal SET and the rising edge of the clock signal CLK. The delay time Td2 between the second delay signal RESET and the first delay signal SET is the time interval between the rising edge of the second delay signal RESET and the rising edge of the first delay signal SET, and the delay time Td2 is positively correlated with the phase difference between the rising edge of the second delay signal RESET and the rising edge of the first delay signal SET.

[0049] By implementing the embodiment of the present application, the first voltage-controlled delay line VCDL1 and the second voltage-controlled delay line VCDL2 can replace the comparator to delay the signal, thereby avoiding the logic error and the duty cycle limitation caused by using the comparator to delay the signal, and further reducing the delay time of the control circuit 21 and improving the transient response speed of the control circuit 21. In addition, the delay time between the first delay signal and the clock signal and the delay time between the second delay signal and the first delay signal can be adjusted in real time according to the absolute value of the difference, and the control flexibility of the delay time is stronger.

[0050] It can be understood that the first voltage-controlled delay line VCDL1 and the second voltage-controlled delay line VCDL2 can be two independent devices. Alternatively, the first voltage-controlled delay line VCDL1 and the second voltage-controlled delay line VCDL2 can also be integrated into an integrated structure.

[0051] Referring to FIG. 6, which is another circuit schematic of the power converter according to an embodiment of the present application. As shown in FIG. 6, the flip-flop circuit 213 shown in FIG. 5 includes a flip-flop FF and an inverter NOT. For example, the flip-flop FF can be a reset set (RS) flip-flop or a JK flip-flop, which are examples and are not limited herein. The first input of the flip-flop FF is connected to the first input of the flip-flop circuit 213 to receive the first delay signal SET output by the first voltage controlled delay line VCDL1. The second input of the flip-flop FF is connected to the second input of the flip-flop circuit 213 to receive the second delay signal RESET output by the second voltage controlled delay line VCDL2. For example, when the flip-flop FF is an RS flip-flop, the first input of the flip-flop FF is the set input S and the second input of the flip-flop FF is the reset input R. The output of the flip-flop FF is connected to the first output of the flip-flop circuit 213 and the input of the inverter NOT, and the output of the inverter NOT is connected to the second output of the flip-flop circuit 213.

[0052] The flip-flop FF is configured to output a duty cycle signal Q to the first switch S1 and output an inverted duty cycle signal to the second switch S2 via the inverter NOT based on the first delay signal SET and the second delay signal RESET, so that the difference between the output voltage of the power converter 2 and the voltage of the load 3 is less than a preset threshold. The preset threshold is a value that is preset or determined by the internal components of the power converter 2. When the duty cycle signal Q is a high level signal, the inverted duty cycle signal is a low level signal, and when the duty cycle signal Q is a low level signal, the inverted duty cycle signal is a high level signal. It should be understood that the duty cycle signal Q output by the flip-flop FF can be amplified by the driver circuit 22 and then output to the first switch S1 to control the conduction or non-conduction of the first switch S1, and the inverted duty cycle signal output by the inverter NOT can be amplified by the driver circuit 22 and then output to the second switch S2 to control the conduction or non-conduction of the second switch S2, so that the difference between the output voltage of the power converter 2 and the voltage of the load 3 is less than the preset threshold, i.e., the output voltage of the power converter 2 is substantially consistent with the voltage of the load 3, thereby ensuring the normal operation of the load 3.

[0053] Exemplarily, the waveform of the duty cycle signal Q can be as shown in FIG. 5. When the first delay signal SET is a high level signal and the second delay signal RESET is a low level signal, the duty cycle signal Q is a high level signal. When the first delay signal SET is a high level signal and the second delay signal RESET is a high level signal, the duty cycle signal Q is a low level signal. When the first delay signal SET is a low level signal and the second delay signal RESET is a high level signal, the duty cycle signal Q is a low level signal. When the first delay signal SET is a low level signal and the second delay signal RESET is a low level signal, the duty cycle signal Q keeps the level signal of the last time, i.e. keeps the low level signal unchanged.

[0054] By implementing the embodiment of the present application, the first switch S1 and the second switch S2 can be controlled to be turned on or turned off in real time according to the duty cycle signal and the inverted duty cycle signal, so as to quickly adjust the output voltage of the power converter 2 to meet the voltage requirement of the load 3.

[0055] It can be understood that the flip-flop FF and the inverter NOT can be two independent devices. Alternatively, the inverter NOT can also be integrated inside the flip-flop FF to form an integrated structure.

[0056] It can be understood that the control circuit 21 adjusts the hysteresis upper limit value of the ripple voltage Vramp in the hysteresis control mode through the first operational amplifier OPA1 and the first voltage-controlled delay line VCDL1, and adjusts the hysteresis lower limit value of the ripple voltage Vramp in the hysteresis control mode through the second operational amplifier OPA2 and the second voltage-controlled delay line VCDL2. The hysteresis control mode is a control mode designed for the load 3 that requires a faster load transient response, which can also be referred to as a ripple control mode. The hysteresis upper limit value and the hysteresis lower limit value can be adjusted by the gain of the first operational amplifier OPA1 and the gain of the second operational amplifier OPA2. For example, the hysteresis upper limit value is negatively related to the gain of the first operational amplifier OPA1, and the hysteresis lower limit value is negatively related to the gain of the second operational amplifier OPA2. In addition, the control circuit 21 can also replace the comparator in the traditional hysteresis control mode with the voltage-controlled delay line, and convert the control signal obtained according to the difference between the reference voltage Vref and the ripple voltage Vramp into a delay signal containing time domain information such as phase difference and delay time, thereby avoiding the problems of logic error and duty cycle limitation caused by using the comparator for signal delay, and further reducing the delay time of the control circuit 21 and improving the transient response speed of the control circuit 21. In summary, the control mode adopted by the control circuit 21 can be referred to as a hysteresis control mode based on time domain information, and this hysteresis control mode based on time domain information is also a nonlinear control mode, so the control circuit 21 can provide closed-loop control capability for the power converter 2, and compared with the traditional PID control mode, the system dynamic performance of the power converter 2 is greatly improved.

[0057] For example, when the input voltage of the power converter 2 is 1.8V, the output voltage is 0.9V, the switching frequency is 50MHz, the control circuit 21 adopts the traditional PID control mode, and the load shedding speed of the control circuit 21 is 40A / 150ns, the waveform of the output voltage of the power converter 2 can be as shown in FIG. 7A, the output voltage of the power converter 2 drops by ΔV=104Mv, and after a recovery time Δt=1μs, the control circuit 21 can control the output voltage of the power converter 2 to rise to a difference between the output voltage of the power converter 2 and the voltage of the load 3 less than a preset threshold. When the control circuit 21 adopts the hysteresis control mode based on time domain information provided in the embodiments of the present application, and the load shedding speed of the control circuit 21 is 40A / 150ns, the waveform of the output voltage of the power converter 2 can be as shown in FIG. 7B, the output voltage of the power converter 2 drops by ΔV=40Mv, and after a recovery time Δt=0.9μs, the control circuit 21 can control the output voltage of the power converter 2 to rise to a difference between the output voltage of the power converter 2 and the voltage of the load 3 less than a preset threshold. Thus, compared with the traditional PID control mode, the hysteresis control mode based on time domain information provided in the embodiments of the present application has a smaller drop amplitude of the output voltage of the power converter 2 and a shorter recovery time, and the system dynamic performance of the power converter 2 is better.

[0058] It should be noted that the terms "first", "second" are only for the purpose of description, and cannot be understood or implied as indicating or suggesting relative importance.

[0059] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A power converter, characterized by, The power converter comprises an input end, a first switch, a second switch, an output end and a control circuit; the input end of the power converter is used for connecting a power supply; the first switch and the second switch are connected in series and then connected to the input end of the power converter; two ends of the second switch are connected to the output end of the power converter; and the output end of the power converter is used for connecting a load; The control circuit comprises an operational amplifier circuit, a voltage-controlled delay circuit and a flip-flop circuit; a first input end of the operational amplifier circuit is used for receiving a reference voltage; a second input end of the operational amplifier circuit is used for receiving a ripple voltage of the output end of the power converter; a first output end of the operational amplifier circuit is connected to a first input end of the voltage-controlled delay circuit; a second output end of the operational amplifier circuit is connected to a second input end of the voltage-controlled delay circuit; a third input end of the voltage-controlled delay circuit is used for receiving a clock signal; a first output end of the voltage-controlled delay circuit is connected to a first input end of the flip-flop circuit; a second output end of the voltage-controlled delay circuit is connected to a second input end of the flip-flop circuit; a first output end of the flip-flop circuit is connected to the first switch; and a second output end of the flip-flop circuit is connected to the second switch.

2. The power converter of claim 1, wherein, The operational amplifier circuit comprises a first operational amplifier and a second operational amplifier; a non-inverting input end of the first operational amplifier and an inverting input end of the second operational amplifier are connected to the first input end of the operational amplifier circuit; an inverting input end of the first operational amplifier and a non-inverting input end of the second operational amplifier are connected to the second input end of the operational amplifier circuit; an output end of the first operational amplifier is connected to the first output end of the operational amplifier circuit; and an output end of the second operational amplifier is connected to the second output end of the operational amplifier circuit; The first operational amplifier is used for outputting a first control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage; The second operational amplifier is used for outputting a second control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage.

3. The power converter of claim 2, wherein, The voltage-controlled delay circuit comprises a first voltage-controlled delay line and a second voltage-controlled delay line; a first input end of the first voltage-controlled delay line is connected to the first input end of the voltage-controlled delay circuit; a first input end of the second voltage-controlled delay line is connected to the second input end of the voltage-controlled delay circuit; a second input end of the first voltage-controlled delay line is connected to the third input end of the voltage-controlled delay circuit; an output end of the first voltage-controlled delay line is connected to a second input end of the second voltage-controlled delay line and the first output end of the voltage-controlled delay circuit; and an output end of the second voltage-controlled delay line is connected to the second output end of the voltage-controlled delay circuit; The first voltage-controlled delay line is used for delaying the clock signal based on the first control signal and outputting a first delay signal to the second voltage-controlled delay line and the flip-flop circuit; The second voltage-controlled delay line is used for delaying the first delay signal based on the second control signal and outputting a second delay signal to the flip-flop circuit.

4. The power converter of claim 3, wherein, The trigger circuit comprises a flip-flop and an inverter, wherein a first input end of the flip-flop is connected to the first input end of the trigger circuit, a second input end of the flip-flop is connected to the second input end of the trigger circuit, an output end of the flip-flop is connected to the first output end of the trigger circuit and an input end of the inverter, and an output end of the inverter is connected to the second output end of the trigger circuit. The flip-flop is configured to output a duty cycle signal to the first switch and output an inverted duty cycle signal to the second switch through the inverter based on the first delay signal and the second delay signal, so that a difference between an output voltage of the power converter and a voltage of the load is less than a preset threshold.

5. The power converter of claim 3 or 4, wherein a delay time between the first delay signal and the clock signal is positively correlated with an absolute value of a difference between the reference voltage and the ripple voltage.

6. The power converter of any one of claims 3-5, wherein a delay time between the second delay signal and the first delay signal is positively correlated with an absolute value of a difference between the reference voltage and the ripple voltage.

7. The power converter of any of claims 1-6, wherein, The control circuit further comprises a voltage-controlled oscillation circuit, an input end of the voltage-controlled oscillation circuit is connected to an output end of the power converter, and an output end of the voltage-controlled oscillation circuit is connected to a third input end of the voltage-controlled delay circuit. The voltage-controlled oscillation circuit is configured to output the clock signal to the voltage-controlled delay circuit based on a sampled output voltage of the power converter.

8. The power converter of any of claims 1-7, wherein, The power converter further comprises an inductor, the inductor is connected between a series connection point of the first switch and the second switch and an output end of the power converter. The control circuit further comprises a current sampling circuit, an input end of the current sampling circuit is connected between the series connection point of the first switch and the second switch and the inductor, and an output end of the current sampling circuit is connected to a second input end of the operational amplifier circuit. The current sampling circuit is configured to collect a current flowing through the inductor and output the ripple voltage to the operational amplifier circuit based on the current flowing through the inductor.

9. A control circuit for a power converter, characterized by The control circuit comprises an operational amplifier circuit, a voltage-controlled delay circuit, and a trigger circuit, the power converter comprises an input end, a first switch, a second switch, and an output end, the first switch and the second switch are connected in series and connected to the input end of the power converter, and two ends of the second switch are connected to the output end of the power converter. The first input end of the operational amplifier circuit is used for receiving a reference voltage, the second input end of the operational amplifier circuit is used for receiving a ripple voltage of an output end of the power converter, the first output end of the operational amplifier circuit is connected with the first input end of the voltage-controlled delay circuit, the second output end of the operational amplifier circuit is connected with the second input end of the voltage-controlled delay circuit, the third input end of the voltage-controlled delay circuit is used for receiving a clock signal, the first output end of the voltage-controlled delay circuit is connected with the first input end of the flip-flop circuit, the second output end of the voltage-controlled delay circuit is connected with the second input end of the flip-flop circuit, and the first output end of the flip-flop circuit is used for connecting the first switch, and the second output end of the flip-flop circuit is used for connecting the second switch.

10. The control circuit of claim 9, wherein, The operational amplifier circuit comprises a first operational amplifier and a second operational amplifier, wherein the non-inverting input end of the first operational amplifier and the inverting input end of the second operational amplifier are connected with the first input end of the operational amplifier circuit, the inverting input end of the first operational amplifier and the non-inverting input end of the second operational amplifier are connected with the second input end of the operational amplifier circuit, the output end of the first operational amplifier is connected with the first output end of the operational amplifier circuit, and the output end of the second operational amplifier is connected with the second output end of the operational amplifier circuit. The first operational amplifier is used for outputting a first control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage. The second operational amplifier is used for outputting a second control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage.

11. The control circuit of claim 10, wherein, The voltage-controlled delay circuit comprises a first voltage-controlled delay line and a second voltage-controlled delay line, wherein the first input end of the first voltage-controlled delay line is connected with the first input end of the voltage-controlled delay circuit, the first input end of the second voltage-controlled delay line is connected with the second input end of the voltage-controlled delay circuit, the second input end of the first voltage-controlled delay line is connected with the third input end of the voltage-controlled delay circuit, the output end of the first voltage-controlled delay line is connected with the second input end of the second voltage-controlled delay line and the first output end of the voltage-controlled delay circuit, and the output end of the second voltage-controlled delay line is connected with the second output end of the voltage-controlled delay circuit. The first voltage-controlled delay line is used for delaying the clock signal based on the first control signal and outputting a first delay signal to the second voltage-controlled delay line and the flip-flop circuit. The second voltage-controlled delay line is used for delaying the first delay signal based on the second control signal and outputting a second delay signal to the flip-flop circuit.

12. The control circuit of claim 11, wherein, The flip-flop circuit comprises a flip-flop and an inverter, wherein the first input end of the flip-flop is connected with the first input end of the flip-flop circuit, the second input end of the flip-flop is connected with the second input end of the flip-flop circuit, the output end of the flip-flop is connected with the first output end of the flip-flop circuit and the input end of the inverter, and the output end of the inverter is connected with the second output end of the flip-flop circuit. The trigger is configured to output a duty cycle signal to the first switch and output an inverted duty cycle signal to the second switch through the inverter based on the first delay signal and the second delay signal, so that a difference between an output voltage of the power converter and a voltage of the load is less than a preset threshold. 13.The control circuit of claim 11 or 12, wherein a delay time between the first delay signal and the clock signal is positively related to an absolute value of a difference between the reference voltage and the ripple voltage. 14.The control circuit of any one of claims 11-13, wherein a delay time between the second delay signal and the first delay signal is positively related to an absolute value of a difference between the reference voltage and the ripple voltage.

15. The control circuit according to any one of claims 9-14, characterized by The control circuit further comprises a voltage-controlled oscillation circuit, an input terminal of the voltage-controlled oscillation circuit is connected to an output terminal of the power converter, and an output terminal of the voltage-controlled oscillation circuit is connected to a third input terminal of the voltage-controlled delay circuit. The voltage-controlled oscillation circuit is configured to output the clock signal to the voltage-controlled delay circuit based on a sampled output voltage of the power converter.

16. The control circuit of any of claims 9-15, wherein, The control circuit further comprises a current sampling circuit, and the power converter further comprises an inductor connected between a series connection point of the first switch and the second switch and an output terminal of the power converter, an input terminal of the current sampling circuit is connected between the series connection point of the first switch and the second switch and the inductor, and an output terminal of the current sampling circuit is connected to a second input terminal of the operational amplifier circuit. The current sampling circuit is configured to collect a current flowing through the inductor and output the ripple voltage to the operational amplifier circuit based on the current flowing through the inductor.

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