Data transmission method, apparatus and system, and device, cluster, product and medium

Abstract

Provided in the present application are a data transmission method, apparatus and system, and a device, a cluster, a product and a medium. The method is applied to a transit device, and comprises: receiving first signaling sent by an input / output chip over a first channel, wherein the first signaling comprises control information and data information, the first channel is one of a plurality of channels between the input / output chip and the transit device, the transit device is a memory controller or a cache, and the control information is used for carrying an operation request of the input / output chip to write data in the data information into the transit device; and on the basis of the first signaling, sending a first response to the input / output chip. The solution can effectively reduce signaling interaction processes, thereby improving the transmission efficiency.

Description

Data transmission method, device, system, equipment, cluster, product and medium

[0001] The present application claims priority to the Chinese patent application No. 202411245732.7, filed on September 5, 2024, with the State Intellectual Property Office of China, and entitled "Data transmission method, device, system, equipment, cluster, product and medium", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of computers, and in particular to a data transmission method, device, system, equipment, cluster, product and medium. BACKGROUND

[0003] As shown in FIG. 1, the computing device can include a processor 110, a cache 120, a memory controller 130, and an input / output chip 140. Among them, the processor 110, the cache 120, the memory controller 130, and the input / output chip 140 communicate through a bus 150. The memory controller 130 is a controller of the memory, used to control the memory. Any two nodes include a request channel, a response channel, a data channel, and a listening channel. Among them, the request channel is used to transmit signaling about the request, the response channel is used to transmit signaling about the response, the data channel is used to transmit signaling about the data, and the listening channel is used to transmit signaling about the listening.

[0004] When the input / output chip 140 receives data, it needs to be sent to the processor 110 through the memory controller 130 and the cache 120. However, at present, the chips need to go through very complex handshake procedures to realize data transmission, resulting in very low data transmission efficiency. SUMMARY

[0005] The present application provides a data transmission method, device, system, equipment, cluster, product and medium, which can effectively reduce the signaling interaction process and improve the transmission efficiency.

[0006] In a first aspect, a data transmission method is provided. A transit device receives a first signaling sent by an input / output chip on a first channel, and sends a first response to the input / output chip based on the first signaling. The first signaling includes control information and data information. The first channel is one of a plurality of channels between the input / output chip and the transit device. The transit device is a memory controller or a cache. The control information is used to carry an operation request of the input / output chip to write data in the data information to the transit device. For example, the first channel can be a request channel or a data channel between the input / output chip and the transit device. The first channel can also be a listening channel or a response channel between the input / output chip and the transit device, or even a newly created channel. In an existing protocol, the control information can be transmitted through a request channel between the input / output chip and the transit device, and the data information is transmitted through a data channel between the input / output chip and the transit device. However, in this application, the control information and the data information are carried in one signaling and transmitted in one channel (for example, a request channel or a data channel).

[0007] In the above solution, the control information and the data information originally specified by the transmission protocol to be transmitted through two channels are combined into one signaling and transmitted through one channel, thereby reducing the complexity of signaling interaction and improving the efficiency of data transmission.

[0008] In some possible designs, the first response sent by the transit device to the input / output chip based on the first signaling includes: in a case where a number of signalings processed by the transit device is greater than or equal to a number threshold, sending a first failure response to the input / output chip and discarding the first signaling; and in a case where the number of signalings processed by the transit device is less than the number threshold, sending a first success response to the input / output chip. The number threshold is determined according to a processing capability of the transit device. Here, the transit device is a cache. The processing capability of the transit device can be determined according to a number of processors of the transit device, a clock frequency of the processor, a number of registers of the processor, and the like.

[0009] In the above scheme, since the capacity of the cache is smaller than the capacity of the memory, the memory unconditionally receives the data information received by the input / output chip, and thus the memory does not send a failure response to the input / output chip. However, the cache receives the data information received by the input / output chip only when needed. Now, the data information is sent to the cache by the input / output chip bypassing the memory, on the premise that the cache needs the data received by the input / output chip, so that the data received by the input / output chip is sent to the cache in advance. Therefore, the cache needs to have the ability to reject, i.e., the ability to send a failure response to the input / output chip.

[0010] In some possible designs, a first operation code carried in the operation code field of the first failure response is different from a second operation code carried in the operation code field of the first success response.

[0011] In some possible designs, the data information includes values of a data error field, a data state field, a data critical shot identification field, a data shot number identification field, a data validity field, a data field, and a byte error field.

[0012] In some possible designs, the control information includes values of a data size field, an address field, a non-secure flag field, a memory attribute field, a snoop attribute field, a logical processor identification field, an expected completion acknowledgement field, and a memory partition monitoring field. The values of the data size field, the address field, the non-secure flag field, the memory attribute field, the snoop attribute field, the logical processor identification field, and the expected completion acknowledgement field of the control information are carried in the reserved field of the first signaling.

[0013] In some possible designs, the control information further includes values of one or more of a prefetch target node identification field, a prefetch target node valid identification field, a prefetch logical processor identification field, a prefetch logical processor valid identification field, and a memory partition monitoring field. The values of the prefetch target node identification field and the prefetch target node valid identification field of the control information are carried in any one of a master node identification field and a data buffer identification field of the first signaling; the values of the prefetch logical processor identification field and the prefetch logical processor valid identification field of the control information are carried in a data validity field of the first signaling; and the value of the memory partition monitoring field of the control information is carried in the other one of the master node identification field and the data buffer identification field of the first signaling.

[0014] In some possible design, the transit device is a memory controller. After receiving the first signaling sent by the input / output chip, the method further includes: sending second signaling to a cache through a second channel, and receiving a second response sent by the cache based on the second signaling. The second signaling includes monitoring information and data information, and the second channel is one of multiple channels between the memory controller and the cache. The monitoring information is used to instruct the cache to ensure cache coherence with other caches and to inform the cache to pull data in the data information from the memory controller. The second channel can be a monitoring channel or a data channel between the memory controller and the cache. The second channel can also be a request channel or a response channel between the memory controller and the cache, or even a newly built channel. In the existing protocol, the monitoring information is transmitted through the monitoring channel between the memory controller and the cache, and the data information is transmitted through the data channel between the memory controller and the cache. However, in this application, the monitoring information and the data information are carried in one signaling and transmitted in one channel (for example, the monitoring channel or the data channel).

[0015] In the above solution, the monitoring information and the data information originally specified by the transmission protocol to be transmitted through two channels are combined into one signaling and transmitted through one channel, thereby reducing the complexity of signaling interaction and improving the efficiency of data transmission.

[0016] In some possible design, the monitoring information includes a value of a prefetch logical processor identification field, a prefetch logical processor valid identification field, an address field, and a non-secure flag field. The values of the prefetch logical processor identification field and the prefetch logical processor valid identification field of the monitoring information are carried in any one of a master node identification field and a data buffer identification field in the second signaling. The values of the address field and the non-secure flag field of the monitoring information are carried in a data validity field in the second signaling.

[0017] In some possible design, the monitoring information further includes a value of a memory partition monitoring field, and the value of the memory partition monitoring field of the monitoring information is carried in the other one of the master node identification field and the data buffer identification field in the second signaling.

[0018] In a second aspect, a data transmission method is provided. An input / output chip sends first signaling to a relay device through a first channel, and receives a first response sent by the relay device based on the first signaling. The first signaling includes control information and data information, the first channel is one of multiple channels between the input / output chip and the relay device, the relay device is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip to write data in the data information to the relay device.

[0019] In some possible designs, the first response sent by the relay device to the input / output chip based on the first signaling includes:

[0020] When the number of signaling processed by the relay device is greater than a number threshold, a first failure response is sent to the input / output chip, and the first signaling is discarded, where the number threshold is determined according to a processing capability of the relay device. When the number of signaling processed by the relay device is less than the number threshold, a first success response is sent to the input / output chip. The processing capability of the relay device is determined according to a number of processors, a clock frequency of the processors, a number of registers of the processors, and the like.

[0021] In some possible designs, a first operation code carried in an operation code field of the first failure response is different from a second operation code carried in an operation code field of the first success response.

[0022] In some possible designs, the data information includes values of a data error field, a data state field, a data critical shot identification field, a data shot number identification field, a data validity field, a data field, and a byte error field.

[0023] In some possible designs, the control information includes values of a data size field, an address field, a non-secure flag field, a memory attribute field, a listen attribute field, a logical processor identification field, and an expected completion acknowledgement field. The values of the data size field, the address field, the non-secure flag field, the memory attribute field, the listen attribute field, the logical processor identification field, and the expected completion acknowledgement field of the control information are carried in a reserved field of the first signaling.

[0024] In some possible design, the control information further includes one or more of values of a prefetch target node identification field, a prefetch target node valid identification field, a prefetch logical processor identification field, a prefetch logical processor valid identification field, and a memory partition monitoring field. The values of the prefetch target node identification field and the prefetch target node valid identification field of the control information are carried in any one of a master node identification field and a data buffer identification field of the first signaling; the values of the prefetch logical processor identification field and the prefetch logical processor valid identification field of the control information are carried in a data validity field of the first signaling; and the value of the memory partition monitoring field of the control information is carried in the other one of the master node identification field and the data buffer identification field of the first signaling.

[0025] In a third aspect, a data transmission apparatus is provided, and the apparatus includes:

[0026] a receiving module, configured to receive first signaling sent by an input / output chip through a first channel, where the first signaling includes control information and data information, the first channel is one of a plurality of channels between the input / output chip and the data transmission apparatus, the data transmission apparatus is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip for writing data in the data information to the relay device;

[0027] a sending module, configured to send first response to the input / output chip based on the first signaling.

[0028] In a fourth aspect, a data transmission apparatus is provided, and the apparatus includes:

[0029] a sending module, configured to send first signaling to a relay device through a first channel, where the first signaling includes control information and data information, the first channel is one of a plurality of channels between the data transmission apparatus and the relay device, the relay device is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip for writing data in the data information to the relay device;

[0030] a receiving module, configured to receive first response sent by the relay device based on the first signaling.

[0031] In a fifth aspect, a data transmission system is provided, and the system includes a relay device and an input / output chip, where the relay device is configured to perform the method in any one of the first aspect, and the input / output chip is configured to perform the method in any one of the second aspect.

[0032] A sixth aspect provides a computing device comprising a processor, a relay device, and an input / output chip, the relay device being configured to perform the method as described in any of the first aspects, and the input / output chip being configured to perform the method as described in any of the second aspects.

[0033] In a seventh aspect, a computing device cluster is provided, comprising multiple computing devices, at least the computing devices being the devices described in the sixth aspect.

[0034] Eighthly, a computer program product comprising instructions is provided, characterized in that, when the instructions are executed by a computing device, the computing device performs the operational steps of the method described in either the first or second aspect.

[0035] A ninth aspect provides a computer-readable storage medium including computer program instructions that, when executed by a computing device, cause the computing device cluster to perform operational steps as described in either the first or second aspect. Attached Figure Description

[0036] Figure 1 is a schematic diagram of the structure of a computing device provided by the prior art;

[0037] Figure 2 is a flowchart illustrating a data transmission method provided in this application;

[0038] Figure 3 is a flowchart illustrating another data transmission method provided in this application;

[0039] Figure 4 is a schematic diagram of a chip packaging form provided in this application;

[0040] Figure 5 is a schematic diagram of the structure of a data transmission system provided in this application. Detailed Implementation

[0041] Referring to Figure 2, which is a flowchart illustrating a data transmission method provided in this application, the data transmission method in this embodiment transmits data from the input / output chips to the processor step by step. As shown in Figure 2, the data transmission method in this embodiment includes:

[0042] S201: The input / output chip sends a first signaling message to the high-speed register through the first channel. Correspondingly, the high-speed register receives the first signaling message sent by the input / output chip through the first channel.

[0043] The first signaling is used for directly writing data in the input / output chip into the cache. In the prior art, since the capacity of the cache is usually small, after the input / output chip receives the data, the data is usually written into a memory with large capacity, then the cache reads the data from the memory, and the processor reads the data from the cache. In the data transmission method of the application, the processor directly writes the data into the cache, and the processor can directly read the data from the cache without the process of reading the data from the memory by the cache and then reading the data from the cache by the processor.

[0044] The first signaling includes control information and data information. The first signaling is transmitted through a first channel. The first channel is one of a plurality of channels between the input / output chip and the cache. The control information is used for carrying an operation request of the input / output chip for writing data in the data information into the cache. For example, the first channel can be a request channel or a data channel between the input / output chip and the cache. The first channel can also be a snoop channel or a response channel between the input / output chip and the cache, or even a newly built channel. In the existing transmission protocol, the control information can be transmitted through the request channel between the input / output chip and the cache, and the data information is transmitted through the data channel between the input / output chip and the cache. However, in the application, the control information and the data information are carried in one signaling and transmitted in one channel (for example, the request channel or the data channel). The transmission protocol can be a cache coherence interconnect (CHI) protocol, a modified, exclusive, shared, invalid (MESI) protocol, etc. Taking the cache coherence protocol as an example, there are four channels between the input / output chip and the cache, including a request channel, a response channel, a data channel and a snoop channel. The request channel is used for transmitting signaling about requests (referred to as request signaling), the response channel is used for transmitting signaling about responses (referred to as response signaling), the data channel is used for transmitting signaling about data (referred to as data signaling), and the snoop channel is used for transmitting signaling about snoop (referred to as snoop signaling).

[0045] Under the prior art condition, to realize the direct writing of data in the input / output chip into the cache usually needs two signaling, first, the input / output chip sends "request signaling" through the request channel, so as to inform the cache that the input / output chip is ready to send data to the cache, and the cache is ready to receive data. Then, the input / output chip sends "data signaling" through the data channel, so as to send data to the cache. In the present application, the first signaling realizes the combination of "request signaling" and "data signaling", that is, the first signaling carries the content of the field in the "request signaling" (i.e., control information) which should be transmitted in the request channel and the content of the field in the "data signaling" (i.e., data information) which should be transmitted in the data channel.

[0046] The input / output chip can send the first signaling to the cache through the data channel or the request channel. However, the implementation mode of the first signaling transmitted through the data channel is different from that of the first signaling transmitted through the request channel. Specifically, when the first signaling is transmitted through the request channel, it can only be transmitted through the format of the request channel. When the first signaling is transmitted through the data channel, it can only be transmitted through the format of the data channel.

[0047] The control information includes the values of the data size field, the address field, the non-secure flag field, the memory attribute field, the snoop attribute field, the logical processor identification field, the expected completion acknowledgement field and the memory partition monitoring field which should be transmitted in the request channel according to the agreement. Optionally, the control information further includes the values of one or more of the prefetch target node identification field, the prefetch target node valid identification field, the prefetch logical processor identification field, the prefetch logical processor valid identification field and the memory partition monitoring field.

[0048] The data information includes the values of the data error field, the data state field, the data critical beat identification field, the data beat number identification field, the data validity field, the data field and the byte error field which should be transmitted in the data channel according to the agreement.

[0049] (1) When the first signaling is transmitted through the request channel, the first signaling can include the fields shown in Table 1:

[0050] Table 1 Fields of the first signaling

[0051] The service quality priority field is used to indicate the priority of the write unique full store request. The target node identification field is used to carry the identification of the target node of the write unique full store request, where the target node is a cache. The source node identification field is used to carry the identification of the source node of the write unique full store request, where the source node is an input / output chip. The transaction identification is used to carry the identification of the transaction of the first signaling. The prefetch target node identification field (Stash NID) is used to carry the identification of the cache for caching (STASH). The prefetch target node valid identification field is used to indicate whether the cache is for caching (STASH). The prefetch logical processor identification field is used to carry the identification of the logical processor for caching (STASH). The prefetch logical processor valid identification field is used to indicate whether the logical processor is for caching (STASH). The operation code field is used to carry various operation codes of the first signaling. The data size field is used to carry the size of the data in the first signaling. The address field is used to carry the storage address. The non-secure flag field is used to indicate whether the transaction is a secure transaction. The memory attribute field is used to define the access attribute of the memory. The snoop attribute field is used to define the attribute of the snoop operation. The logical processor identification is used to carry the identification of the logical processor. The expected completion acknowledgement is used to indicate whether the first signaling needs to return a response signaling. The memory partition monitoring is used to partition and monitor the memory resources. The reserved field is used for other uses.

[0052] It can be understood that the fields of the above first signaling are only used as a specific example, and in actual application, more or fewer fields can be included, which are not limited specifically herein. In addition, the length of each field of the above first signaling is only used as a specific example, and in actual application, the length of each field can include more or fewer bits, which are not limited specifically herein.

[0053] Therefore, the control information (that is, the value of the field required to be transmitted in the request channel according to the agreement) can be carried into the corresponding field of the first signaling. For example, the value of the data size field in the control information is carried in the data size field of the first signaling, the value of the non-secure flag field in the control information is carried in the non-secure flag field of the first signaling, and other fields such as the address field, the memory attribute field, the snoop attribute field, the logical processor identification field, the expected completion acknowledgement field, and the memory partition monitoring field are also the same. The data information is carried in the free field of the first signaling, for example, in the reserved field.

[0054] (2) When the first signaling is transmitted through the data channel, the first signaling can include the fields as shown in Table 2:

[0055] Table 2 Fields of the first signaling

[0056] The service quality priority field (QoS) is used to indicate the priority level of the first signaling. The target node identification field is used to carry the identification of the target node of the first signaling, where the target node is the cache. The source node identification field is used to carry the identification of the source node of the first signaling, where the source node is the input / output chip. The transaction identification is used to carry the identification of the transaction of the first signaling. The operation code field is used to carry various operation codes of the first signaling. The master node identification field is used to mark the master node that processes the request. In a read request, when the data is not returned to the request node by the master node but by other nodes that hold the data, bypassing the master node, the request node is told which master node should send the completion response. The operation code field is used to carry various operation codes of the first signaling. The data error field is used to indicate whether the data is wrong. The data state field is used to indicate the state of the data, such as shared, exclusive, whether modified, etc. The data source field is used to carry the identification of the data source. The busy field is used to indicate the degree of busyness of the downstream. The data buffer identification field is used to carry the buffer number prepared by the downstream node for receiving the write data in a write request, so that the data issued by the request node can be written into the correct buffer. The data key beat identification is used to carry the identification of the data key beat. The data beat number identification is used to carry the identification of the data beat number. The tracking identification field is used to indicate whether the data is tracked. The reserved field is used to reserve other uses. The data validity is used to indicate whether each byte in the data is valid. The data field is used to carry the data. The byte error field is used to indicate whether there is an error correction code (ECC) in each 64 bits of the data.

[0057] It can be understood that the fields of the first signaling described above are only used as a specific example, and in actual application, more or fewer fields can be included, which are not limited specifically herein. In addition, the length of each field of the first signaling described above is only used as a specific example, and in actual application, the length of each field can include more or fewer bits, which are not limited specifically herein.

[0058] Therefore, the data information (that is, the values of the fields required to be transmitted in the data channel according to the agreement) can be carried into the corresponding fields of the first signaling. For example, the value of the data error field in the data information is carried in the data error field of the first signaling, the value of the data state field in the data information is carried in the data state field of the first signaling, and other fields such as the data key beat identification field, the data beat number identification field, the data validity field, the data field, the byte error field, etc. are the same. The control information can be carried in the idle field of the first signaling, such as one or more of the master node identification field, the data buffer identification field, the reserved field, and the data validity field, etc.

[0059] The master node identification field in the first signaling is used to mark the master node processing the request. In the read request, when the data is not returned by the master node but by other nodes holding the data directly to the requesting node bypassing the master node, the requesting node is informed of which master node should send the completion response to, and the master node identification field in the first signaling is not needed, thus, the master node identification field in the first signaling is an idle field.

[0060] The data buffer identification field in the first signaling is used to mark the number of the buffer prepared for receiving the write data. Since the buffer is allocated by the node itself when the "request signaling" and "data signaling" are combined by the first signaling, the buffer does not need to be determined in advance, thus, the data buffer identification field in the first signaling is not needed, thus, the data buffer identification field in the first signaling is an idle field.

[0061] The reserved field in the first signaling is used for reservation for other uses, and is originally a field not used, thus, the reserved field in the first signaling is an idle field.

[0062] The data validity field in the first signaling is used to indicate whether the byte in the data field in the data signaling is valid, and the content of the data validity field in the first signaling can be restored by combining the address field and the data size field, thus, in order to maximize the use of each field in the first signaling, the data validity field in the first signaling can be left empty as an idle field.

[0063] It can be understood that the idle field described above is only a specific embodiment, and in actual application, the idle field can further include more or less fields, or even other fields, which are not limited here.

[0064] In a specific embodiment, the control information can be carried in the idle field of the first signaling, and the specific implementation is as follows:

[0065] The value of the prefetch target node identification field and the prefetch target node validity identification field is carried in any one of the master node identification field and the data buffer identification field in the first signaling. Since the length of the data buffer identification field in the first signaling is 10 bits, and the length of the value of the prefetch target node identification field in the control information is 7-12 bits, the size of the two is comparable, and the content of the prefetch target node identification field in the control information can be inserted into the data buffer identification field in the first signaling. Of course, if the length of the prefetch target node identification field is actually less than 10 bits, the content of the prefetch target node validity identification field (1 bit) can also be inserted into the data buffer identification field in the first signaling. If the length of the data buffer identification field in the first signaling is not enough, the reserved field in the first signaling can also be used.

[0066] The values of the data size field, the address field, the non-secure flag field, the memory attribute field, the snoop attribute field, the logical processor identification field, and the expected completion acknowledgement field of the control information are carried in the data validity field of the first signaling. In addition, the values of the prefetch logical processor identification field and the prefetch logical processor valid identification field can also be carried in the data validity field of the first signaling. Since the length of the data validity field in the first signaling is 64 bits, and the length of the prefetch logical processor identification field in the control information is 5 bits, the length of the prefetch logical processor valid identification field is 1 bit, the length of the data size field is 3 bits, the length of the address field is 45-52 bits, the length of the non-secure flag field is 2 bits, the length of the memory attribute field is 4 bits, the length of the snoop attribute field is 5 bits, and the length of the expected completion acknowledgement field is 1 bit, when the length of the address field is no more than 43 bits, the contents of the prefetch logical processor identification field, the prefetch logical processor valid identification field, the data size field, the address field, the non-secure flag field, the memory attribute field, the snoop attribute field, the logical processor identification field, and the expected completion acknowledgement field in the control information can all be inserted into the data validity field of the first signaling.

[0067] The value of the memory partition monitoring field of the control information is carried in the other one of the master node identification field and the data buffer identification field of the first signaling. Since the length of the master node identification field in the first signaling is 7-12 bits, and the length of the memory partition monitoring field in the control information is 11 bits, the value in the memory partition monitoring field of the control information can be inserted into the master node identification field in the first signaling. If the length of the master node identification field is not enough, the reserved field can be borrowed, or the memory partition monitoring field can be cropped.

[0068] The reserved field of the first signaling can be used to carry a first merge identification, which is used to indicate that the first signaling is a special signaling different from the data signaling. The first merge identification can occupy one or more bits, for example, the first merge identification can occupy one bit, and when the first merge identification is 1, it indicates that the signaling is the first signaling. Since originally all the data transmitted from the data channel is the normal data signaling, now the data transmitted from the data channel includes the first signaling in addition to the data signaling, so the first merge identification needs to be carried in the reserved field to distinguish whether the signaling is a normal signaling or the first signaling.

[0069] It can be understood that the above first signaling is only a specific example, and in actual application, it can also be implemented in other ways, for example, the control information can all be filled into the reserved field of the first signaling, or the prefetch target node identification field and the prefetch target node valid identification field can be filled into the data buffer identification field of the first signaling, and the others remain unchanged, etc.

[0070] After the cache receives the first signaling, the first merge identifier is read from the reserved field, and it is determined that the signaling is not ordinary data signaling, but the first signaling. Then, the cache obtains the control information and the data information from the first signaling. Then, the cache prepares to receive data according to the control information, and saves the data in the cache according to the data information. Since there can be multiple caches, in order to ensure the consistency of multiple caches, only when the cache has the exclusive data permission of the cache, the data can be saved in the cache. Therefore, if the cache has the exclusive data permission, the cache can directly save the data in the cache, if the cache does not have the exclusive data permission, the cache can first send a consistency signaling to the memory controller. After the memory controller receives the consistency signaling, it is determined that the cache needs the exclusive data permission. After the memory controller negotiates with other caches, the cache is given the exclusive data permission, and the message of the exclusive data permission of the cache is sent to the cache through the completion signaling.

[0071] In the case that the number of signalings processed by the transit device is greater than or equal to the number threshold, the first signaling is discarded, and step S202 is entered. The number threshold is determined according to the processing capacity of the transit device. The processing capacity of the transit device can be determined according to the number of processors of the transit device, the clock frequency of the processor, the number of registers of the processor, etc. In the case that the number of signalings processed by the transit device is less than the number threshold, step S203 is entered.

[0072] S202: The cache sends a first failure response to the input / output chip through the response channel. Correspondingly, the input / output chip receives the first failure response sent by the cache through the response channel.

[0073] The first failure response is used to notify the input / output chip that the write operation to the cache is failed. Since the capacity of the cache is smaller than that of the memory, the memory is to unconditionally receive the data received by the input / output chip, and thus the memory is not to send the failure response to the input / output chip. However, the cache is to receive the data received by the input / output chip when needed. The present application is to use the input / output chip to directly write the data to the cache, which actually assumes that the cache needs the data received by the input / output chip, and thus sends the data received by the input / output chip to the cache in advance. However, in fact, the cache does not necessarily need the data received by the input / output chip. For example, when the cache is busy, the cache does not need the input / output chip to send the data to the cache. Therefore, the cache needs to have the ability to reject, i.e., the ability to send the failure response to the input / output chip. The first failure response can include the fields shown in Table 3:

[0074] Table 3 Fields of the first failure response

[0075] The quality of service priority field (QoS) is used to indicate the priority of the first failure response. The target node identification field is used to carry the identification of the target node of the first failure response, where the target node is the input / output chip. The source node identification field is used to carry the identification of the source node of the first failure response, where the source node is the cache. The transaction identification is used to carry the identification of the transaction of the first failure response. The operation code field is used to carry the first operation code of the first failure response. The data error field is used to indicate whether the data is wrong. The data state field is used to indicate the state of the data, such as shared, exclusive, whether modified, etc. The pull data field is used to indicate whether the data needs to be pulled from the input / output chip. Since the input / output chip has already sent the data to the cache in advance, the data does not need to be pulled here. The busy field is used to indicate the degree of busyness of the downstream. The tracking identification field is used to indicate whether the data is tracked. The data buffer identification field is used to write the buffer number prepared by the downstream node for receiving the write data when the write request is issued, so that the data issued by the request node can be written into the correct buffer.

[0076] S203: The cache sends the listen unique stash (SnpUniqueStash) signaling to the processor through the listening channel. Correspondingly, the processor receives the listen unique stash signaling sent by the cache through the listening channel.

[0077] The listening unique store signaling is used to inform the processor that the data can be pulled from the cache. In a specific embodiment, the listening unique store signaling sent by the cache to the processor can be similar to the listening unique store signaling sent by the cache to the processor in the prior art, which will not be described here.

[0078] After the processor receives the listening unique store signaling sent by the cache, the processor knows that the data can be obtained from the cache. Similarly, since the data corresponding to the storage address in the processor can be stored in the old data, after the processor receives the listening unique store signaling sent by the cache, in order to ensure the consistency of the data, the old data in the storage address needs to be invalidated, so that the processor will not incorrectly use the old data in the storage address which has been invalidated, thereby causing an error.

[0079] S204: The processor sends a data pull request to the cache through the request channel. Correspondingly, the cache receives the data pull request sent by the processor through the request channel.

[0080] The data pull request is used to pull the data from the cache. In a specific embodiment, the data pull request sent by the processor to the cache can be similar to the data pull request sent by the processor to the cache in the prior art, which will not be described here.

[0081] If the processor needs to use the data, it will determine whether the data stored in the storage address corresponding to the data in the processor is valid. If the data in the storage address is valid, the processor can directly use the data in the storage address. If the data in the storage address is invalid, the processor cannot use the data in the storage address, but sends a data pull request to the cache. Here, the data in the storage address in the processor has been invalidated, so the processor needs to send a data pull request to the memory controller.

[0082] S205: The cache sends a first success response to the input / output chip through the response channel. Correspondingly, the input / output chip receives the first success response sent by the cache through the response channel.

[0083] The first success response is used to inform the input / output chip that the data is successfully written into the cache. The first success response and the first failure response include the same fields, which are shown in Table 3. The difference between the first success response and the first failure response is that the value of the opcode field of the first success response is the first opcode, and the value of the opcode field of the first failure response is the second opcode, i.e., the value of the opcode field of the first success response is different from the value of the opcode field of the first failure response.

[0084] S206: The cache sends data transfer (CompData) signaling to the processor through the data channel. Accordingly, the processor receives the data transfer signaling sent by the cache through the data channel.

[0085] The data transfer signaling is used to send data to the processor. In a specific embodiment, the data transfer signaling can be similar to the data transfer signaling sent by the cache to the processor in the existing data transfer method, which will not be described here.

[0086] After the processor receives the data transfer signaling sent by the cache, the processor can obtain data from the data transfer signaling, store the data in a corresponding storage address, and set the data in the storage address as valid. Thus, the processor can use the data in the storage address.

[0087] S207: The processor sends completion acknowledgement (CompAck) signaling to the cache through the response channel. Accordingly, the cache receives the completion acknowledgement signaling sent by the processor through the response channel.

[0088] The completion acknowledgement signaling is used to inform the cache that the data has been successfully received. In a specific embodiment, the completion acknowledgement signaling can be similar to the completion acknowledgement signaling sent by the processor to the cache in the existing data transfer method, which will not be described here.

[0089] Referring to FIG. 3, FIG. 3 is a flow diagram of another data transfer method provided by the present application. The data transfer method in the embodiment is used to transfer data in an input / output chip to a processor step by step. As shown in FIG. 3, the data transfer method in the embodiment includes:

[0090] S301: The input / output chip sends first signaling to the memory controller through the first channel. Accordingly, the memory controller receives the first signaling sent by the input / output chip through the first channel.

[0091] The first signaling is used to directly write data in the input / output chip into the memory controller, and then wait for the processor to read the data from the memory controller.

[0092] The first signaling includes control information and data information. The first signaling is transmitted through a first channel. The first channel is one of multiple channels between the input / output chip and the memory controller. The control information is used to carry an operation request of the input / output chip to write data in the data information to the memory controller. For example, the first channel can be a request channel or a data channel between the input / output chip and the memory controller. The first channel can also be a snoop channel or a response channel between the input / output chip and the memory controller, or even a newly created channel. In the existing transmission protocol, the control information can be transmitted through the request channel between the input / output chip and the memory controller, and the data information is transmitted through the data channel between the input / output chip and the memory controller. However, in the present application, the control information and the data information are carried in one signaling and transmitted in one of the channels (for example, the request channel or the data channel). According to the cache coherence protocol, there are four channels between the input / output chip and the memory controller, including the request channel, the response channel, the data channel, and the snoop channel.

[0093] Under the existing technical conditions, to achieve direct writing of data in the input / output chip into the memory controller, two signalings are generally required. First, the input / output chip sends a "request signaling" through the request channel, so as to notify the memory controller that the input / output chip is ready to send data to the memory controller, and the memory controller is ready to receive data. Then, the input / output chip sends a "data signaling" through the data channel, so as to send data to the memory controller. In the present application, the first signaling realizes the combination of the "request signaling" and the "data signaling", that is, the first signaling simultaneously carries the content of the field in the "request signaling" (i.e., the control information) that should be transmitted in the request channel according to the transmission protocol, and the content of the field in the "data signaling" (i.e., the data information) that should be transmitted in the data channel according to the transmission protocol.

[0094] The input / output chip can send the first signaling to the memory controller through the data channel or the request channel. However, the implementation of the first signaling transmitted through the data channel is different from the implementation of the first signaling transmitted through the request channel. Specifically, when the first signaling is transmitted through the request channel, it can only be transmitted through the format of the request channel. When the first signaling is transmitted through the data channel, it can only be transmitted through the format of the data channel.

[0095] It can be understood that the first signaling in step S301 of the data transmission method of the embodiment and the first signaling in step S201 of the data transmission method shown in FIG. 2 are basically the same, and the difference is that the target node identification field in the first signaling in step S301 is the identification of the memory controller, and the target node identification field in the first signaling in step S201 is the identification of the cache.

[0096] S302: The memory controller sends a first success response to the input / output chip through the response channel. Correspondingly, the input / output chip receives the first success response sent by the memory controller through the response channel.

[0097] The first success response sent by the memory controller to the input / output chip through the response channel is used to notify the input / output chip that the memory controller successfully receives the data. In a specific embodiment, the first success response in step S302 of the data transmission method of the embodiment and the first success response in step S205 of the data transmission method shown in FIG. 2 are basically the same, and the difference is that the source node identification field in the first success response in step S302 is the identification of the memory controller, and the source node identification field in the first success response in step S205 is the identification of the cache.

[0098] S303: The memory controller sends a second signaling to the cache through the fourth channel. Correspondingly, the cache receives the second signaling sent by the memory controller through the fourth channel.

[0099] The second signaling is used to directly write the data in the memory controller into the cache, and then wait for the processor to read the data from the cache.

[0100] The second signaling includes monitoring information and data information. The second signaling includes monitoring information and data information, the second channel is one of the plurality of channels between the memory controller and the cache, the monitoring information is used to instruct the cache to ensure cache coherence with other caches and notify the cache to pull data in the data information from the memory controller. According to the regulation of the cache coherence protocol, there are four channels between the memory controller and the cache, including a request channel, a response channel, a data channel, and a monitoring channel.

[0101] Under the prior art condition, to realize the direct writing of data in the memory controller into the cache usually needs two signaling, first, the memory controller sends the "monitoring signaling" through the monitoring channel, so as to inform the cache that the memory controller is ready to send data to the cache, and the cache is ready to receive data. Then, the memory controller sends the "data signaling" through the data channel, so as to send the data to the cache. In the present application, the second signaling realizes the combination of the "monitoring signaling" and the "data signaling", that is, the second signaling carries the content of the field in the "monitoring signaling" (i.e., the monitoring information) which should be transmitted in the monitoring channel and the content of the field in the "data signaling" (i.e., the data information) which should be transmitted in the data channel.

[0102] The memory controller can send the second signaling to the cache through the data channel or the monitoring channel. However, the implementation of the second signaling transmitted through the data channel is different from the implementation of the second signaling transmitted through the monitoring channel. Specifically, when the first signaling is transmitted through the monitoring channel, it can only be transmitted through the format of the monitoring channel. When the second signaling is transmitted through the data channel, it can only be transmitted through the format of the data channel.

[0103] The monitoring information includes the pre-fetch logic processor identification field, the pre-fetch logic processor valid identification field, the address field and the non-secure flag field. Optionally, the monitoring information also includes the value of the memory partition monitoring field.

[0104] The data information includes the values of the data error field, the data state field, the data key beat identification field, the data beat number identification field, the data validity field, the data field, the byte error field and the like which are required to be transmitted in the data channel according to the agreement.

[0105] (1) When the second signaling is transmitted through the monitoring channel, the second signaling can include the fields shown in Table 4:

[0106] Table 4 Fields of the second signaling

[0107] The service quality priority field is used to indicate the priority level of the second signaling. The target node identification field is used to carry the identification of the target node of the second signaling, where the target node is the cache. The source node identification field is used to carry the identification of the source node of the second signaling, where the source node is the memory controller. The transaction identification is used to carry the identification of the transaction of the second signaling. The prefetch target node identification field (Stash NID) is used to carry the identification of the cache for caching (STASH). The prefetch target node valid identification field is used to indicate whether the cache is for caching (STASH). The prefetch logical processor identification field is used to carry the identification of the logical processor for caching (STASH). The prefetch logical processor valid identification field is used to indicate whether the logical processor is for caching (STASH). The operation code field is used to carry various operation codes of the second signaling. The address field is used to carry the memory address. The non-secure flag field is used to indicate whether the transaction is a secure transaction. The tracking identification field is used to indicate whether the data is tracked. The memory partition monitoring is used to indicate which bytes in the data signaling are valid. The reserved field is used to leave other uses.

[0108] It can be understood that the above-mentioned fields of the second signaling are only used as a specific example, and in actual application, more or fewer fields can be included, which are not limited here. In addition, the length of each field of the above-mentioned second signaling is only used as a specific example, and in actual application, the length of each field can include more or fewer bits, which are not limited here.

[0109] Therefore, the monitoring information (that is, the value of the field required to be transmitted in the monitoring channel according to the agreement) can be carried into the corresponding field of the second signaling. For example, the value of the prefetch target node identification field in the monitoring information is carried in the prefetch target node identification field of the second signaling, the value of the prefetch target node valid identification field in the monitoring information is carried in the prefetch target node valid identification field of the second signaling, and other fields such as the address field, the non-secure flag field, the memory partition monitoring field, etc. of the monitoring information are also the same. The data information is carried in the free field of the second signaling, for example, in the reserved field.

[0110] (2) When the second signaling is transmitted through the data channel, the second signaling can include the fields as shown in Table 2:

[0111] Therefore, the data information (i.e. the value of the field required to be transmitted in the data channel according to the agreement) can be carried into the corresponding field of the second signaling. For example, the value of the data error field in the data information is carried into the data error field of the second signaling, the value of the data state field in the data information is carried into the data state field of the second signaling, and the same applies to other fields such as the data key shot identification field, the data shot number identification field, the data validity field, the data field, the byte error field, etc. The monitoring information can be carried in the idle field of the second signaling, such as one or more of the master node identification field, the data buffer identification field, the reserved field, and the data validity field, etc.

[0112] The master node identification field in the second signaling is used to mark the master node processing the request. In the read request, when the data is not returned by the master node but by other nodes holding the data directly to the requesting node bypassing the master node, the requesting node is informed of which master node should send the completion response, and the master node identification field in the second signaling is not required to be used, therefore, the master node identification field in the second signaling is an idle field.

[0113] The data buffer identification field in the second signaling is used to mark the number of the buffer prepared for receiving the write data. Since the "monitoring signaling" and "data signaling" are combined through the second signaling, and the buffer is allocated by the node itself without the need of determining the buffer in advance, the data buffer identification field is not required to be used, therefore, the data buffer identification field in the second signaling is an idle field.

[0114] The reserved field in the second signaling is also used for reserving other uses, and is originally a field not used, therefore, the reserved field in the second signaling is an idle field.

[0115] The data validity field in the second signaling is used to indicate whether the byte in the data field in the data signaling is valid, and the content of the data validity field in the second signaling can be restored through the combination of the address field and the data size field, therefore, in order to maximize the use of each field in the second signaling, the data validity field in the second signaling can be left empty as an idle field.

[0116] It can be understood that the above idle field is only a specific embodiment, and in actual application, the idle field can further include more or less fields, or even other fields, which are not specifically limited here.

[0117] In a specific embodiment, the specific implementation of the monitoring information carried in the idle field of the second signaling is as follows:

[0118] The value of the pre-fetch logic processor identification field and the pre-fetch logic processor valid identification field is carried in any one of the master node identification field and the data buffer identification field in the second signaling. Since the length of the data buffer identification field in the second signaling is 10 bits, and the length of the pre-fetch target node identification field in the listening information is 7-12 bits, the size of the two is comparable, and the content of the pre-fetch target node identification field in the listening information can be inserted into the data buffer identification field in the second signaling. Of course, if the length of the pre-fetch target node identification field is actually less than 10 bits, then the content of the pre-fetch target node valid identification field (1 bit) can also be inserted into the data buffer identification field in the second signaling. If the length of the data buffer identification field is not enough, the reserved field can also be borrowed.

[0119] The value of the address field and the non-security flag field is carried in the data validity field in the second signaling. Since the length of the data validity field can be 64 bits, the length of the address field is 45-52 bits, and the length of the non-security flag field is 2 bits, the content of the address field and the non-security flag field in the listening information can be inserted into the data validity field in the second signaling.

[0120] The value of the memory partition monitoring field of the listening information is carried in the other of the master node identification field and the data buffer identification field in the second signaling. Since the length of the master node identification field in the second signaling is 7-12 bits, and the length of the memory partition monitoring field in the control information is 11 bits, the value in the memory partition monitoring field in the control information can be inserted into the master node identification field in the first signaling. If the length of the master node identification field is not enough, the reserved field can be borrowed, or the memory partition monitoring field can be cropped.

[0121] The reserved field of the second signaling can be used to carry a second merge identification, which is used to indicate that the second signaling is a special signaling different from the data signaling. The second merge identification can occupy one or more bits, for example, the second merge identification can occupy one bit, and when the second merge identification is 1, it indicates that the signaling is the second signaling. Because originally transmitted from the data channel is all ordinary data signaling, now in addition to the data signaling, the second signaling is also transmitted from the data channel, so the second merge identification needs to be carried in the reserved field to distinguish whether the signaling is an ordinary signaling or a second signaling.

[0122] It can be understood that the above-mentioned second signaling is only a specific example, and in actual application, it can also be implemented in other ways, for example, the listening information can be filled into the reserved field of the second signaling, or the pre-fetch target node identification field and the pre-fetch target node valid identification field can be filled into the data buffer identification field of the second signaling, and the others remain unchanged, etc.

[0123] After the cache receives the second signaling, the second merge identifier is read from the reserved field, it is determined that the signaling is not the ordinary data signaling, but the second signaling, then the cache obtains the monitoring information and the data information from the second signaling. Then, the cache prepares to receive data according to the monitoring information, and saves the data in the cache according to the data information. Since there can be multiple caches, in order to ensure the consistency of multiple caches, only when the cache has the exclusive data permission of the cache, the data can be saved in the cache. Therefore, if the cache has the exclusive data permission, the cache can directly save the data in the cache, if the cache does not have the exclusive data permission, the cache can first send a consistency signaling to the memory controller, after the memory controller receives the consistency signaling, it is determined that the cache needs the exclusive data permission, the memory controller gives the cache the exclusive data permission after negotiating with other caches, and sends the message of the exclusive data permission of the cache to the cache through the completion signaling.

[0124] S304: The cache sends a second response to the memory controller through the response channel. Correspondingly, the memory controller receives the second response sent by the cache through the response channel.

[0125] The second response is used to notify the memory controller that the high-speed cache successfully receives the data. In a specific embodiment, the second response of step S304 in the data transmission method of the embodiment is basically the same as the completion confirmation signaling of step S206 in the data transmission method shown in FIG. 2, the difference is that the source node identifier field in the second response of step S304 is the identifier of the cache, and the destination node identifier field is the identifier of the memory controller, while the source node identifier field in the second response of step S206 in the completion confirmation signaling is the identifier of the processor, and the destination node identifier field is the identifier of the cache.

[0126] S305: The cache sends a monitoring unique storage signaling to the processor through the monitoring channel. Correspondingly, the processor receives the monitoring unique storage signaling sent by the cache through the monitoring channel.

[0127] The cache sends a monitoring unique storage signaling to the processor through the monitoring channel to notify the processor that the data can be pulled from the cache. In a specific embodiment, the monitoring unique storage signaling sent by the cache to the processor in step S203 of the data transmission method shown in FIG. 2 is similar to the monitoring unique storage signaling, which will not be described here.

[0128] After the processor receives the monitoring unique storage signaling sent by the cache, the processor knows that the data can be obtained from the cache. Similarly, since the storage address corresponding to the data in the processor can store old data, after the processor receives the monitoring unique storage signaling sent by the cache, in order to ensure the consistency of the data, the old data in the storage address needs to be invalidated, so that the processor will not incorrectly use the old data in the storage address of the processor which has been invalidated, thereby causing an error to occur.

[0129] S306: The processor sends a data pull request to the cache through the request channel. Correspondingly, the cache receives the data pull request sent by the processor through the request channel.

[0130] The data pull request can be similar to the data pull request sent by the processor to the cache in step S204 of the data transmission method shown in FIG. 2, and will not be described here.

[0131] S307: The cache sends data transmission signaling to the processor through the data channel. Correspondingly, the processor receives the data transmission signaling sent by the cache.

[0132] The data transmission signaling can be similar to the data transmission signaling sent by the cache to the processor in step S206 of the data transmission method shown in FIG. 2, and will not be described here.

[0133] S308: The processor sends a completion confirmation signaling to the cache through the response channel. Correspondingly, the cache receives the completion confirmation signaling sent by the processor through the response channel.

[0134] The completion confirmation signaling can be similar to the completion confirmation signaling in step S207 of the data transmission method shown in FIG. 2, and will not be described here.

[0135] In a possible embodiment, the processor 110, the cache 120, the memory controller 130 and the input / output chip 140 shown in FIG. 1 can adopt the packaging form shown in FIG. 4. The input / output chip 140 is arranged on the left of the transmission channel, the cache 120 is arranged on the right of the transmission channel, the memory controller 130 is arranged on the left of the cache 120, and the processor 110 is arranged on the right of the cache 120. Because the packaging form makes the distance between the input / output chip 140 and the memory controller 130 very far, and the distance between the memory controller 130 and the processor 110 very far. When the input / output chip 140 needs to communicate with the memory controller 130, it needs to pass through the transmission channel and the cache, and the transmission time is very long. When the memory controller 130 needs to communicate with the processor 110, it needs to pass through the cache, and the transmission time is also very long. Therefore, when the data in the input / output chip is transmitted to the processor step by step by using the data transmission method of the prior art, the communication delay is very long because of the large number of handshakes. When the data in the input / output chip is transmitted to the processor step by step by using the data transmission method shown in FIG. 2 of the present application, the communication delay is reduced because the number of handshakes is reduced, and the input / output chip can directly write data into the cache which is close instead of the memory controller which is far, thereby reducing the communication delay. When the data in the input / output chip is transmitted to the processor step by step by using the data transmission method shown in FIG. 3 of the present application, the number of handshakes is effectively reduced by using two combined signals, i.e., the first signaling and the second signaling, thereby reducing the communication delay.

[0136] Referring to FIG. 5, FIG. 5 is a structural schematic diagram of a data transmission device provided by the present application. As shown in FIG. 5, the data transmission device provided by the present application comprises an input / output chip and a relay device. The input / output chip comprises a receiving module 211 and a sending module 212. The relay device comprises a sending module 221 and a receiving module 222.

[0137] The sending module 212 of the input / output chip sends a first signaling to the receiving module 222 of the relay device through a first channel. Then, the sending module 221 of the relay device sends the first signaling to the receiving module 211 of the input / output chip based on the first signaling. The first signaling comprises control information and data information, the first channel is one of a plurality of channels between the input / output chip and the relay device, the relay device is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip for writing data in the data information into the relay device.

[0138] The sending module 212 can be configured to perform the steps performed by the sender in step S201 shown in FIG. 2 or step S301 shown in FIG. 3 for sending the first signaling. The receiving module 222 can be configured to perform the steps performed by the receiver in step S201 shown in FIG. 2 or step S301 shown in FIG. 3 for sending the first signaling.

[0139] The sending module 221 can be configured to perform the steps performed by the sender in step S202 shown in FIG. 2 for sending the first failure response, step S205 shown in FIG. 2 for sending the first success response, or step S302 shown in FIG. 3 for sending the first success response. The receiving module 211 can be configured to perform the steps performed by the receiver in step S202 shown in FIG. 2 for sending the first failure response, step S205 shown in FIG. 2 for sending the first success response, or step S302 shown in FIG. 3 for sending the first success response.

[0140] For the sake of simplicity, the data transmission apparatus is not described in detail here. For details, please refer to FIG. 2, FIG. 3, and the related description.

[0141] The embodiment of the present application further provides a computing device cluster. The computing device cluster includes at least one computing device as shown in FIG. 1. The server can be a central server, an edge server, or a local server in a local data center, etc.

[0142] The embodiment of the present application further provides a computer program product containing instructions. The computer program product can be software or a program product containing instructions, which can run on a computing device or be stored in any available medium. When the computer program product runs on at least one computing device, the at least one computing device is caused to perform the method for preventing redundant code generation.

[0143] The embodiment of the present application further provides a computer readable storage medium. The computer readable storage medium can be any available medium that a computing device can store or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk), etc. The computer readable storage medium contains instructions, which instruct the computing device to perform the method for preventing redundant code generation.

[0144] Finally, it should be noted that: the above examples are used to illustrate the technical solutions of the present application, but not limited to them; although the present application is described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. A data transmission method, characterized by, The method is applied to a relay device, and the method comprises: receiving first signaling sent by an input / output chip on a first channel, wherein the first signaling comprises control information and data information, the first channel is one of multiple channels between the input / output chip and the relay device, the relay device is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip to write data in the data information to the relay device; sending a first response to the input / output chip based on the first signaling.

2. The method of claim 1, wherein, The sending of the first response to the input / output chip based on the first signaling comprises: in a case where a quantity of signaling processed by the relay device is greater than or equal to a quantity threshold, sending a first failure response to the input / output chip and discarding the first signaling, wherein the quantity threshold is determined according to a processing capability of the relay device; in a case where the quantity of signaling processed by the relay device is less than the quantity threshold, sending a first success response to the input / output chip.

3. The method of claim 2, wherein, A first operation code carried in an operation code field of the first failure response is different from a second operation code carried in an operation code field of the first success response.

4. The method according to any one of claims 1 to 3, characterized in that, The control information comprises a data size field, an address field, a non-secure flag field, a memory attribute field, a snoop attribute field, a logical processor identification field, and a value of an expected completion acknowledgement field, the data size field, the address field, the non-secure flag field, the memory attribute field, the snoop attribute field, the logical processor identification field, and the value of the expected completion acknowledgement field of the control information are carried in a reserved field of the first signaling.

5. The method of claim 4, wherein, The control information further comprises a value of one or more of a prefetch target node identification field, a prefetch target node valid identification field, a prefetch logical processor identification field, a prefetch logical processor valid identification field, and a memory partition monitoring field; the value of the prefetch target node identification field and the prefetch target node valid identification field is carried in any one of a home node identification field and a data buffer identification field of the first signaling; the value of the prefetch logical processor identification field and the prefetch logical processor valid identification field is carried in a data validity field of the first signaling; the value of the memory partition monitoring field of the control information is carried in the other one of the home node identification field and the data buffer identification field of the first signaling.

6. The method according to any one of claims 1 to 5, characterized in that, In a case where the relay device is a memory controller, after receiving the first signaling sent by the input / output chip on the first channel, the method further comprises: sending second signaling to a cache through a second channel, wherein the second signaling comprises listening information and the data information, the second channel is one of multiple channels between the memory controller and the cache, the listening information is used to instruct the cache to ensure cache coherency with other caches and to inform the cache to pull data in the data information from the memory controller; and receiving a second response sent by the cache based on the second signaling.

7. The method of claim 6, wherein, The monitoring information includes a pre-fetch logical processor identification field, a pre-fetch logical processor valid identification field, an address field of the monitoring information, and a non-secure flag field, Values of the pre-fetch logical processor identification field and the pre-fetch logical processor valid identification field are carried in any one of a master node identification field and a data buffer identification field in the second signaling; Values of the address field and the non-secure flag field are carried in a data validity field in the second signaling.

8. The method of claim 7, wherein, The monitoring information further includes a value of a memory partition monitoring field, and the value of the memory partition monitoring field of the monitoring information is carried in the other one of the master node identification field and the data buffer identification field in the second signaling.

9. A data transmission method, characterized by, The method is applied to an input / output chip, and the method comprises: sending, through a first channel, a first signaling to a relay device, wherein the first signaling includes control information and data information, the first channel is one of a plurality of channels between the input / output chip and the relay device, the relay device is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip to write data in the data information to the relay device; receiving a first response sent by the relay device based on the first signaling.

10. The method of claim 9, wherein, The receiving the first response sent by the relay device based on the first signaling comprises: in a case where a quantity of signalings processed by the relay device is greater than a quantity threshold value, receiving a first failure response sent by the relay device based on the first signaling, wherein the quantity threshold value is determined according to a processing capability of the relay device; in a case where the quantity of signalings processed by the relay device is less than the quantity threshold value, receiving a first success response sent by the relay device based on the first signaling.

11. The method of claim 10, wherein, A first operation code carried in an operation code field of the first failure response is different from a second operation code carried in an operation code field of the first success response.

12. The method according to any one of claims 9-11, characterized in that, The control information includes a data size field, an address field, a non-secure flag field, a memory attribute field, a listening attribute field, a logical processor identification field, and a value of an expected completion acknowledgement field, and before the first signaling is sent to the relay device through the first channel, the method further comprises: carrying the values of the data size field, the address field, the non-secure flag field, the memory attribute field, the listening attribute field, the logical processor identification field, and the expected completion acknowledgement field of the control information in a reserved field of the first signaling.

13. The method of claim 12, wherein, The control information further includes values of one or more of a pre-fetch target node identification field, a pre-fetch target node valid identification field, a pre-fetch logical processor identification field, a pre-fetch logical processor valid identification field, and a memory partition monitoring field, and the method further comprises: carrying the values of the pre-fetch target node identification field and the pre-fetch target node valid identification field of the control information in any one of a master node identification field and a data buffer identification field of the first signaling; The value of the pre-fetch logical processor identification field and the value of the pre-fetch logical processor valid identification field of the control information are carried in a reserved field of the first signaling; The value of the memory partition monitoring field of the control information is carried in the other one of the master node identification field and the data buffer identification field of the first signaling.

14. A data transmission apparatus, characterized by comprising: The apparatus comprises: The receiving module is configured to receive first signaling sent by an input / output chip through a first channel, wherein the first signaling comprises control information and data information, the first channel is one of a plurality of channels between the input / output chip and a data transmission apparatus, the data transmission apparatus is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip for writing data in the data information to the relay device. The sending module is configured to send first response to the input / output chip based on the first signaling.

15. A data transmission apparatus, characterized by comprising: The apparatus comprises: The sending module is configured to send first signaling to a relay device through a first channel, wherein the first signaling comprises control information and data information, the first channel is one of a plurality of channels between the data transmission apparatus and the relay device, the relay device is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip for writing data in the data information to the relay device. The receiving module is configured to receive first response sent by the relay device based on the first signaling.

16. A data transmission system, characterized by The system comprises a relay device and an input / output chip, the relay device is configured to perform the method of any one of claims 1 to 8, and the input / output chip is configured to perform the method of any one of claims 9 to 13.

17. A computing device, comprising: The computing device comprises a processor, a relay device, and an input / output chip, the relay device is configured to perform the method of any one of claims 1 to 8, and the input / output chip is configured to perform the method of any one of claims 9 to 13.

18. A cluster of computing devices, characterized in that, The system comprises a plurality of computing devices, at least one of the computing devices is the device of claim 17.

19. A computer program product comprising instructions, characterized in that, The instructions, when executed by a computing device, cause the computing device to perform the operational steps of the method of any one of claims 1 to 13.

20. A computer-readable storage medium, characterized in that, The computer program instructions, when executed by a computing device, cause the computing device cluster to perform the operational steps of the method of any one of claims 1 to 13.

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