Methods of determining RFIC layout

Abstract

There is described computer-implemented methods of determining a layout for a radio- frequency integrated circuit, RFIC One such method comprises: retrieving, from a database of layout designs, a plurality of candidate layout designs for the layout of the RFIC; generating a plurality of local child layout designs, wherein each of the local child layout designs is generated by applying an evolution to a selected one of the plurality of retrieved candidate layout designs; determining performance parameters of one or more selected local child layout designs; adding the one or more selected local child layout designs together with the associated determined performance parameters to the database of layout designs; generating a plurality of global child layout designs, wherein each of the global child layout designs is generated by applying an evolution to a respective one of the plurality of retrieved candidate layout designs; determining performance parameters of one or more selected global child layout designs; adding the one or more selected global child layout designs together with the associated determined performance parameters to the database of layout designs; and selecting as the determined layout for the RFIC, from the updated database of layout designs, a layout design whose associated performance parameters most closely match target performance parameters provided by a user. Another such method comprises: providing data associated with one or more design parameters of a candidate RFIC layout design; applying a Bayesian neural network, BNN, to the provided data to determine: predicted performance parameters of an RFIC having a layout in accordance with the candidate RFIC layout design, and a prediction uncertainty associated with the corresponding one or more predicted performance parameters; and adjusting the candidate RFIC layout design based on the predicted performance parameters and the prediction uncertainty to determine the layout of the RFIC.

Description

[0001] 008841090 1

[0002] METHODS OF DETERMINING RFIC LAYOUT

[0003] Field of the Invention

[0004] The present invention relates to methods for designing and optimising the layout of radio-frequency integrated circuits and particularly, although not exclusively, to optimising the layout of power amplifier radio-frequency integrated circuits.

[0005] Background

[0006] In an increasingly connected world, radio-frequency (RF) communications and transmissions have been vital to realising communication, navigation (e.g., radar), and the interconnection of devices - for example as part of the Internet of Things (loT).

[0007] To realise RF communication and transmission, radio-frequency integrated circuits (RFICs) have been developed. RFICs facilitate wireless transmission of radio-frequency signals and offer systems the benefit of providing a single-technology solution for realising a wireless transceiver.

[0008] RFICs find use in a variety of contexts, including wireless communication (e.g., in an loT setting), radar systems, wireless sensor networks, and satellite communications. In some configurations, RFICs can be configured to operate as and be used as power amplifiers (PA) to boost the power / amplitude of a received radio-frequency signal.

[0009] RFICs may comprise a variety of components arranged according to a schematic and physical implementation (known as a ‘layout’). These components may include any one or more of: impedance matches, low-noise amplifiers, modulators, demodulators, power amplifiers, and radio-frequency switches. The layouts for different RFICs configured for different use cases may differ drastically depending on the user requirements for the RFIC, and the layout of an RFIC is known to impact the performance / efficiency of an RFIC’s operation.

[0010] The present invention has been devised in light of the above considerations.

[0011] Summary of the Invention

[0012] In a general sense, the present disclosure provides methods for determining a radio-frequency integrated circuit (RFIC) layout. These methods may include the application of an appropriately trained Bayesian neural network (BNN) to determine the RFIC layout (based on both a predicted performance of a candidate layout design and a prediction uncertainty indicative of a degree of uncertainty in the BNN’s prediction); and / or the implementation of a hybridised search model that implements both local and global searches of the design parameter space to ensure that the performance of the determined layout is optimised.

[0013] In a first aspect, there is provided a computer-implemented method of determining a layout for a radiofrequency integrated circuit (RFIC). The method comprises: retrieving from a database of layout designs, 008841090 2 a plurality of candidate layout designs for the layout of the RFIC; and generating a plurality of local child layout designs. Each of the local child layout designs is generated by applying an evolution to a selected one of the plurality of retrieved candidate layout designs. The method further comprises: determining performance parameters of one or more selected local child layout designs; and adding the one or more selected local child layout designs together with the associated determined performance parameters to the database of layout designs. The method further comprises generating a plurality of global child layout designs. Each of the global child layout designs is generated by applying an evolution to a respective one of the plurality of retrieved candidate layout designs. The method further comprises: determining performance parameters of one or more selected global child layout designs; and adding the one or more selected global child layout designs together with the associated determined performance parameters to the database of layout designs. The method further comprises selecting, as the determined layout from the RFIC, from the updated database of layout designs, a layout design whose associated performance parameters most closely match target performance parameters provided by a user.

[0014] In the context of RFIC layout design, there may be a plurality of design parameters that need to be selected and refined to arrive at a final (selected) RFIC layout. These design parameters may define an n-dimensional design parameter space, wherein each dimension of the design parameter space corresponds to one of the plurality of design parameters to be selected and refined.

[0015] For a given potential RFIC, the plurality of design parameters may include the electrical and / or physical properties of components of the RFIC. For example, the plurality of design parameters may include capacitance values of each of the electrical components of the RFIC, inductance values of each of the electrical components of the RFIC, resistance values of each of the electrical components of the RFIC, the lengths and / or widths of microstrip lines of the RFIC and / or gate widths of transistors of the RFIC.

[0016] In some examples, the plurality of design parameters include: capacitance values of each of the capacitor elements of the RFIC, lengths of each microstrip line of the RFIC, and gate widths of each transistor of the RFIC.

[0017] The design parameter space may be populated by a plurality of layout designs that are stored in the database. Each layout design may be represented within the design parameter space as an n- dimensional layout vector. For each layout design, the value of each of the plurality of parameters defines the value of each of the components of the corresponding layout vector.

[0018] In this context, the generation of the plurality of local child layout designs, the determination of performance parameters of one or more selected local child layout designs, and the addition of the one or more selected child layout designs may correspond to a local search within the design parameter space about a point defined by the selected one of the plurality of retrieved candidate layout designs. These operations may, therefore, be referred to collectively herein as a local search phase of the methods described herein.

[0019] Similarly, the generation of the plurality of global child layout designs, the determination of performance parameters of one or more selected global child layout designs, and the addition of the one or more selected global child layout designs may correspond to a global search within the design parameter 008841090 3 space about respectively different points in the design parameter space, each defined by the respective one of the plurality of retrieved candidate layout designs. These operations may, therefore, be referred to collectively herein as a global search phase of the methods described herein.

[0020] In this way, the methods described herein provide a hybridised searching model for accurately and efficiently searching the design parameter space to obtain a design for an RFIC layout that satisfies the target performance parameters provided by the user. The hybridised searching model described herein may be particularly useful as it may ensure that the design layout returned as the determined layout for the RFIC is not merely a ‘local’ optimal solution that best satisfies the target performance parameters only within a local region of the design parameter space, but rather is a true or potentially ‘global’ optimal solution across the entire design parameter space.

[0021] The evolution applied in the local and / or global phases may be a respective differential evolution or other evolutionary algorithm, or other optimisation approach.

[0022] That is, both the local and global search phases of the methods described herein may be executed by implementing a differential evolution or other evolutionary optimisation approach to iteratively identify an optimal layout design (based e.g., on the target performance parameters provided by the user) proximal to a respective point in the design parameter space.

[0023] In this sense, each of the child layout designs (whether local or global) may be a new layout design not previously stored in the database of layout designs that are iteratively generated to explore the design parameter space in an effort to identify one or more optimal points within the design parameter space.

[0024] Performance parameters of a RFIC may be parameters indicative of the performance of an RFIC in use. The performance parameters of the RFIC may include any one or more of: an operating frequency range of the RFIC, an input matching ratio of the RFIC, an output matching of the RFIC, a gain of the RFIC (e.g., if the RFIC is a power amplifier), a gain ripple of the RFIC (e.g., if the RFIC is a power amplifier), a power-added efficiency (PAE) of the RFIC (e.g., if the RFIC is a power amplifier), an output power of the RFIC, and / or amplitude-to-phase modulation of the RFIC.

[0025] Determining the performance parameters of a layout design (e.g., the selected local child layout design(s) and / or the selected global child layout design(s)) may involve determining the performance of the layout design based on the known physical and electrical properties of an RFIC having the layout design.

[0026] As can be seen from the above, the target performance parameters provided by the user may constitute a multi-element list of interrelated parameters that may be particularly challenging to optimise using known methods.

[0027] In some examples, the target performance parameters provided by the user may comprise a range of acceptable values for each performance parameter of the RFIC.

[0028] Accordingly, selecting the determined layout for the RFIC may involve selecting a layout design from the updated database of layout designs whose performance parameters all satisfy the criteria (e.g., lie within the ranges) set out in the target performance parameters provided by the user. 008841090 4

[0029] In some examples, the user may designate a priority allocation to one or more of the target performance parameters. In such cases, the optimisation layout design method described herein may involve prioritising the optimisation of the performance parameters that have been designated as a relatively higher priority than those performance parameters that have been designated as a relatively lower priority by the user.

[0030] In some embodiments, the plurality of candidate layout designs retrieved from the database of layout designs may be selectively retrieved based on respectively determined performance parameters for each of the layout designs stored in the database and the target performance parameters provided by the user.

[0031] In some examples, each layout design stored in the database may be stored together with (e.g., linked to) associated performance parameters that have been determined for the corresponding layout design.

[0032] The performance parameters of each layout design stored in the database may be determined before storing the layout designs in the database so that the associated performance parameters with each layout design can be entered into the database contemporaneously (e.g., simultaneously or near- simultaneously) with the corresponding layout design.

[0033] In cases where a layout design is entered into the database before determining the associated performance parameters, the associated performance parameters may be subsequently determined and added to the database in a way that links the associated performance parameters with the corresponding layout design.

[0034] For example, the associated performance parameters may be determined at a device, system or server external / remote from the database and communicate the determined associated performance parameters to the database.

[0035] Additionally or alternatively, the database may be communicatively linked to one or more processors configured to execute logic that causes any of the one or more processors to determine performance parameters associated with any layout design that is stored in the database that is not stored with associated performance parameters. The database may, for each non-associated layout design, receive associated performance parameters from the one or more processors and store the associated performance parameters with (e.g., linked with) the corresponding layout design.

[0036] In some embodiments, the selected retrieved candidate layout design may be the retrieved candidate layout design whose associated performance parameters most closely match the target performance parameters provided by the user.

[0037] As discussed above, the target performance parameters provided by the user may constitute a multielement list of interrelated parameters that may be particularly challenging to optimise using known methods.

[0038] As discussed above, in some examples, the target performance parameters provided by the user may comprise a range of acceptable values for each performance parameter of the RFIC. 008841090 5

[0039] Accordingly, the selectively retrieved candidate layout designs may be selected layout designs whose performance parameters all satisfy the criteria (e.g., lie within the ranges) set out in the target performance parameters provided by the user.

[0040] In some examples, the user may designate a priority allocation to one or more of the target performance parameters. In such cases, the selective retrieval of candidate layout designs from the database may involve prioritising the performance parameters that have been designated as a relatively higher priority than those performance parameters that have been designated as a relatively lower priority by the user when determining which of the layout designs stored in the database should be selectively retrieved.

[0041] In some embodiments, a global child layout design may be generated for each retrieved candidate layout design.

[0042] In other words, there may be a one-to-one relationship between the plurality of retrieved candidate layout designs and the plurality of global child layout designs. For example, a differential evolution (or other evolutionary algorithms) may be applied separately to each of the plurality of retrieved candidate layout designs to generate a corresponding global child layout design.

[0043] In some embodiments, each of the local child layout designs may be generated by applying a random differential evolution to the selected retrieved candidate layout design.

[0044] In some embodiments, each of the local child layout designs may be generated by applying a predetermined differential evolution and / or a random differential evolution to the respective one of the plurality of candidate designs.

[0045] The differential evolutions applied to generate the global and child layout designs may be the same differential evolution.

[0046] Alternatively, a first type of differential evolution may be applied to generate the plurality of child layout designs and a second, different, type of differential evolution may be applied to generate the plurality of global child layout designs.

[0047] In some examples, a first common differential evolution may be applied to generate each of the local child layout designs while a second (different) common differential evolution may be applied to generate each of the global child layout designs.

[0048] In some examples, a different differential evolution may be applied to generate each of the local child layout designs.

[0049] In some examples, a different differential evolution may be applied to generate each of the global, child layout designs.

[0050] In some embodiments, the database of layout designs may be initialised by sampling a plurality of layout designs from a design parameter space of layout designs and determining respective performance parameters for each sampled layout design.

[0051] As described above, there may be a plurality of design parameters that need to be selected and refined to arrive at a final (selected) RFIC layout. These design parameters may define the n-dimensional design 008841090 6 parameter space, wherein each dimension of the design parameter space corresponds to one of the plurality of design parameters to be selected and refined.

[0052] For a given potential RFIC, the plurality of design parameters may include the electrical and / or physical properties of components of the RFIC. For example, the plurality of design parameters may include capacitance values of each of the electrical components of the RFIC, inductance values of each of the electrical components of the RFIC, resistance values of each of the electrical components of the RFIC, the lengths and / or widths of microstrip lines of the RFIC and / or gate widths of transistors of the RFIC.

[0053] In some examples, the plurality of design parameters include: capacitance values of each of the capacitor elements of the RFIC, lengths of each microstrip line of the RFIC, and gate widths of each transistor of the RFIC.

[0054] Sampling the design parameter space may involve generating a random (or quasi-random or nearrandom) sample of the parameter values to define a random (or quasi-random or near-random) set of vectors within the design parameter space, each of the set of vectors defining a respective layout design. In this way, a broad population of layout designs may be generated covering the scope of the design parameter space.

[0055] Sampling the design parameter space may use any one or more known statistical sampling methods. In some examples, sampling the design parameter space may involve any one or more of: random sampling, Latin hypercube sampling, and orthogonal sampling.

[0056] In some examples, sampling the design parameter space may involve Latin hypercube sampling the design parameter space. This may ensure that successive samples of the design parameter space are taken in a way that takes account of previously sampled design layout vectors such that the design parameter space may be sampled fairly across the full scope of the design parameter space. In other words, Latin hypercube sampling may reduce the risk of over-sampling from a particular region of the design parameter space and under-sampling from another region.

[0057] In some embodiments, each of the determined performance parameters may be determined using loadpull simulations, harmonic balance simulations and / or electromagnetic simulations.

[0058] Load-pull simulations and electromagnetic simulations are known methods of determining performance parameters associated with an RFIC layout. Such simulations may be computationally expensive and time-consuming. As such, an advantage achieved by the methods described herein is the significant reduction in the number of layout designs that are subjected to full load-pull simulations and / or electromagnetic simulations.

[0059] In particular, as provided by the methods described herein, it is not necessary to determine the performance parameters associated with all the plurality of child layout designs (local and global). To do so would represent a significant computational burden and time-cost. Instead, the methods described herein provide an approach that allows the filtering of the child layout designs to identify those one or more child layout designs most likely to satisfy the criteria prescribed by the target performance parameters provided by the user such that associated performance parameters are determined only for 008841090 7 those selected one or more child layout designs. In this way, the computational burden and time required to select an RFIC layout is reduced compared to prior approaches.

[0060] In some embodiments, the method may further comprise: repeating the retrieving the plurality of candidate layout designs, the generating a plurality of local child layout designs, the determined performance parameters of one or more selected local child layout designs, the adding the one or more selected local child layout designs, the generating a plurality of global child layout designs, the determining performance parameters of one or more selected global child layout designs, and the adding the one or more selected global child layout designs until at least one of the layout designs stored in the updated database of layout designs satisfies a predetermined stopping criterion.

[0061] In other words, the local search phase and / or the global search phase (as described above) may be repeatedly iterated one or more times until a predetermined stopping criterion is satisfied.

[0062] In some examples, the predetermined stopping criterion may be a criterion requiring that at least one layout design stored in the (updated) database has performance parameters associated therewith that are sufficiently close to the target performance parameters provided by the user.

[0063] For example, as set out above, the target performance parameters provided by the user may constitute a multi-element list of interrelated parameters that may be particularly challenging to optimise using known methods.

[0064] As described above, in some examples, the target performance parameters provided by the user may comprise a range of acceptable values for each performance parameter of the RFIC.

[0065] Accordingly, the stopping criterion may be a criterion that requires that at least one layout design stored in the database be associated with performance parameters - all of which satisfy the criteria (e.g., lie within the ranges) set out in the target performance parameters provided by the user.

[0066] In some embodiments, the method may further comprise, after adding the selected one or more global child layout designs to the database of layout designs: reconstructing the population of retrieved candidate layout designs.

[0067] The population of retrieved candidate layout designs may be considered to be a collective term for the group of candidate layout designs making up the plurality of retrieved candidate layout designs.

[0068] In the context of evolutionary search algorithms and, in particular, such algorithms that execute some form of local search phase, there is a risk of trapping the search in a local optimum. This, therefore, increases the risk that the ‘true’ optimum candidate solution may not be found.

[0069] Accordingly, reconstructing the population of retrieved candidate layout designs may involve reconstituting the plurality of retrieved candidate layout designs (e.g., between iterations of the hybridised search of the methods described herein) to maintain, or even increase, the population diversity of the plurality of retrieved candidate layout designs. A population diversity may be thought of as an indicator of the breadth of coverage across the design parameter space of the corresponding population. 008841090 8

[0070] In some embodiments, reconstructing the population of retrieved candidate layout designs comprises selecting, from the database of layout designs, a number of selected layout designs. The number of selected layout designs may be larger than the number of retrieved candidate layout designs. Reconstructing the population may further comprise: clustering the selected layout designs into a plurality of clusters; selecting, from each cluster, the layout design whose associated performance parameters most closely match the target parameters provided by the user; and reconstructing the population of retrieved candidate layout designs using the layout designs selected from each cluster.

[0071] In this way, the reconstructed population of retrieved candidate layout designs may be used in a subsequent iteration of the hybridised search of the methods described herein such that the population diversity of the population of retrieved candidate layout designs is not reduced / limited between iterations.

[0072] Further, by reconstructing the population in the manner set out above, it can be ensured that the full design parameter space is sampled to reconstruct the population in a manner that includes the one or more selected local child layout designs and / or one or more selected global child layout designs that have been previously added to the database in earlier iteration(s) of the hybridised search described herein.

[0073] In this way, the overall methods described herein provide an approach that allows the hybridised search to efficiently approach the optimal solution to satisfy the target performance parameters provided by the user in a way that does not prematurely sacrifice the scope of the search by inadvertently restricting the population of retrieved candidate layout designs (i.e., the population to be searched) to a local (as opposed to global) optimum.

[0074] In some examples, the number of clusters making up the plurality of clusters may be equal to the number of layout designs making up the number of retrieved candidate layout designs. In this way, the size of the population of retrieved candidate layout designs may be maintained across iterations of the hybridised search described herein.

[0075] In some examples, clustering the selected layout designs into a plurality of clusters may involve implementing any suitable known clustering algorithm. The implemented clustering algorithm may, for example, be a k-means clustering algorithm. Alternatively, the implemented clustering algorithm may be any other clustering algorithm, for example: a density-based spatial clustering algorithm, a Gaussian mixture model algorithm, a Balance Iterative Reducing and Clustering algorithm, and affinity propagation clustering algorithm, a mean-shift clustering algorithm, or an OPTCIS (ordering points to identify the clustering structure) algorithm.

[0076] In a particular example, the number of selected layout designs may be double the number of retrieved candidate layout designs. In such examples, each cluster formed by clustering the selected layout designs may consist of a pair of selected layout designs.

[0077] In some embodiments, generating the plurality of local child layout designs, v', may comprise applying a differential evolution to the selected one of the plurality of retrieved candidate layout designs, xbest, such that each local child layout design is defined as: vi = xbest+.(xrl _xr2) 008841090 9

[0078] Fi may be a local search scaling factor. xr1and xr2may be respectively different layout designs randomly selected from the plurality of retrieved candidate layout designs.

[0079] In some embodiments, generating the plurality of global child layout designs, u', may comprise applying a differential evolution to respective ones fo the plurality of retrieved candidate layout designs, x', such that each global child layout design is defined as: u1= x' + Fg■ (xbest- x1) + Fg■ (xrl- xr2)

[0080] Fgmay be a global search scaling factor. xbestmay be the selected one of the plurality of retrieved candidate layout designs. xr1and xr2may be respectively different layout designs randomly selected from the plurality of retrieved candidate layout designs.

[0081] In some embodiments, the local search scaling factor may be smaller than the global search scaling factor.

[0082] In some examples, the local search scaling factor may have a value between 0 and 2. For example, the local search scaling factor may have a value between 0 and 1 , or between 0 and 0.5. In some cases, the local search scaling factor may have a value of 0.2.

[0083] In some examples, the global search scaling factor may have a value between 0 and 2. For example, the global search scaling factor may have a value between 0.5 and 2, or between 0.5 and 1 . In some cases, the global search scaling factor may have a value of 0.8.

[0084] In some examples, the number of retrieved candidate design layouts may be greater than the number of design parameters forming the design parameter space. For example, the number of retrieved candidate design layouts may be at least double the number of design parameters, at least 5 times the number of design parameters or at least 10 times the number of design parameters. In some cases, the number of retrieved candidate design layouts may be 4 times the number of design parameters.

[0085] In some embodiments, the method may further comprise: predicting performance parameters of each of the plurality of local or global child layout designs. The one or more selected local or global child layout designs may be the one or more child or global layout designs whose predicted performance parameters most closely match the target performance parameters provided by the user.

[0086] That is, the methods described herein may further comprise: predicting performance parameters of each of the plurality of local child layout designs. The one or more selected local child layout designs may be the one or more local child layout designs whose predicted performance parameters most closely match the target performance parameters provided by the user.

[0087] Similarly, the methods described herein may further comprise: predicting performance parameters of each of the plurality of global child layout designs. The one or more selected global child layout designs may be the one or more global child layout designs whose predicted performance parameters most closely match the target performance parameter provided by the user.

[0088] Predicting the performance parameters of a child layout design may involve, using an appropriate estimate technique (e.g., a machine-learning based algorithm) to predict, in a relatively lightweight 008841090 10 fashion, likely performance parameters associated with the child layout design without carrying out a full determination (e.g., via load-pull simulations, electromagnetic simulations or similar).

[0089] The prediction may, for example, not be based on detailed electromagnetic or circuit theory determinations / calculations but rather based on, for example, pattern recognition of trends in performance parameters amongst layout designs having similar design parameters.

[0090] In this way, child layout designs may be filtered out of the hybridised search process if they appear, based on the predicted performance parameters to be unsuitable candidates to be the selected RFIC layout.

[0091] As the methods used to predict the performance parameters of the child layout design are intrinsically less intensive (in terms of both computing resources and time) than a definitive determination of the performance parameters (e.g., through load-pull simulations, electromagnetic simulations, or similar), the overall computational burden of the methods described herein may be reduced, and the methods may be carried out in a shorter timeframe.

[0092] In some embodiments, each of the local or global child layout designs may be a candidate RFIC layout design. Predicting the performance parameters of each of the plurality of candidate RFIC layout designs may comprise: providing data associated with one or more design parameters of each candidate RFIC layout design; and applying a respective Bayesian neural network (BNN) to the provided data to determine: the predicted performance parameters of a respective one of the candidate RFIC layout designs, and a prediction uncertainty associated with the corresponding predicted performance parameters.

[0093] In another aspect there is provided a method of determining a layout for a radio-frequency integrated circuit (RFIC). The method comprises: providing data associated with one or more design parameters of a candidate RFIC layout design; applying a Bayesian neural network (BNN) to the provided data to determine: predicted performance parameters of an RFIC having a layout in accordance with the candidate RFIC layout design, and a prediction uncertainty associated with the corresponding predicted performance parameters; and adjusting the candidate RFIC layout design based on the predicted performance parameters and the prediction uncertainty to determine the layout for the RFIC.

[0094] Adjusting the candidate RFIC layout design based on the predicted performance parameters and the prediction uncertainty may involve adjusting one or more design parameters of the candidate RFIC layout design based on the predicted optimal performance parameters of the candidate RFIC layout design relative to one or more target performance parameters provided by a user.

[0095] Using a BNN to predict the performance parameters of a candidate RFIC layout design is computationally more efficient (and benefits from a lower time complexity) than conventional Gaussian processes. The inventors have found that implementing BNNs as opposed to Gaussian processes led to computational time that was reduced by a factor of more than 50. 008841090 11

[0096] Once trained, the data provided to the BNN that is associated with the one or more design parameters of the candidate RFIC layout design may be the values of each of the design parameters of the candidate RFIC layout design.

[0097] For a given potential RFIC, the plurality of design parameters may include the electrical and / or physical properties of components of the RFIC. For example, the plurality of design parameters may include capacitance values of each of the electrical components of the RFIC, inductance values of each of the electrical components of the RFIC, resistance values of each of the electrical components of the RFIC, the lengths and / or widths of microstrip lines of the RFIC and / or gate widths of transistors of the RFIC.

[0098] In some examples, the plurality of design parameters include: capacitance values of each of the capacitor elements of the RFIC, lengths of each microstrip line of the RFIC, and gate widths of each transistor of the RFIC.

[0099] As BNNs may be implemented as computationally lightweight models, each candidate RFIC layout design may be analysed to predict its respectively associated predicted performance parameters by a bespoke BNN that has been specifically trained to predict the performance parameters of that RFIC layout design.

[0100] The predicted performance parameters may include predicted values of the performance parameters of the candidate RFIC layout design that the BNN predicts would be determined - for example by a load-pull or electromagnetic simulation.

[0101] These performance parameters may be parameters indicative of the performance of an RFIC in use. The performance parameters of the RFIC may include any one or more of: an operating frequency range of the RFIC, an input matching ratio of the RFIC, an output matching of the RFIC, a gain of the RFIC (e.g., if the RFIC is a power amplifier), a gain ripple of the RFIC (e.g., if the RFIC is a power amplifier), a power- added efficiency (PAE) of the RFIC (e.g., if the RFIC is a power amplifier), an output power of the RFIC, and / or amplitude-to-phase modulation of the RFIC.

[0102] In addition to predicting performance parameters of the input candidate RFIC layout design, the or each BNN is configured to determine a prediction uncertainty. The prediction uncertainty is a statistically grounded indication of the likelihood that the predicted performance parameters are correct.

[0103] In some embodiments, of any of the methods described herein, the method may further comprise: prescreening the or each candidate RFIC layout design to filter out candidate RFIC layout designs having an associated prediction uncertainty greater than a predetermined uncertainty threshold.

[0104] In this way, only those candidate RFIC layout designs for which the determined prediction uncertainty is sufficiently low may be processed to have their performance parameters determined (e.g., by load-pull or electromagnetic simulation) in the more computationally-intensive performance parameter determination process described herein.

[0105] Put another way, the computational and time resources required to definitively determine the performance parameters of a candidate RFIC layout design on those candidates are only spent on those candidate 008841090 12

[0106] RFIC layout designs for which the confidence in the values of the predicted performance parameters is sufficiently high. This, in effect, prevents wastage of computational and time resources.

[0107] In some embodiments, of any of the methods described herein, the predetermined uncertainty threshold may be a lower confidence bound defined based on a predictive distribution having an average value, y(x), and a standard distribution, s(x)

[0108] For example, the predetermined uncertainty threshold may take the form of a lower confidence bound that may be expressed as:

[0109] Yicb(x) = y(x) - ios(x) where yicb defines the lower confidence bound (i.e., the predetermined uncertainty threshold), and w is a scale factor defining how many standard deviations from the average the lower confidence bound is set. The scale factor may be between 0 and 5, between 0 and 3 or between 0 and 1 . In some cases, the scale factor may be 2.

[0110] In some examples, the prediction uncertainty may be a covariance of the predicted performance parameters over the design parameter space.

[0111] In other examples, the predetermined uncertainty threshold may be based on a determination of a likelihood that the prediction uncertainty is capable of being improved. In other words, the predetermined uncertainty threshold may take the form of a selection of a predetermined number of candidate RFIC layout designs from amongst a plurality of candidate RFIC layout designs, wherein the selected predetermined number of candidate RFIC layout designs corresponds to those candidate RFIC layout designs having the lowest determined prediction uncertainties amongst the plurality of candidate RFIC layout designs.

[0112] In some embodiments, of any of the methods described herein, the or each BNN may be a feedforward neural network comprising a plurality of stochastic weights and biases set to optimise an evidence lower bound.

[0113] In some embodiments, of any of the methods described herein, the or each BNN may be trained using training data comprising a plurality of sample layout designs. The plurality of sample layout designs may have been selectively retrieved from a database of layout designs based on their similarity with the candidate RFIC layout design.

[0114] The plurality of sample layout designs retrieved to train the or each BNN may be formed from a group of layout designs stored in the database that have the shortest distance in the design parameter space to the candidate RFIC layout design.

[0115] For example, the plurality of sample layout designs selectively retrieved may be those having the shortest Euclidean distance to the candidate RFIC layout design and / or the greatest cosine similarity with the candidate RFIC layout design.

[0116] In some embodiments, the RFIC may be circuitry configured to operate as a power amplifier. 008841090 13

[0117] Additionally or alternatively, the RFIC may be circuitry configured to operate as a transceiver, a modulator, a demodulator, a low-noise amplifier or any other RFIC-based component.

[0118] In another aspect, there is provided a computer comprising a memory and one or more processors configured to carry out any of the methods described herein.

[0119] In another aspect, there is provided a computer-readable medium comprising logic that, when executed by a processor, causes the processor to carry out any of the methods described herein.

[0120] In another aspect, there is provided a computer program product comprising instructions that, when executed by a computer, cause the computer to carry out any of the methods described herein.

[0121] For the avoidance of doubt, any one or more of the methods described herein may optionally further comprise providing an optimised RFIC having a layout according to the selected RFIC layout design derived according to the methods described herein.

[0122] In the described embodiments of the invention, the system may be implemented as any form of a computing and / or electronic device. Such a device may comprise one or more processors which may be microprocessors, controllers or any other suitable type of processors for processing computer executable instructions to control the operation of the device in order to gather and record routing information. In some examples, for example, where a system on a chip architecture is used, the processors may include one or more fixed function blocks (also referred to as accelerators) which implement a part of the method in hardware (rather than software or firmware). Platform software comprising an operating system or any other suitable platform software may be provided at the computing-based device to enable application software to be executed on the device.

[0123] Moreover, the acts described herein may be embodied using computer-executable instructions that can be implemented by one or more processors and / or stored on a computer-readable medium or media. The computer-executable instructions can include routines, sub-routines; programs; threads of execution, and / or the like. Still further, results of acts of the methods can be stored in a computer-readable medium, displayed on a display device, and / or the like.

[0124] The order of the operations of the methods described herein is exemplary, but the steps may be carried out in any suitable order, or simultaneously where appropriate. Additionally, steps may be added or substituted in, or individual steps may be deleted from any of the methods without departing from the scope of the subject matter described herein. Aspects of any of the examples described above may be combined with aspects of any of the other examples described to form further examples without losing the effect sought.

[0125] Various functions described herein can be implemented in hardware, software, or any combination thereof. If implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media may include, for example, computer-readable storage media. Computer-readable storage media may include volatile or non-volatile, removable or non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. A 008841090 14 computer-readable storage media can be any available storage media that may be accessed by a computer. By way of example, and not limitation, such computer-readable storage media may comprise RAM, ROM, EEPROM, flash memory or other memory devices, CD-ROM or other optical disc storage, magnetic disc storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

[0126] Although illustrated as a local device it will be appreciated that the computing device may be located remotely and accessed via a network or other communication link (for example using a communication interface).

[0127] The term 'computer' is used herein to refer to any device with processing capability such that it can execute instructions. Those skilled in the art will realise that such processing capabilities are incorporated into many different devices and therefore the term 'computer' includes PCs, servers, mobile telephones, personal digital assistants and many other devices.

[0128] Those skilled in the art will realise that storage devices utilised to store program instructions can be distributed across a network. For example, a remote computer may store an example of the process described as software. A local or terminal computer may access the remote computer and download a part or all of the software to run the program. Alternatively, the local computer may download pieces of the software as needed, or execute some software instructions at the local terminal and some at the remote computer (or computer network). Those skilled in the art will also realise that by utilising conventional techniques known to those skilled in the art that all, or a portion of the software instructions may be carried out by a dedicated circuit, such as a DSP, programmable logic array, or the like.

[0129] It will be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages. Variants should be considered to be included into the scope of the invention.

[0130] Any of the features, embodiments, aspects or examples set out above may be combined in any combination except where such a combination is clearly impermissible or expressly avoided.

[0131] Summary of the Figures

[0132] Embodiments and experiments illustrating the principles of the invention will now be discussed with reference to the accompanying figures in which:

[0133] Figure 1 shows a high-level schematic flow for a process of selecting an RFIC layout design.

[0134] Figure 2 shows a hybridised search process comprising local and global search phases in accordance with the methods described herein.

[0135] Figure 3 shows a method for pre-screening and filtering candidate RFIC layout designs. 008841090 15

[0136] Figure 4 shows an exemplary BNN architecture suitable for pre-screening candidate RFIC layout designs.

[0137] Figure 5 shows an exemplary schematic of an RFIC for which an optimised layout is determined using the methods described herein.

[0138] Figure 6 shows the design parameters (variable) to be determined for the schematic of Figure 5.

[0139] Figure 7 demonstrates the results of the methods described herein (in terms of the selected RFIC layout) across a range of operating frequencies of the RFIC of Figure 5.

[0140] Figure 8 compares the convergence trend of the methods described herein with the convergence trend of a prior surrogate model-assisted evolutionary algorithm (SAEA) for the RFIC of Figure 5.

[0141] Figure 9 shows an exemplary schematic of a second RFIC for which an optimised layout is determined using the methods described herein.

[0142] Figure 10 shows the design parameters (variable) to be determined for the schematic of Figure 9.

[0143] Figure 11 demonstrates the results of the methods described herein (in terms of the selected RFIC layout) across a range of operating frequencies of the RFIC of Figure 9.

[0144] Figure 12 compares the convergence trend of the methods described herein with the convergence trend of a prior surrogate model-assisted evolutionary algorithm (SAEA) for the RFIC of Figure 9.

[0145] Detailed Description of the Invention

[0146] Aspects and embodiments of the present invention will now be discussed with reference to the accompanying figures. Further aspects and embodiments will be apparent to those skilled in the art. All documents mentioned in this text are incorporated herein by reference.

[0147] Figure 1 shows a high-level schematic flow for a process of selecting an RFIC layout design. This process may be suitable for determining the layout of, for example, a power amplifier RFIC. The method may be considered to be an optimisation-oriented design process using the methods described herein.

[0148] In an operation 100, the optimisation-oriented RFIC layout design problem is set, for example by a user of the methods described herein providing one or more target performance parameters for a given RFIC.

[0149] In an operation 200, one or more candidate RFIC layout designs may be generated as candidate solutions to the design problem provided by the user.

[0150] In an operation 250, at least one of the candidate RFIC layout design(s) are selected for performance parameter determination - i.e., at least one of the candidate RFIC layout design(s) is selected and the associated performance parameters are determined using, for example, electromagnetic, harmonic balance and / or load-pull simulations.

[0151] In an operation 300, a selected RFIC layout design whose determined performance parameters most closely match the target performance parameters provided by the user is returned to the user as the layout for the user’s RFIC. 008841090 16

[0152] In the context of the methods described herein, operations 200 and 250 are expanded below in relation to

[0153] Figures 2 and 3.

[0154] Figure 2 shows a hybridised search process comprising local and global search phases in accordance with the methods described herein.

[0155] In an operation 202, a database of RFIC layout designs is initialised. Initialising the database involves sampling a plurality of possible layout designs from an n-dimensional design parameter space. Each possible layout design defines a vector in the design parameter space. The design parameter space is defined with each possible design parameter being assigned a dimension whose bounds are defined by the possible range of values that the corresponding design parameter can take. These bounds may be set by a user of the methods described herein or may be set based on known limitations (e.g., manufacturing and / or regulatory restrictions) on the possible ranges of values that may be taken for each design parameter.

[0156] Sampling the design parameter space to populate the database with the plurality of possible layout designs may involve sampling a number, a, of possible layout designs using, for example, Latin hypercube sampling.

[0157] For each of the possible layout designs sampled to populate the database, electromagnetic, load-pull and / or harmonic balance simulations are carried out to determine their performance parameters. The initialisation of the database may be a one-time operation, as repeating the initialisation may be a costly operation, both in terms of time and in terms of computing resources.

[0158] In an operation 204, a plurality of candidate layout designs are retrieved from the database based on a comparison of the performance parameters associated with the layout designs in the database and target performance parameters provided by a user.

[0159] In an operation 206, it is determined whether a stopping criterion of the method has been satisfied. That is, it is determined whether there is stored, in the database of possible layout designs, a layout whose performance parameters satisfy the criteria provided by the user in the targe performance parameters (in other words, whether a stored layout design satisfies a specification provided by the user).

[0160] If a layout design stored in the database does satisfy the stopping criterion, that satisfying layout design is returned to the user in operation 300.

[0161] However, if no layout design satisfies the stopping criterion, the method proceeds to implement a hybridised search framework to find an optimal solution to the design problem presented by the user.

[0162] As will be apparent to the skilled person, operations 204 and 206 may be interchanged or may be carried out iteratively. For example, a structured search query of the database may be executed to determine if the stopping criterion is satisfied by any of the layout designs stored in the database. If one of the stored layout designs does satisfy the stopping criterion, that layout design may be retrieved from the database and returned to the user as the RFIC layout. Meanwhile, if none of the stored layout designs satisfy the stopping criterion, a plurality, K, of layout designs may be retrieved from the database to form a population, P. 008841090 17

[0163] The population P is composed of a number of individual retrieved candidate layout designs =

[0164] (xx, ...,xd) e Rdwherein each retrieved candidate layout design is defined by a vector Xi within the design parameter space Rd(where, in this case, the number of design parameters is expressed as ‘d’).

[0165] In an operation 208, a plurality of local child layout design solutions are generated.

[0166] Generating the plurality of local child layout design solutions involves identifying a ‘best’ one of the plurality of retrieved candidate layout designs - that is, identifying which of the plurality of retrieved candidate layout designs has associated performance parameters that most closely match the target performance parameters provided by the user.

[0167] Generating the plurality of local child layout design solutions, V', involves applying a differential evolution of the form: vi = xbest+ F1.(xrl _xr2 )

[0168] In this context, v' is a candidate local child layout design obtained from applying the differential evolution above, xbestis the identified best one of the plurality of retrieved candidate layout designs, Fi is a local search scaling factor having a value between 0 and 2, and xr1and xr2are two mutually exclusive candidate layout designs randomly selected from the plurality of retrieved candidate layout designs.

[0169] In some cases, the index T may cover the range of 1 to K. In other words, the number of generated local child layout designs may be equal to the number of retrieved candidate layout designs.

[0170] Generating the plurality of local child layout design solutions, V', may further involve applying a random crossover operator to the plurality of candidate local child layout designs. The random crossover operator may be defined by: (I) randomly selecting a variable index jrande {1, ... ,A}, (II) for each j = 1 to A, generating a uniformly distributed random number rand that has a value between 0 and 1 , and (ill) setting the local child layout design, V' as: VJ=J fv\ if (vrcznd < CR)7||Jj--Jjrand ,

[0171] (x\ otherwise where CR is the crossover rate and has a value between 0 and 1 . By adjusting the crossover rate, the likelihood of the local child layout design, V', taking the value of the candidate local child layout design, v', can be adjusted relative to the likelihood of the local child layout design, V', taking the value of one of the plurality of retrieved candidate layout designs, x'.

[0172] In an operation 210, the performance parameters of the local child layout designs are predicted and the local child layout designs are pre-screened (e.g., based on a determined prediction uncertainty) to filter out those child layout designs for which the confidence in the value(s) of the predicted performance parameters is below a predetermined confidence threshold. The predicting and pre-screening of operation 210 are discussed in more detail below in relation to Figure 3.

[0173] In an operation 212, the local child layout design(s) having the best one (or optionally best one or more) predicted performance parameters after pre-screening - i.e., having associated therewith the predicted performance parameters that most closely match the target performance parameters - are selected. The 008841090 18 performance parameters of the selected one or more local child layout designs are determined, for example using load-pull, electromagnetic and / or harmonic balancing simulations.

[0174] In a particular example, only one local child layout design (the ‘best) is selected for simulation in operation 212.

[0175] In an operation 214, the selected local child layout design(s) is / are added to the database of layout designs together with the associated determined (i.e., determined as in operation 212, not predicted as in operation 210) performance parameters.

[0176] Operations 208 to 214 as set out above may be collectively referred to as the local search phase of the hybridised search model of Figure 2.

[0177] In an operation 216, a plurality of global child layout design solutions are generated.

[0178] Generating the plurality of global child layout design solutions, U', involves applying a differential evolution of the form: ul= xl+ Fg- xbest- xL) + Fg(xrl- xr2)

[0179] In this context, u' is a candidate global child layout design obtained from applying the differential evolution above, x' is a corresponding one of the plurality of retrieved candidate layout designs, xbestis the identified best one of the plurality of retrieved candidate layout designs (as described above in relation to operation 208), Fgis a global search scaling factor having a value between 0 and 2 (optionally subject to the condition: Fi < Fg), and xr1and xr2are two mutually exclusive candidate layout designs randomly selected form the plurality of retrieved candidate layout designs.

[0180] In some cases, the index T may cover the range of 1 to A. In other words, the number of generated global child layout designs may be equal to the number of retrieved candidate layout designs.

[0181] Generating the plurality of global child layout design solutions, U', may further involve applying a random crossover operator to the plurality of candidate global child layout designs. The random crossover operator may be defined by: (i) randomly selecting a variable index jrande {1, ... ,A}, (ii) for each j = 1 to A, generating a uniformly distributed random number rand that has a value between 0 and 1 , and (iii) setting the global child layout design, V' as: where CR is the crossover rate and has a value between 0 and 1 . By adjusting the crossover rate, the likelihood of the global child layout design, U', taking the value of the candidate global child layout design, u', can be adjusted relative to the likelihood of the global child layout design, U', taking the value of one of the plurality of retrieved candidate layout designs, x'.

[0182] In some cases, the crossover operator applied to generate the local child layout designs may be the same operator as the crossover operator applied to generate the global child layout designs.

[0183] In an operation 218, the performance parameters of the global child layout designs are predicted and the global child layout designs are pre-screened (e.g., based on a determined prediction uncertainty) to filter 008841090 19 out those child layout designs for which the confidence in the value(s) of the predicted performance parameters is below a predetermined confidence threshold. The predicting and pre-screening of operation 218 may be the same as that described in relation to operation 210 and is discussed in more detail below in relation to Figure 3.

[0184] In an operation 220, the global child layout design(s) having the best one (or optionally best one or more) predicted performance parameters after pre-screening - i.e., having associated therewith the predicted performance parameters that most closely match the target performance parameters - are selected. The performance parameters of the selected one or more global child layout designs are determined, for example using load-pull, electromagnetic and / or harmonic balancing simulations.

[0185] In a particular example, only one global child layout design (the ‘best’) is selected for simulation in operation 220.

[0186] In an operation 222, the selected global child layout design(s) is / are added to the database of layout designs together with the associated determined (i.e., determined as in operation 220, not predicted as in operation 218) performance parameters.

[0187] Operations 216 to 222 as set out above may be collectively referred to as the global search phase of the hybridised search model.

[0188] In an operation 224, the population, P, of the retrieved candidate layout designs is reconstructed to avoid an inadvertent local (as opposed to global) optimisation.

[0189] Reconstructing the population may involve executing the following operations: (i) selecting the (at least) 2K layout designs from the database whose determined performance parameters most closely match the target performance parameters provided by the user (i.e., selecting a number of layout designs from the database that is at least double the number of retrieved candidate layout designs retrieved in operation 204); (ii) clustering the selected layout designs into K clusters (e.g., pairs) using an appropriate clustering algorithm such as k-means clustering; and (iii) selecting, from each of the clusters, the layout design whose associated performance parameters most closely match the target performance parameters provided by the user, to form the new population P’.

[0190] The method then returns to operation 206 to determine if either the local child layout design(s) or the global child layout design(s) added to the database satisfy the stopping criterion. If none of these added child layout designs satisfy the stopping criterion, the local search phase of operations 208 to 214, the global search phase of operations 216 to 222 and the population reconstruction of operation 224 are repeated using the new population P’ until a layout design that does satisfy the stopping criterion is found.

[0191] Figure 3 shows a method for pre-screening and filtering candidate RFIC layout designs. This method may be implemented as part of operation 210 and / or operation 218 of Figure 2 for each local child layout design and each global layout design. In the context of Figure 3, any RFIC layout design for which performance parameters are predicted using this method is referred to herein as a candidate RFIC layout.

[0192] In an operation 226, the performance parameters of the candidate RFIC layout are predicted. The predictions may be determined by execution of an appropriate prediction engine such as a machine 008841090 20 learning engine. The machine learning engine may be structured as a Bayesian neural network (BNN), the structure of which is discussed below in relation to Figure 4.

[0193] In an operation 228, a prediction uncertainty indicative of a degree of uncertainty / confidence in the values of the predicted performance parameters is determined.

[0194] In an operation 230, the determined prediction uncertainty is compared with a predetermined threshold (e.g., an uncertainty threshold or confidence threshold). The predetermined threshold may, for example, be a lower confidence bound (or, equivalently, an upper uncertainty bound).

[0195] If the determined prediction uncertainty is less than the uncertainty threshold (i.e., confidence is greater than a confidence threshold), the candidate RFIC layout is retained in operation 232. This candidate RFIC layout is then made available for selection in operations (and determination of the associated performance parameters) in operation 212 or 220, as appropriate.

[0196] In contrast, if the determined prediction uncertainty is greater than the uncertainty threshold (i.e., confidence is less than a confidence threshold), the candidate RFIC layout is discarded in operation 234.

[0197] In this way, the method of Figure 3 provides a mechanism by which candidate RFIC layouts can be screened for prediction confidence / uncertainty to ensure that computational and time resources associated with the full determination of performance parameters are not unnecessarily wasted.

[0198] Figure 4 shows an exemplary BNN architecture suitable for pre-screening candidate RFIC layout designs.

[0199] The BNN of Figure 4 is structured as a feedforward neural network comprising a plurality of neurons arranged as an input layer, one or more (in some cases, two) hidden layers and an output layer, interconnected by a series of weights and biases.

[0200] For a given candidate RFIC layout, the corresponding BNN is trained using a selected number, T, of layout designs in the database, the selected layout designs being the T nearest samples (based on Euclidean distance in the design parameter space) to the candidate RFIC layout.

[0201] BNN’s are trained with a stochastic set of weights and biases, 0 = [w1(....w h^ ... , bk] having a probability distribution p(0).

[0202] Training a BNN involves obtaining the posterior probability distribution p(0,D) given a training dataset, D. Methods for training BNNs are known in the art.

[0203] Given a posterior probability distribution, p(0,D), the BNN can be configured to sample the weights and biases, 0, from the posterior probability distribution to form a sampled hypothesis set. The predicted performance parameters, y, of the candidate RFIC layout, can be determined from this sampled hypothesis set e.g., according to: where 0 is the sampled hypothesis set, whose size is |0|, <t>(x) is the BNN model, and 0i is the set of weights and biases of the BNN. 008841090 21

[0204] Further, the BNN is trained to determine the prediction uncertainty in the predicted performance parameters. This prediction uncertainty may be a covariance of the predicted performance parameters, expressed as: where Zy|x,D is the covariance of the predicted performance parameters given the input design parameters, x.

[0205] This determined performance uncertainty can then be confirmed with a lower confidence bound, ytb, taking the form: yicb(x) = y(x) - ws(x) where s(x) is the standard distribution of the predicted performance parameter, and w is a predetermined constant.

[0206] In the context of the methods described herein, the BNN may be configured with four layers: a first input layer having one neuron for each of the design parameters, d, that can be varied, a first hidden layer having 2d neurons, a second hidden layer having a number of neurons that is the greater of d and 2m, where m is the number of performance parameters, and an output layer having one neuron for each of the performance parameters.

[0207] From this predicted

[0208] Illustrative examples of the application of the methods described herein will now be set out.

[0209] Example 1: a 27-31 GHz class-AB power amplifier suitable for satellite application

[0210] Figure 5 shows an exemplary schematic of an RFIC for which an optimised layout is determined using the methods described herein.

[0211] The RFIC of Figure 5 is a 27-31 GHz class-AB power amplifier suitable for satellite application. The RFIC is constructed using a GaN-on-Si 100 nm technology.

[0212] For this RFIC, the input signal is first amplified by the driver stages, and then split equally by a nonisolated divider and amplified in two branches, which are combined at the end of the output. The power amplifier of Figure 5 is configured to operate over the frequency range 27 to 31 GHz. In practical implementations, achieving consistent performance (e.g., gain, output power and power amplifier efficiency) over the entire bandwidth is challenging due to the multi-stage nature of the RFIC.

[0213] Each of the four matching circuits of the RFIC of Figure 5 are connected at the top-level circuit. The drain voltage and gate voltage of all stages are fixed to be 12 V and -1 .25 V respectively.

[0214] The target performance parameters provided by the user for the RFIC of Figure 5 are set out below in Table 1 : 008841090 22

[0215] Table 1: Target Performance Parameters for Example 1

[0216] The RFIC of Figure 5 has 27 design parameters that can be varied, as shown in Figure 6. Design parameters C1 to C10 are capacitance values of capacitors. Design parameters L1 to L14 are the lengths of microstrip lines (having fixed widths of 60 pm). Design parameters W1 to W3 are gate widths of transistors.

[0217] To solve this problem, the methods described herein were implemented to identify the optimized RFIC layout to satisfy the target performance parameters set out in Table 1 above. In line with the methods described herein, to determine the optimised RFIC layout, a BNN for pre-screening each child layout design is used having 27 neurons in the input layer, 54 neurons in the first hidden layer (2 x 27), 27 neurons in the second hidden layer (the greater of 27 and 2 x 7), and 7 neurons in the output layer.

[0218] The number of retrieved candidate layout designs from the database is 108 (A = 4d), the BNN is trained using the 108 nearest layout designs in terms of Euclidean distance (T = 4d), the global search scaling factor, Fg, is 0.8, the local search scaling factor, Fi, is 0.2, the crossover rate, CR, is 0.8, and the constant for establishing the lower confidence bound, w, is 2. The upper bounds and lower bounds for each of these design parameters are set out in Table 2 below, together with the values for each design parameter selected by carrying out the method of Figures 2 and 3 above to select an optimised RFIC layout for the RFIC of Figure 5. The values of the capacitances are expressed in fF, the values of the lengths of the microstrip lines are expressed in pm, and the values of the gate widths of the transistors are expressed in pm. 008841090 23

[0219] Table 2: Design parameter ranges and optimised values for Example 1

[0220] The determined performance parameters for an RFIC having the layout prescribed by the optimised values set out in Table 2 are set out below in Table 3:

[0221] Table 3: Determined performance parameters for optimised RFIC layout of Example 1 As can be seen from Tables 1 to 3, implementing the methods described herein successfully satisfies the criteria prescribed by the user’s target performance criteria.

[0222] Further, as can be seen from Figure 7, an RFIC manufactured according to the optimized layout prescribed in Table 2 above, achieves large gain and power added efficiencies within the operation band of the RFIC of Figure 5 across a broad range of output powers. Figure 8 compares the convergence trend of the methods described herein with the convergence trend of a prior surrogate model-assisted evolutionary algorithm (SAEA) for the RFIC of Figure 5. For Example 1 , each simulation took approximately 5-6 minutes and the maximum budget was 1200 simulations (i.e., about five days).

[0223] As can be seen from Figure 8, the methods described herein are able to determine the optimum RFIC layout after an average of 516 full load-pull, electromagnetic or harmonic balancing simulations. For this 008841090 24 challenging power amplifier design problem, the methods described herein are capable of returning a layout-level high-performance RFIC design in about 2 days.

[0224] In contrast, the prior SAEA was able to determine an RFIC layout that satisfied all the target performance parameters within 1200 full simulations only 50% of the time and, when it did determine a suitable RFIC layout within 1200 full simulations it required an average of 1142 full simulations - more than double the resource requirement of the methods described herein.

[0225] The methods described herein accordingly demonstrably represent a significant improvement in the efficiency with which an optimal RFIC layout can be determined.

[0226] Example 2: a 24-31 GHz Wideband Doherty MMIC power amplifier

[0227] Figure 9 shows an exemplary schematic of a second RFIC for which an optimised layout is determined using the methods described herein.

[0228] The RFIC of Figure 9 is a 24-31 GHz wideband Doherty power amplifier with a driver stage and a final stage.

[0229] The input signal is split by a coupler with an isolation resistor, which is then fed forward into the two branches that have different bias classes (a main branch and an auxiliary branch). The two branches amplify the signal separately and are combined at the output without isolation. Due to an active load-pull interaction between the main and auxiliary branches, it is very challenging to design a multistage Doherty power amplifier that operates over a wide bandwidth.

[0230] The drain voltage of all stages is 12 V. The gate voltage of the main branch is -1.25 V, while -2.6 V and - 2.2 V are used in the driver and final stages in the auxiliary path respectively.

[0231] The target performance parameters provided by the user for the RFIC of Figure 9 are set out below in Table 4: 008841090 25

[0232] Table 4: Target Performance Parameters for Example 2

[0233] The RFIC of Figure 9 has 31 design parameters that can be varied, as shown in Figure 10. Design parameters C1 to C12 are capacitance values of capacitors. Design parameters L1 to L14 are lengths of microstrip lines. Design parameters W1 to W4 are widths of microstrip lines. Design parameter R1 is the resistance value of a resistor.

[0234] To solve this problem, the methods described herein were implemented to identify the optimized RFIC layout to satisfy the target performance parameters set out in Table 4 above. In line with the methods described herein, to determine the optimised RFIC layout, a BNN for pre-screening each child layout design is used having 31 neurons in the input layer, 62 neurons in the first hidden layer (2 x 31 ), 31 neurons in the second hidden layer (the greater of 31 and 2 x 10), and 10 neurons in the output layer.

[0235] The number of retrieved candidate layout designs from the database is 124 (A = 4d), the BNN is trained using the 124 nearest layout designs in terms of Euclidean distance (T = 4d), the global search scaling factor, Fg, is 0.8, the local search scaling factor, Fi, is 0.2, the crossover rate, CR, is 0.8, and the constant for establishing the lower confidence bound, w, is 2. The upper bounds and lower bounds for each of these design parameters are set out in Table 5 below, together with the values for each design parameter selected by carrying out the method of Figures 2 and 3 above to select an optimised RFIC layout for the RFIC of Figure 9. The values of the capacitances are expressed in fF, the values of the lengths of the microstrip lines are expressed in pm, the values of the widths of the microstrip lines are expressed in pm, and the value of the resistance is expressed in Q 008841090 26

[0236] Table 5: Design parameter ranges and optimised values for Example 2

[0237] The determined performance parameters for an RFIC having the layout prescribed by the optimised values set out in Table 5 are set out below in Table 6:

[0238] Table 6: Determined performance parameters for optimised RFIC layout of Example 2 As can be seen from Tables 4 to 6, implementing the methods described herein successfully satisfies the criteria prescribed by the user’s target performance criteria.

[0239] Further, as can be seen from Figure 11 , an RFIC manufactured according to the optimized layout prescribed in Table 5 above, achieves large gain and power added efficiencies within the operation band of the RFIC of Figure 9 across a broad range of output powers. Figure 12 compares with convergence trend of the methods described herein with the prior SAEA for the RFIC of Figure 9. For Example 2, each simulation took approximately 6-7 minutes and the maximum budget was 1000 simulations (i.e., about five days).

[0240] As can be seen from Figure 12, the methods described herein are able to determine the optimum RFIC layout after an average of 574 full simulations (approximately 60 hours). In contrast, the prior SAEA was unable to determine an optimised RFIC layout within the allocated computing resource.

[0241] The methods described herein accordingly demonstrably represent a significant improvement in the efficiency with which an optimal RFIC layout can be determined. 008841090 27

[0242] The features disclosed in the foregoing description, or in the following claims, or in the accompanying drawings, expressed in their specific forms or in terms of a means for performing the disclosed function, or a method or process for obtaining the disclosed results, as appropriate, may, separately, or in any combination of such features, be utilised for realising the invention in diverse forms thereof.

[0243] While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when given this disclosure. Accordingly, the exemplary embodiments of the invention set forth above are considered to be illustrative and not limiting. Various changes to the described embodiments may be made without departing from the spirit and scope of the invention.

[0244] For the avoidance of any doubt, any theoretical explanations provided herein are provided for the purposes of improving the understanding of a reader. The inventors do not wish to be bound by any of these theoretical explanations.

[0245] Any section headings used herein are for organizational purposes only and are not to be construed as limiting the subject matter described.

[0246] Throughout this specification, including the claims which follow, unless the context requires otherwise, the word “comprise” and “include”, and variations such as “comprises”, “comprising”, and “including” will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps.

[0247] The terms “a” (or “an”), as well as the terms “one or more” and “at least one” can be used interchangeably herein.

[0248] The term “and / or” as used herein is to be taken as specific disclosure of each of specified listed features or components with or without one or more of the others. Thus, the term “and / or” as used in a phrase such as “A, B and / or C” encompasses each of: A and B and C; A and B; A and C; B and C; A or B or C; A or C; A or C; B or C; only A; only B; and only C.

[0249] The use of the term “comprise” and “include” to refer to the inclusion of integers, steps and / or operations nonetheless also encompasses aspects, examples and embodiments that may be analogously described with the term “consist” in respect of those integers, steps and / or operations.

[0250] It must be noted that, as used in the specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Ranges may be expressed herein as from “about” one particular value, and / or to “about” another particular value. When such a range is expressed, another embodiment includes from the one particular value and / or to the other particular value. Similarly, when values are expressed as approximations, by the use of the antecedent “about,” it will be understood that the particular value forms another embodiment. The term “about” in relation to a numerical value is optional and means for example + / - 10%.

Claims

1. 008841090 28Claims:1 . A computer-implemented method of determining a layout for a radio-frequency integrated circuit, RFIC, the method comprising: retrieving, from a database of layout designs, a plurality of candidate layout designs for the layout of the RFIC; generating a plurality of local child layout designs, wherein each of the local child layout designs is generated by applying an evolution to a selected one of the plurality of retrieved candidate layout designs; determining performance parameters of one or more selected local child layout designs; adding the one or more selected local child layout designs together with the associated determined performance parameters to the database of layout designs; generating a plurality of global child layout designs, wherein each of the global child layout designs is generated by applying an evolution to a respective one of the plurality of retrieved candidate layout designs; determining performance parameters of one or more selected global child layout designs; adding the one or more selected global child layout designs together with the associated determined performance parameters to the database of layout designs; and selecting as the determined layout for the RFIC, from the updated database of layout designs, a layout design whose associated performance parameters most closely match target performance parameters provided by a user.

2. The computer-implemented method according to claim 1 , wherein the plurality of candidate layout designs retrieved from the database of layout designs are selectively retrieved based on respectively determined performance parameters for each of the layout designs stored in the database and the target performance parameters provided by the user.

3. The computer-implemented method according to claim 1 or 2, wherein the selected retrieved candidate layout design is the retrieved candidate layout design whose associated performance parameters most closely match the target performance parameters provided by the user.

4. The computer-implemented method according to any preceding claim, wherein a global child layout design is generated for each retrieved candidate layout design.

5. The computer-implemented method according to any preceding claim, wherein each of the local child layout designs is generated by applying a random differential evolution to the selected retrieved candidate layout design.

6. The computer-implemented method according to any preceding claim, wherein each of the global child layout designs is generated by applying a predetermined differential evolution and / or a random differential evolution to the respective one of the plurality of candidate designs.008841090 297. The computer-implemented method according to any preceding claim, wherein the database of layout designs is initialised by sampling a plurality of layout designs from a design parameter space of layout designs and determining respective performance parameters for each sampled layout design.

8. The computer-implemented method according to any preceding claim, wherein each of the determined performance parameters is determined using load-pull simulations, harmonic balance simulations, and / or electromagnetic simulations.

9. The computer-implemented method according to any preceding claim, the method further comprising: repeating the retrieving the plurality of candidate layout designs, the generating a plurality of local child layout designs, the determining performance parameters of one or more selected local child layout designs, the adding the one or more selected local child layout designs, the generating a plurality of global child layout designs, the determining performance parameters of one or more selected global child layout designs, and the adding the one or more selected global child layout designs until at least one of the layout designs stored in the updated database of layout designs satisfies a predetermined stopping criterion.

10. The computer-implemented method according to any preceding claim, further comprising, after adding the selected one or more global child layout designs to the database of layout designs: reconstructing a population of the retrieved candidate layout designs.

11. The computer-implemented method according to claim 10, wherein reconstructing the population of the retrieved candidate layout designs comprises: selecting, from the database of layout designs, a number of selected layout designs, wherein the number of selected layout designs is larger than the number of retrieved candidate layout designs; clustering the selected layout designs into a plurality of clusters; selecting, from each cluster, the layout design whose performance parameters most closely match the target performance parameters provided by the user; and reconstructing the population of the retrieved candidate layout designs using the layout designs selected from each cluster.

12. The computer-implemented method according to any preceding claim, wherein generating the plurality of local child layout designs, v', comprises applying a differential evolution to the selected one of the plurality of retrieved candidate layout designs, xbest, such that each local child layout design is defined as: vi=xbest+ F[. (xrl _xr2 wherein Fi is a local search scaling factor, and xr1and xr2are respectively different layout designs randomly selected from the plurality of retrieved candidate layout designs.008841090 3013. The computer-implemented method according to any preceding claim, wherein generating the plurality of global child layout designs u', comprises applying a differential evolution to respective ones of the plurality of retrieved candidate layout designs, x', such that each global child layout design is defined as: u1= x' + Fg■ (xbest- x1) + Fg■ (xrl- xr2), wherein Fgis a global search scaling factor, xbestis the selected one of the plurality of retrieved candidate layout designs, and xr1and xr2are respectively different layout designs randomly selected from the plurality of retrieved candidate layout designs.

14. The computer-implemented method according to claim 13, as dependent on claim 12, wherein the local search scaling factor is smaller than the global search scaling factor.

15. The computer-implemented method according to claim 1 , further comprising: predicting performance parameters of each of the plurality of local or global child layout designs, wherein the one or more selected local or global child layout designs are the one or more child or global layout designs whose predicted performance parameters most closely match the target performance parameters provided by the user.

16. The computer-implemented method according to claim 15, wherein each of the local or global child layout designs is a candidate RFIC layout design, and wherein predicting the performance parameters of each of the plurality of candidate RFIC layout designs comprises: providing data associated with one or more design parameters of each candidate RFIC layout design; and applying a respective Bayesian neural network, BNN, to the provided data to determine: the predicted performance parameters of candidate RFIC layout designs, and a prediction uncertainty associated with the corresponding predicted performance parameters.

17. A computer-implemented method of determining a layout for a radio-frequency integrated circuit, RFIC, the method comprising: providing data associated with one or more design parameters of a candidate RFIC layout design; applying a Bayesian neural network, BNN, to the provided data to determine: predicted performance parameters of an RFIC having a layout in accordance with the candidate RFIC layout design, and a prediction uncertainty associated with the corresponding one or more predicted performance parameters; and adjusting the candidate RFIC layout design based on the predicted performance parameters and the prediction uncertainty to determine the layout for the RFIC.008841090 3118. The computer-implemented method according to claims 16 or 17, further comprising: pre-screening the or each candidate RFIC layout design to filter out candidate RFIC layout designs having an associated prediction uncertainty greater than a predetermined uncertainty threshold.

19. The computer-implemented method according to claim 18, wherein the predetermined uncertainty threshold is a lower confidence bound defined based on a predictive distribution having an average value, y(x), and a standard distribution, s(x).

20. The computer-implemented method according to any of claims 16 to 19, wherein the or each BNN is a feedforward neural network comprising a plurality of stochastic weights and biases set to optimise an evidence lower bound.

21. The computer-implemented method according to any of claims 16 to 20, wherein the or each BNN is trained using training data comprising a plurality of sample layout designs, the plurality of sample layout designs having been selectively retrieved from a database of layout designs based on their similarity with the candidate RFIC layout design.

22. The method according to any preceding claim, wherein the RFIC is circuitry configured to operate as a power amplifier.

23. A computer comprising a memory and one or more processors configured to carry out the method of any preceding claim.

24. A computer-readable medium comprising logic that, when executed by a processor, causes the processor to carry out the method of any of claims 1 to 22.

25. A computer program product comprising instructions that, when executed by a computer, cause the computer to carry out the method of any of claims 1 to 22.

Images