Memory cell device

Abstract

A memory cell device comprising: first and second tuneable inverter modules, wherein each inverter module comprises at least one tuneable load configured to set a threshold voltage for the inverter module, wherein each inverter module is configured to receive an input signal and output an output signal in dependence on the voltage of the input signal and the threshold voltage, wherein the threshold voltages of the first and second tuneable inverter modules define a matching window, wherein the device further comprises an output module configured to receive output signals from the first and second tuneable inverter modules and configured to output a match signal and / or a contribution to a match signal in response to the output signals representing or indicating that the input signal has a voltage in the matching window, wherein at least one of a) and b): a) the device comprises a tuning module configured to tune the load of the tuneable load of each of the first and second inverter modules thereby to set the matching window; b) wherein the output module comprises a pull up or pull down circuit for coupling a high voltage to a match line in response to the voltage of the input signal being in the matching window.

Description

[0001] MEMORY CELL DEVICE

[0002] Field

[0003] The present invention relates to a memory cell device and system and method, for example, a memory cell device for performing template or other data matching and / or other content addressable memory operations.

[0004] Background

[0005] Edge computing relates to an area of computing in which processing and data storage resources are brought closer to sources of data than in conventional computing systems. Edge computing is important in applications such as wearable and implantable medical devices and such applications introduce additional and / or alternative challenges to conventional computing systems, for example, due to the strict requirements of area and power requirements at the edge.

[0006] Machine learning applications in and outside of edge computing may present additional and / or alternative computational bottlenecks in areas such as memory access and data transfer.

[0007] Summary of Invention

[0008] According to a first aspect, there is provided, a memory cell device comprising: first and second tuneable inverter modules, wherein each inverter module comprises at least one tuneable load configured to set a threshold voltage for the inverter module, wherein each inverter module is configured to receive an input signal and output an output signal in dependence on the voltage of the input signal and the threshold voltage, wherein the threshold voltages of the first and second tuneable inverter modules define a matching window, wherein the device further comprises an output module configured to receive output signals from the first and second tuneable inverter modules and configured to output a match signal and / or a contribution to a match signal in response to the output signals representing or indicating that the input signal has a voltage in the matching window.

[0009] The memory cell device may further comprise a supply voltage rail. The output module may comprise circuity that forms part of a conductive path between the supply voltage line and a match line in response to the input signal having a voltage in the matching

[0010] 55650902-1 window. The conductive path may pass through at least one, optionally both, of the inverter modules. The device may be configured to divert a source voltage line to a matchline in response to the input.

[0011] The output module may be configured to be controlled by the first and second inverter modules. The output module may comprises a comparison circuit configured to output a match signal based on a comparison of the received signals.

[0012] The first and second tuneable inverter modules and output module may comprise part of a tuneable complementary metal oxide semiconductor (CMOS) circuit. The first and second inverter modules may be part of a tuneable RRAM-CMOS (resistive randomaccess - complementary metal oxide semiconductor) memory circuit.

[0013] The tuneable load may comprise a resistive load and / or trimming element. Each inverter module may be configured to receive the same input signal.

[0014] The memory cell device may be for template matching. The memory cell device may comprise analogue content addressability. The input signal may form part of a search query or other query.

[0015] The memory cell device may form part of a content addressable memory and / or sensing device.

[0016] The tuneable load may comprise a mersister and / or other device configured to store a tuneable non-volatile resistance, wherein the threshold voltage is in dependence on at least the stored tuneable non-volatile resistance.

[0017] Each inverter module may comprise a hybrid RRAM-CMOS inverter.

[0018] Each inverter module may comprise a pMOS and an nMOS transistor. The pMOS and nMOS transistor may be connected in series. The at least one tuneable load may be connected to a terminal of the pMOS and / or the nMOS transistor.

[0019] The terminal of each of the pMOS and / or the nMOS transistor may comprise the drain or source terminal.

[0020] 55650902-1 The at least one tuneable load may comprise a first tuneable load and a second tuneable load. The least one tuneable load may comprise a first tuneable load and the device comprises a second, non-tuneable load. The first and / or second inverter module may comprise a first tuneable load and a second tuneable non-tuneable load. The threshold of each inverter module may be dependent on a ratio of one property of the first load to the second load. The at least one property may comprise a resistance and / or a conductance.

[0021] The device of any preceding claim, wherein each inverter module comprises a pMOS and an nMOS transistor, wherein the at least one tuneable load of the inverter module comprises a first tuneable load that is connected to a terminal of the pMOS or nMOS transistor and inverter module comprises a second, tuneable or non-tuneable load connected to the other of the pMOS or nMOS transistor.

[0022] The tuneable loads may be connected to a drain or source terminal of the inverter module.

[0023] The inverter modules may be coupled to a high voltage source wherein the inverter is configured to output an output signal having the high output voltage in response to the input voltage being below the threshold voltage and output the signal having the low voltage in response to the input voltage in response to the input voltage being above the threshold voltage. The high voltage source may be a working voltage or supply voltage. The high voltage source may be, for example, Vdd. The low voltage source may be, for example, GND,

[0024] The output module may comprise first and second controllable switching devices coupled to the first and second inverter modules respectively and wherein the output of the inverter modules are provided as control signals to the first and second controllable switching devices and wherein the output module is configured to output a match signal in response to the input voltage being in the matching window. The first and second controllable switching devices may comprise, for example, first and second transistors.

[0025] 55650902-1 The output module may comprise a pull up or pull down circuit for coupling a high voltage to a match line in response to the voltage of the input signal being in the matching window.

[0026] The output module may comprise a first and a second transistor gated by the output signal of the inverter modules.

[0027] The output signals of the inverter modules may have substantially different voltages when the input signal is in the matching window. The output module may be configured to output a match signal in response to receiving substantially different output signals from the inverter modules.

[0028] A first output may be substantially equal to a low reference voltage, such as GND, and the second output may be high reference voltage, such as a Vdd or other circuit supply voltage.

[0029] Each inverter module may comprise a voltage divider arrangement formed at least in part by their respective tuneable load.

[0030] Each inverter module may comprises a two transistor and two resistor (2T2R) arrangement.

[0031] The device may further comprise a tuning module configured to tune the load of the tuneable load of each of the first and second inverter modules thereby to set the matching window.

[0032] The tuning module may comprises a first output line connected to the first inverter module and a second output line connected to the second inverter module. The tuning module may comprise a first conductive path formed between a first bitline and a second bitline via the first inverter module and a second conductive path between a first bitline and a second bitline, wherein the resistive states of the tuneable loads can be tuned by controlling the voltage of the bitlines.

[0033] According to a second aspect, there is provided a memory device comprising:

[0034] 55650902-1 a plurality of memory cell devices wherein the plurality of matching windows of the memory cell devices form a signal template; an input module configured to receive one or more analogue signal, and provide said one or more analogue signals or signals derived from said one or more analogue signals as input to the plurality of memory devices; an output module configured to receive output from the plurality of memory devices and determine a match between the one or more analogue signals or signals derived from said one or more analogue signals and the stored template based on the output of the plurality of memory devices.

[0035] Each memory cell devices may be configured to define a matching window. The memory cell device may be in accordance with the first aspect or as described.

[0036] The memory device may form part of a template matching module for determining a match between the signal template and an analogue input. The memory device may be programmable to store a template. A template may be represented and / or stored as a plurality of template samples. Each memory cell device may be configured to store a matching window representing a template sample. The device may comprise a sampling module for sampling the one or more analogue signal to obtain a plurality of samples. Determining a match may comprise providing a sample to each of the memory cell devices and performing a matching process between the sample and the matching window.

[0037] The plurality of matching windows may form a signal envelope. A match between the analogue signal and the template may correspond to the analogue signal being substantially inside said envelope.

[0038] The output module comprises a signal combining or accumulator circuit for combining output signals from at least some of the plurality of memory devices to produce a combined signal representing a match and / or proportional to a degree of match between the analogue signal and the template.

[0039] The analogue signal may comprise or be derived from a time varying signal and / or a bio-signal and / or a sensed signal representing a physical stimulus.

[0040] 55650902-1 The analogue signal may represent any physical stimulus converted into a continuous and / or time varying signal. The analogue signal may comprise a temperature, light intensity and / or a biosignal potential. The analogue signal may comprise image data.

[0041] The input module may be configured to sample the analogue signal to produce a plurality of samples as input signals to the plurality of memory devices.

[0042] The plurality of memory cell devices may be arranged as an array.

[0043] The plurality of memory device may be configured to store data, for example as one or more templates, and may be configured to performing a matching process between the one or more input signals and the stored data. The memory device may be configured to output the address of matched data.

[0044] The input signal may represent a search query. The plurality of memory device may be configured to store data to be searched. The device may be configured to perform a search of the stored data by providing one or more signals to the memory device.

[0045] The output signal may be configured to output a signal representing an address of stored data that matches and / or has the highest degree of match and / or matches above a pre-determined threshold to the stored data.

[0046] The template may be representative of a pre-determined state or classification of an input signal.

[0047] According to a third aspect, there is provided a sensing device comprising: a sensor configured to sense a physical stimulus and produce an analogue signal in response to sensing the physical stimulus and / or configured to receive a sensor signal representative or indicative of a physical stimulus; the sensing device further comprises a memory cell device according to the first aspect or the memory device of the second aspect.

[0048] The sensing device may comprise a sensor. The sensing device may comprise a networked wearable or implantable device.

[0049] 55650902-1 According to a fourth aspect, there is provided a method of operating a memory cell device comprising: receiving, at each of a first and second inverter module, an input signal, wherein each inverter module comprises a tuneable load having a respective threshold voltage, wherein the threshold voltages define a matching window; receiving, at each of the first and second inverter modules, an input signal; outputting, by the inverter modules, an output signal in dependence on the voltage of the input signal and the threshold voltage of the inverter module, receiving output signals from the first and second tuneable inverter modules and outputting a match signal and / or a contribute to a match signal based on the output signals representing or at least indicating that the input signal has a voltage in the matching window.

[0050] The method may further comprise outputting, by the inverter modules, an output signal in dependence on the voltage of the input signal and the threshold voltage of the inverter module and / or receiving output signals from the first and second tuneable inverter modules and outputting a match signal based on the output signals representing or at least indicating that the input signal has a voltage in the matching window.

[0051] According to a fifth aspect, there is provided, a memory cell device comprising: first and second tuneable inverter modules, wherein each inverter module comprises at least one tuneable load configured to set a threshold for the inverter module, wherein each inverter module is configured to receive an input signal and output an output signal in dependence on the input signal and the threshold, wherein the thresholds of the first and second tuneable inverter modules define a matching window, wherein the device further comprises an output module configured to receive output signals from the first and second tuneable inverter modules and configured to output a match signal and / or a contribution to a match signal in response to the output signals representing or indicating that the input signal is in the matching window. The threshold may comprise a voltage or other measure of an electronic signal.

[0052] 55650902-1 Features of one aspect may be provided as features of any other aspects. For example, features of the devices of the first, second, third and fifth aspect may be provided as features of the method and vice versa.

[0053] Brief Description of Drawings

[0054] Various embodiments will now be described by way of example only, and with reference to the accompanying drawings, of which:

[0055] Figure 1 is a circuit diagram of a memory cell device, in accordance with an embodiment;

[0056] Figure 2 is an illustration of operation of the memory cell device of Figure 1 ;

[0057] Figure 3 is a set of plots showing signals of the memory cell device during operation;

[0058] Figure 4 is a schematic view of a sensing device comprising an array of memory cell devices, in accordance with an embodiment;

[0059] Figure 5 is schematic overview of an application of the memory cell devices;

[0060] Figure 6 is a schematic view of a memory system, in accordance with an embodiment;

[0061] Figure 7 is a diagram showing a configuration of a memory system, in accordance with an embodiment, and

[0062] Figure 8 is a set of plots showing simulation results.

[0063] Detailed Description

[0064] Figure 1 depicts a memory cell device 10. In the present embodiment, the device is described in terms of two sub-modules: a tuning module 12 and a memory module 14. The memory module 14 has a first inverter module 16a, a second inverter module 16b and an output or read out module 18. The memory cell device may also be referred to as a template matching pixel (also known as a texel or TXL). The tuning module may be referred to as programming or write module.

[0065] As described in the following, the memory cell device is capable of storing two voltage levels in the form of resistive configurations that define a matching window. In the present embodiment, the matching window is stored by the memory cell device as two voltage threshold values. The memory cell device is configured to determine if an input voltage is in the matching window. In the present embodiment, the TXL compares the input voltage to the upper and lower thresholds to determine a match.

[0066] 55650902-1 Each inverter module is configured to set a respective threshold voltage to define a matching window. In this embodiment, the first inverter module sets a high threshold and the second inverter window sets an lower threshold. Each inverter module has a tuneable load configured to set the threshold voltage. In the following embodiment, the tuneable load is a resistive random-access memory (RRAM) element. In some embodiments, the tuneable load is a resistive element or trimming element. In some embodiments, the tuneable load comprises a memory-resistor (memristor or memristive) device. In some embodiments, the tuneable load comprises any device configured to store a tuneable non-volatile resistance or conductance.

[0067] The memory device is coupled to a number of external or shared lines. In detail, the memory device is coupled to a pair of complimentary bitlines (BL and BLbar) 30, 32; a pair of further threshold setting lines 34, 36 (PREN1 and PREN2) and an input line 38. The memory device is further coupled to a ground line 42 and a matchline 44. PREN in this case stands for PRogram ENable, since these access transistors are used during the programming / characterisation phase of operation. PREN1 for access transistor of the first RRAM (RRAM of the first inverter) and PREN2 for access transistor of the second RRAM (RRAM of the second inverter).

[0068] In detail, the tuning module 12 is coupled to the threshold setting lines 34, 36. Each of the first and second inverter modules are coupled to the bitline 30 and the ground line 42. The output module 18 is coupled to the bitline 30 and the matchline 44.

[0069] Internally, the modules are connected as follows. The tuning module 12 has a first output 50 line connected to the first inverter module 16a and a second output line 52 connected to the second inverter module 16b. The first inverter module 16a has an output line 54 (OUT_HI) connected to the output module 18 and the second inverter module 16b has an output line 56 (OUT_LO) connected to the output module 18.

[0070] Turning first to first inverter module, the first inverter module has a RRAM element (RMI) 20a, a resistor (Ri) 22a, a first transistor (MPI) 24a and a second transistor (MNI) 26b. In the present embodiment, the first transistor 24a is a p-MOS transistor and the second transistor 26a is an n-MOS transistor. Likewise the second inverter module 16b has a RRAM element 20b, a resistor 22b, a first transistor 24b and a second transistor

[0071] 55650902-1 26b. For brevity only the first inverter module 16a is described in detail in the following, however, it will be understood that in the present embodiment, the second inverter module 16b has the same components as the first inverter module 16a.

[0072] In the first inverter module 16a, the RRAM element, RMi, 20a is connected between the bitline 30 and the first transistor 24a (MPI). The RRAM element 20a is connected to a source terminal of the first transistor 24a (MPI). The resistor (R1) 22a is connected between the second transistor 26a (MNI) and the ground line 42. The resistor 22a is connected to a source terminal of the second transistor 26a (MNI). The first transistor (MPI) and second transistor (MNI) are connected in series. The first and second transistors are each connected to the input line 38 at their respective gate terminals. The first and second transistors are each connected at their drain terminals to the first inverter module output line 54 (denoted as OUT_HI) which in itself connects the first and second transistors to the output module 18 (by opening / closing the first transistor 62 of output module 18).

[0073] In each inverter module, the RRAM element, resistor and two transistors form a potential divider circuit arrangement. In the present embodiment, by changing the resistive state of the RRAM element of each inverter module, a switching point of the inverter module can be set thus defining a threshold voltage of each inverter module.

[0074] The RRAM elements of the present embodiment are one example of a tuneable load. Various devices may be considered a tuneable load. For example, memristors, FeRAM, STTRAM, PCMRAM and others are different forms or technological implementations of components exhibiting resistive switching. Alternatively, the tuneable load may be a non-memristor tuneable resistive load, such as a floating gate transistor. It will be understood that any other tuneable resistor may be used in place of the RRAM elements.

[0075] In the described embodiments, a resistor and RRAM element pair is described. In the present embodiment, only the upper resistive elements are tuneable loads in the form of programmable RRAM devices, while the lower resistive elements take the form of conventional polysilicon-based resistors. It will be understood that in further embodiments, each inverter module may include two tuneable loads for setting the respective threshold, for example, a RRAM element or memristor pair may be

[0076] 55650902-1 provided. In the present embodiment, the threshold of each inverter module is set by the two resistive elements: specifically the ratio of the (tuneable) RRAM and (fixed) resistor pair. In such embodiment, the actual threshold may be stored into the upper RRAM element per inverter module and the other RRAM element is set to an appropriate geometric mean value (between the lowest and highest conductance value attainable by the RRAM devices) and is used as a reference conductance that enables an appropriate ratio in the hybrid voltage divider (hybrid inverter). The use of two RRAM devices per bound may enable a better dynamic range for expressing conductance thresholds in our design. In such embodiments, the reference (lower) RRAM devices are meant to be programmed once with a periodic refresh of their state to eliminate any conductance drift. The threshold RRAM devices (upper) are configured to be programmed each time a new set of patterns is to be mapped into the TXL-CAM system.

[0077] The input line 38 is connected to the input of the RRAM-CMOS inverter modules (specifically, these correspond to gate nodes of the MOS components in a conventional CMOS connectivity). The RRAM devices are placed between the pMOS and VDD connection (provide by BL) and between the nMOS and the GND node for the pull-up and pull-down network of the hybrid inverter, respectively.

[0078] The output of the first inverter module 16a is connected to an input of the output module 18. The output of the inverter module is therefore a midpoint signal of the memory circuit, referred to as OUT_HI. Likewise, the output of the second inverter module 16b is connected to an input of the output module. The output of the second inverter module 16b is therefore a midpoint signal of the memory circuit, referred to as OUT_LO. As such, the output of one hybrid inverter module controls the gate of the output pMOS device of the output module and the output of the other hybrid inverter controls the gate of the output nMOS device of the output module.

[0079] Each inverter may be referred to as a hybrid RRAM-CMOS inverter and, in the present embodiments, is a 2T2R circuit with each such hybrid inverter mapping one of the two thresholds / bounds. In the present embodiment, the threshold of each inverter module is effectively defined based on the ratio of the upper and lower RRAM device which shifts the voltage threshold of the hybrid inverter (thus the value of input voltage that the inverter changes output). The RRAM element and resistor are thus used to set a

[0080] 55650902-1 switch point of each of the inverter modules. The RRAM and resistor therefore operate to define a function that maps the analogue input signal to the output voltage of each inverter module (which corresponds to the midpoint signals OUT_LO and OUT_HI).

[0081] In further detail, when the voltage of the input signal (Vin) is lower to the switch point of the first inverter, then OUT_HI has a high value. It will be understood that the same effect can be achieved using different memristor configurations. Similar comments apply to the second inverter module in which when the voltage of the input signal (Vin) is lower to the switch point of the second inverter then OUT_HI has a high value. As such, the output of each inverter is high for inputs lower than the threshold or low for inputs equal or higher than the threshold.

[0082] In particular the second inverter module is coupled to same input line as the first inverter module. The second inverter module has an output coupled to the output module. The second inverter module outputs a signal (OUT_LO) to the output module. The RRAM element and resistor thus form a potential divider. By changing the resistive state of the RRAM element, the switch point of the inverter module can be modified.

[0083] The OUT_LO and OUT_HI are either high (VDD) or low (GND). If the OUT_HI of the first inverter is lower I to the switch point (the threshold of the inverter) then it opens the nMOS and (depending on the status of the other two transistors of the output module) the potential conductiveness of the output path to ML line 44 could be a maximum).

[0084] Each inverter has a current draw only during the switching point. This is the dynamic power consumption of the inverter and is the case for this RRAM-CMOS as well as the conventional CMOS inverters. This has nothing to do with the functionality of the TXL but it is affecting the performance when total power consumption is to be measured either for the cell or the system.

[0085] The first inverter module and second inverter module can therefore be operated to define a high and low threshold that defines a matching window. Operation of the inverter modules in response to input signals is described in further detail with reference to Figure 2.

[0086] 55650902-1 In addition to the first and second inverter modules, the memory device, in the present embodiment, has a tuning module 12 and an output module 18.

[0087] Turning first to the output module 18, this module is configured to process the output of the inverter modules. The output module has three controllable switching devices. In this embodiment, the controllable switching devices are MOSFET transistor devices. The transistors include first output module transistor (MMLN) 62 and second output module transistor (MMLP) 64. The first output module transistor is an nMOS transistor and are referred to as such. The second output module transistor is a pMOS transistor and referred to as such. The nMOS transistor 62 is connected to an output of the first inverter module and the pMOS transistor 64 is connected to an output of the second inverter module. The nMOS and pMOS are controlled by the output signals from the first and second inverter, respectively. While the present embodiment describes nMOS and pMOS transistors, it will be understood that in further embodiments, other controllable switch devices may be suitable in place of those transistors.

[0088] The nMOS and pMOS transistors are provided in a series circuit arrangement with a third transistor 66. The three transistors are provided in series between bitline 30 and matchline 44. As described in the following, the three transistors form a pull up circuit arrangement for coupling a high voltage of the bitline to the match line in response to the voltage of the input signal being in the matching window. In some embodiments, the pMOS and nMOS are serially connected to multiply the low and high threshold memory read.

[0089] The third transistor 66 is a power-gating pMOS device that enables the charge of the matchline when the memory read operation is active. The pMOS device also performs a current limiting operation to appropriate adjust the charging rate of the matchline. This is performed by applying an appropriate biasing voltage (VEN) to partially open the power-gating pMOS. This per cell current limiter is useful for calibrating the cell charging capability depending on the size of the implemented array and / or the detection requirements of the accompanying sense amplifiers. Embodiments of arrays and sense amplifiers are described below.

[0090] Turning to the tuning module 12 this module is configured to set or otherwise tune the load of each inverter module. In particular, in the present embodiment, the tuning

[0091] 55650902-1 module is configured to set a resistive state of the RRAM element of each of the inverter modules to define and control the matching window.

[0092] The tuning module 12 has a first transistor 58 (MPI) and a second transistor (MP2) 60. The first transistor 58 is connected to the second inverter module 16b and the second transistor 60 is connected to the first inverter module 16a. The two transistors are nMOS devices and operate as access transistors during programming / tuning of the RRAM array.

[0093] The first transistor 58 is connected between the BLBAR line 32 and the PRENi line 34. In particular, the BLBAR line 32 is connected to the source electrode of the first transistor 58 and the PRENi line 34 is connected to the gate electrode of the first transistor 58. The drain electrode of the first transistor 58 is connected to a bottom electrode 63 associated with the RRAM device RM2 of the second inverter module. Specifically, the bottom electrode 63 is between RM2 and the first transistor (MP2) 24b of the second inverter module.

[0094] Likewise, the second transistor 60 is connected between the bitline 32 (BLBAR) and the PREN2 line 36. In particular, the bitline 32 (BLBAR) is connected to the source electrode of the second transistor 60 and the PREN2 line 36 is connected to the gate electrode of the second transistor 60. The drain electrode of the second transistor 60 is connected to a bottom electrode 61 (BEM1) associated with the RRAM device RM1 of the first inverter module. The bottom electrode 61 is between RM1 and the first transistor (MPI) 24a of the first inverter module.

[0095] These MOSFET transistor devices are operable as access transistors during a programming or setup mode of the RRAM array in which the resistance or conductance state of the RRAM devices are set. During programming mode the RRAM elements are set to appropriate resistive and / or conductance states. As described with reference to Figure 2(d), during programming mode, the path connecting the RRAM to the ACAM cell is cut-off and the circuit uses these extra 2 nMOS devices to effectively operate the two RRAM elements as two 1T1 R circuits. By accessing the RRAM devices between the BL and BEMs and BEM2 bottom electrodes provides a direct low resistance path for programming the RRAM devices. As a result of the tuning process, a matching window is defined between the first and second inverter modules.

[0096] 55650902-1 After programming the RRAM-based resistances and / or conductances to appropriate values using the tuning module, an input signal is introduced to the input of each of the dual hybrid inverters that store or map the two thresholds. The comparison of the input voltage to the matching window is described in further detail with reference to Figure 2. As described above, the output module forms a pull-up network consisting of pMOS and nMOS devices that is configured to detect a match of the input when it sits in the matching window (between the lower and upper bound of the cell). In response to the voltage being in the matching window (a matching event) the output module connects a high rail voltage (VDD) provided via BL line 30 to the matchline 18. In response to the voltage not being in the matching window (a mismatch event) there is no connection. The output module 18 is power gated by a pMOS device that is controlled by the global enable signal. The enable signal either cuts-off the power to the output module 18 (for example, during initialisation / programming) or biases the power gating pMOS to a specific resistive state (for example, during the evaluation phase).

[0097] The biasing of the output module 18 may effectively enforce a current limiting effect which results in a quick spike-like pulse of specific amplitude to appear in the matchline (for a given time of evaluation period). The charge limiting effect on the output module may have two effects, firstly, it may limit the power consumption per cell due to smaller voltage level transitions for the matchline. Secondly, it may enables the analogue accumulation of charge in the matchline since it allows a definition of a threshold above which the accumulated charge in the matchline triggers a match. The charge for each cell may be accumulated using an analogue integrator circuit based on capacitors networks.

[0098] As described below, the memory device is configured to be used a cell or texel as part of a larger array of memory devices. In such a configuration, the circuit is configured to perform a pattern matching operation between an input query and the stored patterns or templates of the array. At the level of the cell, part of the input query is provided as an input signal via input line 38 and a matching process between the input signal and matching window is performed. In such systems, the matchline is a common matchline shared between a group of memory devices. As such, each cell that matches outputs a contribution to the overall matchline signal (for example, per row of the array). In some embodiments, a common matchline for a group is configured to accumulate charge depending on the number of cells that match their respective portion of the input query.

[0099] 55650902-1 If multiple cells have a match with the corresponding part of the query input then multiple connection to VDD are enabled and the match line is driven at some specific rate (dependent on the number of match enable available per TXL-CAM array) to high voltage. The output sense amplifier reads the match line and can detect if there is an (overall) match of the query to a specific TXL-CAM word. The sense amplifiers are calibrated to detect a specific voltage level which is translated to match based on the time-to-charge of the match line. In case no such voltage level is observed in a specific timeframe, then the word is considered to have a mismatch.

[0100] The texel may be understood as a fundamental building block that stores part of a template in the form of a template sample. Each template sample is stored as a matching window. In some embodiments, the memory cell device output a metric of the similarity memory cell is a distancing circuit. In some embodiments, the template is stored as a set of matching window that define a row and / or wordline and / or matchline.

[0101] Figure 2 depicts, in further operation the matching process between input signal and matching window of the memory device 10.

[0102] In Figure 2(a), the memory module receives an input signal with a voltage within the matching window. In Figure 2(b), the memory module receives an input signal with a voltage above the high threshold of the matching window. In Figure 2(c) the memory module receives an input signal with a voltage below the high threshold of the matching window. In Figure 2(d) the memory module is in a programming mode.

[0103] In Figures 2(a), 2(b) and 2(c) the PREN_1 and PREN_2 lines for programming the RRAM devices are set to GND. In the Figures 2(a), an input is received at both the first inverter module 16a and the second inverter module 16b via the input line 38 and delivered to the gate terminal of each of the pMOS and nMOS transistors of the first and second inverter modules 16a, 16b.

[0104] Each inverter module is operable to form conductive paths in dependence on the input received from the input line. In the present embodiment, the first inverter module defines the higher threshold value of the matching window.

[0105] 55650902-1 The first inverter module 16a is operable to form a first conductive path (206a) from the BL to the nMOS transistor 62 of the output module via the RRAM device 20a and pMOS transistor 24a of the first inverter module 16a, in response to the input voltage being below the threshold voltage of the inverter module (the upper threshold of the matching window). As such, in response to the input signal being below the threshold voltage of the inverter module 16a (the upper threshold) the first inverter module controls the switching device (nMOS transistor 62) to an open state.

[0106] The first inverter module 16a is operable to form a second conductive path (208a) from the GND line to the nMOS transistor via the resistive element R1 and nMOS transistor in response to the input voltage being above the threshold voltage. As such, in response to the input signal being above the threshold voltage of the first inverter module 16a, the first inverter module controls the switching device (nMOS transistor 62) to a closed or off state.

[0107] Likewise, the second inverter module 16b defines the lower threshold value of the matching window. Similar to the first inverter module, the second inverter module 16a is operable to form a first conductive path (206b) from the BL to the pMOS transistor of the output module via the RRAM device and pMOS transistor of the second inverter module, in response to the input voltage being below the threshold voltage of the second inverter module. In contrast to the first inverter module, in response to the input signal being below the threshold voltage of the second inverter module 16b (the lower threshold) the second inverter module 16b controls the switching device (pMOS transistor 64) to a closed or off state.

[0108] The second first inverter module 16b is operable to form a second conductive path (path 208b) from the GND line to the pMOS transistor 62 via the resistive element R1 and nMOS transistor of the second inverter module in response to the input voltage being above the threshold voltage. As such, in response to the input signal being above the threshold voltage of the second inverter module 16b, the second inverter module controls the switching device (pMOS transistor 64) to an open or on state.

[0109] In summary the first inverter module (defining the upper threshold) operates its corresponding switching device to be open or on when the input signal is below the threshold and to be closed or off when above the threshold. The second inverter

[0110] 55650902-1 module (defining the lower threshold) operates its corresponding switching device to be closed when the input signal is below that threshold and to be open when above their threshold.

[0111] The first inverter is connected to an nMOS devices in the output circuit. Thus, the nMOS will be on when the output of the first inverter is high and off when the output is low. The second inverter is connected to a pMOS device which will be off when the output of the second inverter is high and on when the output is low. Only when both nMOS and pMOS of the output circuit are on is the input to the TXL cell considered to be within the matching window and thus causing a match / hit for this TXL cell.

[0112] In Figure 2(a), the input signal is in the matching window and has a voltage between the lower threshold and the upper threshold. As such the input signal is above the threshold of the first inverter module (the lower threshold) causing the first inverter module to open the nMOS transistor 62 via conductive path 206a. The input signal is below the threshold of the second inverter module 16b causing the second inverter module to open the pMOS transistor 64. Thus, a conductive path 210 is formed between the bit line and the match line in the output module.

[0113] In Figure 2(b), the input signal is outside the matching window, specifically, above the high threshold. As such the input signal is above the threshold of the first inverter module (OUT_HI is low) causing the first inverter module to close the nMOS transistor via conductive path 208a. The input signal is also above the threshold of the first inverter module (OUT_LO is low) causing the second inverter module to open the pMOS transistor via conductive path 208b. As such, the nMOS transistor 62 of the output module substantially blocks a conductive path between the bit line and the match line.

[0114] In Figure 2(c) the input signal is outside the matching window, specifically, below the low threshold. As such the input signal is below the threshold of the first inverter module (OUT_HI is high) causing the first inverter module to open the nMOS transistor 62 via conductive path 206a. The input signal is also above the threshold of the first inverter module (OUT_LO is high) causing the second inverter module to close the pMOS transistor 62 via conductive path 206b. As such the pMOS transistor of the

[0115] 55650902-1 output module substantially blocks a conductive path between the bit line and the match line.

[0116] In Figure 2(d), programming of the RRAM elements of the first inverter module and the second inverter modules is illustrated. The INPUT and ENABLE lines are set to a high voltage level (Vdd) to close a conductive path between the RRAM devices and the associated transistors in each inverter module and in read out module. The first transistor and second transistor are controlled to be conductive individually to form the first conductive path 202 and the second conductive close 204, respectively. The first conductive path 202 is formed between the first bitline, the RRAM device of the first inverter module, the second transistor of the tuning module and the second bitline. By controlling the voltage on the bitlines, the resistive state of the RRAM device of the first inverter module can be tuned and set. The second conductive path 204 is formed between the first bitline, the RRAM device of the second inverter module, the first transistor of the tuning module and the second bitline. By controlling the voltage on the bitlines, the resistive state of the RRAM device of the second inverter module can be tuned and set.

[0117] By accessing the RRAM devices between the BL and BEM1 and BEM2 bottom electrodes, a direct low resistance path for programming the RRAM devices is provided. The included nMOS devices enable proper therefore provide access to program the RRAM devices. In this specific configuration, only the upper resistive elements are assumed to be programmable RRAM devices, while the lower resistive elements take the form of conventional polysilicon-based resistors. However, in further embodiments, both the upper and lower resistive elements may be tuneable and therefore additional tuning circuity may be provided.

[0118] Figure 3 depicts graphs of simulation results for a typical match and mismatch case for a memory device, in accordance with an embodiment. The device implements a conditional charging matchline paradigm, with the matchline being connected to GND before being charged to a specific voltage level based on the matching degree of the pattern matching operation. The discharged matchline that only charges upon memory hit can be considered advantageous energy-wise especially in applications with sparse hit events. More specifically, the figure illustrates the voltage of specific nodes in the ACAM cells. Although there is some noise in the matchline, the classification can be

[0119] 55650902-1 performed accurately by sampling within the pattern matching operation window, thus when the TXLEN is low. These simulations were performed using 5V components from a commercial 180nm CMOS technology. High voltage 5V MOSFETs were selected for the cell design to withstand the higher electroforming voltages that can be as high as 5V.

[0120] The above parameters are to be understood as referring to the type of devices used by the simulations. In embodiments, a 180nm technology is used that has two types of operating voltages: devices operating at 2V and devices operating at 5V. The 5V device may be preferred as they are more compatible with some RRAM technologies that require higher programming voltages (especially during the initial electroforming operation). In a sense, 5V is the nominal Vdd that should be used when operating these devices but in our case Vdd for the cell is 3.3V. The reason behind the lower power supply for the cell’s operational voltage is not only for power savings but also to satisfy the requirement of not apply high voltage bias to RRAM devices during normal ACAM operation. High voltage bias above 3V could result in RRAM state drifting, thus unwanted programming of the device.

[0121] Figure 4 depicts a schematic diagram of a sensing device that incorporates an array of memory devices such as the memory device described in relations to Figures 1 to 3. In particular, Figure 4 depicts a near sensor application of the memory device (also referred to as a TXL ACAM).

[0122] In this application, the sensing device has a sensor including a sensor front end 402 for obtaining a sensor signal (an analogue signal) and a transmission line 404 for transmitting the signal towards a signal processing and memory module 406. The signal processing module 406 has a pre-processing and encoding module and a classifier module. An output of the signal processing module is provided to a signal transmitter 408 for free space or other modes of transmission.

[0123] The processing and memory module has an array of memory devices, such as those described above. The pre-processing and encoding module pre-processes the analogue signal and encoded the signal into an input query for searching through the array of memory devices. The array of memory devices may be referred to as a RRAM- based ACAM classification engine.

[0124] 55650902-1 The plurality of memory devices or cells for template matching. An analogue input vector (VinO to 3) is sampled from the continuous analogue signal obtained by the sensor. The vector may be represented as 4 input voltage values (VmO, Vjn1, Vjn2, Vjn3). These input voltage values are captured by the sample and hold circuit and used to perform an analogue template matching in the TXL array. By sampling the signal a plurality of sample signals, or samples, are generated each sample representing a value of the signal at a time point.

[0125] The signal may be sampled if necessary for separate analogue values to be captured as the query. These values can be used to drive the ACAM array and perform a template matching operation. An example operation could be spike sorting. In more general machine learning applications, a set of attributes of a specific object are encoded as real values which can be represented circuit-wise with analogue signals. These attributes may then be used similarly to the sample of the sensing and template matching example.

[0126] The samples are supplied to the array in parallel and form a query input. The query input is provided through sample and hold circuitry 412. As described above, each memory device or TXL is configured to store a matching window. A plurality of such memory devices are provided as an array 416. Based on the data stored in each memory device, a matching window is defined. A matching comparison is performed a matching module 416.

[0127] As each cell is configured to store a matching window, a groups of cells, for example, a row of cells, can together store a template. In certain embodiments, a template may be represented as a plurality of discrete template samples. Together the template samples may define a time dependent function or envelope. A template match may therefore correspond to each sample signal having a value in the corresponding matching window. As such, a template match may correspond to an analogue signal being inside the signal envelope.

[0128] The query value of each cell being is compared with this memory-defined window. If the input is within the match window then this results in a memory hit while if the input is outside the match window there is a memory miss.

[0129] 55650902-1 It will be understood that different degrees of match between the query and defined template can result in different outcomes and different output, in some embodiments. The matching module 416 may be configured to perform different matching operations.

[0130] For example, if a query results in all cells in a row result in a hit then this corresponds to a full template match event. In that case, the array can respond with a template match address to classify the input query template.

[0131] Matching conditions include exact template match, a best match and a threshold match. In some embodiment, a best match select the stored template which is closest to the input query. In some embodiment, a threshold match outputs one or more templates which match within a threshold value. For different matching instructions a different matching comparator network may be implemented.

[0132] The signal online template matching application envisioned for the proposed RRAM- CMOS ACAM follows the conventional flow of capturing and pre-processing the signal through an appropriate analogue front-end and then encoding the signal into an appropriately formatted input query to search through

[0133] Figures 5(a) to 5(d) illustrate, in overview, a TXL ACAM array operable as part of a classifier.

[0134] Figure 5(a) depicts a classifier formed of an ACAM array. Figure 5(b) illustrates a prediction output from the classifier. Figure 5(c) depicts an example ACAM array forming a classifier. Figure 5(d) depicts the memory cell, in accordance with an embodiment, as described above.

[0135] Figure 5(a) depicts a front-end encoder module 504 that receives an input signal and encodes the signal as a query or query key. The query key is then passed to the array of memory cell devices 506. The array of memory cells devices are used to calculate a Euclidean distance between the query input and the patterns (or templates) stored in the array. The device also has an output decoder module comprising a plurality of sense amplifiers 508. In some embodiments, the query is distributed to the columns of the array to enable a parallel search operation while all rows of the array are organised

[0136] 55650902-1 as matchlines that calculate and send to the sense amplifiers (SAs) the Euclidean distance of the query and the template stored in this matchline.

[0137] Figure 5(d) graphically represents the calculation of Euclidean distances between a query 510 and a plurality of templates (for example, template 512). The query and templates are represented as points in a Euclidean vector space (hyperspace). Figure 5(d) represents the distance between the query and all templates stored in corresponding groups of memory cells.

[0138] A number of different distance metrics may be used to calculate the distance between two points in a given vector space (for example, a template and query or two templates). As non-limiting examples, these include Hamming distance, cosine similarity, Jaccard scoring. The selection of one may be dependent on, for example, the research area and application.

[0139] In the present embodiments, a Euclidean distance metric is selected. Although the exact method for calculating the distance may change, the distance metrics perform the same operation, to calculate a degree of similarity between two patterns. Such a calculation may be performed per quanta of information, thus for a binary pattern per bit of information. For the analogue templates described above, this takes the form of comparing each quanta of our templates (i.e. attributes of template) and calculate the rate of matching, thus how close a query attribute is to the value of a the corresponding template attribute. This takes the form of real valued comparisons. The results of these comparisons are weighted and accumulated into a singular value that represent the matching rate of the two templates (similarly to what we would do in statistics with correlation coefficient). The specific ACAM implementation under investigation perform all the above in the analogue domain, thus at the output of each template (at each row of the module) a singular value that corresponds to the degree of match (matching rate) of this template with the query. The higher the output value the higher the matching rate.

[0140] Figure 5(d) depicts a circuit schematic of the proposed 9-transistors-4-resistors (9T4R) pixel design for analogue template matching applications. As described above, the cell can map two threshold (a low and a high threshold) through the use of its non-volatile RRAM devices (RM1 and RM2). The use of the hybrid RRAM-CMOS inverter design

[0141] 55650902-1 enables the movement of the threshold voltage of the inverter depending on the resistive ratio of RM1-R1 and RM2-R2 (through source degeneration of the MOSFET devices). The memory part of the cell is comprised from the two RRAM-CMOS inverter modules while the per cell readout circuit (3T Cell Comparison part) is comprised from MMEN, MMLP and MMLN devices. The MPR1 and MPR2 devices of the 2T write bypass circuit are used for accessing the RRAM for programming.

[0142] The RRAM elements are one example of a tuneable load. Various devices may be considered a tuneable load. For example memristor devices, FeRAM, STTRAM, PCMRAM and others are different forms or technological implementations of components exhibiting resistive switching. Alternatively, the tuneable load may be a non-memristor tuneable resistive load, such as a floating gate transistor. The skilled person would understand that further alternatively any other tuneable resistor may be used in place of the memristor.

[0143] The memory cell device may be considered a hybrid device in terms of technologies used to implement it. In embodiments, a Resistive RAM (RRAM) and CMOS technology are combined. Instead of a conventional CMOS only inverters, the design uses a hybrid design that implements an inverter with both conventional (CMOS) and emerging (RRAM) technologies. Hence, hybrid refers to the technology integration aspect of the circuit.

[0144] In the above described embodiment, it was described that the output voltages of the inverter module should have substantially different voltages when the input signal is in the matching window and that the output circuit is configured to output a match signal in response to receiving substantially different output signals from the inverter modules. In this embodiment, the voltages should be close to VDD and GND but slightly deviating from the actual rail values due to the voltage drop across the RRAM elements. Thus, the values will be close to the rail values to open / close effectively the MOSFET devices found in the third branch (to perform a conditional XOR operation per TXL cell).

[0145] The above embodiments relate to a circuit that is used for analogue template matching applications as part of an analogue content addressable memory (ACAM). As described above, two hybrid RRAM-CMOS inverters are used to map the analogue

[0146] 55650902-1 thresholds. The per cell comparison is performed by two complementary devices (one pMOS and one nMOS) that map the low and upper bound. An extra pMOS device is used for the per cell comparison branch as tuneable trimming element to control the charging contribution of the cell to the matchline. Additionally, two extra MOSFETs are used to enable an alternative path for the RRAM devices to be programmed.

[0147] Embodiments described above may enable the implementation of low-power ACAM arrays aimed at, for example, machine learning related classification tasks. Due to its low-power design, the above embodiments may offer a promising candidate for implementing in-sensor or near-sensor associative memory -based template matching at the edge (for example, unmanned image sensor, wearable bio-signal detectors).

[0148] An important aspect of using a more complex design like the 9T4R against known configurations is the use of hybrid RRAM-CMOS inverters as a method of reducing the dynamic power consumption of the memory read operation. The memory read operation in many RRAM-based cells usually involves the use of voltage dividers (i.e. through the use of 1-transistor-l-RRAM (1T1 R) memory cells), thus creating a direct path between a high voltage node and the ground. Embodiments described above that use RRAM-CMOS-based inverters, for example, a 2T2R primitive circuit, may be capable of performing a memory read operation and having only temporary dynamic power dissipation (pMOS and nMOS conductive at the same time). The "memory read" operation for the case of 2T2R hybrid inverter is therefore encoded into the inverter's threshold voltage. Hence, the power dissipation on the comparator side may be reduced with smaller transitions of the matchline charging-discharging cycle, but also the power dissipation of the ACAM cell during the memory read operation may be reduced. Moreover, the use of RRAM-based ratio-based mapping of the analogue threshold values may enable the integration of a wider range of RRAM technologies that showcase different ranges of resistive states, into the proposed 9T4R.

[0149] In the above described embodiments, an output match signal is described. In some embodiments, more than one cell device may be coupled to a common output and each cell device may output a contribution to a combined match signal in response to a match. The match signal may be defined by the number of cells matching for each template. For each cell matching, a path between Vdd=3.3V and the discharged matchline may be created. In some embodiments, the charging of the matchline could

[0150] 55650902-1 represent multi-bit output, dependent on the number of charge packets send to the matchline which is equal to the number of cells that output a match event (input is within the matching window of the cell).

[0151] Although description of particular embodiments has been provided above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives to the described embodiments which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in any embodiment, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein. In particular, one of ordinary skill in the art will understand that one or more of the features of the embodiments of the present disclosure described above with reference to the drawings may produce effects or provide advantages when used in isolation from one or more of the other features of the embodiments of the present disclosure and that different combinations of the features are possible other than the specific combinations of the features of the embodiments of the present disclosure described above.

[0152] The following non-limiting comments regarding the device and experimental results are provided.

[0153] A comparison to a known cell type was performed. For the comparison, both cell types were designed and simulated in the same commercially available 180nm technology and the same assumptions for the integrated RRAM technology were used towards adapting the MOSFET devices to the RRAM specifications (e.g. high current pass- through the accompanying MOSFET devices). The precharge / enable signals period was set for tclock=15ns with 1 / 3 of the signal (t_evaluate=5ns) during assigned for memory read operation and 2 / 3 of the signal (t_initialise=Ons) for pre- charging / initialisation. It is assumed that 10ns of precharge are useful in case a large ACAM matchline needs to be precharged to VDD. The memory part of both cells is power gated and is turned off during the matchline initialisation phase.

[0154] It was observed that for both match and mismatch the proposed 9T4R exhibits better power consumption over the evaluation period (which was set for one t_clock=15ns

[0155] 55650902-1 period). The cell therefore may offer advantages in terms of power consumption. This power saving characteristics of the 9T4R cell design can be further enhanced in a system-level applications, for example, for in-sensor or near-sensor approaches for bio-signal classification, and area that is known to have sparse event while requires continuous, or near continuous, sensing and classification of the input stimulus.

[0156] The IC design developed using the proposed 9T4R ACAM cell as its building block. A 9T4R-based 32x48 ACAM array alongside the necessary peripherals to access the RRAM devices for programming and reading as well as for performing the parallel template search and match operation was integrated into a single silicon IC with all CMOS circuits being implemented as computing substrate and the RRAM devices are added with our in-house Back-End-Of-Line (BEOL) process. A block diagram of the prototype IC is shown in Figure 6 while physical layout floorplan of the implemented prototype IC is shown in Figure 7.

[0157] Since the prototype IC is aimed at analogue template matching based on analogue information captured through a single input channel, a custom S&H circuits to sample and capture the incoming analogue input. This may be useful for applications such as spike-sorting in BMI and other bio-signal capture and vectorisation applications. Thus, the assumption followed for this IC design is that the front-end is supplying a pre- processed analogue signal and with the design this signal does not need to be converted to digital domain for the pattern matching operation. After the sampling operation is complete, analogue buffers are used to supply the input samples to the ACAM array as the input query to be identified with the stored templates. Due to the nature of the proposed ACAM design, a custom capacitor-based accumulator circuit for gathering the match event contributions is used per matchline. The accumulator is attached to the sense amplifier used to digitise the ACAM read operation. The sense amplifier is a voltage-mode dynamic latch comparator variant customised to sense the range of matchline voltage readout. The outputs of the sense amplifiers are connected to a Parallel In Serial Out (PISO) shift register. Configuration digital signals are stored in a general Serial In Parallel Out (SIPO) shift register. Custom drivers to enable programming and characterisation of the RRAM devices, alongside the control logic, is also designs for this proof-of-concept IC. Custom drivers are used for this prototype IC design for testing purposes.

[0158] 55650902-1 A block diagram of the TXL-ACAM IC is shown in Figure 6(a), where all the main modules of the implemented proof-of-concept IC are shown. The schematic of the sample and hold circuit, the analogue drivers, the programming circuit and the sense amplifiers are all shown in 6(b),(c),(d),(e), respectively.

[0159] Figure 6 depicts a system-level block diagram of a TXL-ACAM integrated circuit. At the centre of the block diagram is the main ACAM array while in periphery the circuits for capturing and driving the analogue input vector, supplying power and controlling the array as well as reading the ACAM are implemented. Figure 6 depicts: (b) a sample and hold circuit schematic; (c) Analogue drivers for providing the query input to the array circuit schematic; (d) a Programming circuit schematic and (e) a sense amplifier circuit schematic.

[0160] Figure 7 depicts a layout design of a TXL-ACAM IC for analogue template matching. The integrated circuit includes the main array closely integrated with sense amplifiers. From the top side, decoding circuitry with sample and hold array is used to sample an analogue input which is used as the analogue input vector for the 9T4R array. On the left side, a deserialiser shift register (SIPO shift register) is configured to load configuration bits and decoding logic is used to control the row drivers. The row drivers can access the RRAM devices of the array with either polarity (i.e. for SET and RESET conductance writing operations). The bottom side includes a column decoder which is enable when a writing operation is under way. The column decoder alongside the row drivers can select a single RRAM device when entering characterisation mode. On the left side, a serialiser shift register (PISO shift register) is used to load the output of the sense amplifiers and shift all outputs through a single output pin.

[0161] Figure 8 depicts simulation results of the integrated chip implemented in a commercially available 180nm CMOS technology with the data-driven RRAM model. The SA_CLK shows the sense amplifier clock signal controlling the equalisationevaluation cycle of the comparator. The TXLEN is the array global enable signal that opens the output branch of cells enabling them to charge the matchline. The TXLEN has custom high and low level voltage values calibrated for fully breaking and partially making the output circuit. The SARESEN controls the leakage path that resets the matchline between subsequent pattern search operations. The signals ML_OUT represent a part of the 48 matchlines that for this example operation centre around the

[0162] 55650902-1 hit event. The signals SA_OUT are the sense amplifier outputs of the respective matchlines. For our design, the SA_OUT = 0V level indicate a pattern hit while a SA_OUT=5V level indicates a pattern miss.

[0163] In the present embodiment, the system is configured to perform in two modes: an analogue template matching mode, where analogue input vectors is applied in parallel to all entries in the ACAM array and the results of this memory read are sensed by the sense amplifiers and serialised with the PISO output shift register, and a programming mode, where the programming drivers are used to characterise / program individual RRAM devices. For the programming mode, row and column decoders are used to isolate specific RRAM devices for programming.

[0164] The proposed 9T4R-based ACAM physical layout IC design is shown in Figure 7(a), alongside some notation to provide more information on the sub-systems employed for the proof-of-concept design. The physical layout of the proposed ACAM array was designed using a commercially available 180nm technology for CMOS and our inhouse RRAM technology based on measurements of Pt / A1Ox_2 / TiOx / Pt metal oxide bi-layer metal-insulator-metal (MIM) RRAM devices. The RRAM technology employed has been shown to exhibit strong multi-bit memory operation.

[0165] Some rows to the RRAM-based ACAM array are replaced with rows that include conventional polysilicon-based resistor devices (based on the same commercial 180nm technology used for the MOSFET devices). This array configuration is applied for calibration purposes and readout assist purposes (reference point when reading a RRAM device for characterisation) as well as enabling an integrated testing infrastructure towards helping with characterising the IC's behaviour with different RRAM technologies integrate. Thus, the total 48 x 32 ACAM array of this IC has 32 x 32 RRAM-based rows and 16 x 32 polysilicon-based rows (the two sub-arrays are unified into a single array as shown in Fig. 7(a)).

[0166] The area utilisation of the main array covers the majority of the total IC area (approximately 66.3% of the total area). From the implemented peripherals, the programming drivers and the S&H channels are two of the largest block of the IC with area usage of approximately 8.8% and 6.3%. For design validation, we performed postlayout simulation on this proof-of-concept IC after extracting the resistive and

[0167] 55650902-1 capacitive parasitic of the physical layout. Since the RRAM model used to perform prelayout simulations is not yet adapted into fully adapted into a component with included parasitic extracted look-up-table, for the purpose of validating the main functionality of the design post-layout, the RRAM components are replaced with polysilicon-based resistors in a similar manner with the polysilicon-based part of the initial IC which is used for calibration and RRAM read reference. Although this is not enabling us to include the full intrinsic characteristics of the RRAM devices into our design, we are using this method to provide a baseline ideal result to prove the functionality of our array design alongside the implemented peripheral and how they are affected by resistive and capacitive parasitics.

[0168] An example operation of the analogue pattern matching operation is shown in Figure 8. More specifically, a part of the matchline readout vector alongside the sense amplifier classification and the array and sense amplifier control sequence is showcased. In this example operation we are showcasing the main control signals required to read the TXL-ACAM array. The SA_CLK control the equalisation-evaluation cycle of the sense amplifier. The TXL_EN is the global array enable signal that dictates the reading phase of the ACAM array during the pattern recognition phase. When the query is supplied to the array, TXL_EN enables the charging of the matchline for each cell that has an input that falls between the match window, as determined by the RRAM values. The A_RES_EN is a global matchline control signal that dictates the reset of the matchlines by discharging them through a specific rate. Also the main outputs of the TXL-ACAM array are shown in Figure 8. The matchline outputs ML_OUT to illustrate the chargingdischarging cycle of the pattern search operation. The sense amplifier output SA_OUT showcase the output of the dynamic latch-based circuit based on the comparison between the charging level of each matchline during the specific time when the sense amplifier evaluation starts against a provided threshold voltage VTH which is depicted alongside the ML_OUT traces. For the case of the example operation VTH = 1.4V is set. For our design, the SA_OUT = 0V level indicate a pattern hit while a SA_OUT =5V level indicates a pattern miss.

[0169] At the top part of the IC, the input capture peripherals (part of the analogue front-end) are included. A decoder provides phase control for the sampling operation of the parallel S&H circuit array. Based on the one-hot encoding generated by the digital control circuitry, the piecewise sampling of the analogue input is possible. Each sample

[0170] 55650902-1 is stored in one capacitor device (mimcap device). Transmission gates (TGs) are used to control the sampling of the S&H circuits. The TGs are appropriately sized (W / L = 10p7n / 600nm for both pMOS and nMOS devices of the TG) to enabled the fast charging of the hold capacitor to appropriate levels of charge. When all different samples of the analogue signal have been acquired then a parallel analogue buffing supports the transmission of the analogue vector into the array (for the pattern matching operation). For the case of the programming operation of the array, the input signal is set to logic high (for VDD_TXL=3V). The output of the array (when in normal pattern matching operation mode) is captured by a sense amplifier array. Each sense amplifier is designed as a dynamic latch comparator type of circuit effectively comparing the matchline voltage to a specific predetermined biasing voltage. Each sense amplifier outputs the results of this comparison. All sense amplifier out-puts are connected in parallel to a serialiser circuit (effectively a Parallel Input Serial Output Shift Register). Thus, when the pattern recognition phase is completed, all the outputs of the sense amplifier array are loading into the serialiser and then a bit-stream is send through a single output pin by shifting the contents of the serialiser to this output pin.

[0171] Besides the normal pattern recognition mode of operation, the IC also supports a characterisation mode. In the characterisation mode (also called programming mode), the TXL cell "disconnects" the RRAM devices from the rest of the cell and each RRAM device can be uniquely addressed through the use of accompanying "programming" nMOS devices. Effectively, during the programming / characterisation mode, the array becomes a 1T1R type of crossbar array, thus every TXL (9T4R cell) circuit becomes 2 1T1 R cells. The scheme for the RRAM devices of the cell. The cell design was designed and tested using a commercially available 180nm CMOS technology and a RRAM model adapted on the physical characteristics of our in-house RRAM technology. The proposed 9T4R ACAM cell design integrates the traits of the existing TXL design and enhances the window selectivity by using one hybrid RRAM-CMOS inverter per threshold, enables the easy accessing of each RRAM device in the design for forming and programming operation through the additional nMOS access devices and finally enables the configurable contribution of the cell to the charging matchline through the additional enable pMOS device at the comparator part of the cell. Although this results in a relatively large ACAM cell it enables a low power operation due to its CMOS-oriented design and enhances the available features for operating and configuring arrays of this cell.

[0172] 55650902-1 Furthermore, the IC design aimed at testing the novel 9T4R pixel cell in ACAM applications, alongside the supporting peripherals necessary for performing analogue template matching and RRAM device programming, is designed and tested in simulation using a commercial 180nm technology. The IC was designed using 5V MOSFET components and was fully custom-made following the analogue ASIC design flow in Cadence Virtuoso environment. The correct operation of the system was tested with RC parasitic extracted components towards further validating the proper circuit behaviour of each IC block.

[0173] 55650902-1

Claims

CLAIMS:

1. A memory cell device comprising: first and second tuneable inverter modules, wherein each inverter module comprises at least one tuneable load configured to set a threshold voltage for the inverter module, wherein each inverter module is configured to receive an input signal and output an output signal in dependence on the voltage of the input signal and the threshold voltage, wherein the threshold voltages of the first and second tuneable inverter modules define a matching window, wherein the device further comprises an output module configured to receive output signals from the first and second tuneable inverter modules and configured to output a match signal and / or a contribution to a match signal in response to the output signals representing or indicating that the input signal has a voltage in the matching window, wherein at least one of a) and b): a) the device comprises a tuning module configured to tune the load of the tuneable load of each of the first and second inverter modules thereby to set the matching window; b) wherein the output module comprises a pull up or pull down circuit for coupling a high voltage to a match line in response to the voltage of the input signal being in the matching window.

2. The device as claimed in any preceding claim, wherein the tuneable load comprises a memristor and / or other device configured to store a tuneable non-volatile resistance, wherein the threshold voltage is in dependence on at least the stored tuneable non-volatile resistance.

3. The device as claimed in any preceding claim, wherein each inverter module comprises a pMOS and an nMOS transistor, optionally connected in series, wherein the at least one tuneable load is connected to a terminal of the pMOS and / or the nMOS transistor.

4. The device as claimed in any preceding claim, wherein each inverter comprises either a) the at least one tuneable load comprises a first tuneable load and a second tuneable load or b) the at least one tuneable load comprises a first tuneable load and55650902-1the device comprises a second, non-tuneable load, and wherein the threshold voltage of each inverter module is dependent on a ratio of one property of the first load to the second load.

5. The device as claimed in claim 4, wherein the at least one property comprises a resistance or conductance.

6. The device of any preceding claim, wherein the inverter modules are coupled to a high voltage source, for example, Vdd, and a low voltage source, for example, GND, wherein the inverter is configured to output an output signal having the high output voltage in response to the input voltage being below the threshold voltage and output the signal having the low voltage in response to the input voltage in response to the input voltage being above the threshold voltage7. The device of any preceding claim, wherein the output module comprises first and second controllable switching devices, for example, first and second transistors, coupled to the first and second inverter modules respectively and wherein the output of the inverter modules are provided as control signals to the first and second controllable switching devices and wherein the output module is configured to output a match signal in response to the input voltage being in the matching window.

8. The device of any preceding claim, wherein the output module comprises a first and a second transistor gated by the output signal of the inverter modules.

9. The device of any preceding claim, wherein the output signals of the inverter modules have substantially different voltages when the input signal is in the matching window and wherein the output module is configured to output a match signal in response to receiving substantially different output signals from the inverter modules.

10. The device of any preceding claim, wherein each inverter module comprises a voltage divider arrangement formed at least in part by their respective tuneable load.

11. The circuit of any preceding claim, wherein each inverter module comprises a two transistor and two resistor (2T2R) arrangement.55650902-112. The device of any preceding claim, wherein the tuning module comprises a first output line connected to the first inverter module and a second output line connected to the second inverter module.

13. The device of claim 12, wherein the tuning module comprises a first conductive path formed between a first bitline and a second bitline via the first inverter module and a second conductive path between a first bitline and a second bitline, wherein the resistive states of the tuneable loads can be tuned by controlling the voltage of the bitlines.

14. A memory device comprising: a plurality of memory cell devices as claimed in any of claims 1 to 13, wherein the plurality of matching windows of the memory cell devices form a signal template; an input module configured to receive one or more analogue signal, and provide said one or more analogue signals or signals derived from said one or more analogue signals as input to the plurality of memory devices; an output module configured to receive output from the plurality of memory devices and determine a match between the one or more analogue signals or signals derived from said one or more analogue signals and the stored template based on the output of the plurality of memory devices.

15. The memory device of claim 14, wherein the plurality of matching windows form a signal envelope and wherein a match between the analogue signal and the template correspond to the analogue signal being inside said envelope.

16. The memory device of any of claims 14 and 15, wherein the output module comprises a signal combining or accumulator circuit for combining output signals from at least some of the plurality of memory devices to produce a combined signal representing a match and / or proportional to a degree of match between the analogue signal and the template.55650902-117. The memory device of any of claims 14 to 16, wherein the analogue signal comprises or is derived from a time varying signal and / or a bio-signal and / or a sensed signal representing a physical stimulus.

18. The memory device of any of claims 14 to 17, wherein the input module is configured to sample the analogue signal to produce a plurality of samples as input signals to the plurality of memory devices.

19. The memory device of any of claims 14 to 18, wherein the plurality of memory cell devices are arranged as an array.

20. The memory device of any of claims 14 to 19, wherein the stored template may be representative of a pre-determined state or classification of an input signal.

21. A sensing device comprising: a sensor configured to sense a physical stimulus and produce an analogue signal in response to sensing the physical stimulus and / or configured to receive a sensor signal representative or indicative of a physical stimulus; the sensing device further comprises a memory cell device of claims 1 to 13 or the memory device of any of claims 14 to 20.

22. The sensing device of claim 21, wherein the sensing device may comprise a networked wearable or implantable device.

23. A method of operating a memory cell device comprising: receiving, at each of a first and second inverter module, an input signal, wherein each inverter module comprises a tuneable load having a respective threshold voltage, wherein the threshold voltages define a matching window; receiving, at each of the first and second inverter modules, an input signal; outputting, by the inverter modules, an output signal in dependence on the voltage of the input signal and the threshold voltage of the inverter module, receiving output signals from the first and second tuneable inverter modules and outputting a match signal based on the output signals representing or at55650902-1least indicating that the input signal has a voltage in the matching window, wherein at least one of a) and b): a) the method comprises tuning the load of the tuneable load of each of the first and second inverter modules thereby to set the matching window; b) the method comprises coupling a high voltage to a match line, using a pull up or pull down circuit, for in response to the voltage of the input signal being in the matching window.55650902-1

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