Hybrid switch

Abstract

A hybrid switch (100) includes: an electrical switch LSI (101) for outputting an electrical signal inputted from one of a plurality of input ports to one of a plurality of output ports; O / E converters (111); E / O converters (112); an optical chip (201) for outputting an optical signal inputted from one of a plurality of input ports to one of a plurality of output ports; optical demultiplexers (301); and optical multiplexers (302). Signals obtained by inputting an optical signal to one of the plurality of optical demultiplexers (301) respectively pass through the electrical switch LSI (101) and the optical chip (201), and then are inputted to the same optical multiplexer (302).

Description

Hybrid Switch

[0001] The present invention relates to a hybrid switch, which is essential for data transfer in interconnects that support data centers and high-performance computing.

[0002] To support the massive data processing demands of artificial intelligence and machine learning, large-scale integration (SSI) interconnects are a key technology trend in data centers and high-performance computing (HPC). In Ethernet protocols, Layer 2 SSIs have been doubling in size every three years, enabling them to handle speeds of 25 Tbps and 50 Tbps. The evolution of these SSIs is determining the top-of-rack switches and network configurations in data centers. Similarly, for HPC, systems for AI learning are being built by connecting multiple GPUs (graphics processing units) via high-speed interconnects, as exemplified by NVIDIA's NVswitch. The evolution of NVswitch and the link technologies that use it is determining network configurations.

[0003] These electrical switch LSIs process input packets on a packet-by-packet basis, and based on the destination address contained in the packet, distribute the packet to another port so that it reaches its destination, and output it from the electrical switch LSI. For example, an electrical switch LSI 901 shown in Figure 30 has multiple input lane units 902, multiple output lane units 903, and a fabric circuit 904 that connects the input lane units 902 and the output lane units 903.

[0004] The input lane unit 902 includes a SerDes circuit (not shown) that converts an input signal 911 to the switch LSI 901 from a high-speed serial signal to a low-speed parallel signal, as well as a function to analyze packet headers to determine routing and buffers necessary for signal conversion and routing. Multiple input lane units 902 and an output lane unit 903 are connected to the fabric circuit 904. The fabric circuit 904 can distribute packets from any input port to an output port. For example, in the NVswitch described in Non-Patent Document 1, the fabric circuit 904 is composed of a crossbar circuit. The output lane unit 903 performs header processing so that packets passing through the fabric circuit 904 are forwarded to the appropriate address on the external network. Furthermore, the output lane unit 903 utilizes a buffer to perform bandwidth and transfer control according to the congestion status of the external network, and outputs an output signal 912 to the outside via a SerDes circuit (not shown) that converts a low-speed parallel signal to a high-speed serial signal.

[0005] Electrical switch LSIs have the advantage of being able to control destinations on a packet-by-packet basis, allowing for fine-grained data transfer processing. Input and output signals are transmitted at speeds of around 100 Gbps over distances of several meters or more. For this reason, electrical signals are converted into optical signals and transmitted through optical fibers for communication.

[0006] However, because electrical switch LSIs process packets at a time, they are protocol-dependent and require a specific network and switch LSI protocol, such as Ethernet (registered trademark), PCIe (Peripheral Component Interconnect Express), or a proprietary protocol. Different protocols require different electrical switch LSIs. While electrical switch LSIs can change destinations at a fine granularity, they require packet header processing even when transferring large amounts of data to a single destination, resulting in an increased latency of approximately 100 ns. Furthermore, because electrical switch LSIs perform electrical processing, their power consumption increases almost in proportion to the data transfer capacity, and the power consumption increases as the bandwidth increases. Currently, power consumption per LSI is several hundred watts, and in the future, it will exceed 1 kW, so the power limit is approaching. Furthermore, while communication within the network is carried out using optical fiber, the signal must be converted back to an electrical signal only when passing through the electrical switch LSI.

[0007] “NVIDIA NVSWITCH The World's Highest-Bandwidth On-Node Switch”, NVIDIA Technical Overview, 2018, <https: / / images.nvidia.com / content / pdf / nvswitch-technical-overview.pdf>

[0008] The present invention has been made to solve the above-mentioned problems, and aims to provide a hybrid switch that can reduce delay time compared to electrical packet processing and can send large amounts of data without increasing power consumption.

[0009] The hybrid switch of the present invention comprises an electrical switch LSI configured to receive an electrical signal input from one of a plurality of input ports and output the electrical signal to at least one of a plurality of output ports based on information in the electrical signal; a plurality of O / E converters configured to convert optical signals into electrical signals and input the electrical signals to the corresponding input ports of the electrical switch LSI; a plurality of E / O converters configured to convert electrical signals output from the corresponding output ports of the electrical switch LSI into optical signals; and an optical chip configured to output the optical signal input from one of the plurality of input ports to at least one of the plurality of output ports. and a plurality of optical demultiplexers configured to demultiplex an input optical signal and input it to an input port of a corresponding O / E converter among the plurality of O / E converters and a corresponding input port among the plurality of input ports of the optical chip; and a plurality of optical multiplexers configured to multiplex an optical signal output from a corresponding E / O converter among the plurality of E / O converters and an optical signal output from a corresponding output port among the plurality of output ports of the optical chip, wherein an optical signal input to one of the plurality of optical demultiplexers is input to the same optical multiplexer after passing through the electrical switch LSI and the optical chip, respectively.

[0010] According to the present invention, by using an optical chip in addition to an electrical switch LSI to bypass the electrical switch LSI, signals can be transmitted as is regardless of protocol, delay times can be reduced compared to electrical packet processing, and large amounts of data can be sent without increasing power consumption.This invention takes advantage of the high-granularity processing capabilities of the electrical switch LSI, while providing a bypass that passes large blocks of data through the optical switch as optical signals, thereby achieving protocol independence, reduced delay times and power consumption, and no conversion to electrical signals.

[0011] FIG. 1 is a block diagram showing the configuration of a hybrid switch according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a hybrid switch according to a second embodiment of the present invention. FIG. 3 is a diagram showing an example of electrical wiring connections in a hybrid switch according to the second embodiment of the present invention. FIG. 4 is a diagram showing another example of electrical wiring connections in a hybrid switch according to the second embodiment of the present invention. FIG. 5 is a block diagram showing another configuration of a hybrid switch according to the second embodiment of the present invention. FIG. 6 is a block diagram showing the configuration of a hybrid switch according to a third embodiment of the present invention. FIG. 7 is a block diagram showing the configuration of a hybrid switch according to a third embodiment of the present invention. FIGS. 8A to 8C are diagrams explaining the control procedure according to the third embodiment of the present invention. FIGS. 9A to 9C are diagrams explaining the control procedure according to the third embodiment of the present invention. FIGS. 10A to 10C are diagrams explaining the control procedure according to the third embodiment of the present invention. FIGS. 11A to 11C are diagrams explaining the control procedure according to the third embodiment of the present invention. FIGS. 12A to 12C are diagrams explaining the control procedure according to the third embodiment of the present invention. FIG. 13 is a diagram showing another flow of a control packet according to the third embodiment of the present invention. FIG. 14 is a diagram showing another flow of a control packet according to the third embodiment of the present invention. FIGS. 15A to 15C are diagrams explaining another control procedure according to the third embodiment of the present invention. FIGS. 16A to 16C are diagrams explaining another control procedure according to the third embodiment of the present invention. FIGS. 17A to 17C are diagrams explaining another control procedure according to the third embodiment of the present invention. FIGS. 18A to 18C are diagrams explaining another control procedure according to the third embodiment of the present invention. FIGS. 19A to 19C are diagrams explaining another control procedure according to the third embodiment of the present invention. FIG. 20 is a block diagram showing the configuration of a hybrid switch according to a fourth embodiment of the present invention. FIG. 21 is a block diagram showing another configuration of a hybrid switch according to the fourth embodiment of the present invention. FIG. 22 is a diagram showing the signal flow on a time axis in the second and third embodiments of the present invention. FIG. 23 is a diagram showing the signal flow on a time axis in the case of EEE. FIG. 24 is a block diagram showing the configuration of a hybrid switch according to a sixth embodiment of the present invention.Fig. 25 is a perspective view illustrating the structure of a hybrid switch according to a first embodiment of the present invention. Fig. 26 is a perspective view illustrating the structure of a hybrid switch according to a first embodiment of the present invention. Fig. 27 is a perspective view illustrating the structure of a hybrid switch according to a first embodiment of the present invention. Fig. 28 is a cross-sectional view of a hybrid switch according to a first embodiment of the present invention. Fig. 29 is a block diagram illustrating an example configuration of a computer that realizes the electric switch LSIs according to the first to sixth embodiments of the present invention. Fig. 30 is a block diagram illustrating the configuration of a conventional electric switch LSI.

[0012] [First embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. A hybrid switch 100 shown in Fig. 1 includes an electric switch LSI 101 and an optical chip 201. An input signal 401, which is an optical signal, is input to both the electric switch LSI 101 and the optical chip 201.

[0013] The electrical switch LSI 101 includes therein a plurality of input lane units 102, a plurality of output lane units 103, and a fabric circuit 104 that connects the input lane units 102 and the output lane units 103. The fabric circuit 104 is, for example, composed of a crossbar switch circuit, but may be realized with other configurations as long as it can connect any of the input lane units 102 and the output lane units 103. For example, the fabric circuit 104 may be configured as one large buffer, and the number of the target output lane unit 103 may be included in the header of a packet from any of the input lane units 102, and the destination of the packet may be determined based on the information in the packet header.

[0014] The input section of the input lane section 102 is provided with a plurality of O / E converters 111 that convert optical signals into electrical signals. The output section of the output lane section 103 is provided with a plurality of E / O converters 112 that convert electrical signals into optical signals. An optical demultiplexer 301 is provided in front of the O / E converters 111. Assume that an input signal 401 is input to the hybrid switch 100, for example, at port C shown in FIG. 1 . The optical signal input to port C is demultiplexed by the optical demultiplexer 301 into two directions, to the electrical switch LSI 101 and the optical chip 201. The demultiplexing ratio of the optical demultiplexer 301 may be set to 5:5. Furthermore, since the input to the electrical switch LSI 101 is converted into an electrical signal by the nearest O / E converter 111, the demultiplexing may be performed at a ratio of 9:1, so that the optical power to the optical chip 201 is 9 and the optical power to the electrical switch LSI 101 is 1.

[0015] The optical signal demultiplexed by the optical demultiplexer 301 reaches port Ce of the electrical switch LSI 101, where it is converted into an electrical signal by the O / E converter 111 and enters the input lane unit 102 of the electrical switch LSI 101. The input lane unit 102 has functions such as signal conversion, header processing, routing, and buffering. That is, the input lane unit 102 converts the input signal from a high-speed serial signal to a low-speed parallel signal, determines whether the input signal is a control signal or data by header analysis, and further acquires destination information.

[0016] Based on the header analysis result, the input lane unit 102 controls the fabric circuit 104 to transfer the signal to the appropriate output lane unit 103. Alternatively, the fabric circuit 104 may transfer the signal to the appropriate output lane unit 103 based on the result of the header analysis by the input lane unit 102.

[0017] 1, a signal input to port Ce is output to output lane unit 103 connected to port de. Output lane unit 103 performs header processing on the signal output from fabric circuit 104, taking into account routing in a network outside electrical switch LSI 101. E / O converter 112 converts the electrical signal output from output lane unit 103 into an optical signal.

[0018] When the number of packets is small, there is no problem, but when the number of packets increases, collisions between packets occur within the electrical switch LSI 101 and congestion occurs in the destination network. For this reason, buffers can be provided in the input lane unit 102 and the output lane unit 103 to perform network flow control and priority control according to the packet service level.

[0019] On the other hand, the optical signal input to the optical chip 201 will be described. The optical chip 201 has input ports Ao, Bo, Co, Do, ..., Mo and output ports ao, bo, co, do, ..., no. The input ports Ao, Bo, Co, Do, ..., Mo and the output ports ao, bo, co, do, ..., no are connected via an optical waveguide circuit. In this embodiment, the optical waveguide circuit is configured using only a passive optical circuit 210, without including an active circuit that operates in response to an external signal, such as a switch element.

[0020] The optical circuit 210 may be, for example, an optical branching circuit that splits a signal input from input port Co equally among output ports ao, bo, co, do, ..., no and broadcasts the split signal. Alternatively, an optical circuit 210 may be used in which the output port is uniquely determined according to the wavelength of the input signal 401, such as a circular arrayed-waveguide grating. When the output port is determined according to the wavelength of the input signal 401, for example, if the wavelength of the signal input from port Co is λ0, it is output from port co. If the wavelength of the signal input from port Co is λ1, it is output from port do, and if the wavelength is λ2, it is output from port eo. Furthermore, if the wavelength of the signal input from port Bo is λ1, it is output from port co. If the wavelength is λ2, it is output from port do, and if the wavelength is λ3, it is output from port eo. The example in FIG. 1 illustrates a state in which the wavelength of the input signal 401 is λ1, and the signal input from port Co is output from port do by the optical circuit 210.

[0021] The optical multiplexer 302 multiplexes the optical signal from the electrical switch LSI 101 and the optical signal from the optical chip 201. In the example of Fig. 1, an input signal 401 input to port C is output as an output signal 402 from port d.

[0022] Here, output signal 402 is a combination of optical signals output from electrical switch LSI 101 and optical chip 201, but a delay of about 100 ns occurs on the electrical switch LSI 101 side due to optical-electrical conversion, packet processing, etc. For example, in the case of a 100 Gbps NRZ (Non-Return-to-Zero) signal, a signal delayed by about 10,000 bits = 1,250 bytes compared to the output from optical chip 201 is output from electrical switch LSI 101.

[0023] Therefore, it is necessary to extract the bit string by performing signal processing on the side receiving the output signal 402. Although the signal from the electrical switch LSI 101 and the signal from the optical chip 201 overlap, they are originally the same signal and can be separated. In particular, in the case of NRZ, the optical power is simply modulated with a time shift by intensity modulation, so the signals can be separated using a DSP (Digital Signal Processor) that processes multipath in wireless communication. Alternatively, the time delay and intensity of the signal from the electrical switch LSI 101 can be learned in advance and set as parameters, and then the signals can be separated by inserting signal processing circuits before and after the ADC (Analog to Digital Converter).

[0024] Alternatively, the optical signal from E / O converter 112 may be made relatively small compared to the optical signal from optical chip 201, and an automatic gain adjustment circuit may be provided in the receiver. The receiver may treat the signal from electrical switch LSI 101 as noise when the signals overlap, and may increase the gain and treat the signal as a signal when the signals do not overlap, thereby appropriately extracting the signal from electrical switch LSI 101 and the signal from optical chip 201. By providing a receiver with such a signal separation function, the hybrid switch 100 can be used.

[0025] In Ethernet protocols, PCIe protocols, etc., a packet for acknowledging receipt must be sent from the receiving side to the transmitting side in order to establish a link for transmission and reception. This packet is a small packet for control purposes only, so it does not need to go through the optical chip 201. It can be sent through the electrical switch LSI 101 and returned via a route or port separate from that for data transmission.

[0026] An optical branching circuit was shown as an example of a circuit within an optical chip. When an optical signal is broadcast from the hybrid switch 100 and received by multiple receivers, a transmission / reception link is established when one main receiver replies that reception is complete. In this case, the other sub-receivers only receive the data sent unilaterally, and a reception link is not established, so they cannot reply to the transmitter. Therefore, it is necessary to appropriately configure the main receiver and sub-receivers, taking into account the communication application.

[0027] In this embodiment, the path of the optical chip 201 is specified by the transmission wavelength, and therefore the transmitter that sends a signal to the receiver via the hybrid switch 100 has the function of outputting multiple wavelengths. That is, the transmitter may be, for example, an optical transmitter that is equipped with a tunable wavelength light source or that has the function of selecting and modulating the wavelength of light of multiple wavelengths from multiple external light sources using an internal switch.

[0028] As described above, in this embodiment, a path in the optical chip 201 is defined by using a signal of a specific wavelength as the input signal 401, and the destination of the packet in the electrical switch LSI 101 is defined by providing destination information in the packetized signal 401. This allows the optical chip 201 and the electrical switch LSI to function independently. In this embodiment, the optical chip 201 can be configured using only passive circuits. In this embodiment, the use of the optical chip 201 allows signals to be transmitted as is regardless of the protocol, which reduces delay time compared to electrical packet processing, and enables the transmission of large amounts of data.

[0029] Second Embodiment The configuration of a hybrid switch 100a according to a second embodiment of the present invention is shown in Figure 2. The difference from the first embodiment is that the optical chip 201a includes an active optical circuit 212 consisting of a plurality of switch elements, and a control unit 105 is provided inside the electrical switch LSI 101a to control the optical circuit 212. The control unit 105 sets an optical path that passes through the optical circuit 212 via the electrical wiring 110.

[0030] In this embodiment, when normal small packets or the total communication volume is low, communication is performed only via the electrical switch LSI 101a, and the switch of the optical circuit 212 can be opened so that signals do not pass through the path of the optical chip 201a under control of the control unit 105. On the other hand, when a large amount of data designated to a specific destination flows, the control unit 105 can open the path of the optical chip 201a, which serves as a bypass, to pass signals, while internally discarding packets on the electrical switch LSI 101a side.

[0031] That is, the control unit 105 can select whether to pass a signal through either the electrical switch LSI 101a or the optical chip 201a, thereby allowing them to operate complementarily, so that only one of the signals from the electrical switch LSI 101a or the optical chip 201a is output from the optical multiplexer 302. Therefore, in this embodiment, it is not necessary to add circuits such as a DSP, an ADC, and a signal processing circuit to the receiver that receives the signal via the hybrid switch 100a, and the amount of processing by the receiver can be reduced.

[0032] For example, suppose that an input signal 401 is input to port C shown in FIG. 2 of the hybrid switch 100a. The optical signal input to port C is split by the optical splitter 301 into two directions, to the electrical switch LSI 101a and the optical chip 201a, and reaches port Ce of the electrical switch LSI 101a and port Co of the optical chip 201a. The control unit 105 controls the switch elements that make up the optical circuit 212 of the optical chip 201a. As a result, the optical signal input from port Co is guided to port do by the optical circuit 212. The optical signal from port do is output as output signal 402 from port d via the optical multiplexer 302.

[0033] On the other hand, the optical signal that reaches port Ce is converted into an electrical signal by the O / E converter 111 and input to the electrical switch LSI 101a. The control unit 105 discards the signal so that it is not transmitted to the output lane unit 103. As a result, no signal is output from the electrical switch LSI 101a toward port d. In this way, in this embodiment, it is possible to output a signal that has passed through only either the electrical switch LSI 101a or the optical chip 201a.

[0034] 3 shows a specific example of electrical wiring connections in this embodiment. Electrical wiring 115 is formed from each input lane unit 102 toward the control unit 105. The input lane unit 102 analyzes the packet header of the input signal to determine the packet type, destination information, the size of the data stored in the payload, and the like. If the input lane unit 102 determines from the header analysis that the packet is sending a large amount of data to a specific destination, it guides the packet to the control unit 105 instead of the fabric circuit 104. At this time, the input lane unit 102 adds the header analysis results (destination information and size information) to the packet.

[0035] The control unit 105 discards packets sent from the input lane unit 102 via the electrical wiring 115, and controls the switch elements of the optical circuit 212 so that the signal input to the optical chip 201a is output to the appropriate port of the optical chip 201a corresponding to its destination based on the header analysis results attached to the packet.

[0036] FIG. 4 shows another connection example of this embodiment. The input lane unit 102 analyzes the packet header in the same manner as in FIG. 3 . If the input lane unit 102 determines, as a result of header analysis, that the packet is a packet for sending a large amount of data to a specific destination, the input lane unit 102 guides the packet to an electrical output virtual port do′ provided in the control unit 105 so as to correspond to a port (e.g., de) of the electrical switch LSI 101a corresponding to the destination. Specifically, the input lane unit 102 rewrites the header as a result of header analysis so that the packet is forwarded to port do′. The input lane unit 102 also adds the header analysis results (destination information and size information) to the packet.

[0037] Fabric circuit 104 interprets the header of the packet from input lane unit 102 and sends the packet to electrical output virtual port do' set in control unit 105. Fabric circuit 104 and electrical output virtual ports ao', bo', co', do', ..., no' of control unit 105 are connected by electrical wiring 116. Control unit 105 discards the packet that has reached electrical output virtual port do', and controls the switch element of optical circuit 212 based on the header analysis result added to the packet so that the signal input to optical chip 201a is output to the appropriate port of optical chip 201a that corresponds to its destination.

[0038] The control unit 105 can grasp the packets that have arrived at all electrical output virtual ports ao', bo', co', do', ..., no', and can therefore arbitrate when there are conflicting requests, assign priorities, and make packets wait. For example, if a control packet indicating the flow of a large amount of data from port B to port d arrives immediately after a control packet indicating the flow of a large amount of data from port C to port d arrives, a conflict will occur because the output port d is the same. Therefore, the control unit 105 can connect port C, which is the initial request, and port d via the optical circuit 212 to allow data to flow, and make the data transfer from port B to port d wait.

[0039] As another example, suppose a large amount of data flows from port C to port d, while a large amount of data flows from port A to port a. In this case, there is no contention between the output ports d and a of the hybrid switch 100a. However, the optical circuit 212 cannot establish optical waveguide paths for both the signal from port C to port do and the signal from port Ao to port ao, and can only establish one of the paths (e.g., from port C to port do). When the control unit 105 recognizes this state, it establishes a path from port Co to port do using the optical circuit 212 to flow data from port C to port d, and maintains a state in which data is transferred through the electrical switch LSI 101a to flow data from port A to port a. In this way, by transferring one type of data via the optical chip 201a and the other type of data via the electrical switch LSI 101a, a total of more data can be transferred simultaneously.

[0040] Furthermore, since data can be transferred via optical chip 201a without photoelectric conversion, when a large amount of data has been transferred in a short time, control unit 105 can grasp the situation in which the transfer is completed and switch the data transfer from port A to port a to be via optical chip 201a. In this way, control unit 105 can have a state machine that changes the state over time while monitoring the state.

[0041] 4, compared to the case of Fig. 3, the configuration of Fig. 4 takes time because packets are processed by guiding them to the fabric circuit 104 instead of the input lane unit 102, but it is possible to perform arbitration and flow control according to the service level in situations where contention is likely to occur. However, in the example of Fig. 4, it is necessary to use a switch having a function capable of interpreting packet headers as the fabric circuit 104, rather than a crossbar switch circuit.

[0042] Fig. 5 shows another embodiment of the present invention. In addition to the configuration of Fig. 4, the configuration of Fig. 5 includes electrical wiring 117 from an external device 118, such as a PC (Personal Computer), to the control unit 105. This allows the hybrid switch 100a to be controlled externally, and even when there are multiple hybrid switches 100a, they can be operated in coordination with each other.

[0043] In this embodiment, by also using the switch function of the optical circuit 212, signals are transmitted as is regardless of the protocol, eliminating the need for electrical packet processing. This makes it possible to send large amounts of data bypassing the electrical switch LSI 101a without increasing delay time or power consumption. Furthermore, by providing the control unit 105 in the electrical switch LSI 101a and enabling control of the paths of the optical chip 201a, detailed settings such as arbitration and priority setting become possible.

[0044] 6 and 7 are diagrams showing a configuration in which a transceiver for transmitting and receiving signals and a processor are added to the hybrid switch 100a of FIG. 4. However, while in the configuration of FIG. 4 ports C and Ce are input ports and ports d and de are output ports, in this embodiment ports C and Ce are input ports for large amounts of data and ports d and de are output ports for large amounts of data. In this embodiment, a processor unit that performs processing such as a CPU (Central Processing Unit), GPU, or FPGA (Field-Programmable Gate Array) is called an XPU.

[0045] XPU 501-α performs electrical processing internally to input and output data. An optical transmitter 502 provided immediately adjacent to XPU 501-α converts the electrical signal from XPU 501-α into an optical signal using an E / O converter 504, and inputs the signal to input port C of the hybrid switch 100a. An optical receiver 503 provided immediately adjacent to XPU 501-α converts the optical signal output from output port M of the hybrid switch 100a into an electrical signal using an O / E converter 505, and inputs the electrical signal to XPU 501-α.

[0046] XPU 501-μ, which establishes a link opposite XPU 501-α, is connected to input port n and output port d of hybrid switch 100a. Specifically, optical transmitter 502, located immediately adjacent to XPU 501-μ, converts the electrical signal from XPU 501-μ into an optical signal using E / O converter 504 and inputs it to input port n of hybrid switch 100a. Optical receiver 503, located immediately adjacent to XPU 501-μ, converts the optical signal output from output port d of hybrid switch 100a into an electrical signal using O / E converter 505 and inputs it to XPU 501-μ.

[0047] Furthermore, XPU 501-β, which may compete with XPU 501-α, is connected to input port D and output port P (not shown) of hybrid switch 100a. Specifically, optical transmitter 502, located immediately adjacent to XPU 501-β, converts the electrical signal from XPU 501-β into an optical signal using E / O converter 504 and inputs it to input port D of hybrid switch 100a. Optical receiver 503, located immediately adjacent to XPU 501-β, converts the optical signal output from output port P of hybrid switch 100a into an electrical signal using O / E converter 505 and inputs it to XPU 501-β.

[0048] Let us consider a case where XPU 501-α issues a control signal (control packet) requesting the transmission of a large amount of data to XPU 501-μ, and then transmits the data. At this time, when XPU 501-α transmits the first control packet to input port C of hybrid switch 100a, the header of the control packet is analyzed within electrical switch LSI 101a by the operation described in the second embodiment, and the control packet is transferred to electrical output virtual port do' of control unit 105. Based on the header analysis result added to the control packet, control unit 105 controls the switch element of optical circuit 212 so that the optical signal input to port Co of optical chip 201a is guided to port do.

[0049] Next, XPU 501-α transmits a data packet to input port C of hybrid switch 100a. The data packet arrives at XPU 501-μ via optical circuit 212 and output port d of hybrid switch 100a. Upon arrival of the first data packet, XPU 501-μ returns a control packet to XPU 501-α indicating that reception has begun. This control packet is input to input port n of hybrid switch 100a. When the input lane unit 102 connected to port n determines through header analysis that it is a small-volume control packet, it rewrites the header so that the packet is forwarded to the output port (Me in this case) of the electrical switch LSI 101a that corresponds to the destination. The fabric circuit 104 interprets the header of the packet from input lane unit 102 and sends the control packet to the output lane unit 103 connected to output port Me. In this way, the control packet arrives at XPU 501-α.

[0050] When transmission of all data is completed, XPU 501-α transmits a control packet indicating that transmission is complete to XPU 501-μ. As in the previous operation, the control packet is transferred to the electrical output virtual port do' of the control unit 105. When the control unit 105 receives the control packet indicating that transmission is complete, it releases the path set up by the optical circuit 212.

[0051] Alternatively, when XPU 501-μ has received a large amount of data and completed the process, XPU 501-μ returns a control packet indicating completion of reception to XPU 501-α. This control packet is input to input port n of the hybrid switch 100a. When the input lane unit 102 connected to port n determines through header analysis that the packet is a small-volume control packet, it rewrites the header so that the packet is forwarded to the output port (here, Me) of the electrical switch LSI 101a corresponding to the destination. However, since the control packet indicates completion of reception, it rewrites the header so that the control packet is also forwarded to port do'. The fabric circuit 104 interprets the header of the packet from the input lane unit 102 and sends the control packet to the output lane unit 103 connected to output port Me, as well as to the electrical output virtual port do' of the control packet. When the control unit 105 receives the control packet indicating completion of reception, it releases the path established by the optical circuit 212.

[0052] Specific procedures for the above control are shown in Figures 8A to 12C. Figures 8A, 9A, 10A, 11A, and 12A show the contents of register 1053 of control unit 105, which stores packet type information (Control / Data) received by electrical switch LSI 101a, packet header analysis results by input lane unit 102, and packet routing information determined by control unit 105. Figures 8B, 9B, 10B, 11B, and 12B show the contents of FIFO (Fast-In Fast-Out) registers 1050 and 1051, which store decision information from control unit 105 based on the packet and header analysis results. Figures 8C, 9C, 10C, 11C, and 12C show the contents of path setting register 1052, which stores status information for optical circuit 212.

[0053] 8A, assume that a control packet stating "a large amount of data is sent from XPU 501-α to XPU 501-μ" is issued from XPU 501-α to XPU 501-μ. The packet header analysis results (destination information and size information) by the input lane unit 102 connected to input port Ce are added to the control packet and sent to electrical output virtual port do' of the control unit 105.

[0054] Based on the header analysis results added to the control packet that arrived at the electrical output virtual port do' and the XPU connection information previously grasped by the control unit 105, the control unit 105 recognizes that the path for sending data from XPU 501-α to XPU 501-μ is the path from port Ce to port De. Since a large amount of data is being sent, the control unit 105 determines to use the optical chip 201a. The control unit 105 also determines to subsequently replace port De with electrical output virtual port Do' and to transfer data from port Ce to port Do'. Furthermore, the control unit 105 determines to open a path from port Co to port Do using the optical circuit 212. The control unit 105 stores request information based on these decisions in the request register 1050, as shown in FIG. 8B. At this time, the optical circuit 212 opens a path from port Co to port Do, as shown in FIG. 8C.

[0055] 8A, the size information is "large data," but is not limited to this and may be a value indicating the size. The control unit 105 may determine that a large amount of data is to be sent when the size information is "large data" or the value indicating the size is equal to or greater than a threshold.

[0056] 9B, the control unit 105 holds the information in the request register 1050 unless information is entered into the completion register 1051. Therefore, the path from port Co to port do remains open. Here, XPU 501-μ may notify, by a receipt confirmation packet, that reception is possible via the path via the optical chip 201a.

[0057] Next, Figures 10A, 10B, and 10C show the state when a large amount of data flows from XPU 501-α to XPU 501-μ. The header of this packet is analyzed by the input lane unit 102 connected to port Ce. However, since the packet type is a data packet, the request register is not rewritten. The data packet input to port Ce is guided to the electrical output virtual port do' and discarded by the control unit 105. At this time, the output lane unit 103 connected to port de of the electrical switch LSI 101a is unused, so the control unit 105 may put this output lane unit 103 into a sleep state to reduce power consumption. Meanwhile, port C and port d are connected via the optical chip 201a, and data is transmitted from XPU 501-α to XPU 501-μ.

[0058] When all data transmission is complete, XPU 501-α transmits a control packet to XPU 501-μ indicating that "data transmission from XPU 501-α to XPU 501-μ is complete," as shown in FIG. 11A. Based on the header analysis results added to the control packet that arrived at electrical output virtual port do', the XPU connection information previously known by the control unit 105, and the current setting status, the control unit 105 recognizes that the path for sending packets from XPU 501-α to XPU 501-μ is the path from port Ce to port do'. Furthermore, since data transmission is complete, the control unit 105 determines to end the conversion from port de to electrical output virtual port do' and to close the path from port Co to port do. The control unit 105 stores these decisions in the completion register 1051, as shown in FIG. 11B.

[0059] A rule is set in the control unit 105 that the information held in the completion register 1051 takes priority over the information held in the request register 1050. In other words, the path setting of the optical circuit 212 is overwritten by the information (oldest information) stored in the lowest area of ​​the completion register 1051, and the information stored in the lowest area of ​​the request register 1050 is deleted. Therefore, the optical circuit 212 enters a state in which the path from port Co to port do is closed, as shown in FIG. 12C. The control unit 105 deletes the information in the request register 1050, as shown in FIG. 12B, and also deletes the information in the completion register 1051 that was the basis for determining this deletion.

[0060] In this way, the control unit 105 is equipped with a register 1053 that holds packet type information, packet header analysis results, and packet routing information, a request register 1050 that holds request information corresponding to a control packet requesting data transmission, a completion register 1051 that holds decision information corresponding to a control packet indicating completion of data transmission or completion of data reception, and a path setting register 1052 that holds status information of the optical circuit 212, thereby making it possible to perform path switching and establish transmission and reception links between XPUs.

[0061] Note that, instead of a control packet indicating that "data transmission from XPU 501-α to XPU 501-μ is complete," XPU 501-μ may return a control packet indicating that "data reception from XPU 501-α to XPU 501-μ is complete" to XPU 501-α, thereby deleting the information in request register 1050. The flow of control packets in this case is shown in Figures 13 and 14, and Figures 15A, 15B, and 15C are diagrams replacing Figures 11A, 11B, and 11C.

[0062] 13 and 14, the control packet is guided from port n through the electrical switch LSI 101a to port M. As a result of header analysis of the control packet and routing information, as shown in FIG. 15A, information is obtained that the route for sending the packet is from port ne to port Me, and information that data transfer from port ne to electrical output virtual port do' has been completed.

[0063] Based on the header analysis results added to the control packet that arrived at electrical output virtual port do', the XPU connection information previously grasped by the control unit 105, and the current setting status, the control unit 105 recognizes that the path for sending packets from XPU 501-μ to XPU 501-α is the path from port ne to port do'. Furthermore, the control unit 105 recognizes that the path for sending data from XPU 501-α to XPU 501-μ is the path from port Ce to port do'. Since data reception from XPU 501-α to XPU 501-μ has been completed, the control unit 105 determines to end the conversion from port de to electrical output virtual port do' and to close the path from port Co to port do. The control unit 105 stores this determination information in the completion register 1051 as shown in FIG. 15B. As a result, the information in the request register 1050 is deleted in the same manner as above, and the state transitions to the states shown in FIGS. 12A, 12B, and 12C.

[0064] Cases in which contention occurs are shown in Figures 16A to 19C. Let us assume that a control packet stating "XPU 501-α sends a large amount of data to XPU 501-μ" is issued from XPU 501-α to XPU 501-μ. Furthermore, let us assume that immediately after this, a control packet stating "XPU 501-β sends a large amount of data to XPU 501-μ" is issued from XPU 501-β to XPU 501-μ. Figure 16A shows the state in which the packet type information, the packet header analysis results by the input lane unit 102 connected to input ports Ce and De, and the packet routing information are stored in register 1053 of the control unit 105.

[0065] Based on the header analysis results added to the control packet that arrived at the electrical output virtual port do' and the XPU connection information previously grasped by the control unit 105, the control unit 105 recognizes that the path for sending data from XPU 501-α to XPU 501-μ is the path from port Ce to port De. Since a large amount of data is being sent, the control unit 105 determines to use the optical chip 201a. The control unit 105 also determines to replace port De with electrical output virtual port Do' and to transfer data from port Ce to port Do'. Furthermore, the control unit 105 determines to set (OPEN) a path from port Co to port Do using the optical circuit 212. The control unit 105 stores request information based on these decisions in the request register 1050, as shown in FIG. 16B.

[0066] Based on the header analysis results added to the control packet that next arrived at electrical output virtual port do' and the XPU connection information previously grasped by the control unit 105, the control unit 105 recognizes that the route for sending data from XPU 501-β to XPU 501-μ is the route from port De to port De. Since a large amount of data is to be sent, the control unit 105 determines to use the optical chip 201a. The control unit 105 also determines to replace port De with electrical output virtual port Do' and to transfer data from port De to port Do'. Furthermore, the control unit 105 determines to set a path from port Do to port Do using the optical circuit 212. The control unit 105 stores request information based on these decisions in the request register 1050.

[0067] Because request register 1050 is a FIFO register, the information stored first (information about data transmission from XPU 501-α to XPU 501-μ) is stored in the bottommost area of ​​request register 1050 shown in Figure 16B. The next information (information about data transmission from XPU 501-β to XPU 501-μ) is stored in the second-to-bottom area of ​​request register 1050 shown in Figure 16B.

[0068] Here, there is a conflict between a request to set a path from port Co to port do by the optical circuit 212 and a request to set a path from port Do to port do by the optical circuit 212. The control unit 105 has a rule that the information stored in the lowest area of ​​the request register 1050 (oldest information) takes priority. Therefore, the control unit 105 sets a path from port Co to port do by the optical circuit 212, as shown in FIG. 16C .

[0069] 17A, 17B, and 17C show the state when a large amount of data flows from XPU 501-α to XPU 501-μ. The header of the packet at this time is analyzed by the input lane unit 102 connected to port Ce. However, since the packet type is a data packet, the request register is not rewritten. The data packet input to port Ce is guided to the electrical output virtual port do' and discarded by the control unit 105. Meanwhile, port C and port d are connected via the optical chip 201a, so that data is transmitted from XPU 501-α to XPU 501-μ.

[0070] When XPU 501-μ has completed receiving all the data, it returns a control packet to XPU 501-α stating that "data reception from XPU 501-α to XPU 501-μ is complete." In this case, the header analysis results and routing information of the control packet include information that the path for sending the packet is from port ne to port Me, and information that data transfer from port ne to electrical output virtual port do' has been completed, as shown in FIG.

[0071] Based on the header analysis results added to the control packet that arrived at electrical output virtual port do', the XPU connection information previously grasped by the control unit 105, and the current setting status, the control unit 105 recognizes that the path for sending packets from XPU 501-μ to XPU 501-α is the path from port ne to port do'. Furthermore, the control unit 105 recognizes that the path for sending data from XPU 501-α to XPU 501-μ is the path from port Ce to port do'. Since data reception from XPU 501-α to XPU 501-μ has been completed, the control unit 105 determines to end the conversion from port de to electrical output virtual port do' and to close the path from port Co to port do. The control unit 105 stores these determinations in the completion register 1051 as shown in FIG. 18B.

[0072] As shown in FIG. 18C , the optical circuit 212 is in a state where the path from port Co to port do is closed. The control unit 105 deletes the information stored in the bottommost area (oldest information) of the information in the request register 1050, and also deletes the information in the completion register 1051 that was the basis for determining this deletion. As a result of this deletion, the information stored in the second-lowest area of ​​the request register 1050 is replaced with the information stored in the bottommost area. Therefore, the control unit 105 sets a path from port Do to port do using the optical circuit 212.

[0073] 19A, 19B, and 19C show the state when a large amount of data flows from XPU 501-β to XPU 501-μ. The header of the packet at this time is analyzed by the input lane unit 102 connected to port De. However, since the packet type is a data packet, the request register is not rewritten. The data packet input to port De is guided to the electrical output virtual port do' and discarded by the control unit 105. Meanwhile, port D and port d are connected via the optical chip 201a, so that data is transmitted from XPU 501-β to XPU 501-μ.

[0074] As described above, this embodiment can perform arbitration and priority control when requests conflict. Also, this embodiment can put some of the output lane units 103 of the electrical switch LSI 101a to sleep, allowing more data to bypass the electrical switch LSI 101a and flow through the optical chip 201a.

[0075] In this embodiment, by using the optical chip 201a equipped with a switch function, signals can be transmitted as is regardless of the protocol, and electrical packet processing is unnecessary, so large amounts of data can be sent bypassing the electrical switch LSI 101a without increasing delay time or power consumption. Furthermore, in this embodiment, by providing the control unit 105, paths for the optical chip 201a can be set according to control packets input to the electrical switch LSI 101a, and when communication is congested, control can be performed such as delaying data transmission or using an existing path on the electrical switch LSI 101a side.

[0076] 20 shows the configuration of a hybrid switch 100b according to a fourth embodiment of the present invention. The difference from the third embodiment is that a photodetector 130 is provided to detect light output from output ports ao, bo, co, do, ..., Mo of an optical chip 201b. Furthermore, electrical wiring 135 is provided from the photodetector 130 to a control unit 105b of an electrical switch LSI 101b.

[0077] With this configuration, the control unit 105b can determine whether the path of the optical circuit 212 that it has switched is set appropriately from the detection result of the photodetector 130. In the configuration shown in Figure 4, in order to confirm whether a path is set in the optical circuit 212, the receiving XPU opposite the transmitting XPU had to send a reception completion packet. However, if the XPU is located far from the electrical switch LSI 101a, a latency of about 5 ns per meter is added, and an additional latency of about several tens of ns is added due to packet processing inside the electrical switch LSI 101a.

[0078] On the other hand, in this embodiment, it is not necessary to analyze the contents of the packet to confirm whether the path of the optical circuit 212 is properly set, but it is sufficient to determine whether the optical signal has arrived by checking the presence or absence of optical power. For example, when a path from port Co to port do is set by the optical circuit 212, if the photodetector 130 connected to port do detects light, the control unit 105b can determine that the path has been properly set. Since the output of the photodetector 130 is directly input to the control unit 105b, high-speed processing is possible. This is more effective when the path switching frequency is high.

[0079] Another example of the hybrid switch of this embodiment is shown in Fig. 21. The difference from the configuration shown in Fig. 20 is that in addition to the photodetector 130, a photodetector 131 is provided that detects light input to the input ports Ao, Bo, Co, Do, ..., no of the optical chip 201c.

[0080] For example, when a path from port Co to port Do is set by the optical circuit 212, the control unit 105c of the electrical switch LSI 101c can determine that the path is set appropriately if light is detected by the photodetector 131 connected to port Co and also by the photodetector 130 connected to port Do. In this way, the path setting state of the optical chip 201c can be detected at a physical signal level at high speed and with low power consumption.

[0081] [Fifth Embodiment] Figure 22 is a diagram showing the signal flow on the time axis in the second and third embodiments. Figure 22(a) shows the signal flowing through the electrical switch LSI 101a, and Figure 22(b) shows the signal flowing through the optical chip 201a. After the control packet P0, data packets P1, P2, P3, and P4 are consecutively arranged.

[0082] Here, based on the header processing analysis of control packet P0, the control unit 105 performs processing to open the bypass on the optical chip 201a side. However, as shown in FIG. 22, it takes a switching time for the bypass to open. During this switching time, data packets begin to flow on the electrical switch LSI 101a side. If data packet P2 is in the middle of being processed when the path on the optical chip 201a opens, data packets P3 and onward will flow on the optical chip 201a side. The electrical switch LSI 101a has a latency of about 100 ns. Therefore, when the path on the optical chip 201a side opens, the data flowing on the optical chip 201a side will be earlier in time.

[0083] In this way, the data path can be switched from the electrical switch LSI 101a side to the optical chip 201a side. However, there is a possibility that the data packet P2 will be fragmented during the switching. The portion of the data packet P2 that reaches the receiver is the signal output from the electrical switch LSI 101a combined with the signal output from the optical chip 201a, and as explained in the first embodiment, signal processing can be performed on the receiver side. Alternatively, the data packet P2 may be stored in a buffer of the electrical switch LSI 101a during the switching, and only the data packet P2 may be retransmitted from the electrical switch LSI 101a after the data transfer is completed.

[0084] The example in Figure 22 assumes a case where, once a link is established, data continues to be sent regardless of whether information is available, as in the case of an Ethernet protocol. On the other hand, functions such as entering a sleep state midway through a link are also being added to reduce power consumption. Examples include IEEE 802.3az (EEE: Energy Efficient Ethernet) and the L0s and L1 states of the PCIe protocol. In such cases, signal processing, such as that in the example in Figure 22, can be reduced by switching the switch to an idle state in which no signal is being output.

[0085] FIG. 23 is a diagram showing the signal flow on a time axis in the case of EEE. (a) in FIG. 23 shows the signal flowing through the electrical switch LSI 101a, and (b) in FIG. 23 shows the signal flowing through the optical chip 201a. In EEE LPI (Low Power Idle) mode, the device starts up in the following sequence: an IDLE signal, followed by Sleep, multiple Refreshes, an Alert, and a Wake. When a data path switching request is received from the electrical switch LSI 101a to the optical chip 201a, the control unit 105 switches the path at the point after Sleep. This allows the path to be switched without interrupting data packets. As described above, this embodiment can control the path switching while taking into account the difference in latency between the electrical switch LSI 101a and the optical chip 201a, which has the advantage of allowing information to be transferred without omission when the path is switched.

[0086] [Sixth Example] In the first to fifth examples, the optical chips 201 and 201a form a one-to-one link, but as shown in Figure 24, the optical chip 201d of the hybrid switch 100d may output the same signal to multiple ports. The example in Figure 24 shows a case where the optical circuit 212d adds a signal from port Co to port do and outputs it to port bo. In this way, the optical circuit 212d may be used, or a splitter circuit such as a broadcast circuit may be used. Furthermore, the electrical switch LSIs 101, 101a, and 101b may output signals to multiple ports.

[0087] 25, 26, and 27 are perspective views illustrating the structure of the hybrid switch 100 of the first embodiment, and Fig. 28 is a cross-sectional view of the hybrid switch 100. The hybrid switch 100 includes an optical chip 201, an electric switch LSI 101, an O / E converter 111, and an E / O converter 112.

[0088] 25 to 27 show the manufacturing procedure for the hybrid switch 100. The electric switch LSI 101 is flip-chip mounted on a package substrate 807 with the front surface facing downwards and electrically connected. Similarly, the O / E converter 111 and the E / O converter 112 are also mounted on the package substrate 807. The O / E converter 111 and the electric switch LSI 101, and the E / O converter 112 and the electric switch LSI 101 are connected by electrical wiring, respectively. The electric switch LSI 101 has through-silicon vias 822 and pads 812 on its back surface.

[0089] The optical chip 201 is provided with a plurality of waveguides 810, waveguide switches 811 (switch elements), pads 812 of the waveguide switches 811, etc. As shown in Fig. 26 , the optical chip 201 is mounted on the electrical switch LSI 101 with its surface facing downward so that the pads 812 of the optical chip 201 are connected to the through silicon vias 822 of the electrical switch LSI 101. By connecting the pads 812 of the waveguide switches 811 to the through silicon vias 822, the optical chip 201 can be controlled from a control unit inside the electrical switch LSI 101.

[0090] 27, the fiber array 805 is connected to optical waveguides 810 (ports Ao, Bo, Co, Do, ..., Mo, ports ao, bo, co, do, ..., no) that reach the chip end face, the O / E converter 111, and the E / O converter 112. The fiber array 805 is provided with a plurality of fiber coupler type optical demultiplexers 301 and optical multiplexers 302.

[0091] FIG. 28 shows a structure in which a heat spreader 808 is mounted on an optical chip 201. A pad 812 of the optical chip 201 and a through-silicon via 822 of the electrical switch LSI 101 are connected by a connection bump 813, such as a copper pillar. The through-silicon via 822 and the connection bump 813 form electrical wiring connecting the optical chip 201 and the control unit 105. Similarly, a connection bump 824 connects the wiring of the package substrate 807 and the electrical switch LSI 101. The connection bumps 813 and 824 are protected by an underfill material 830. This structure reduces the distance between the control unit of the electrical switch LSI 101 and the optical circuit of the optical chip 201 to a few millimeters or less, thereby providing the advantage of extremely small communication delays. While FIGS. 25 to 28 illustrate the first embodiment, the hybrid switches of the second to sixth embodiments can also be fabricated using a similar structure.

[0092] As described above, this embodiment has the effect of shortening the time required for the control unit of the electrical switch LSI to set up a path in an optical circuit.

[0093] At least a part of the input lane unit 102, output lane unit 103, and control units 105, 105b, and 105c described in the first to sixth embodiments can be realized by a computer equipped with a CPU (Central Processing Unit), a storage device, and an interface, and a program that controls these hardware resources. An example configuration of this computer is shown in FIG. 29.

[0094] The computer includes a CPU 600, a storage device 601, and an interface device (I / F) 602. The I / F 602 is connected to the hardware unit of the input lane unit 102, the hardware unit of the output lane unit 103, and the hardware units of the control units 105, 105b, and 105c. In such a computer, a program for implementing the method of the present invention is stored in the storage device 601. The CPU 600 executes the processes described in the first to sixth embodiments in accordance with the program stored in the storage device 601.

[0095] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes.

[0096] (Supplementary Note 1) A hybrid switch of the present invention comprises an electric switch LSI configured to receive an electric signal input from one of a plurality of input ports and output the electric signal to at least one of a plurality of output ports based on information of the electric signal; a plurality of O / E converters configured to convert an optical signal into an electric signal and input the electric signal to a corresponding input port of the electric switch LSI; a plurality of E / O converters configured to convert an electric signal output from a corresponding output port of the electric switch LSI into an optical signal; and a plurality of E / O converters configured to output the optical signal input from one of the plurality of input ports to at least one of a plurality of output ports. the optical chip configured to receive the optical signal from the optical switch LSI and the optical chip, a plurality of optical demultiplexers configured to demultiplex an input optical signal and input the demultiplexed signal to an input port of a corresponding O / E converter among the plurality of O / E converters and a corresponding input port among the plurality of input ports of the optical chip, and a plurality of optical multiplexers configured to multiplex an optical signal output from a corresponding E / O converter among the plurality of E / O converters and an optical signal output from a corresponding output port among the plurality of output ports of the optical chip, and the optical signal input to one of the plurality of optical demultiplexers is input to the same optical multiplexer after passing through the electrical switch LSI and the optical chip, respectively.

[0097] (Supplementary Note 2) In the hybrid switch described in Supplementary Note 1, the optical chip includes an optical circuit configured to determine a path to be guided depending on the wavelength of an optical signal input to the input port, and an output port of the optical chip is uniquely identified depending on the wavelength of the optical signal.

[0098] (Supplementary Note 3) In the hybrid switch according to Supplementary Note 2, the optical circuit is a cyclic arrayed-waveguide grating.

[0099] (Supplementary Note 4) A hybrid switch of the present invention includes an electrical switch LSI configured to output an electrical signal input from one of a plurality of input ports to at least one of a plurality of output ports based on information of the electrical signal; a plurality of O / E converters configured to convert optical signals into electrical signals and input them to corresponding input ports of the electrical switch LSI; a plurality of E / O converters configured to convert electrical signals output from corresponding output ports of the electrical switch LSI into optical signals; an optical chip configured to output the optical signal input from one of the plurality of input ports to at least one of a plurality of output ports; and a plurality of O / E converters configured to split the input optical signal and split it into an input port of a corresponding one of the plurality of O / E converters and a plurality of input ports of the optical chip. and a plurality of optical multiplexers configured to multiplex an optical signal output from a corresponding one of the plurality of E / O converters with an optical signal output from a corresponding one of the plurality of output ports of the optical chip, wherein the optical chip comprises an optical circuit including a plurality of switch elements, the electrical switch LSI is connected to the switch elements via first electrical wiring, and comprises a control unit configured to control the switch elements based on information of the electrical signal to set a path along which the optical signal is guided in the optical chip, and an optical signal input to one of the plurality of optical demultiplexers is input to the same optical multiplexer after passing through the electrical switch LSI and the optical chip.

[0100] (Appendix 5) In the hybrid switch described in Appendix 4, after setting the path of the optical chip, the control unit discards the electrical signal input to the input port of the electrical switch LSI without outputting it to the output port of the electrical switch LSI, and the optical signal input to one of the plurality of optical demultiplexers is output only from the optical chip.

[0101] (Supplementary Note 6) In the hybrid switch described in Supplementary Note 4 or 5, the electrical switch LSI includes a plurality of input lane units, each of whose input ports is connected to the output of a corresponding one of the plurality of O / E converters, a plurality of output lane units, each of whose output ports is connected to the input of a corresponding one of the plurality of E / O converters, a fabric circuit connecting the plurality of input lane units and the plurality of output lane units, the control unit, and second electrical wiring connecting the plurality of input lane units and the control unit, and each of the plurality of input lane units has at least the function of analyzing a packetized electrical signal and extracting destination information, and transmits the packetized electrical signal and the destination information to the control unit via the second electrical wiring.

[0102] (Supplementary Note 7) In the hybrid switch according to Supplementary Note 4 or 5, the electrical switch LSI comprises: a plurality of input lane units, each having an input port connected to an output of a corresponding one of the plurality of O / E converters; a plurality of output lane units, each having an output port connected to an input of a corresponding one of the plurality of E / O converters; a fabric circuit configured to output an electrical signal input from one of the plurality of input lane units to at least one of the plurality of output lane units based on information of the electrical signal; the control unit; and second electrical wiring connecting the plurality of input lane units and the control unit, Each unit has at least the function of analyzing the packetized electrical signal to extract destination information and size information of the subsequent packet, and the function of rewriting information of the packetized electrical signal based on the destination information and the size information so that the packetized electrical signal, the destination information, and the size information are sent from the fabric circuit to the control unit, and the control unit controls the switch element based on the destination information and the size information to set a path along which the optical signal is guided in the optical chip, and performs arbitration control and priority control in accordance with predetermined rules when multiple optical signals are input simultaneously to the multiple optical demultiplexers.

[0103] (Supplementary Note 8) In the hybrid switch described in Supplementary Note 4, the electrical switch LSI, the plurality of O / E converters, and the plurality of E / O converters are mounted on the same substrate and are electrically connected to each other by wiring on the substrate, the optical chip is mounted on the electrical switch LSI, switch elements of the optical chip are electrically connected to a control unit of the electrical switch LSI via the first electrical wiring formed in the electrical switch LSI, and input ports of the plurality of O / E converters and the plurality of optical demultiplexers, output ports of the plurality of E / O converters and the plurality of optical multiplexers, input ports of the optical chip and the plurality of optical demultiplexers, and output ports of the optical chip and the plurality of optical multiplexers are respectively connected by optical fibers.

[0104] 100, 100a, 100b, 100c, 100d... hybrid switch, 101, 101a, 101b... electrical switch LSI, 102... input lane section, 103... output lane section, 104... fabric circuit, 105, 105b, 105c... control section, 111, 505... O / E converter, 112, 504... E / O converter, 118... external device, 130, 131... photodetector, 201, 201a, 201b, 201c... optical chip, 210, 212, 212d... optical circuit, 301... optical splitter, 302... optical multiplexer, 501-α, 501-β, 501-μ... XPU, 502... optical transmitter, 503... optical receiver, 1050 to 1053... register.

Claims

1. An optical communication system comprising: an electrical switch LSI configured to output an electrical signal input from one of a plurality of input ports to at least one of a plurality of output ports based on information in the electrical signal; a plurality of O / E converters configured to convert optical signals into electrical signals and input them to corresponding input ports of the electrical switch LSI; a plurality of E / O converters configured to convert electrical signals output from corresponding output ports of the electrical switch LSI into optical signals; an optical chip configured to output an optical signal input from one of a plurality of input ports to at least one of a plurality of output ports; a plurality of optical demultiplexers configured to demultiplex the input optical signal and input it to an input port of a corresponding O / E converter among the plurality of O / E converters and a corresponding input port among the plurality of input ports of the optical chip; and a plurality of optical multiplexers configured to multiplex an optical signal output from a corresponding E / O converter among the plurality of E / O converters and an optical signal output from a corresponding output port among the plurality of output ports of the optical chip, A hybrid switch characterized in that an optical signal input to one of the plurality of optical demultiplexers is input to the same optical multiplexer after passing through the electrical switch LSI and the optical chip, respectively.

2. A hybrid switch according to claim 1, wherein the optical chip comprises an optical circuit configured so that the path to be guided is determined according to the wavelength of the optical signal input to the input port, and the output port of the optical chip is uniquely identified according to the wavelength of the optical signal.

3. A hybrid switch according to claim 2, wherein the optical circuit is a cyclic arrayed waveguide grating.

4. An electrical switch LSI configured to output an electrical signal input from one of a plurality of input ports to at least one of a plurality of output ports based on information of the electrical signal; a plurality of O / E converters configured to convert optical signals into electrical signals and input them to corresponding input ports of the electrical switch LSI; a plurality of E / O converters configured to convert electrical signals output from corresponding output ports of the electrical switch LSI into optical signals; an optical chip configured to output an optical signal input from one of a plurality of input ports to at least one of a plurality of output ports; a plurality of optical demultiplexers configured to demultiplex an input optical signal and input it to an input port of a corresponding O / E converter among the plurality of O / E converters and a corresponding input port among a plurality of input ports of the optical chip; and a plurality of optical multiplexers configured to multiplex an optical signal output from a corresponding E / O converter among the plurality of E / O converters and an optical signal output from a corresponding output port among a plurality of output ports of the optical chip, wherein the optical chip comprises an optical circuit including a plurality of switch elements, the electrical switch LSI is connected to the switch element via a first electrical wiring and includes a control unit configured to control the switch element based on information of the electrical signal to set a path along which the optical signal is guided in the optical chip, and an optical signal input to one of the plurality of optical demultiplexers is input to the same optical multiplexer after passing through the electrical switch LSI and the optical chip, respectively.

5. A hybrid switch according to claim 4, wherein, after setting the path of the optical chip, the control unit discards the electrical signal input to the input port of the electrical switch LSI without outputting it to the output port of the electrical switch LSI, and an optical signal input to one of the plurality of optical demultiplexers is output only from the optical chip.

6. A hybrid switch according to claim 4 or 5, wherein the electrical switch LSI comprises: a plurality of input lane sections, each of whose input ports is connected to the output of a corresponding one of the plurality of O / E converters; a plurality of output lane sections, each of whose output ports is connected to the input of a corresponding one of the plurality of E / O converters; a fabric circuit connecting the plurality of input lane sections and the plurality of output lane sections; the control section; and second electrical wiring connecting the plurality of input lane sections and the control section, wherein each of the plurality of input lane sections has at least the function of analyzing a packetized electrical signal and extracting destination information, and transmits the packetized electrical signal and the destination information to the control section via the second electrical wiring.

7. A hybrid switch according to claim 4 or 5, wherein the electrical switch LSI comprises: a plurality of input lane sections whose input ports are connected to outputs of corresponding O / E converters among the plurality of O / E converters; a plurality of output lane sections whose output ports are connected to inputs of corresponding E / O converters among the plurality of E / O converters; a fabric circuit configured to output an electrical signal input from one of the plurality of input lane sections to at least one of the plurality of output lane sections based on information of the electrical signal; the control section; and second electrical wiring connecting the plurality of input lane sections and the control section, wherein each of the plurality of input lane sections has at least the function of analyzing a packetized electrical signal to extract destination information and size information of a subsequent packet, and the function of rewriting information of the packetized electrical signal based on the destination information and the size information so that the packetized electrical signal, the destination information, and the size information are sent from the fabric circuit to the control section, The control unit controls the switch element based on the destination information and the size information to set a path along which the optical signal is guided in the optical chip, and performs arbitration control and priority control in accordance with predetermined rules when multiple optical signals are input to the multiple optical demultiplexers simultaneously.

8. A hybrid switch according to claim 4, wherein the electrical switch LSI, the plurality of O / E converters and the plurality of E / O converters are mounted on the same substrate and are electrically connected to one another by wiring on the substrate, the optical chip is mounted on the electrical switch LSI and the switch elements of the optical chip are electrically connected to a control unit of the electrical switch LSI via the first electrical wiring formed on the electrical switch LSI, and the input ports of the plurality of O / E converters and the plurality of optical demultiplexers, the output ports of the plurality of E / O converters and the plurality of optical multiplexers, the plurality of input ports of the optical chip and the plurality of optical demultiplexers, and the plurality of output ports of the optical chip and the plurality of optical multiplexers are each connected by optical fibers.

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