Plasma processing device and etching method

Abstract

This plasma processing device comprises a chamber, a substrate support unit, a gas supply unit, a first high-frequency power supply, a voltage pulse source, a second high-frequency power supply, and a control unit. The substrate support unit is disposed inside the chamber and supports a substrate. The control unit is configured to control so that, when etching the substrate, a processing gas is supplied from the gas supply unit into the chamber, first high-frequency power is supplied from the first high-frequency power supply to turn the processing gas in the chamber into plasma, voltage pulses are supplied from the voltage pulse source to the substrate support unit, and second high-frequency power is supplied, superimposed on the voltage pulses, from the second high-frequency power supply.

Description

Plasma processing apparatus and etching method

[0001] The present disclosure relates to a plasma processing apparatus and an etching method.

[0002] The following Patent Document 1 describes a first RF generating unit including: a chamber; a first matching circuit coupled to the chamber; a second matching circuit coupled to the chamber; a first RF generating unit coupled to the first matching circuit and configured to generate a first RF pulse signal including a plurality of pulse cycles, each of the plurality of pulse cycles including a first period, a second period, and a third period, the first RF pulse signal having a first power level in the first period, a second power level in the second period, and a third power level in the third period, the first period being 30 μs or less; and a second RF generating unit coupled to the second matching circuit and configured to generate a second RF pulse signal including the plurality of pulse cycles, a second RF generating unit, wherein a frequency of the RF pulse signal is lower than a frequency of the first RF pulse signal, and the second RF pulse signal has a fourth power level in the first period and a fifth power level in at least one of the second period and the third period; and a third RF generating unit, coupled to the second matching circuit and configured to generate a third RF pulse signal including the plurality of pulse cycles, wherein the frequency of the third RF pulse signal is lower than a frequency of the second RF pulse signal, and the third RF pulse signal has a sixth power level in the second period and a seventh power level in at least one of the first period and the third period.

[0003] Japanese Patent Application Laid-Open No. 2022-048032

[0004] The present disclosure provides techniques to reduce residue.

[0005] A plasma processing apparatus according to one aspect of the present disclosure includes a chamber, a substrate support, a gas supply, a first high frequency power supply, a voltage pulse source, a second high frequency power supply, and a controller. The substrate support is disposed within the chamber and supports a substrate. The gas supply is configured to supply a process gas into the chamber. The first high frequency power supply is configured to supply a first high frequency power that converts the process gas in the chamber into plasma. The voltage pulse source is configured to supply a voltage pulse obtained by pulsating a DC voltage to the substrate support. The second high frequency power supply is configured to supply a second high frequency power to the substrate support. The controller is configured to control the gas supply to supply the process gas into the chamber from the gas supply, the first high frequency power to convert the process gas in the chamber into plasma, and the voltage pulse source to supply a voltage pulse to the substrate support and the second high frequency power to be superimposed on the voltage pulse to the substrate support.

[0006] According to the present disclosure, residue can be reduced.

[0007] FIG. 1 is a diagram for explaining an example of the configuration of an inductively coupled plasma processing apparatus. FIG. 2A is a diagram showing an example of etching a substrate W according to the first embodiment. FIG. 2B is a diagram showing an example of etching a substrate W according to the first embodiment. FIG. 3A is a diagram showing an example of etching a substrate W according to the first embodiment. FIG. 3B is a diagram showing an example of etching a substrate W according to the first embodiment. FIG. 4A is a diagram showing an example of changes in the potential of a substrate W in the etching method of the first reference example. FIG. 4B is a diagram schematically showing the movement of ions and radicals in plasma in the etching method of the first reference example. FIG. 4C is a diagram showing an example of an energy distribution of ions in the etching method of the first reference example. FIG. 5A is a diagram showing an example of changes in the potential of a substrate W in the etching method of the second reference example. FIG. 5B is a diagram schematically showing the movement of ions and radicals in plasma in the etching method of the second reference example. FIG. 5C is a diagram showing an example of an energy distribution of ions in the etching method of the second reference example. FIG. 6 is a diagram showing an example of residue remaining on an etched substrate according to the first embodiment. FIG. 7A is a diagram showing an example of a change in the potential of the substrate W in the etching method of the first embodiment. FIG. 7B is a diagram showing an example of an energy distribution of ions in the etching method of the first embodiment. FIG. 8A is a diagram explaining the process conditions of the etching method of the first reference example in the first verification. FIG. 8B is a diagram explaining the process conditions of the etching method of the first embodiment in the first verification. FIG. 9A is a diagram explaining the process conditions of the etching method of the first embodiment in the second verification. FIG. 9B is a diagram explaining the process conditions of the etching method of the first embodiment in the second verification. FIG. 10A is a diagram explaining the process conditions of the etching method of the first embodiment in the third verification. FIG. 10B is a diagram explaining the process conditions of the etching method of the first embodiment in the third verification. FIG. 11 is a flowchart showing an example of a process sequence of the etching process according to the first embodiment. FIG. 12A is a diagram showing an example of a change in the potential of the substrate W in the etching method of the second embodiment. FIG. 12B is a diagram showing an example of an energy distribution of ions in the etching method of the second embodiment. FIG. 13A is a diagram illustrating a change in the potential of the substrate W when the amplitude of the bias DC signal is changed.FIG. 13B is a diagram illustrating a change in ion energy distribution when the amplitude of the bias DC signal is changed. FIG. 14A is a diagram illustrating a change in the potential of the substrate W when the on-period of the bias DC signal is changed. FIG. 14B is a diagram illustrating a change in ion energy distribution when the on-period of the bias DC signal is changed. FIG. 15A is a diagram illustrating a change in the potential of the substrate W when the amplitude of the bias RF signal is changed. FIG. 15B is a diagram illustrating a change in ion energy distribution when the amplitude of the bias RF signal is changed. FIG. 16A is a diagram illustrating a change in the potential of the substrate W when the off-period of the bias DC signal is changed. FIG. 16B is a diagram illustrating a change in ion energy distribution when the off-period of the bias DC signal is changed. FIG. 17 is a diagram illustrating a change in the potential of the substrate W when the superimposition period for superimposing the bias RF signal is changed. FIG. 18 is a diagram illustrating a change in the potential of the substrate W when the superimposition period for superimposing the bias RF signal is changed.

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the plasma processing apparatus and etching method disclosed herein will be described in detail below with reference to the accompanying drawings. However, the plasma processing apparatus and etching method disclosed herein are not limited to the preferred embodiments.

[0009] In a plasma processing apparatus, a substrate is placed on a substrate support member provided in a chamber, and plasma is generated in the chamber to perform plasma processing such as etching. High vertical processing performance is required in the manufacture of semiconductor devices. Therefore, a known plasma processing apparatus employs an etching method in which a pulsed square-wave DC voltage is applied to a substrate support member to etch the substrate. By applying a square-wave DC voltage to the substrate support member during etching of the substrate, the verticality of ions can be improved, resulting in high vertical processing performance.

[0010] However, the improvement of ion verticality may result in residues remaining at the corners of the etched bottom. Therefore, a technique to reduce the residues is desired.

[0011] First Embodiment [Device Configuration] An example of a plasma processing apparatus according to the present disclosure will be described. In the embodiment described below, a plasma processing apparatus according to the present disclosure will be described as an example of a plasma processing system having a system configuration.

[0012] An example of the configuration of a plasma processing system will be described below: Fig. 1 is a diagram illustrating an example of the configuration of an inductively coupled plasma processing apparatus.

[0013] The plasma processing system includes an inductively coupled plasma processing apparatus 1 and a control unit 2. The inductively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. The plasma processing chamber 10 corresponds to the chamber of the present disclosure. The plasma processing chamber 10 includes a dielectric window. The plasma processing apparatus 1 also includes a substrate support 11, a gas inlet, and an antenna 14. The substrate support 11 is disposed within the plasma processing chamber 10. The antenna 14 is disposed on or above the plasma processing chamber 10 (i.e., on or above the dielectric window 101). The plasma processing chamber 10 has a plasma processing space 10s defined by the dielectric window 101, a sidewall 102 of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space 10s and at least one gas exhaust port for exhausting gas from the plasma processing space 10s. The plasma processing chamber 10 is grounded.

[0014] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.

[0015] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a bias electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, at least one RF / DC electrode coupled to an RF (Radio Frequency) power supply 31 and / or a DC (Direct Current) power supply 32 (described later) may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode functions as a bias electrode. Note that the conductive member of the base 1110 and the at least one RF / DC electrode may function as multiple bias electrodes. Alternatively, the electrostatic electrode 1111b may function as a bias electrode. Therefore, the substrate support 11 includes at least one bias electrode.

[0016] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0017] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 111a.

[0018] The gas inlet is configured to introduce at least one process gas from the gas supply unit 20 into the plasma processing space 10s. In one embodiment, the gas inlet includes a center gas injector (CGI) 13. The center gas injector 13 is disposed above the substrate support 11 and attached to a central opening formed in the dielectric window 101. The center gas injector 13 has at least one gas supply port 13a, at least one gas flow path 13b, and at least one gas inlet port 13c. The process gas supplied to the gas supply port 13a passes through the gas flow path 13b and is introduced into the plasma processing space 10s from the gas inlet port 13c. Note that the gas inlet may include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 102 in addition to or instead of the center gas injector 13.

[0019] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the gas inlet through a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include one or more flow modulation devices to modulate or pulse the flow rate of the at least one process gas.

[0020] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one bias electrode and the antenna 14. This causes a plasma to be formed from at least one process gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of a plasma generating unit configured to generate a plasma from one or more process gases in the plasma processing chamber 10. Furthermore, by supplying a bias RF signal to the at least one bias electrode, a bias potential is generated on the substrate W, thereby attracting ions in the formed plasma to the substrate W.

[0021] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to the antenna 14 and configured to generate a source RF signal (source RF power) for plasma generation via at least one impedance matching circuit. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to the antenna 14. The first RF generating unit 31a corresponds to the first high frequency power supply of the present disclosure. Furthermore, the source RF signal corresponds to the first high frequency power of the present disclosure.

[0022] The second RF generating unit 31b is coupled to at least one bias electrode via at least one impedance matching circuit and is configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal preferably has a frequency in the range of 1 MHz to 100 MHz, more preferably a frequency in the range of 13 MHz to 60 MHz. In one embodiment, the second RF generating unit 31b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one bias electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed. The second RF generating unit 31b corresponds to the second high frequency power source of the present disclosure. The bias RF signal corresponds to the second high frequency power of the present disclosure.

[0023] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a bias DC generator 32a. In one embodiment, the bias DC generator 32a is connected to at least one bias electrode and configured to generate a bias DC signal. The generated bias DC signal is applied to the at least one bias electrode.

[0024] In various embodiments, the bias DC signal may be pulsed, in which a sequence of voltage pulses is applied to at least one bias electrode, and the voltage pulses may have a pulse waveform that is rectangular, trapezoidal, triangular, or a combination thereof.

[0025] The bias DC generator 32a is configured to supply a bias DC signal obtained by pulsing a DC voltage. For example, the bias DC generator 32a is configured to supply a bias DC signal obtained by periodically turning on and off a negative DC voltage. In one embodiment, the bias DC generator 32a is configured to apply a negative DC voltage. The bias DC generator 32a applies a voltage pulse of a predetermined frequency to the bias electrode of the base 1110 as a bias DC signal by turning on and off the DC voltage at a predetermined cycle. The frequency of the bias DC signal is preferably within a range of 100 kHz to 1200 kHz, and more preferably within a range of 400 Hz to 800 Hz. The bias DC generator 32a is configured to change the duty ratio of the bias DC signal by changing the ratio of the on and off periods within one cycle. The bias DC generator 32a corresponds to the voltage pulse source of the present disclosure. The bias DC signal corresponds to the voltage pulse of the present disclosure.

[0026] The antenna 14 includes one or more coils. In one embodiment, the antenna 14 may include an outer coil and an inner coil arranged coaxially. In this case, the RF power supply 31 may be connected to both the outer coil and the inner coil, or to either the outer coil or the inner coil. In the former case, the same RF generator may be connected to both the outer coil and the inner coil, or separate RF generators may be connected to the outer coil and the inner coil separately.

[0027] During plasma processing, the plasma processing apparatus 1 supplies a source RF signal for plasma generation from the first RF generating unit 31a to the antenna 14. During plasma processing, the plasma processing apparatus 1 also supplies a pulsed bias DC signal from the bias DC generating unit 32a to the lower electrode of the base 1110. During plasma processing, the plasma processing apparatus 1 also supplies a bias RF signal from the second RF generating unit 31b superimposed on the bias DC signal.

[0028] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0029] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. This program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read-only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0030] [Plasma Processing Flow] Next, a flow of performing plasma processing such as plasma etching on a substrate W using the plasma processing system according to the embodiment will be briefly described. The substrate W is loaded into the plasma processing chamber 10 via a loading / unloading port (not shown) by a transfer mechanism such as a transfer arm, and placed on the central region 111a of the substrate support 11. The exhaust system 40 evacuates the inside of the plasma processing chamber 10 to a predetermined vacuum level.

[0031] When etching the substrate W, the control unit 2 controls the gas supply unit 20 to supply a processing gas from the gas supply unit 20 into the plasma processing chamber 10. For example, the memory unit 2a2 stores a recipe for plasma processing of the substrate. The recipe stores the gas species and flow rates used in etching. For example, the control unit 2 reads the recipe from the memory unit 2a2 and supplies gas of the gas species registered in the recipe from the gas supply unit 20 into the plasma processing chamber 10 at the registered flow rates.

[0032] The controller 2 controls the first RF generator 31a to supply a source RF signal from the first RF generator 31a to generate plasma from the process gas in the plasma processing chamber 10. For example, the power of the source RF signal is registered in a recipe. The controller 2 supplies the source RF signal from the first RF generator 31a to the antenna 14 at the power registered in the recipe to generate a magnetic force in the plasma processing chamber 10, which generates inductively coupled plasma by generating plasma from the process gas in the plasma processing chamber 10.

[0033] The control unit 2 controls the bias DC generation unit 32a to supply a bias DC signal from the bias DC generation unit 32a to the substrate support unit 11. The control unit 2 controls the bias DC generation unit 32a to control the duty ratio of the bias DC signal. For example, the control unit 2 preferably controls the duty ratio of the bias DC signal to 10% to 80%, and more preferably controls the duty ratio to 10% to 20%. For example, the duty ratio of the bias DC signal is registered in a recipe. The control unit 2 reads the recipe from the storage unit 2a2 and supplies a bias DC signal from the bias DC generation unit 32a having the duty ratio registered in the recipe.

[0034] The control unit 2 controls the second RF generation unit 31b to supply a bias RF signal from the second RF generation unit 31b to the substrate support unit 11 by superimposing the bias RF signal on the bias DC signal. For example, the power of the bias RF signal is registered in a recipe. For example, the control unit 2 reads the recipe from the storage unit 2a2 and supplies the bias RF signal from the second RF generation unit 31b at the power registered in the recipe.

[0035] Here, an example of etching of the substrate W according to the first embodiment will be described. Figures 2A, 2B, 3A, and 3B are views showing an example of etching of the substrate W according to the first embodiment. Figure 2A shows the planar shape of the substrate W before etching as viewed from above. Figure 2B shows the cross-sectional shape of the substrate W before etching, taken along dashed line L1 in Figure 2A. Figure 3A shows the planar shape of the substrate W after etching, taken along dashed line L1 in Figure 3A. Figure 3B shows the cross-sectional shape of the substrate W after etching, taken along dashed line L1 in Figure 3A.

[0036] A base layer 50 is formed on the substrate W before etching, and a fin structure 51 having multiple fins 51a is formed on the base layer 50. A gate material 52 is deposited on the fin structure 51 on the substrate W before etching, and a mask 53 is formed on the gate material 52. Because the fin structure 51 is buried in the gate material 52, it is not shown in FIGS. 2A and 2B . The base layer 50 is a stop layer that suppresses etching of underlying layers and is formed of an oxide (Ox) film, such as a silicon oxide film. The base layer 50 may be SiN, an organic film, or a metal film such as a tungsten film. The fin structure 51 is formed by covering the surface of a silicon layer with an oxide, for example. The multiple fins 51a of the fin structure 51 are formed in parallel in one direction. The gate material 52 is formed of, for example, polycrystalline silicon (polysilicon). The mask 53 is formed by, for example, stacking an oxide layer 53b (Ox) on a SiN layer 53a. The mask 53 is formed with gaps provided in parallel in a direction intersecting one direction.

[0037] 3A and 3B show a substrate W in which the gate material 52 has been etched using a mask 53 until the underlying layer 50 is reached. Examples of pressure conditions and process gases for etching the substrate W are shown below. In the following values, 1 sccm corresponds to approximately 1.69×10 -3 pa・m 3 / s, and 1 mTorr is approximately 0.133 Pa.

[0038] Pressure conditions: Pressure in plasma processing chamber 10: 50 to 100 mTorr. Processing gases: Cl2 gas: 100 to 210 sccm, HBr gas: 70 to 150 sccm, O2 gas: 30 to 60 sccm, Ar gas: 50 to 300 sccm.

[0039] 3A and 3B , as a result of the etching, gate portions 52 a of the gate material 52 remain directly below the mask 53, and the remaining gate portions 52 a function as gates. In the substrate W, each rectangular portion 55 surrounded by the mask 53 and the fin 51 a reaches the underlayer 50.

[0040] Next, an etching method as a reference example will be described, focusing on the differences from the etching method of the first embodiment.

[0041] First, an etching method according to a first reference example will be described. Conventionally, etching methods have been known in which a substrate W is etched by applying high-frequency power as a bias to the substrate support 11. For example, in the etching method according to the first reference example, when etching the substrate W, a source RF signal is supplied from the first RF generator 31a to convert the processing gas in the plasma processing chamber 10 into plasma. Furthermore, in the etching method according to the first reference example, a bias RF signal is supplied from the second RF generator 31b to the lower electrode of the base 1110, without supplying a bias DC signal from the bias DC generator 32a.

[0042] 4A is a diagram showing an example of a change in the potential of the substrate W in the etching method of Reference Example 1. When a bias RF signal, which is high-frequency power, is supplied to the lower electrode of the base 1110, the potential of the substrate W changes sinusoidally in accordance with the fluctuation of the bias RF signal.

[0043] 4B is a diagram schematically illustrating the movement of ions and radicals in plasma in the etching method of the first reference example. In FIG. 4B, the side of the object to be etched, such as the substrate W, is shown as the etch front. The ions and radicals in the plasma are attracted to the substrate W by the potential of the substrate W, etching the substrate W. In the etching method of the first reference example, the potential of the substrate W changes in a sinusoidal manner, scattering the ions and radicals, and the angle of incidence of the ions and radicals incident on the substrate W becomes wider. Furthermore, in the etching method of the first reference example, the energy distribution of the ions and radicals incident on the substrate W becomes wider.

[0044] 4C is a diagram showing an example of ion energy distribution in the etching method of the first reference example. FIG. 4C shows an example of the results of determining the ion energy distribution function (IEDF) of the etching method of the first reference example. The horizontal axis indicates ion energy [eV], with the energy increasing toward the right. The vertical axis indicates the number of ions, with the number of ions increasing toward the top. FIG. 4C also shows the minimum ion energy required for etching the gate material 52 as a threshold E ｔｈ The threshold E ｔｈ is, for example, 25 eV.

[0045] In the etching method of the first reference example, the ion energy distribution is set to a threshold E ｔｈ For the above reasons, although the gate material 52 can be etched, a peak occurs on the low energy side of the energy distribution, and the energy width over which the peak occurs is wide. In the etching method of the first reference example, the energy distribution of ions incident on the substrate W is broad.

[0046] 2A, 2B, 3A, and 3B is etched by the etching method of the first reference example, the sidewall of the gate portion 52 a is also etched, and the roughness of the sidewall of the gate portion 52 a is deteriorated.

[0047] Next, an etching method according to a second reference example will be described. High vertical processing performance is required in the manufacture of semiconductor devices. Accordingly, an etching method is known in which a pulsed square-wave DC voltage is applied to the substrate support 11 to etch the substrate. For example, in the etching method according to the second reference example, when etching the substrate W, a source RF signal is supplied from the first RF generator 31a to generate plasma from the processing gas in the plasma processing chamber 10. Furthermore, in the etching method according to the second reference example, a bias DC signal, which is a pulsed negative DC voltage, is supplied from the bias DC generator 32a to the lower electrode of the base 1110, without supplying a bias RF signal from the second RF generator 31b.

[0048] 5A is a diagram showing an example of a change in the potential of the substrate W in the etching method of Reference Example 2. A bias DC signal, which is a pulsed negative DC voltage, is supplied to the lower electrode of the base 1110, and the potential of the substrate W changes in a rectangular shape in accordance with the fluctuation of the bias DC signal.

[0049] 5B is a diagram schematically illustrating the movement of ions and radicals in plasma in the etching method of the second reference example. In FIG. 5B, the side of the object to be etched, such as the substrate W, is shown as the etch front. The ions and radicals in the plasma are attracted to the substrate W by the potential of the substrate W, etching the substrate W. In the etching method of the second reference example, the potential of the substrate W changes in a rectangular shape, thereby improving the perpendicularity of the ions and radicals incident on the substrate W. Furthermore, in the etching method of the second reference example, the energy distribution of the ions and radicals incident on the substrate W is narrow, resulting in a high energy peak.

[0050] 5C is a diagram showing an example of ion energy distribution in the etching method of the second reference example. FIG. 5C is a diagram showing a schematic ion energy distribution function (IEDF) in the etching method of the second reference example. The horizontal axis indicates ion energy [eV], with the energy increasing toward the right. The vertical axis indicates the number of ions, with the number of ions increasing toward the top. FIG. 5C also shows the threshold E of ion energy required for etching the gate material 52. ｔｈ This shows:

[0051] In the etching method of the second reference example, peaks occur on the high energy side and the low energy side. ｔｈ or less, it does not contribute to etching of the gate material 52. On the high-energy side, the peak is high and the energy width at which the peak occurs is narrow. That is, the etching method of the second reference example results in an energy distribution in which the peak on the high-energy side is acute. This improves the perpendicularity of the ions and radicals incident on the substrate W.

[0052] The etching method of the second reference example can obtain high vertical processing performance due to the high verticality of ions and radicals. For example, when the substrate W shown in Figures 2A, 2B, 3A, and 3B is etched by the etching method of the second reference example, the gate portion 52a can be etched into a vertical shape while suppressing roughness of the sidewall of the gate portion 52a.

[0053] However, in the etching method of the second reference example, due to the improved vertical processing performance of ions, residues of the gate material 52 may remain in the corners of the etched bottom. Fig. 6 is a diagram showing an example of residues remaining on the etched substrate W according to the first embodiment. Fig. 6 shows the planar shape of the substrate W after etching, as viewed from above. Residues 56 remain in each rectangular portion 55 on the etched substrate W.

[0054] Therefore, in the etching method of the first embodiment, when etching the substrate W, the bias DC signal obtained by pulsating a negative DC voltage is supplied from the bias DC generating unit 32a to the lower electrode of the base 1110. Furthermore, in the etching method of the first embodiment, the second RF generating unit 31b supplies a bias RF signal superimposed on the bias DC signal.

[0055] 7A is a diagram showing an example of a change in the potential of the substrate W in the etching method of the first embodiment. A bias DC signal, which is a pulsed negative DC voltage, and a bias RF signal are superimposed and supplied to the lower electrode of the base 1110, so that the potential of the substrate W changes in a rectangular shape in accordance with the fluctuation of the bias DC signal and oscillates in accordance with the bias RF signal.

[0056] 7B is a diagram showing an example of ion energy distribution in the etching method of the first embodiment. FIG. 7B is a diagram showing a schematic ion energy distribution function (IEDF) in the etching method of the first embodiment. The horizontal axis indicates ion energy [eV], with the energy increasing toward the right. The vertical axis indicates the number of ions, with the number of ions increasing toward the top. FIG. 7B also shows the threshold E of ion energy required for etching the gate material 52. ｔｈ This shows:

[0057] In the etching method of the first embodiment, peaks occur on both the high energy side and the low energy side, and the energy width at which the peaks occur is wide. In the etching method of the first embodiment, high vertical processing performance can be obtained by generating a peak on the high energy side. In addition, in the etching method of the first embodiment, the threshold E ｔｈ As a result, a peak is generated over a wide width, so that the incident angle of ions incident on the substrate W can be widened, and the residues 56 can be removed efficiently.

[0058] Next, an example of the verification result obtained by actually etching the substrate W and verifying the amount of residue 56 will be described.

[0059] In the verification, a substrate W was etched using the etching method of the first embodiment and the etching method of the first reference example. The etching method of the first embodiment was divided into two steps, a residue removal step 1 and a residue removal step 2, and the residue removal step 2 was performed in this order after the residue removal step 1. The common conditions for the source RF signal, bias RF signal, and bias DC signal in the residue removal step 1 and the residue removal step 2 during the verification were as follows:

[0060] (Common conditions for the etching method of the first embodiment) Conditions for residue removal step 1 Source RF signal: frequency 27 MHz, power 300 W Bias RF signal: frequency 13 MHz, power 400 W Bias DC signal: frequency 400 kHz, -500 V, duty ratio 0 to 80% Conditions for residue removal step 2 Source RF signal: frequency 27 MHz, power 500 W Bias RF signal: frequency 13 MHz, power 270 W Bias DC signal: frequency 400 kHz, -500 V, duty ratio 0 to 80%

[0061] The duty ratio of the bias DC signal is the ratio of the on period in one cycle of turning on and off −500 V. In the etching method of the first embodiment, the residue removal step 2 is performed after the residue removal step 1, and the duty ratio of the bias DC signal is changed between the residue removal step 1 and the residue removal step 2.

[0062] First, the results of the first verification will be described. In the first verification, the substrate W was etched using the etching method of the first reference example and the etching method of the first embodiment, and the amounts of residues 56 on the substrate W were compared.

[0063] In the first verification, the source RF signal and bias RF signal of the etching method of the first reference example were set as follows.

[0064] (Conditions for the etching method of the first reference example) Source RF signal: frequency 27 MHz, power 500 W Bias RF signal: frequency 13 MHz, power 270 W

[0065] In the first verification, the duty ratios of the bias DC signals in the residue removal step 1 and the residue removal step 2 of the etching method of the first embodiment were set as follows:

[0066] (Conditions of the etching method of the first embodiment) Conditions for residue removal step 1: bias DC signal: not applied (duty ratio 0%) Conditions for residue removal step 2: bias DC signal: frequency 400 kHz, −500 V, duty ratio 80%

[0067] FIG. 8A is a diagram illustrating the process conditions of the etching method of the first reference example during the first verification. To facilitate comparison with the process conditions of the etching method of the first embodiment shown in FIG. 8B , FIG. 8A shows the source RF signal, bias RF signal, and bias DC signal conditions of the etching method of the first reference example, divided into residue removal step 1 and residue removal step 2. In FIG. 8A , the period during which the source RF signal and bias RF signal are supplied during one cycle of 400 kHz during etching is shown with a diagonal line pattern, corresponding to one cycle of the bias DC signal with a frequency of 400 kHz. In the etching method of the first reference example, the source RF signal and bias RF signal are continuously supplied during etching. Therefore, the source RF signal and bias RF signal are shown as being always on during one cycle of 400 kHz with a diagonal line pattern. The source RF signal and bias RF signal are supplied as continuous waves (CW). On the other hand, in the etching method of the first reference example, since no bias DC signal is applied in residue removal step 1 and residue removal step 2, the diagonal line pattern is not shown during one cycle of 400 kHz, and is always shown as off.

[0068] FIG. 8B is a diagram illustrating the processing conditions of the etching method of the first embodiment during the first verification. FIG. 8A shows the conditions of the source RF signal, bias RF signal, and bias DC signal of the etching method of the first embodiment during the first verification, divided into residue removal step 1 and residue removal step 2. In FIG. 8B, the conditions of the source RF signal, bias RF signal, and bias DC signal in residue removal step 1 are the same as those in the first reference example. In residue removal step 1, the bias DC signal is not applied, and the source RF signal and bias RF signal are supplied. In residue removal step 2, the source RF signal, bias RF signal, and bias DC signal are supplied during etching. In residue removal step 2, the bias DC signal is supplied at 400 kHz with a duty cycle of 80%. In FIG. 8B, the bias RF signal in residue removal step 2 is shown as being on for 80% of one cycle of 400 kHz, as indicated by the hatched pattern.

[0069] In the first verification, the amount of residue 56 on the substrate W in the etching method of the first reference example was 1.61 [nm], and the amount of residue 56 on the substrate W in the etching method of the first embodiment was 1.45 [nm]. This shows that the etching method of the first embodiment can reduce the amount of residue 56 more than the etching method of the first reference example.

[0070] Next, the results of the second verification will be described. In the second verification, in the etching method of the first embodiment, the residue removal step 1 was performed under the same conditions as in the first reference example, and the duty ratios of the bias DC signal in the residue removal step 2 were set to 80% and 10%, respectively, to etch the substrate W, and the amounts of residue 56 on the substrate W were compared.

[0071] 9A and 9B are diagrams illustrating the processing conditions of the etching method of the first embodiment during the second verification. Each of these diagrams shows the periods during which the source RF signal, bias RF signal, and bias DC signal are supplied for each period of one cycle of 400 kHz during etching, divided into residue removal step 1 and residue removal step 2. In the second verification, in residue removal step 2, the duty ratio of the bias DC signal during etching was set to 80% ( FIG. 9A ) and 10% ( FIG. 9B ), respectively. The conditions for residue removal step 1 were the same as those in the first reference example.

[0072] In the second verification, the amount of residue 56 on the substrate W was 2.21 [nm] when the duty ratio was 80% ( FIG. 9A ), and the amount of residue 56 on the substrate W was 1.67 [nm] when the duty ratio was 10% ( FIG. 9B ). This shows that in the etching method of the first embodiment, the amount of residue 56 can be reduced by lowering the duty ratio of the bias DC signal. Note that the reason why the amount of residue 56 differs between the first and second verifications when the duty ratio is 80% is because the configuration of the substrate W is slightly different between the first and second verifications.

[0073] Next, the results of the third verification will be described. In the third verification, in the etching method of the first embodiment, the duty ratio of the bias DC signal in the residue removal step 2 was set to 10%, and in the residue removal step 1, the bias DC signal was not applied and the duty ratio was set to 20%, and etching of the substrate W was performed, and the amounts of residue 56 were compared.

[0074] 10A and 10B are diagrams illustrating the processing conditions of the etching method of the first embodiment during the third verification. Each of these diagrams shows the periods during which the source RF signal, bias RF signal, and bias DC signal are supplied for each period of one 400 kHz cycle during etching, divided into residue removal step 1 and residue removal step 2. In the third verification, the bias DC signal was set to not be applied during etching ( FIG. 10A ) and to 20% ( FIG. 10B ). The duty ratio of the residue removal step 2 was set to 10% in both cases.

[0075] In the third verification, in residue removal step 1, the amount of residue 56 on the substrate W was 1.67 [nm] when no bias DC signal was applied during etching ( FIG. 10A ), and the amount of residue 56 on the substrate W was 1.1 [nm] when the duty ratio was set to 20% ( FIG. 10B ). From this, it can be seen that in the etching method of the first embodiment, the amount of residue 56 can be reduced by applying a bias DC signal even in residue removal step 1.

[0076] In the above-described verification, the etching method of the first embodiment was divided into two steps, residue removal step 1 and residue removal step 2, and the substrate W was etched by performing residue removal step 2 after residue removal step 1. However, the etching method of the first embodiment is not limited to this. The etching method of the first embodiment may be divided into three or more steps. Furthermore, the etching method of the first embodiment may not be divided into steps, and the substrate W may be etched by maintaining a constant duty ratio of the bias DC signal during etching. The substrate W may be etched using only the steps of the etching method of the first embodiment, or may be etched by combining the etching method of the first embodiment with another etching method.

[0077] [Flowchart] The flow of an etching process including the etching method of the present disclosure will be described. Fig. 11 is a flowchart showing an example of a processing sequence of the etching process according to the first embodiment. The etching process of Fig. 11 is performed when etching of the substrate W is started.

[0078] The controller 2 controls the gas supply unit 20 to start supplying the process gas from the gas supply unit 20 and supply the process gas into the plasma processing chamber 10 (step S10). The controller 2 controls the first RF generator 31a to start supplying a source RF signal from the first RF generator 31a and convert the process gas in the plasma processing chamber 10 into plasma (step S11). The controller 2 controls the bias DC generator 32a to start supplying a bias DC signal from the bias DC generator 32a and supply the bias DC signal to the substrate support unit 11 (step S12). The controller 2 controls the second RF generator 31b to start supplying a bias RF signal from the second RF generator 31b and supply the bias RF signal to the substrate support unit 11 by superimposing it on the bias DC signal (step S13). Note that the order of steps S11 to S13 may be reversed. Furthermore, some or all of steps S11 to S13 may be executed as a single step.

[0079] The control unit 2 determines whether etching has ended (step S14). For example, the control unit 2 determines that etching has ended when a predetermined condition for ending etching is met. If etching has not ended (step S14: No), the control unit 2 returns to step S14. If etching has ended (step S14: Yes), the control unit 2 controls the supply of the process gas, the supply of the source RF signal, the supply of the bias DC signal, and the supply of the bias RF signal to stop, and ends the process.

[0080] As a result, the etching process according to the first embodiment can achieve high vertical processing performance. Also, the etching method according to the first embodiment can reduce the residues 56.

[0081] The etching process shown in FIG. 11 is an example and is not limited thereto. The etching process may include other steps. Furthermore, the etching process may be performed as part of another process. For example, when etching the substrate W down to the stop layer by sequentially performing multiple processes, the etching process shown in FIG. 11 may be performed as an etching process that reaches the stop layer of the substrate W. For example, when etching the substrate W shown in FIGS. 2A, 2B, 3A, and 3B, the control unit 2 may control the etching process shown in FIG. 11 to be performed when etching the bottom of the rectangular portion 55 that has reached the base layer 50.

[0082] Second Embodiment Next, a second embodiment will be described. The configuration of the plasma processing system according to the second embodiment is similar to the configuration of the plasma processing system according to the first embodiment shown in FIG. 1, and therefore, description thereof will be omitted.

[0083] The bias DC generating unit 32a supplies a bias DC signal that is pulsed by periodically turning on and off a negative polarity DC voltage.

[0084] The second RF generating unit 31b does not supply a bias RF signal while the bias DC signal is on, and supplies a bias RF signal while the bias DC signal is off.

[0085] In the etching method of the second embodiment, a bias RF signal is not superimposed during an ON period when the DC voltage of the bias DC signal is ON, but is superimposed and supplied during an OFF period when the DC voltage of the bias DC signal is OFF.

[0086] 12A is a diagram showing an example of a change in the potential of the substrate W in the etching method of the second embodiment. A bias RF signal is superimposed on the bias DC signal during an OFF period of the bias DC signal and supplied to the lower electrode of the base 1110, whereby the potential of the substrate W changes in a rectangular shape in accordance with the fluctuation of the bias DC signal and oscillates in accordance with the bias RF signal during the OFF period.

[0087] 12B is a diagram showing an example of ion energy distribution in the etching method of the second embodiment. FIG. 12B is a diagram showing a schematic ion energy distribution function (IEDF) in the etching method of the second embodiment. The horizontal axis indicates ion energy [eV], with the energy increasing toward the right. The vertical axis indicates the number of ions, with the number of ions increasing toward the top. FIG. 12B also shows the threshold E of ion energy required for etching the gate material 52. ｔｈ This shows:

[0088] In the etching method of the second embodiment, peaks occur on the high energy side and the low energy side.

[0089] In the etching method of the second embodiment, the bias RF signal is not superimposed on the ON period of the bias DC signal, so the peak on the high energy side is high and the energy width at which the peak occurs is narrow. In the etching method of the second embodiment, the peak on the high energy side is sharply angled, resulting in an energy distribution. As a result, the etching method of the second embodiment can achieve high vertical processing performance because the verticality of ions and radicals is high.

[0090] In addition, in the etching method of the second embodiment, the bias RF signal is superimposed during the off period of the bias DC signal, so that the threshold E ｔｈ As a result, a peak occurs over a wide width. As a result, in the etching method of the second embodiment, the incident angle of ions incident on the substrate W can be widened, and the residues 56 can be efficiently removed, thereby reducing the amount of residues 56.

[0091] In the etching methods of the first and second embodiments described above, the height of the peak on the high-energy side and the energy at which the peak occurs can be independently changed by changing the amplitude of the bias DC signal and the on-period of the bias DC signal, without changing the height of the peak on the low-energy side and the energy at which the peak occurs.

[0092] FIG. 13A is a diagram illustrating a change in the potential of the substrate W when the amplitude of the bias DC signal is changed. FIG. 13A shows a case in which the amplitude of the bias DC signal is changed by changing the negative voltage during the on period of the bias DC signal in the etching method of the second embodiment. In FIG. 13A, the negative voltage during the on period of the bias DC signal is changed more significantly toward the right, resulting in a greater change in the potential of the substrate W during the on period. FIG. 13B is a diagram illustrating a change in the energy distribution of ions when the amplitude of the bias DC signal is changed. FIG. 13B shows a case in which the amplitude of the bias DC signal is changed by changing the negative voltage during the on period of the bias DC signal in the etching method of the second embodiment. The energy of ions attracted to the substrate W changes depending on the potential of the substrate W. Therefore, by changing the amplitude of the bias DC signal, the energy range in which a high-energy peak occurs can be changed.

[0093] FIG. 14A is a diagram illustrating a change in the potential of the substrate W when the on-period of the bias DC signal is changed. FIG. 14A shows a case where the on-period of the bias DC signal is changed in the etching method of the second embodiment. In FIG. 14A, the on-period of the bias DC signal is lengthened toward the right, and the period T1 during which the potential of the substrate W is negative is longer toward the right. FIG. 14B is a diagram illustrating a change in the energy distribution of ions when the on-period of the bias DC signal is changed. FIG. 14B shows a case where the on-period of the bias DC signal is changed in the etching method of the second embodiment. The longer the period during which the potential of the substrate W is negative, the more ions are attracted to the substrate W. Therefore, by changing the on-period of the bias DC signal, the height of the peak on the high-energy side can be changed.

[0094] Furthermore, in the etching methods of the first and second embodiments described above, by changing the amplitude of the bias RF signal and the off period of the bias DC signal, it is possible to independently change the height of the peak on the low energy side and the range of energy at which the peak occurs, without changing the height of the peak on the high energy side and the energy at which the peak occurs.

[0095] FIG. 15A is a diagram illustrating a change in the potential of the substrate W when the amplitude of the bias RF signal is changed. FIG. 15A shows a case where the amplitude of the bias RF signal is changed in the etching method of the second embodiment. In FIG. 15A, by changing the amplitude of the bias RF signal more to the right, the oscillation width of the potential of the substrate W during the off period becomes larger to the right. FIG. 15B is a diagram illustrating a change in the energy distribution of ions when the amplitude of the bias RF signal is changed. FIG. 15B shows a case where the amplitude of the bias RF signal is changed in the etching method of the second embodiment. The energy of ions attracted to the substrate W changes depending on the potential of the substrate W. Therefore, by changing the amplitude of the bias RF signal, the energy range in which a peak on the low energy side occurs can be changed.

[0096] FIG. 16A is a diagram illustrating a change in the potential of the substrate W when the off period of the bias DC signal is changed. FIG. 16A shows a case where the off period of the bias DC signal is changed in the etching method of the second embodiment. In FIG. 16A, the off period of the bias DC signal is lengthened toward the right, and the period T2 during which the potential of the substrate W is near 0 becomes longer toward the right. FIG. 16B is a diagram illustrating a change in the energy distribution of ions when the off period of the bias DC signal is changed. FIG. 16B shows a case where the off period of the bias DC signal is changed in the etching method of the second embodiment. The longer the period T2 during which the potential of the substrate W is near 0, the more ions are attracted to the substrate W during the period T2. Therefore, by changing the off period of the bias DC signal, the height of the peak on the low energy side can be changed.

[0097] The on-period and off-period of the bias DC signal can be changed by changing the cycle and duty ratio of the bias DC signal. Thus, in the etching methods of the first and second embodiments, the energy distribution of ions incident on the substrate W can be adjusted by changing the cycle, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal. For example, in the etching methods of the first and second embodiments, the heights of the peaks on the low-energy side and the high-energy side and the energy ranges in which the peaks occur can be adjusted by changing the cycle, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal.

[0098] During etching of the substrate W, the control unit 2 may control the period, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal. For example, in the etching of the substrate W shown in FIGS. 2A, 2B, 3A, and 3B, a hole surrounded by a mask 53 and a fin 51a is formed in the gate material 52. The control unit 2 controls the period, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal when forming the hole in the gate material 52 by etching. For example, the control unit 2 controls the period, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the peak on the high-energy side is high and the peak on the low-energy side is low until the bottom of the hole reaches the underlayer 50. Then, once the bottom of the hole reaches the underlayer 50, the control unit 2 controls the period, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the peak on the low-energy side is high and the energy range in which the peak on the low-energy side occurs is widened. This allows the plasma processing apparatus 1 to achieve high vertical processing performance. Furthermore, the plasma processing apparatus 1 can reduce residues 56.

[0099] Furthermore, the etching methods of the first and second embodiments have been described above with reference to an example in which a bias RF signal is superimposed over the entire OFF period of the bias DC signal. However, this is not limiting. The etching methods of the first and second embodiments may also superimpose a bias RF signal over part of the OFF period of the bias DC signal. Figure 17 is a diagram illustrating changes in the potential of the substrate W when the superimposition period for the bias RF signal is changed. Figure 17 shows that in the etching method of the second embodiment, the height of the low-energy peak can be changed by changing the length of the superimposition period T4 in which the bias RF signal is superimposed within the OFF period T3 of the bias DC signal.

[0100] Furthermore, the etching methods of the first and second embodiments have been described above with reference to an example in which a bias RF signal is superimposed over the entire OFF period of the bias DC signal. However, this is not limiting. In the etching methods of the first and second embodiments, if the rectangularity of the bias DC signal is poor, the bias RF signal may not be superimposed during the transitional period in which the potential of the substrate W changes in response to the ON / OFF change of the bias DC signal, but may be superimposed after the transitional period has elapsed. FIG. 18 is a diagram illustrating the change in the potential of the substrate W when the superimposition period T4 for the bias RF signal is changed. A transitional period T5 occurs in the potential of the substrate W, during which the bias DC signal transitions to near zero after the bias DC signal is turned off. In FIG. 18 , the bias RF signal is turned off during the period T5 after the bias DC signal is turned off, so that the bias RF signal is not superimposed on the bias DC signal, and the bias RF signal is superimposed on the bias DC signal after the period T5 has elapsed. In the etching methods of the first and second embodiments, when the rectangularity of the bias DC signal is poor, the bias RF signal is not superimposed during the transition period, but is superimposed after the transition period has passed, thereby making it possible to generate peaks on both the low-energy side and the high-energy side.

[0101] Furthermore, the etching methods of the first and second embodiments have been described above using an example in which the substrate W shown in FIGS. 2A and 2B is etched. However, the present invention is not limited to this. The substrate W may be any substrate as long as a target film to be etched is formed on an underlying layer. The target film to be etched may be, for example, an oxide film such as a silicon oxide film, or a metal film such as a SiN film, an organic film, or a tungsten film. The underlying layer may be any material that has an etching selectivity with respect to the target film to be etched. The etching methods of the first and second embodiments can be applied to any process of etching a hole in a target film of the substrate W that reaches the underlying layer.

[0102] (Effects) As described above, the plasma processing system (plasma processing apparatus) according to the above embodiment includes the plasma processing chamber 10, the substrate support 11, the gas supply unit 20, the first RF generator 31a (first high-frequency power supply), the bias DC generator 32a (voltage pulse source), the second RF generator 31b (second high-frequency power supply), and the controller 2. The substrate support 11 is disposed in the plasma processing chamber 10 and supports a substrate W. The gas supply unit 20 is configured to supply a processing gas into the plasma processing chamber 10. The first RF generator 31a is configured to supply a source RF signal (first high-frequency power) that converts the processing gas in the plasma processing chamber 10 into plasma. The bias DC generator 32a is configured to supply a bias DC signal (voltage pulse) obtained by pulsing a DC voltage to the substrate support 11. The second RF generator 31b is configured to supply a bias RF signal (second high-frequency power) to the substrate support 11. When etching the substrate W, the control unit 2 is configured to control the following: supplying a processing gas from the gas supply unit 20 into the plasma processing chamber 10; supplying a source RF signal from the first RF generating unit 31 a to plasmatize the processing gas in the plasma processing chamber 10; supplying a bias DC signal from the bias DC generating unit 32 a to the substrate support unit 11; and supplying a bias RF signal from the second RF generating unit 31 b superimposed on the bias DC signal. As a result, the plasma processing system according to the embodiment can reduce residues.

[0103] The bias DC generator 32a is configured to periodically turn on and off the negative DC voltage and to change the ratio of the on and off periods within one cycle, thereby changing the duty ratio of the bias DC signal. The controller 2 is configured to control the duty ratio of the bias DC signal to 10% to 80%. This allows the plasma processing system according to the embodiment to reduce residues.

[0104] Furthermore, the control unit 2 is configured to control the duty ratio of the bias DC signal to 10% to 20%. This allows the plasma processing system according to the embodiment to reduce residues.

[0105] The substrate W has a target film to be etched formed on an underlayer. The controller 2 is configured to control the duty ratio of the bias DC signal so that the closer the bottom of a hole formed in the target film by etching is to the underlayer, the smaller the duty ratio of the bias DC signal. This allows the plasma processing system according to the embodiment to reduce residue at the bottom of the hole.

[0106] The bias DC generator 32a is configured to periodically turn on and off a negative DC voltage to supply a bias DC signal. The second RF generator 31b is configured not to supply a bias RF signal during the on period, but to supply a bias RF signal during the off period. This allows the plasma processing system according to the embodiment to reduce residues. The plasma processing system according to the embodiment also achieves high vertical processing performance.

[0107] The substrate W has a target film to be etched formed on an underlayer. The controller 2 is configured to perform the above-described control when the bottom of a hole formed in the target film by etching reaches the underlayer. This allows the plasma processing system according to the embodiment to reduce residue at the bottom of the hole.

[0108] The substrate W also has, on an underlayer 50, a fin structure 51 having a plurality of fins 51a, a gate material 52 deposited on the fin structure 51, and a mask 53 on the gate material 52, in that order. The control unit 2 is configured to perform the above-described control when etching the gate material 52 deposited between the plurality of fins 51a of the substrate W until the underlayer 50 is exposed. As a result, the plasma processing system according to the embodiment can reduce residues 56 at the bottom of holes (rectangular portions 55) where the underlayer 50 is exposed.

[0109] The bias DC generator 32a is configured to supply a bias DC signal having a frequency of 100 kHz to 1200 kHz, thereby enabling the plasma processing system according to the embodiment to achieve high vertical processing performance.

[0110] Furthermore, the gate material is polycrystalline silicon, and the underlayer is a silicon oxide film. This allows the plasma processing system according to the embodiment to reduce residues at the bottom of the hole where the silicon oxide film formed in the polycrystalline silicon is exposed. This allows the plasma processing system according to the embodiment to reduce residues.

[0111] The controller 2 is also configured to control the period, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal during etching of the substrate W. This allows the plasma processing system according to the embodiment to adjust the heights of the peaks on the low-energy side and the high-energy side of the ion energy distribution, as well as the energy ranges in which the peaks occur.

[0112] The substrate W has a target film to be etched formed on an underlayer. The control unit 2 is configured to control the period, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the energy distribution of ions incident on the substrate W has a high peak on the high energy side and a low peak on the low energy side until the bottom of a hole formed in the target film by etching reaches the underlayer. Once the bottom of the hole reaches the underlayer, the low energy peak becomes high and the energy range in which the low energy peak occurs becomes wider. This allows the plasma processing system according to the embodiment to reduce residue. Furthermore, the plasma processing system according to the embodiment can achieve high vertical processing performance.

[0113] Although the embodiments have been described above, the disclosed embodiments should be considered to be illustrative in all respects and not restrictive. Indeed, the above-described embodiments may be embodied in various forms. Furthermore, the above-described embodiments may be omitted, substituted, or modified in various forms without departing from the scope and spirit of the claims.

[0114] For example, in the above embodiment, the plasma etching process is performed on a semiconductor wafer as the substrate W, but the present invention is not limited to this.

[0115] It should be noted that the disclosed embodiments are illustrative in all respects and should not be considered limiting. Indeed, the above-described embodiments may be embodied in various forms. Furthermore, the above-described embodiments may be omitted, substituted, or modified in various forms without departing from the scope and spirit of the appended claims.

[0116] In addition, the following supplementary notes are disclosed regarding the above-described embodiment.

[0117] a control unit configured to control, when etching the substrate, the process gas to be supplied from the gas supply unit into the chamber, the first high frequency power to be supplied from the first high frequency power supply to the substrate support unit to turn the process gas in the chamber into plasma, and the voltage pulse source to supply the first high frequency power to the substrate support unit to turn the process gas in the chamber into plasma, and the voltage pulse source to supply the voltage pulse to the substrate support unit and the second high frequency power to be supplied from the second high frequency power supply to the substrate support unit to superimpose the voltage pulse on the voltage pulse.

[0118] (Supplementary Note 2) The plasma processing apparatus according to Supplementary Note 1, wherein the voltage pulse source is configured to periodically turn on and off a negative DC voltage and change the ratio of the on and off periods within one cycle to change the duty ratio of the voltage pulse, and the control unit is configured to control the duty ratio of the voltage pulse to be between 10% and 80%.

[0119] (Supplementary Note 3) The plasma processing apparatus according to Supplementary Note 2, wherein the control unit is configured to control the duty ratio of the voltage pulse to 10% to 20%.

[0120] (Appendix 4) The plasma processing apparatus according to appendix 2 or 3, wherein the substrate has a target film to be etched formed on a base layer, and the control unit is configured to control the duty ratio of the voltage pulse to become smaller as the bottom of a hole formed in the target film by etching becomes closer to the base layer.

[0121] (Supplementary Note 5) The plasma processing apparatus according to any one of Supplementary Notes 1 to 4, wherein the voltage pulse source is configured to periodically turn on and off a negative polarity DC voltage to supply the voltage pulse, and the second high frequency power supply is configured not to supply the second high frequency power during the on period, and to supply the second high frequency power during the off period.

[0122] (Appendix 6) The plasma processing apparatus according to any one of Appendices 1 to 5, wherein the substrate has a target film to be etched formed on a base layer, and the control unit is configured to perform the control when the bottom of a hole formed in the target film by etching reaches the base layer.

[0123] (Supplementary Note 7) The plasma processing apparatus according to any one of Supplementary Notes 1 to 6, wherein the substrate has, on an underlying layer, a fin structure having a plurality of fins, a gate material deposited on the fin structure, and a mask on the gate material, in that order, and the control unit is configured to perform the control when etching the gate material deposited between the plurality of fins of the substrate until the underlying layer is exposed.

[0124] (Supplementary Note 8) The plasma processing apparatus according to any one of Supplementary Notes 1 to 7, wherein the voltage pulse source is configured to supply a voltage pulse having a frequency of 100 kHz to 1200 kHz.

[0125] (Supplementary Note 9) The plasma processing apparatus according to Supplementary Note 7, wherein the gate material is polycrystalline silicon.

[0126] (Supplementary Note 10) The plasma processing apparatus according to Supplementary Note 7 or 9, wherein the underlayer is a silicon oxide film.

[0127] (Supplementary Note 11) The plasma processing apparatus according to any one of Supplementary Notes 1 to 10, wherein the control unit is configured to control a period, a duty ratio, and an amplitude of the voltage pulse and an amplitude of the second high frequency power during etching of the substrate.

[0128] (Appendix 12) The plasma processing apparatus according to any one of Appendices 1 to 11, wherein the substrate has a target film to be etched formed on a base layer, and the control unit is configured to control the period, duty ratio and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the peak on the high energy side of the energy distribution of ions incident on the substrate is high and the peak on the low energy side is low until the bottom of a hole formed in the target film by etching reaches the base layer, and when the bottom of the hole reaches the base layer, the peak on the low energy side is high and the range of energy where the peak on the low energy side occurs is wide.

[0129] a first high frequency power supply configured to supply a first high frequency power that turns the processing gas in the chamber into plasma; a voltage pulse source configured to supply a voltage pulse obtained by pulsating a DC voltage to the substrate support portion; and a second high frequency power supply configured to supply a second high frequency power to the substrate support portion, the etching method comprising the steps of: when etching the substrate, supplying the processing gas from the gas supply portion into the chamber; supplying a first high frequency power from the first high frequency power supply to turn the processing gas in the chamber into plasma; supplying the voltage pulse from the voltage pulse source to the substrate support portion; and supplying the second high frequency power from the second high frequency power supply superimposed on the voltage pulse.

[0130] REFERENCE SIGNS LIST 1 Plasma processing apparatus 2 Control unit 2a Computer 2a1 Processing unit 2a2 Memory unit 2a3 Communication interface 10 Plasma processing chamber 11 Substrate support 13 Central gas injection unit 14 Antenna 20 Gas supply unit 21 Gas source 22 Flow rate controller 30 Power supply 31 RF power supply 31a First RF generation unit 31b Second RF generation unit 32 DC power supply 32a Bias DC generation unit 40 Exhaust system 50 Underlayer 51 Fin structure 51a Fin 52 Gate material 52a Gate portion 53 Mask 53a SiN layer 53b Oxide layer 55 Rectangular portion 56 Residue 101 Dielectric window 102 Sidewall 111 Main body 112 Ring assembly 1111 Electrostatic chuck W Substrate

Claims

a first high frequency power supply configured to supply a first high frequency power that converts the processing gas in the chamber into plasma; a voltage pulse source configured to supply a voltage pulse obtained by pulsating a DC voltage to the substrate support; a second high frequency power supply configured to supply a second high frequency power to the substrate support; and a control unit configured to control, when etching the substrate, the gas supply unit to supply the processing gas into the chamber, the first high frequency power supply to supply a first high frequency power to convert the processing gas in the chamber into plasma, and the voltage pulse source to supply the voltage pulse to the substrate support unit and the second high frequency power supply to supply the second high frequency power superimposed on the voltage pulse.

2. The plasma processing apparatus according to claim 1, wherein the voltage pulse source is configured to periodically turn a negative DC voltage on and off and to change the ratio of the on and off periods within one cycle, thereby making it possible to change the duty ratio of the voltage pulse, and the control unit is configured to control the duty ratio of the voltage pulse to be between 10% and 80%.

3. The plasma processing apparatus according to claim 2, wherein the control unit is configured to control the duty ratio of the voltage pulse to 10% to 20%.

4. The plasma processing apparatus according to claim 2, wherein the substrate has a target film to be etched formed on a base layer, and the control unit is configured to control the duty ratio of the voltage pulse to be smaller as the bottom of a hole formed in the target film by etching approaches the base layer.

5. The plasma processing apparatus according to claim 1, wherein the voltage pulse source is configured to periodically turn on and off a negative polarity DC voltage to supply the voltage pulse, and the second high frequency power supply is configured not to supply the second high frequency power during the on period, but to supply the second high frequency power during the off period.

6. The plasma processing apparatus according to claim 1, wherein the substrate has a target film to be etched formed on a base layer, and the control unit is configured to perform the control when the bottom of a hole formed in the target film by etching reaches the base layer.

7. The plasma processing apparatus according to claim 1, wherein the substrate has, on an underlying layer, a fin structure having a plurality of fins, a gate material deposited on the fin structure, and a mask on the gate material, in that order; and the control unit is configured to perform the control when the gate material deposited between the plurality of fins on the substrate is etched until the underlying layer is exposed.

8. The plasma processing apparatus of claim 1, wherein the voltage pulse source is configured to supply voltage pulses at a frequency between 100 kHz and 1200 kHz.

9. The plasma processing apparatus according to claim 7, wherein the gate material is polycrystalline silicon.

10. The plasma processing apparatus according to claim 7, wherein the underlayer is a silicon oxide film.

11. The plasma processing apparatus according to claim 1, wherein the control unit is configured to control the period, duty ratio and amplitude of the voltage pulse and the amplitude of the second high frequency power during etching of the substrate.

12. The plasma processing apparatus of claim 1, wherein the substrate has a target film to be etched formed on a base layer, and the control unit is configured to control the period, duty ratio and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the energy distribution of ions incident on the substrate has a high peak on the high energy side and a low peak on the low energy side until the bottom of a hole formed in the target film by etching reaches the base layer, and when the bottom of the hole reaches the base layer, the peak on the low energy side becomes high and the range of energy at which the peak on the low energy side occurs becomes wide.

13. An etching method for a plasma processing apparatus comprising: a chamber; a substrate support portion disposed within the chamber and supporting a substrate; a gas supply portion configured to supply a processing gas into the chamber; a first high frequency power supply configured to supply a first high frequency power that converts the processing gas in the chamber into plasma; a voltage pulse source configured to supply a voltage pulse obtained by pulsating a DC voltage to the substrate support portion; and a second high frequency power supply configured to supply a second high frequency power to the substrate support portion, the etching method comprising the steps of: when etching the substrate, supplying the processing gas from the gas supply portion into the chamber; supplying a first high frequency power from the first high frequency power supply to convert the processing gas in the chamber into plasma; supplying the voltage pulse from the voltage pulse source to the substrate support portion; and supplying the second high frequency power from the second high frequency power supply superimposed on the voltage pulse.

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