Memory device and memory system

Abstract

The present invention reduces damage to a memory cell caused by writing. This memory device includes a memory cell block and a write circuit. The memory cell block is formed by a plurality of memory cells, each of which includes a variable resistance element and a cell transistor connected in series, and in which either a first logic state or a second logic state is written. The write circuit performs writing simultaneously to each memory cell in the memory cell block, and performs writing based on write data and inverted writing in which data obtained by inverting the logic state with respect to the write data is written to the memory cell.

Description

Memory device and memory system

[0001] The present disclosure relates to memory devices and memory systems.

[0002] In MRAM (Magnetoresistive RAM), which uses a magnetic memory element as a nonvolatile memory element, a voltage-driven magnetic memory element has been proposed in which data is written by applying a pulse voltage. Such MRAM uses a magnetic memory element with a magnetic tunnel junction (MTJ) structure in which a tunnel barrier layer is sandwiched between two magnetic layers (a storage layer and a reference layer).

[0003] This magnetic memory element is in a high resistance state when the magnetization directions of the two magnetic layers are different, and in a low resistance state when the magnetization directions of the two magnetic layers are the same. MRAM uses this change in resistance to store data.

[0004] In a memory device using such a magnetic memory element, a memory device (magnetic random access memory) has been proposed that performs writing by switching between a high resistance state and a low resistance state depending on the direction of a current passed through the magnetic memory element during writing (see, for example, Patent Document 1). This magnetic random access memory controls the temperature dependency of the write pulse current.

[0005] Japanese Patent Application Laid-Open No. 2004-326951

[0006] However, the above-mentioned conventional technology does not take into consideration damage to memory cells caused by writing, and there is a problem that writing shortens the life of the memory device.

[0007] Therefore, the present disclosure proposes a memory device and a memory system that reduce damage to memory cells caused by writing and have a longer lifespan.

[0008] The memory device of the present disclosure has a memory cell block consisting of a plurality of memory cells each having a variable resistance element and a cell transistor connected in series, and each having either a first logic state or a second logic state written thereto, and a write circuit that simultaneously writes to each memory cell of the memory cell block and performs both writing based on write data and inverted writing, in which data whose logic state is inverted from the write data is written to the memory cell.

[0009] 1 is a diagram illustrating an example configuration of a memory system according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example configuration of a memory element according to a first embodiment of the present disclosure. FIG. 3 is a diagram illustrating an example configuration of a memory cell according to the first embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example of writing to a memory cell according to the first embodiment of the present disclosure. FIG. 5 is a diagram illustrating another example of writing to a memory cell according to the first embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example configuration of a write circuit according to the first embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of a write process according to the first embodiment of the present disclosure. FIG. 8 is a diagram illustrating an example of a write process according to the first embodiment of the present disclosure. FIG. 9 is a diagram illustrating an effect of the write process according to the first embodiment of the present disclosure. FIG. 10 is a diagram illustrating an example configuration of a write circuit according to a second embodiment of the present disclosure. FIG. 11 is a diagram illustrating another example configuration of a write circuit according to the second embodiment of the present disclosure. FIG. 12 is a diagram illustrating an example configuration of a write circuit according to a third embodiment of the present disclosure. FIG. 13 is a diagram illustrating an example of a write process according to the third embodiment of the present disclosure. FIG. 14 is a diagram illustrating an example of a write process according to the third embodiment of the present disclosure. FIG. 15 is a diagram illustrating an example of a write process according to the third embodiment of the present disclosure. FIG. 16 is a diagram illustrating an example configuration of a write circuit according to a fourth embodiment of the present disclosure. FIG. 17 is a diagram illustrating another example configuration of a write circuit according to the fourth embodiment of the present disclosure.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order. Note that in the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted. 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment

[0011] (1. First Embodiment) <Configuration of Memory System> FIG. 1 is a diagram illustrating an example configuration of a memory system according to an embodiment of the present disclosure. This diagram is a block diagram illustrating an example configuration of a memory system 1. The memory system 1 includes an interface unit 2, a memory control unit 3, a memory cell array 10, a word line address decoder 60, a word line control circuit 20, a bit line address decoder 50, a bit line control circuit 30, and a sense amplifier 40. The memory system 1 also includes a voltage generation circuit 70. While this embodiment describes an example having a memory interface connected to a host system, the memory system 1 can be applied to memory systems with other configurations. For example, the memory system 1 can also be applied to an embedded memory, an integrated memory, or an integrated storage device having an I / O that connects to an internal bus or logic circuit integrated in a SoC (System on a Chip). The memory system 1 can also be considered a semiconductor device. The memory cell array 10 , word line address decoder 60 , word line control circuit 20 , bit line address decoder 50 , bit line control circuit 30 , voltage generating circuit 70 and sense amplifier 40 of the memory system 1 constitute a memory device 4 .

[0012] The interface unit 2 is used to communicate with a host system or the like that uses the memory system 1 .

[0013] The memory control unit 3 communicates with a host system or the like. This memory control unit 3 receives commands from the host system or the like and controls the writing and reading of data based on the received commands. The memory control unit 3 in FIG. 1 outputs write and read addresses to the word line address decoder 60 and the bit line address decoder 50. The memory control unit 3 also outputs control signals to the word line control circuit 20 and the voltage generation circuit 70. The memory control unit 3 also sends write data to the sense amplifier 40 and obtains read data from the sense amplifier 40.

[0014] The memory cell array 10 is configured by arranging memory cells 100 for storing data in a two-dimensional matrix. Each memory cell 100 includes a memory element 120 and a cell transistor 110.

[0015] The memory element 120 has a magnetic tunnel junction (MTJ) structure in which a tunnel barrier layer is sandwiched between two magnetic layers (a storage layer and a reference layer). The resistance of the memory element 120 varies depending on the magnetization directions of the two magnetic layers. The memory element 120 is in a high-resistance state when the magnetization directions of the two magnetic layers are different, and in a low-resistance state when the magnetization directions are the same. The state in which the magnetization directions are the same is called a parallel state, and the state in which the magnetization directions are different is called an anti-parallel state. This magnetization direction can be changed by applying a write voltage to the MTJ element. For example, values ​​"0" and "1" can be associated with the low-resistance state and the high-resistance state of the MTJ element to store one bit of data. The values ​​"0" and "1" can also be referred to as low-level voltage (L) and high-level voltage (H).

[0016] The cell transistor 110 is an element connected to one end of the memory element 120 and controls the application of voltage to the memory element 120. For example, an n-channel MOS transistor can be used for this cell transistor 110.

[0017] In the memory cell 100, word lines 11, bit lines 12, and source lines 13 are arranged. The word lines 11 are made up of a plurality of word lines WL. The bit lines 12 are made up of a plurality of bit lines BL. The source lines 13 are made up of a plurality of source lines SL. The word lines WL and bit lines BL transmit control signals. The source lines SL transmit signals from the memory elements 120. In the memory cell array 10, a plurality of word lines WL are wired in the row direction, and a plurality of bit lines BL and source lines SL are wired in the column direction.

[0018] The word line address decoder 60 selects a word line WL of the memory cell array 10 based on a control signal from the memory control unit 3 .

[0019] The word line control circuit 20 outputs a control signal to the word line WL selected by the word line address decoder 60 .

[0020] The bit line address decoder 50 selects a bit line BL of the memory cell array 10 based on a control signal from the memory control unit 3 .

[0021] The bit line control circuit 30 outputs a control signal to the bit line BL selected by the bit line address decoder 50 .

[0022] The sense amplifier 40 reads data by detecting the current flowing through the memory cell 100 during reading. The read data is output to the memory control unit 3.

[0023] The voltage generating circuit 70 is a circuit that generates a voltage to be applied when writing to and reading from the memory cell 100 .

[0024] Writing to the memory cell 100 can be performed by switching the memory element 120 between a low resistance state and a high resistance state depending on the data to be written. The memory element 120 can switch between a low resistance state and a high resistance state depending on the direction of a current flowing during writing. Details of writing to the memory element 120 will be described later.

[0025] Reading can be performed by applying a predetermined read voltage to the memory element 120 of the memory cell 100 and detecting the current flowing through the memory cell 100. The read voltage is preferably lower than the write voltage.

[0026] The memory device 4 includes a write circuit 80, which will be described later. The configuration of the bit lines BL and source lines SL may differ from that shown in FIG.

[0027] <Memory element> Fig. 2 is a diagram showing a configuration example of a memory element according to the first embodiment of the present disclosure. The figure is a schematic cross-sectional view showing a configuration example of a memory element 120. As described above, in the memory element 120, the tunnel barrier layer 123 is disposed between the memory layer 124 and the reference layer 122. Furthermore, the memory element 120 is configured in a shape in which the memory layer 124 and the like are sandwiched between the electrode 125 and the electrode 121.

[0028] The electrodes 121 and 125 can be made of, for example, Cu, Al, Au, Pt, Ti, and Ru.

[0029] The memory layer 124 is a magnetic layer whose magnetization direction is variable. The states in which the magnetization direction of the memory layer 124 is the same as and different from the magnetization direction of the reference layer 122 correspond to a parallel alignment state and an antiparallel alignment state, respectively. The memory element 120 is in a low resistance state in the parallel alignment state and in a high resistance state in the antiparallel alignment state. The memory layer 124 is composed of any one of Ti, V, Cr, Mn, Fe, Co, and Ni.

[0030] The tunnel barrier layer 123 is a layer that separates the storage layer 124 and the reference layer 122. The tunnel barrier layer 123 may be made of, for example, MgO. The tunnel barrier layer 123 is also called an insulating layer.

[0031] The reference layer 122 is a magnetic layer whose magnetization direction is invariable, and may be made of a ferromagnetic layer containing at least one of Fe, Co, Ni, and Mn.

[0032] Writing to the memory element 120 can be performed by changing the direction of magnetization of the memory layer 124 in accordance with the write data. Writing data "0" can be performed by aligning the magnetization direction of the memory layer 124 with the magnetization direction of the reference layer 122. In the example of FIG. 2 , by flowing a write current in a direction from electrode 121 to electrode 125, the magnetization direction of the memory layer 124 can be aligned with the magnetization direction of the reference layer 122. Writing data "1" can be performed by reversing the magnetization direction of the memory layer 124 from the magnetization direction of the reference layer 122. In the example of FIG. 2 , by flowing a write current in a direction from electrode 125 to electrode 121, the magnetization direction of the memory layer 124 can be reversed from the magnetization direction of the reference layer 122. In this case, for example, by changing the direction of the current, the direction of the magnetic field applied to the memory layer 124 changes, and the magnetization direction of the memory layer 124 can be switched. The memory element 120 is an example of a "variable resistance element" in the present disclosure.

[0033] <Memory Cell> FIG. 3 is a diagram showing a configuration example of a memory cell according to the first embodiment of the present disclosure. This diagram shows a configuration example of a memory cell 100. As described above, the memory cell 100 includes a memory element 120 and a cell transistor 110 connected in series. As described above, the cell transistor 110 can be configured as an n-channel MOS transistor. For convenience, the two terminals of the memory cell 100 are referred to as a first terminal 101 and a second terminal 102. One of the drain and source of the cell transistor 110 is connected to one terminal of the memory element 120. The other of the drain and source of the cell transistor 110 is connected to the first terminal 101. The other terminal of the memory element 120 is connected to the second terminal 102.

[0034] 3, a first terminal 101 of the memory cell 100 is connected to a source line SL. A second terminal 102 of the memory cell 100 is connected to a bit line BL. A gate, which is a control terminal of the cell transistor 110, is connected to a word line WL.

[0035] FIG. 3 illustrates a switch 21 included in the word line control circuit 20 and switches 31 and 32 included in the bit line control circuit 30. During writing, the switch 21 is turned on, and a gate drive voltage Vwl is applied to the gate of the cell transistor 110 via the word line WL, causing the cell transistor 110 to be conductive. Furthermore, the switches 31 and 32 are driven, and a write voltage is applied to the memory cell 100. During writing of data "0" shown in FIG. 3, the switch 32 is switched to the side of the write voltage Vw, and the switch 31 is switched to the side of the common ground line (GND). As a result, the write voltage Vw is applied to the second terminal 102, and a write current flows in the direction of the solid arrow in FIG. 3, thereby writing data "0." During writing of data "1" shown in FIG. 3, the switch 32 is switched to the side of the common ground line (GND), and the switch 31 is switched to the side of the write voltage Vw. As a result, a write voltage Vw is applied to the first terminal 101, causing a write current to flow in the direction of the dotted arrow in FIG. 3, and data "1" is written.

[0036] 4A and 4B are diagrams showing an example of writing to a memory cell according to the first embodiment of the present disclosure. As described above, the memory cell 100 includes a cell transistor 110 made of an n-channel MOS transistor.

[0037] 4A shows the voltages at various parts of the memory cell 100 when data "0" is written to the memory cell 100. In the example shown in the figure, a higher voltage (write voltage Vw) is applied to the second terminal 102 than to the first terminal 101. In the figure, the dashed-dotted line represents Vwl. The dashed line represents the voltage at the first terminal 101. Vgs in the figure represents the voltage applied between the gate and source of the cell transistor 110. In the figure, Vgs is a relatively high voltage.

[0038] 4A, writing is performed by applying voltages of the same polarity, with the first terminal 101 as a reference, to the second terminal 102 and the control terminal (gate) of the cell transistor 110. The logic state written to the memory cell 100 by such a writing operation is referred to as a first logic state. In FIG. 4A, "0" corresponds to the first logic state.

[0039] 4B shows the voltages at various parts of the memory cell 100 when data "1" is written to the memory cell 100. In the example of FIG. 4B, a higher voltage (write voltage Vw) is applied to the first terminal 101 relative to the second terminal 102. In the figure, the source and drain of the cell transistor 110 are at a potential close to the gate drive voltage Vwl, resulting in a relatively low Vgs.

[0040] 4B, writing is performed by applying voltages of different polarities, with respect to the first terminal 101, to the second terminal 102 and the control terminal (gate) of the cell transistor 110. The logic state written to the memory cell 100 by such a writing operation is referred to as the second logic state. In FIG. 4B, "1" corresponds to the second logic state.

[0041] 5A and 5B are diagrams showing another example of writing to a memory cell according to the first embodiment of the present disclosure. The memory cell 100 in Figures 5A and 5B has a cell transistor 111 arranged in place of the cell transistor 110. This cell transistor 111 is configured as a p-channel MOS transistor.

[0042] 5A illustrates the writing of data "1." In the example shown in the figure, a lower voltage (write voltage Vw) is applied to the second terminal 102 relative to the first terminal 101. That is, a voltage of the same polarity, based on the first terminal 101, is applied to the second terminal 102 and the control terminal (gate) of the cell transistor 110 to perform the write operation. In the figure, the memory cell 100 is in the first logic state and has a relatively high Vgs.

[0043] 5B illustrates the writing of data "0." In the example of FIG. 5B, a higher voltage (write voltage Vw) is applied to the second terminal 102 relative to the first terminal 101. That is, voltages of different polarities relative to the first terminal 101 are applied to the second terminal 102 and the control terminal (gate) of the cell transistor 110 to perform writing. In FIG. 5B, the memory cell 100 is in the second logic state and has a relatively low Vgs.

[0044] 4A and 4B and 5A and 5B, in the first logic state, a relatively high voltage is applied between the gate and source of the cell transistor 110 during writing, increasing the likelihood of gate insulating film breakdown. In contrast, in the second logic state, the voltage between the gate and source of the cell transistor 110 decreases during writing, reducing the burden on the gate oxide film. In this way, by increasing the number of the second logic state compared to the first logic state, breakdown of the memory cell 100 can be reduced.

[0045] <Write Circuit> FIG. 6 is a diagram showing an example of the configuration of a write circuit according to the first embodiment of the present disclosure. This diagram illustrates an outline of the circuits of the bit line address decoder 50, bit line control circuit 30, memory cell array 10, and sense amplifier 40 shown in FIG. 1 . The diagram also illustrates a determination unit 81, a data conversion unit 82, and a read data conversion unit 84. The determination unit 81, the data conversion unit 82, the bit line address decoder 50, and the bit line control circuit 30 in FIG. 6 constitute a write circuit 80. This write circuit 80 writes data to each memory cell block (memory cell block 200 described below) consisting of a plurality of memory cells 100. That is, the write circuit 80 simultaneously writes either a first logic state or a second logic state to each memory cell 100 in the memory cell block 200. Furthermore, the write circuit 80 can write data to the memory cells 100 by increasing the second logic state from the first logic state.

[0046] 6 is configured by arranging a plurality of memory cell blocks 200 in a matrix. Each memory cell block 200 can be configured by seven memory cells 100, for example.

[0047] The determination unit 81 determines whether or not to perform data inversion processing on the data group of the memory cell block 200. The determination unit 81 can determine that data inversion processing should be performed when, for example, the number of "0"s is greater than the number of "1"s in the data group of the memory cell block 200. Here, the inversion processing is processing that inverts the logic of each of the data groups of the memory cell block 200. Details of the inversion processing will be described later.

[0048] The data conversion unit 82 performs inversion processing based on the determination result of the determination unit 81. If the determination result of the determination unit 81 indicates that inversion processing is not to be performed, the data conversion unit 82 outputs the data as is to the bit line address decoder 50. Here, the process of writing the inverted data group to the memory cells 100 of the memory cell block 200 is referred to as inversion writing.

[0049] The read data conversion unit 84 performs a process of reversing the logic of each data group when the data read from the memory cell block 200 has been inverted and written.

[0050] <Write Process> Figures 7A and 7B are diagrams showing an example of a write process according to the first embodiment of the present disclosure. Figure 7A is a diagram showing a configuration example of a memory cell block 200. The memory cell block 200 in the figure shows an example configured with seven memory cells 100. Note that a write information holding unit 150 is added to the memory cell block 200 in the figure. This write information holding unit 150 is a memory cell that holds inverted write information. This inverted write information is a flag indicating that inverted write has been performed.

[0051] 7B is a diagram showing the processing in the write circuit 80 and the read data conversion unit 84. The figure shows the processing of data groups in each unit of the write circuit 80. The write data 300 in the figure represents the write data of the memory cell block 200. The rectangles in the write data 300 represent bits. The judgment unit 81 judges whether the number of "0"s in the write data 300 is greater than the number of "1"s. This can be done by counting and comparing the number of "0"s and the number of "1"s. In the example shown in the figure, the number of "0"s is greater than the number of "1"s, so the judgment unit 81 determines that inversion processing should be performed.

[0052] The data conversion unit 82 performs an inversion process based on the determination result of the determination unit 81. As a result, the data of each bit of the write data 300 is inverted. The thick rectangles in FIG. 7B represent bits whose data has been inverted. In addition, inverted write information 301 is added to the write data 300. A "1" in FIG. 7B represents the inverted write information 301. This write data 300 is written to the memory cell block 200, and inverted writing is performed. In addition, the inverted write information 301 is held in the write information holding unit 150. Note that the value in parentheses represents write data when inversion process is not performed. Since inversion process is not performed, the inverted write information 301 is not added ("0" is written to the write information holding unit 150). This write data 300 and inverted write information 301 are input to the bit line address decoder 50 and written to the memory cell block 200.

[0053] Next, at the time of reading, read data 310 is read from the memory cell block 200. At the same time, inverted write information 301 is also read from the write information holding unit 150. The read data 310 and inverted write information 301 are input to the read data conversion unit 84 via the sense amplifier 40. The read data conversion unit 84 inverts the data of the read data 310 based on the inverted write information 301. The data inversion can be performed by, for example, an exclusive OR gate circuit. Note that the read data conversion unit 84 does not perform data inversion processing if the inverted write information 301 is not read.

[0054] In this way, the write circuit 80 performs an inversion process when there are many "0"s, i.e., the first logic state, in the data group of the memory cell block 200. This makes it possible to reduce the number of "0"s, i.e., the first logic state, in the data group written to the memory cell block 200. This reduces the probability of the cell transistor 110 in the memory cell 100 being destroyed. For example, when the memory cell 100 is manufactured using a 22 nm process, it has been confirmed that a 0.1 V decrease in the gate voltage of the MOS transistor extends the lifespan by 10 times.

[0055] 8 is a diagram showing the effect of the write process according to the first embodiment of the present disclosure. This figure shows an example of performing inversion writing on a 7-bit data group. "Before conversion" in this figure shows the write data group before the inversion process. Cases where the number of "0" bits is 0 to 7 are shown. "After conversion" in this figure shows the case where the inversion process is performed when the number of "0" bits is greater than the number of "1" bits. Furthermore, "bit occurrence probability" in this figure shows the occurrence probability of "0" and "1" bits before and after conversion. In the data group after conversion, the occurrence probability of "0" bits decreases.

[0056] Here, it is assumed that writing a "0" bit consumes or reduces the lifetime by 10 times compared to writing a "1" bit. Then, the average lifetime consumption of the cell transistor 110 when writing 100 times can be reduced by half by performing the conversion.

[0057] Note that the configuration of the memory device 4 according to the first embodiment of the present disclosure is not limited to this example. For example, a configuration in which the read data conversion unit 84 in FIG. 6 is omitted may be adopted. In this case, the data read from the memory cell block 200 and the inverted write information are output as read data.

[0058] In this way, the memory device 4 according to the first embodiment of the present disclosure performs data inversion processing based on the number of first logic states in the data group to be written to the memory cell block 200. This reduces the number of times the first logic state is written, which increases the burden on the cell transistor 110 of the memory cell 100, and reduces damage to the cell transistor 110. This allows the memory device 4 to have a longer life.

[0059] (2. Second Embodiment) The memory device 4 of the first embodiment described above performs data inversion processing based on the number of first logic states in the data group to be written to the memory cell block 200. In contrast, the memory device 4 of the second embodiment of the present disclosure differs from the first embodiment described above in that it further performs processing based on temperature.

[0060] <Configuration of Write Circuit> Fig. 9 is a diagram showing a configuration example of a write circuit according to the second embodiment of the present disclosure. Similar to Fig. 6, this figure is a block diagram showing a configuration example of a write circuit 80. The write circuit 80 in Fig. 9 differs from the write circuit 80 in Fig. 6 in that it further includes a temperature detection unit 85.

[0061] The temperature detection unit 85 detects the temperature of the memory device 4. The temperature detection unit 85 outputs the detected temperature to the determination unit 81.

[0062] 9 determines whether to perform inversion writing based on temperature. For example, when the temperature detected by the temperature detection unit 85 is higher than a predetermined threshold, and the number of "0"s (first logic state) in the data group is greater than the number of "1"s (second logic state), the determination unit 81 can determine that inversion processing should be performed.

[0063] The gate of the cell transistor 110 is more likely to be destroyed in a high-temperature environment. Therefore, a method of performing inversion writing is adopted when the temperature of the memory cell 100, etc., becomes high. This allows only normal writing to be performed when the environment is not high temperature, thereby reducing the processing load.

[0064] <Other Configurations of the Write Circuit> The write circuit 80 can also change the processing depending on the detected temperature. For example, in addition to determining whether to perform the inversion processing when the detected temperature is higher than the predetermined threshold value, the write circuit 80 may further determine whether to perform the inversion processing when the detected temperature is lower than a predetermined threshold value (second threshold value) and the number of "1"s in the data group is greater than "0"s. In this case, the write circuit 80 can have the same configuration as that shown in FIG. 9.

[0065] 10 is a diagram showing another example configuration of a write circuit according to the second embodiment of the present disclosure. This diagram shows an example configuration of a memory cell block 200 when the above-described write circuit 80 is employed. The memory cell block 200 shown in this diagram has a write information holding unit 151 added to the write information holding unit 150. This write information holding unit 151 is a memory cell that holds a flag indicating that an inversion process (inversion write) has been performed when the number of "1"s in a data group is greater than "0".

[0066] The read data conversion unit 84 performs a process of re-inverting the data group based on the inverted write information in the write information holding unit 150 and the write information holding unit 151 .

[0067] In a low temperature environment, the write characteristics of "1" may deteriorate in the memory cell 100. In such a case, if the number of data "1"s is large, an inversion process is performed to reduce the number of "1"s, thereby reducing the occurrence of write failures in the memory cell 100.

[0068] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0069] In this way, in the memory device 4 according to the second embodiment of the present disclosure, the write circuit 80 determines whether to perform data inversion processing based on the temperature, thereby enabling the write processing to be performed in accordance with the temperature characteristics of the memory cell 100.

[0070] (3. Third Embodiment) The memory device 4 of the first embodiment described above performs inversion processing of a data group in accordance with the logic state of the write data group in the memory cell block 200. In contrast, the memory device 4 of the third embodiment of the present disclosure differs from the first embodiment described above in that it performs inversion processing on data of specific bits in the memory cell block 200.

[0071] 11 is a diagram illustrating a configuration example of a write circuit according to a third embodiment of the present disclosure. Similar to FIG. 6, this diagram illustrates a configuration example of a write circuit 80. The write circuit 80 in this diagram differs from the write circuit 80 in FIG. 6 in that the determination unit 81 is omitted.

[0072] 11 performs an inversion process on data of a specific memory cell 100 in the memory cell block 200. Also, the read data conversion unit 84 in Fig. 11 performs an inversion process on data of the read data corresponding to the specific memory cell 100. For example, the memory cell 100 corresponding to the most significant bit (MSB) of the memory cell block 200 can be used as this specific memory cell 100.

[0073] FIG. 12 is a diagram illustrating an example of a write process according to the third embodiment of the present disclosure. The upper part of the diagram illustrates a data group in the memory cell block 200. This diagram illustrates an example in which the data in the data group follows a normal distribution. The graph in the diagram represents a normal distribution. In such a case, the MSB of the data group is more likely to be "0." Meanwhile, bits other than the MSB are approximately equally likely to be "0" and "1." The lower part of the diagram illustrates an example of data. For example, when capturing images using a surveillance camera or an in-vehicle camera in an environment such as nighttime, the upper bits of image data or linear PCM (audio quantization) are often "0." Therefore, when writing such data, inversion processing of the MSB data, which often becomes "0," can reduce damage to the memory cell 100 corresponding to that bit.

[0074] 13 is a diagram showing an example of a write process according to the third embodiment of the present disclosure. Similar to FIG. 7B, this diagram shows the processing in the write circuit 80 and the read data conversion unit 84. The processing in this diagram differs from the write process in FIG. 7B in that an inversion process is performed on data corresponding to a specific bit of the memory cell block 200.

[0075] The data conversion unit 82 performs an inversion process on the data corresponding to the MSB of the memory cell block 200 in the write data 300. As in Fig. 7B, the thick rectangles represent bits that have undergone the inversion process. Note that, unlike the process in Fig. 7B, the write information holding unit 151 is not provided, and therefore the inverted write information 301 is not used.

[0076] The read data conversion unit 84 performs inversion processing on only the MSB data of the read data 310 .

[0077] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0078] In this way, the memory device 4 according to the third embodiment of the present disclosure performs an inversion process on the data of a specific memory cell 100 in the memory cell block 200. This makes it possible to reduce the number of times the first logic state is written to the specific memory cell 100.

[0079] (4. Fourth Embodiment) A variation of the memory device 4 of the first embodiment will be described.

[0080] 14 is a diagram showing a configuration example of a write circuit according to a fourth embodiment of the present disclosure. Similar to FIG. 6, this figure is a block diagram showing a configuration example of a write circuit 80. The write circuit 80 in this figure differs from the write circuit 80 in FIG. 6 in that it further includes a determination unit 86 and a data conversion unit 87.

[0081] The write circuit 80 of FIG. 14 can write to a plurality of memory cell blocks 200 simultaneously.

[0082] 15 is a diagram showing another example of the configuration of a write circuit according to the fourth embodiment of the present disclosure. Similar to FIG. 14, this figure is a block diagram showing an example of the configuration of a write circuit 80. The write circuit 80 in this figure differs from the write circuit 80 in FIG. 14 in that it further includes a rotator 88.

[0083] The rotator 88 distributes the number of write operations among the plurality of memory cell blocks 200 .

[0084] The configuration of the fourth embodiment of the present disclosure can be applied to other embodiments. Specifically, the write circuit 80 of FIGS. 13 and 14 can be applied to the second and third embodiments of the present disclosure.

[0085] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0086] The present technology can also be configured as follows: (1) A memory device having a memory cell block configured of a plurality of memory cells each including a variable resistance element and a cell transistor connected in series, and each memory cell being written with either a first logic state or a second logic state, and a write circuit that simultaneously writes to each memory cell of the memory cell block and performs writing based on write data and inverted writing that writes data obtained by inverting the logic state of the write data into the memory cell. (2) The memory device according to (1), wherein the memory cell is configured such that one of the drain and source of the cell transistor is connected to one terminal of the variable resistance element, and the memory cell comprises a first terminal to which the other of the drain and source of the cell transistor is connected and a second terminal connected to the other terminal of the variable resistance element, wherein the first logic state is a logic state in which voltages of the same polarity with respect to the first terminal are applied to the second terminal and a control terminal of the cell transistor during writing, and the second logic state is a logic state in which voltages of different polarities with respect to the first terminal are applied to the second terminal and the control terminal of the cell transistor during writing. (3) The memory device according to (2), wherein the write circuit performs the inversion write based on the number of the first logic states in the write data for each of the memory cells in the memory cell block. (4) The memory device according to (2), further comprising a temperature detection unit for detecting the temperature of the memory cell block, and wherein the write circuit performs the inversion write based on the temperature. (5) The memory device according to (4), wherein the write circuit performs the inversion write based on the number of the first logic states in the write data of each of the memory cells of the memory cell block when the temperature is higher than a predetermined threshold. (6) The memory device according to (4), wherein the write circuit performs the inversion write based on the number of the second logic states in the write data of each of the memory cells of the memory cell block when the temperature is lower than a predetermined threshold.(7) The memory device according to any one of (1) to (6), further comprising a write information holding unit that holds inversion write information, which is information on the inversion write, and wherein the write circuit causes the write information holding unit to hold the inversion write information when the inversion write is performed. (8) The memory device according to (7), further comprising a read data conversion unit that converts the logical state of data read from the memory cell block based on the inversion write information of the write information holding unit. (9) The memory device according to (7), which outputs data simultaneously read from each memory cell of the memory cell block and the inversion write information of the write information holding unit as read data. (10) The memory device according to (1), wherein the write circuit performs the inversion write on a specific memory cell of the memory cell block. (11) The memory device according to (10), wherein the write circuit performs the inversion write on a memory cell corresponding to the most significant bit of the memory cell block as the specific memory cell. (12) A memory system comprising: a memory cell block consisting of a plurality of memory cells each having a variable resistance element and a cell transistor connected in series, and each having either a first logic state or a second logic state written therein; a write circuit that simultaneously writes to each memory cell of the memory cell block and performs writing based on write data and inverted writing that writes data whose logical state is inverted from the write data into the memory cell; and a memory control unit that controls the memory device.

[0087] REFERENCE SIGNS LIST 1 memory system 3 memory control unit 4 memory device 10 memory cell array 30 bit line control circuit 50 bit line address decoder 80 write circuit 81, 86 determination unit 82, 87 data conversion unit 85 temperature detection unit 100 memory cell 101 first terminal 102 second terminal 110, 111 cell transistor 120 memory element 150, 151 write information holding unit 200 memory cell block

Claims

1. A memory device having a memory cell block composed of a plurality of memory cells each having a variable resistance element and a cell transistor connected in series, and each having either a first logic state or a second logic state written thereto, and a write circuit which simultaneously writes to each memory cell of the memory cell block and performs both writing based on write data and inverted writing, which writes data whose logic state is the inverted version of the write data into the memory cell.

2. The memory cell is configured such that one of the drain and source of the cell transistor is connected to one terminal of the variable resistance element, and is provided with a first terminal to which the other of the drain and source of the cell transistor is connected and a second terminal connected to the other terminal of the variable resistance element, wherein the first logic state is a logic state in which voltages of the same polarity with respect to the first terminal are applied to the second terminal and a control terminal of the cell transistor during writing, and the second logic state is a logic state in which voltages of different polarities with respect to the first terminal are applied to the second terminal and a control terminal of the cell transistor during writing.

3. The memory device according to claim 2, wherein said write circuit performs said inversion write based on the number of said first logic states in the write data of each of said memory cells in said memory cell block.

4. The memory device according to claim 2, further comprising a temperature detection unit that detects the temperature of the memory cell block, wherein the write circuit performs the inverse write based on the temperature.

5. The memory device according to claim 4, wherein the write circuit performs the inversion write based on the number of the first logic states in the write data of each of the memory cells in the memory cell block when the temperature is higher than a predetermined threshold.

6. The memory device according to claim 4, wherein the write circuit performs the inversion write based on the number of the second logic states in the write data of each of the memory cells in the memory cell block when the temperature is lower than a predetermined threshold.

7. The memory device according to claim 1, further comprising a write information holding unit that holds inversion write information, which is information about the inversion write, and wherein the write circuit causes the write information holding unit to hold the inversion write information when the inversion write is performed.

8. The memory device according to claim 7, further comprising a read data conversion section for converting the logical state of data read from said memory cell block based on the inverted write information of said write information holding section.

9. The memory device according to claim 7, wherein data simultaneously read from each memory cell of said memory cell block and the inverted write information of said write information holding section are output as read data.

10. The memory device according to claim 1, wherein said write circuit performs said inversion write to a specific memory cell in said memory cell block.

11. The memory device according to claim 10, wherein said write circuit performs said inversion write by treating a memory cell corresponding to the most significant bit of said memory cell block as said specific memory cell.

12. A memory system comprising: a memory cell block consisting of a plurality of memory cells each having a variable resistance element and a cell transistor connected in series, and each having either a first logic state or a second logic state written therein; a write circuit that simultaneously writes to each memory cell of the memory cell block and performs writing based on write data and inverted writing, in which data whose logical state is inverted from the write data is written to the memory cell; and a memory control unit that controls the memory device.

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