Display substrate, preparation method therefor, and display apparatus

Abstract

A display substrate, a preparation method therefor, and a display apparatus. The display substrate comprises a plurality of sub-pixels. At least one of the sub-pixels comprises a pixel driving circuit. The pixel driving circuit at least comprises a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a first shield electrode (71), and a second shield electrode (72). A first electrode of the fourth transistor (T4) is coupled to a second power line (82). The second power line (82) is disposed on the side of the fourth transistor (T4) away from the third transistor (T3). The first shield electrode (71) and the second shield electrode (72) are respectively disposed on two sides of the fourth transistor (T4) and are connected to the second power line (82). The first shield electrode (71), the second shield electrode (72), and the second power line (82) form a first shield structure surrounding the fourth transistor (T4) on three sides.

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and particularly relates to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] Micro Organic Light-Emitting Diode (Micro-OLED) is a micro display developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED not only can realize active addressing of pixels, but also can realize preparation of pixel driving circuit structure on a silicon-based substrate, which is conducive to reducing the system volume and realizing light weight. Silicon-based OLED has the advantages of small volume, high resolution, high refresh rate and the like, and is widely applied in virtual reality or augmented reality near-eye display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of protection of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit comprising at least a first transistor, a second transistor, a third transistor and a fourth transistor, a first electrode of the first transistor being coupled with a data signal line, a second electrode of the first transistor being coupled with a gate electrode of the third transistor, a first electrode of the second transistor being coupled with a first power supply line, a second electrode of the second transistor being coupled with a first electrode of the third transistor, a first electrode of the fourth transistor being coupled with a second power supply line, a second electrode of the fourth transistor being coupled with a second electrode of the third transistor, the first power supply line being configured to provide a first power supply signal to the pixel driving circuit, the second power supply line being configured to provide a second power supply signal to the pixel driving circuit; a shape of the second power supply line is linear or polygonal extending along a first direction, and the second power supply line is disposed on a side of the fourth transistor away from the third transistor, a shape of the data signal line is linear or polygonal extending along a second direction, the first direction and the second direction intersecting; in at least one sub-pixel, the pixel driving circuit further comprises a first shielding electrode and a second shielding electrode, the first shielding electrode and the second shielding electrode are respectively disposed on two sides of the fourth transistor in the first direction, and are respectively connected with the second power supply line, the first shielding electrode, the second shielding electrode and the second power supply line form a first shielding structure surrounding the fourth transistor on three sides; the first shielding electrode has a first electrode length, the second shielding electrode has a second electrode length, a ratio of the first electrode length to the second electrode length is 0.95 to 1.05, and the first electrode length and the second electrode length are dimensions in the second direction.

[0006] In an exemplary embodiment, the fourth transistor comprises at least a fourth gate electrode; the first shielding electrode is disposed between two adjacent fourth gate electrodes in the first direction; a first end of the first shielding electrode is connected with the second power supply line, and a second end of the first shielding electrode is connected with a first electrode of the fourth transistor after extending along the second direction or an opposite direction of the second direction.

[0007] In an exemplary embodiment, a second electrode of the third transistor is connected with a second electrode of the fourth transistor through a third node electrode; the second shielding electrode is disposed between two adjacent third node electrodes in the first direction; a first end of the second shielding electrode is connected with the second power supply line, and a second end of the second shielding electrode extends along the second direction or an opposite direction of the second direction.

[0008] In an example embodiment, the third node electrode comprises at least a first sub-electrode, a second sub-electrode and a third sub-electrode, the first and third sub-electrodes are in the shape of a strip extending along the first direction, the second sub-electrode is in the shape of a strip extending along the second direction, and the two ends of the second sub-electrode are connected to the first and third sub-electrodes respectively, forming a "C" shape; the first sub-electrode is connected to the second electrode of the third transistor, and the third sub-electrode is connected to the second electrode of the fourth transistor, and the orthographic projection of the third sub-electrode on the display substrate plane at least partially overlaps the fourth gate electrode of the fourth transistor.

[0009] In an example embodiment, the third node electrode further comprises a fourth sub-electrode, the fourth sub-electrode is in the shape of a strip extending along the first direction, and is arranged on the side of the second sub-electrode away from the third sub-electrode and connected to the second sub-electrode; the third sub-electrode has a first extension length, and the fourth sub-electrode has a second extension length, the first extension length is greater than the second extension length, the first extension length is the distance between the end of the third sub-electrode away from the second sub-electrode and the second sub-electrode, and the second extension length is the distance between the end of the fourth sub-electrode away from the second sub-electrode and the second sub-electrode.

[0010] In an example embodiment, the first power supply line is in the shape of a straight line or a broken line extending along the first direction, and is arranged on the side of the third transistor away from the fourth transistor; in at least one sub-pixel, the pixel driving circuit further comprises a third shielding electrode and a fourth shielding electrode, the third and fourth shielding electrodes are arranged on the two sides of the third transistor in the first direction respectively, and are connected to the first power supply line respectively, the third shielding electrode, the fourth shielding electrode and the first power supply line form a second shielding structure surrounding the third transistor on four sides.

[0011] In an example embodiment, the third shielding electrode comprises at least a first vertical electrode and a first horizontal electrode, the first end of the first vertical electrode is connected to the first power supply line, the second end of the first vertical electrode extends towards the fourth transistor and is connected to the first end of the first horizontal electrode, and the second end of the first horizontal electrode extends towards the fourth shielding electrode; the fourth shielding electrode comprises at least a second vertical electrode and a second horizontal electrode, the first end of the second vertical electrode is connected to the first power supply line, the second end of the second vertical electrode extends towards the fourth transistor and is connected to the first end of the second horizontal electrode, and the second end of the second horizontal electrode extends towards the third shielding electrode.

[0012] In an exemplary embodiment, the first vertical electrode is disposed between gate electrodes of two third transistors adjacent in the first direction, and the first horizontal electrode is disposed between the third transistor and the fourth transistor.

[0013] In an exemplary embodiment, a second electrode of the first transistor is connected to a gate electrode of the third transistor through a first node electrode; the second vertical electrode is disposed between two first node electrodes adjacent in the first direction, and the second horizontal electrode is disposed between the third transistor and the fourth transistor.

[0014] In an exemplary embodiment, in at least one pixel row, part of adjacent sub-pixels share the same first vertical electrode, one first vertical electrode and two first horizontal electrodes in two sub-pixels are an integrated structure connected to each other, forming a "T" shape.

[0015] In an exemplary embodiment, in at least one pixel row, part of adjacent sub-pixels share the same second vertical electrode, one second vertical electrode and two second horizontal electrodes in two sub-pixels are an integrated structure connected to each other, forming a "T" shape.

[0016] In an exemplary embodiment, the third transistor includes at least a third active region, and the fourth transistor includes at least a fourth active region; the first horizontal electrode or the second horizontal electrode has a first distance from the third active region, and the first horizontal electrode or the second horizontal electrode has a second distance from the fourth active region, the first distance being smaller than the second distance; the first distance is a distance between an edge of the first horizontal electrode or the second horizontal electrode close to the third active region and an edge of the third active region close to the first horizontal electrode or the second horizontal electrode, and the second distance is a distance between an edge of the first horizontal electrode or the second horizontal electrode close to the fourth active region and an edge of the fourth active region close to the first horizontal electrode or the second horizontal electrode.

[0017] In an example embodiment, in at least one of the sub-pixels, the first lateral electrode has a first shielding length, the second lateral electrode has a second shielding length, and the first vertical electrode and the second vertical electrode have a third shielding length, and a ratio of a sum of the first shielding length and the second shielding length to the third shielding length is greater than or equal to 0.6; wherein the first shielding length is a distance between an end of the first lateral electrode away from the first vertical electrode and the first vertical electrode, the second shielding length is a distance between an end of the second lateral electrode away from the second vertical electrode and the second vertical electrode, and the third shielding length is a distance between an edge of the first vertical electrode close to the second vertical electrode and an edge of the second vertical electrode close to the first vertical electrode.

[0018] In an example embodiment, the pixel driving circuit further includes a first node electrode and a first capacitor, a second electrode of the first transistor is connected to a gate electrode of the third transistor through the first node electrode, and the first capacitor includes at least a first plate and a second plate, the gate electrode of the third transistor serves as the first plate, a normal projection of the second plate on a display substrate plane at least partially overlaps a normal projection of the first plate on the display substrate plane, a second plate connecting block is disposed on the second plate, the second plate connecting block is disposed on a side of the second plate close to the first node electrode and connected to the second plate, the second plate connecting block has a block shape, the first node electrode has a "C" shape, and the second plate connecting block and the first node electrode form an interdigital structure.

[0019] In an example embodiment, the first node electrode includes at least a fifth sub-electrode, a sixth sub-electrode, and a seventh sub-electrode, the fifth sub-electrode and the seventh sub-electrode have a strip shape extending along the first direction, the sixth sub-electrode has a strip shape extending along the second direction, and two ends of the sixth sub-electrode are connected to the fifth sub-electrode and the seventh sub-electrode, respectively, the seventh sub-electrode and the second plate have a first electrode spacing, the second plate connecting block and the sixth sub-electrode have a second electrode spacing, the first electrode spacing and the second electrode spacing are dimensions in the first direction, and the second electrode spacing is greater than the first electrode spacing.

[0020] In an exemplary embodiment, the third transistor comprises at least a third active region; the seventh sub-electrode comprises a first region and a second region, a projection of the first region on a display substrate plane at least partially overlaps a projection of the third active region on the display substrate plane, a projection of the second region on the display substrate plane does not overlap a projection of the third active region on the display substrate plane; the first region has a fourth extension length, the second region has a fifth extension length, the fourth extension length and the fifth extension length are dimensions in the first direction; the fifth extension length is less than the fourth extension length, and the fifth extension length is greater than 0.5 times the fourth extension length.

[0021] In an exemplary embodiment, in at least one unit row, pixel driving circuits in adjacent sub-pixels are symmetrically arranged with respect to a first center line, in at least one unit column, pixel driving circuits in adjacent sub-pixels are symmetrically arranged with respect to a second center line, the first center line is a straight line located between adjacent pixel rows and extending along the first direction, and the second center line is a straight line located between adjacent pixel columns and extending along the second direction.

[0022] In an exemplary embodiment, the first transistor comprises at least a first gate electrode, the second transistor comprises at least a second gate electrode, in at least one unit row, the first gate electrodes of some adjacent sub-pixels are an integral structure connected to each other, and the second gate electrodes of some adjacent sub-pixels are an integral structure connected to each other.

[0023] In another aspect, the present disclosure also provides a display device comprising the foregoing display substrate.

[0024] In yet another aspect, the present disclosure also provides a preparation method of a display substrate, the display substrate comprising a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns; the preparation method comprising:

[0025] A pixel driving circuit is formed in at least one sub-pixel, the pixel driving circuit at least includes a first transistor, a second transistor, a third transistor and a fourth transistor, a first electrode of the first transistor is coupled with a data signal line, a second electrode of the first transistor is coupled with a gate electrode of the third transistor, a first electrode of the second transistor is coupled with a first power supply line, a second electrode of the second transistor is coupled with a first electrode of the third transistor, a first electrode of the fourth transistor is coupled with a second power supply line, a second electrode of the fourth transistor is coupled with a second electrode of the third transistor, the first power supply line is configured to provide a first power supply signal to the pixel driving circuit, the second power supply line is configured to provide a second power supply signal to the pixel driving circuit; a shape of the second power supply line is linear or zigzag along a first direction, and the second power supply line is arranged on a side of the fourth transistor away from the third transistor, a shape of the data signal line is linear or zigzag along a second direction, the first direction and the second direction intersect; in at least one sub-pixel, the pixel driving circuit further includes a first shielding electrode and a second shielding electrode, the first shielding electrode and the second shielding electrode are arranged on two sides of the fourth transistor in the first direction respectively, and are connected with the second power supply line respectively, the first shielding electrode, the second shielding electrode and the second power supply line form a first shielding structure surrounding the fourth transistor on three sides; the first shielding electrode has a first electrode length, the second shielding electrode has a second electrode length, a ratio of the first electrode length to the second electrode length is 0.95 to 1.05, and the first electrode length and the second electrode length are dimensions in the second direction.

[0026] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and serve to explain the principles of the present disclosure, and do not limit the present disclosure. The shapes and sizes of the components in the drawings do not reflect true proportions, but are intended to schematically illustrate the present disclosure.

[0028] FIG. 1 is a structural schematic diagram of a silicon-based OLED display device;

[0029] FIG. 2 is a plan structural schematic diagram of a display area in a silicon-based OLED display device;

[0030] FIG. 3 is a cross-sectional structural schematic diagram of a display area in a silicon-based OLED display device;

[0031] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit;

[0032] FIG. 5 is a driving timing diagram of the pixel driving circuit shown in FIG. 4;

[0033] FIG. 6 is a plan view of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] FIG. 7 is a schematic view of the display substrate after forming a pattern of N-well regions, P-well regions, and active regions according to an exemplary embodiment of the present disclosure;

[0035] FIGS. 8A and 8B are schematic views of the display substrate after forming a pattern of gate conductive layers according to an exemplary embodiment of the present disclosure;

[0036] FIGS. 9A and 9B are schematic views of the display substrate after forming a pattern of N-type doped regions according to an exemplary embodiment of the present disclosure;

[0037] FIGS. 10A and 10B are schematic views of the display substrate after forming a pattern of P-type doped regions according to an exemplary embodiment of the present disclosure;

[0038] FIG. 11 is a schematic view of the display substrate after forming a pattern of a second insulating layer according to an exemplary embodiment of the present disclosure;

[0039] FIGS. 12A and 12B are schematic views of the display substrate after forming a pattern of a first conductive layer according to an exemplary embodiment of the present disclosure;

[0040] FIG. 13 is a schematic view of the display substrate after forming a pattern of a third insulating layer according to an exemplary embodiment of the present disclosure;

[0041] FIGS. 14A and 14B are schematic views of the display substrate after forming a pattern of a second conductive layer according to an exemplary embodiment of the present disclosure;

[0042] FIGS. 15A and 15B are schematic views of the display substrate after forming a pattern of a fourth insulating layer and a third conductive layer according to an exemplary embodiment of the present disclosure;

[0043] FIG. 16 is a schematic view of the display substrate after forming a pattern of a fifth insulating layer according to an exemplary embodiment of the present disclosure;

[0044] FIGS. 17A and 17B are schematic views of the display substrate after forming a pattern of a fourth conductive layer according to an exemplary embodiment of the present disclosure;

[0045] FIGS. 18A and 18B are schematic views of the display substrate after forming a pattern of a sixth insulating layer and a fifth conductive layer according to an exemplary embodiment of the present disclosure;

[0046] FIG. 19 is a schematic view of the display substrate after forming a pattern of a seventh insulating layer according to an exemplary embodiment of the present disclosure;

[0047] FIGS. 20A and 20B are schematic views of the display substrate after forming a pattern of a sixth conductive layer according to an exemplary embodiment of the present disclosure;

[0048] FIG. 21 is a schematic view of the display substrate after forming a pattern of an eighth insulating layer according to an exemplary embodiment of the present disclosure;

[0049] FIGS. 22A and 22B are schematic views of the display substrate after forming a pattern of a seventh conductive layer according to an exemplary embodiment of the present disclosure;

[0050] FIG. 23 is a structural schematic diagram of a first capacitor and a second capacitor according to an embodiment of the present disclosure.

[0051] Legend of reference signs:

[0052] 10A - N-well region; 10B - P-well region; 11 - first active region;

[0053] 12 - second active region; 13 - third active region; 14 - fourth active region;

[0054] 15 - first power region; 16 - second power region; 20A - N-type doped region;

[0055] 20B - P-type doped region; 21 - first gate electrode; 22 - second gate electrode;

[0056] 24 - fourth gate electrode; 31 - first scan signal line; 32 - second scan signal line;

[0057] 33 - third scan signal line; 41 - first connection electrode; 42 - second connection electrode;

[0058] 43 - first node electrode; 44 - fourth connection electrode; 45 - third node electrode;

[0059] 51 - eleventh connection electrode; 52 - twelfth connection electrode; 53 - thirteenth connection electrode;

[0060] 54 - fourteenth connection electrode; 55 - fifteenth connection electrode; 61 - twenty-first connection electrode;

[0061] 62 - twenty-second connection electrode; 63 - twenty-third connection electrode; 71 - first shielding electrode;

[0062] 72 - second shielding electrode; 73 - third shielding electrode; 74 - fourth shielding electrode;

[0063] 81 - first power line; 82 - second power line; 83 - data signal line;

[0064] 84 - anode connecting electrode; 91 - first connecting line; 92 - second connecting line;

[0065] 93 - third connecting line; 94 - fourth connecting line; 95 - fifth connecting line;

[0066] 96 - sixth connecting line; 97 - seventh connecting line; 101 - silicon substrate;

[0067] 102 - driving circuit layer; 103 - light emitting structure layer; 104 - first encapsulation layer;

[0068] 105 - color film structure layer; 106 - second encapsulation layer; 107 - cover plate layer;

[0069] 110 - first electrode plate; 120 - second electrode plate; 130 - third electrode plate;

[0070] 140 - fourth electrode plate; 150 - fifth electrode plate; 160 - sixth electrode plate;

[0071] 170 - electrode plate connecting electrode; 201 - first insulating layer; 202 - second insulating layer;

[0072] 203 - third insulating layer; 204 - fourth insulating layer; 205 - fifth insulating layer;

[0073] 206 - sixth insulating layer; 207 - seventh insulating layer; 208 - eighth insulating layer. DETAILED DESCRIPTION

[0074] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically describe the embodiments of the present disclosure with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. Those skilled in the art can easily understand that the manners and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other in any manner without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the detailed description of some known functions and known components is omitted. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the general design.

[0075] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0076] In the present specification, ordinal numbers such as "first", "second", and "third" are provided to avoid confusion of components, and are not intended to be limiting in terms of number.

[0077] In the present specification, in order to facilitate the description and simplify the description, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0078] In the present specification, unless specifically defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0079] In this specification, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region refers to a region where current flows mainly.

[0080] In this specification, in order to distinguish between two terminals of a transistor other than the gate electrode, one of the terminals is directly described as a first terminal and the other is directly described as a second terminal, where the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. In the case of using a transistor with opposite polarity or in the case where the direction of current flow is changed in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0081] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between the components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having various functions.

[0082] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0083] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, a "insulating film" can be replaced with an "insulating layer".

[0084] In this specification, "formation in the same layer" refers to a structure formed by patterning two (or more) kinds of structures in the same patterning process, and the materials thereof can be the same or different. For example, the materials of precursors for forming the plurality of structures in the same layer are the same, and the materials finally formed can be the same or different.

[0085] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, and deformation.

[0086] In the present disclosure, "about" means not strictly limited to the boundary, allowing values within the range of process and measurement errors.

[0087] FIG. 1 is a structural schematic diagram of a silicon-based OLED display device. As shown in FIG. 1, the silicon-based OLED display device can include a display area and a non-display area. The display area can include a plurality of scanning signal lines, a plurality of data signal lines, and a plurality of sub-pixels Pxij forming a plurality of pixel rows and a plurality of pixel columns, the plurality of scanning signal lines are respectively arranged in the plurality of pixel rows, and the plurality of data signal lines are respectively arranged in the plurality of pixel columns. Each sub-pixel Pxij can include at least a pixel driving circuit and a light-emitting device, the pixel driving circuit is configured to provide a current required for light emission to the connected light-emitting device, the pixel driving circuit of each sub-pixel Pxij can be connected to the scanning signal line of the corresponding pixel row and the data signal line of the corresponding pixel column, the sub-pixel Pxij can refer to the sub-pixel of the i-th pixel row and the j-th pixel column, the pixel driving circuit of the sub-pixel Pxij is connected to the i-th scanning signal line and the j-th data signal line respectively, and i and j can be natural numbers. The non-display area can include at least a gate driver (GD) and a source driver (SD), the gate driver is connected to the plurality of scanning signal lines in the display area respectively, and the gate driver is configured to provide a required timing signal to the connected pixel driving circuit to realize a row-by-row scanning function. The source driver is connected to the plurality of data signal lines in the display area respectively, and the source driver is configured to provide a required data signal to the connected pixel driving circuit to realize switching and control of a display picture.

[0088] In an exemplary embodiment, the silicon-based OLED display device can be a one chip display architecture (One Chip), in which a gate driver, a source driver, a clock control circuit, an image processing unit, and a storage unit are integrated on the same chip. The chip of the One Chip architecture includes both digital and analog parts, which belongs to a mixed signal chip.

[0089] In another exemplary embodiment, the silicon-based OLED display device can be a two chip display architecture (Two Chip), in which a gate driver and a source driver are integrated in a display substrate, and a clock control circuit, an image processing unit, a mobile industry processor interface (MIPI), and a storage unit are integrated in a chip, which is connected to the display substrate by a COC process and bonding.

[0090] FIG. 2 is a schematic diagram of a planar structure of a display region in a silicon-based OLED display device. As shown in FIG. 2, in a direction parallel to the plane of the display device, the display region can include a plurality of pixel units P arranged in a matrix manner, at least one pixel unit P can include a first sub-pixel P1 emitting light of a first color, a second sub-pixel P2 emitting light of a second color, and a third sub-pixel P3 emitting light of a third color, each of the three sub-pixels can include a pixel driving circuit and a light-emitting device, the pixel driving circuit in each sub-pixel is connected to a scan signal line and a data signal line, respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in each sub-pixel is connected to the pixel driving circuit in the sub-pixel, and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit in the sub-pixel.

[0091] In exemplary embodiments, the first sub-pixel P1 can be a red (R) sub-pixel emitting red light, the second sub-pixel P2 can be a blue (B) sub-pixel emitting blue light, and the third sub-pixel P3 can be a green (G) sub-pixel emitting green light.

[0092] In exemplary embodiments, the shape of the sub-pixel can be any one or more of a triangle, a square, a rectangle, a diamond, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, and the three sub-pixels can be arranged in a horizontal side-by-side manner, a vertical side-by-side manner, a triangular shape, etc., which are not limited in the present disclosure. In other possible implementations, the pixel unit can include four sub-pixels, which are not limited in the present disclosure.

[0093] FIG. 3 is a schematic diagram of a cross-sectional structure of a display region in a silicon-based OLED display device, illustrating a structure for realizing full color using white light + color film. As shown in FIG. 3, in a direction perpendicular to the display device, the silicon-based OLED display device can include a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on a side of the light-emitting structure layer 103 away from the silicon substrate 101, a color film structure layer 105 disposed on a side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on a side of the color film structure layer 105 away from the silicon substrate 101, and a cover plate layer 107 disposed on a side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device can include other film layers, which are not limited in the present disclosure.

[0094] In an example embodiment, the silicon substrate 101 can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 can be prepared on the silicon substrate 101 by a silicon semiconductor process, and can include a plurality of circuit units, which can at least include a pixel driving circuit, the pixel driving circuit being connected to a scanning signal line and a data signal line respectively, and the pixel driving circuit including a plurality of transistors and a storage capacitor, only one transistor being taken as an example in FIG. 3. The transistor can include a gate electrode G, a source electrode S and a drain electrode D, the gate electrode G, the source electrode S and the drain electrode D being connected to corresponding connection electrodes respectively through tungsten metal filled vias (i.e., tungsten vias, W-vias), and being connected to other electrical structures (such as a trace, etc.) through the connection electrodes.

[0095] In an example embodiment, the light emitting structure layer 103 can include a plurality of light emitting devices, which can at least include an anode, an organic light emitting layer and a cathode, the anode being connected to the drain electrode D of the transistor through a connection electrode, the organic light emitting layer being connected to the anode, the cathode being connected to the organic light emitting layer, the cathode being connected to a second power supply line, and the organic light emitting layer emitting light under the driving of the anode and the cathode. In an example embodiment, the organic light emitting layer can include an emission layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL). In an example embodiment, for a light emitting device emitting white light, the organic light emitting layers of all sub-pixels can be a common layer connected together.

[0096] In an example embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can adopt a thin film encapsulation (TFE) mode, which can ensure that external water vapor cannot enter the light emitting structure layer. The color film structure layer 105 can at least include a red filter unit, a blue filter unit and a green filter unit, the red filter unit being arranged in a red sub-pixel to filter white light emitted by the light emitting device into red light, the blue filter unit being arranged in a blue sub-pixel to filter white light emitted by the light emitting device into blue light, and the green filter unit being arranged in a green sub-pixel to filter white light emitted by the light emitting device into green light. The cover plate layer 107 can be made of glass or a plastic-based colorless polyimide having a flexible property.

[0097] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in FIG. 4, the pixel driving circuit is a current type 4T2C structure, which can include 4 transistors (a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4) and 2 storage capacitors (a first capacitor C1 and a second capacitor C2), and is coupled with 6 signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DATA, a first power supply line VDD, and a second power supply line VSS).

[0098] In an exemplary embodiment, the pixel driving circuit can include a first node N1, a second node N2, and a third node N3. The first node N1 is coupled with a second electrode of the first transistor T1, a gate electrode of the third transistor T3, and a first end of the first capacitor C1, respectively. The second node N2 is coupled with a second electrode of the second transistor T2, a first electrode of the third transistor T3, a second end of the first capacitor C1, and a first end of the second capacitor C2, respectively. The third node N3 is coupled with a second electrode of the third transistor T3, a second electrode of the fourth transistor T4, and a second end of the second capacitor C2, respectively.

[0099] In an exemplary embodiment, a signal of the first scan signal line S1 can be a write switch (WS) signal, and the first scan signal line S1 can also be referred to as a write switch signal line WS. A signal of the second scan signal line S2 can be a display switch (DS) signal, and the second scan signal line S2 can also be referred to as a display switch signal line DS. A signal of the third scan signal line S3 can be an auto zero (AZ) signal, and the third scan signal line S3 can also be referred to as an auto zero signal line AZ.

[0100] In an exemplary embodiment, the first transistor T1 can be referred to as a source driver transistor or a data write transistor, a gate electrode of the first transistor T1 is coupled with the first scan signal line S1, a first electrode of the first transistor T1 is coupled with the data signal line DATA, and a second electrode of the first transistor T1 is coupled with the first node N1.

[0101] In an exemplary embodiment, the second transistor T2 can be referred to as a threshold voltage (Vth) compensation transistor, a gate electrode of the second transistor T2 is coupled with the second scan signal line S2, a first electrode of the second transistor T2 is coupled with the first power supply line VDD, and a second electrode of the second transistor T2 is coupled with the second node N2.

[0102] In an example embodiment, the third transistor T3 can be referred to as a driver transistor, a gate electrode of the third transistor T3 is coupled to the first node N1, a first electrode of the third transistor T3 is coupled to the second node N2, and a second electrode of the third transistor T3 is coupled to the third node N3.

[0103] In an example embodiment, the fourth transistor T4 can be referred to as an auto zero transistor, a gate electrode of the fourth transistor T4 is coupled to the third scan signal line S3, a first electrode of the fourth transistor T4 is coupled to the second power supply line VSS, and a second electrode of the fourth transistor T4 is coupled to the third node N3.

[0104] In an example embodiment, a first end of the first capacitor C1 is coupled to the first node N1, and a second end of the first capacitor C1 is coupled to the second node N2. A first end of the second capacitor C2 is coupled to the second node N2, and a second end of the second capacitor C2 is coupled to the third node N3.

[0105] In an example embodiment, the light emitting device EL can be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked. The first electrode of the light emitting device EL is connected to the third node N3, and the second electrode of the light emitting device EL is connected to the common voltage line VCOM.

[0106] In an example embodiment, a signal of the first power supply line VDD can be a first power supply signal (high level signal) continuously provided, a signal of the second power supply line VSS can be a second power supply signal (low level signal) continuously provided, a voltage of the first power supply signal is greater than a voltage of the second power supply signal, and a signal of the common voltage line VCOM can be a low level signal continuously provided.

[0107] In an example embodiment, the first transistor T1 to the third transistor T3 can be P-type transistors, and the fourth transistor T4 can be an N-type transistor.

[0108] FIG. 5 is a driving timing diagram of the pixel driving circuit shown in FIG. 4. In an example embodiment, the working process of the pixel driving circuit can include:

[0109] The first stage A1 can be called a reset stage. The signals of the first scan signal line S1 and the second scan signal line S2 are low signals, and the signal of the third scan signal line S3 is a high signal, so that the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on. The first transistor T1 is turned on, so that the bias voltage Vofs output by the data signal line DATA is written into the first capacitor C1, the potential Vg of the first node N1 (i.e. the gate electrode of the third transistor T3) is Vofs, the second transistor T2 is turned on, so that the first power voltage ELVDD output by the first power supply line VDD is written into the second node N2, the potential Vs of the second node N2 (i.e. the first electrode of the third transistor T3) is ELVDD, and the potential Vd of the third node N3 (i.e. the second electrode of the third transistor T3) is Vg+Vth. At this time, the gate-source voltage Vgs of the third transistor T3 is Vcs=ELVDD-Vofs, and Vcs is the storage voltage of the first capacitor C1. ELVDD-V ofs >|Vth|, for the next stage of discharging, and Vth is the threshold voltage of the third transistor T3.

[0110] The second stage A2 can be called a self-discharge stage. The signal of the third scan signal line S3 is a high signal, and the fourth transistor T4 is continuously turned on. The signal of the first scan signal line S1 changes from a low signal to a high signal, so that the first transistor T1 is first turned off, and the first node N1 is floating. Subsequently, the signal of the second scan signal line S2 changes from a low signal to a high signal, so that the second transistor T2 is turned off, the second node N2 forms a loop through the turned-on third transistor T3, the third node N3 and the turned-on fourth transistor T4, and starts discharging, and the potential of the second node N2 decreases. Because the first node N1 is floating, the voltage difference across the first capacitor C1 does not change, so that the potential of the first node N1 decreases with the potential of the second node N2.

[0111] Due to the back gate effect of the third transistor T3, the equivalent threshold voltage |V th_EF | of the third transistor T3 is α(ELVDD-Vs)+|Vth|. As the potential Vs of the second node N2 decreases, the equivalent threshold voltage |V th_EF | of the third transistor T3 gradually increases, and when the equivalent threshold voltage |V th_EF | of the third transistor T3 increases to the gate-source voltage Vgs of the third transistor T3, the third transistor T3 is turned off, and the discharging of the second node N2 stops.

[0112] The third stage A3 can be referred to as a data writing stage and a threshold compensation stage. The signal of the third scan signal line S3 is a high level signal, and the fourth transistor T4 is continuously turned on. The signal of the second scan signal line S2 is a high level signal, and the second transistor T2 is continuously turned off. The signal of the first scan signal line S1 changes from a high level signal to a low level signal, so that the first transistor T1 is turned on. The turning on of the first transistor T1 enables the data voltage Vdata output by the data signal line DATA to be written to the first node N1, and the potential of the first node N1 changes from Vofs to Vdata. Since the second node N2 is floating, threshold compensation can be achieved.

[0113] The fourth stage A4 can be referred to as a light emitting stage. The signals of the second scan signal line S2 and the third scan signal line S3 are low level signals, and the signal of the first scan signal line S1 is a high level signal, so that the second transistor T2 is turned on, and the first transistor T1 and the fourth transistor T4 are turned off. The turning on of the second transistor T2 enables the power supply voltage output by the first power supply line VDD to be provided to the first electrode of the light emitting device EL through the turned-on second transistor T2 and the third transistor T3, so as to drive the light emitting device EL to emit light.

[0114] In the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, so that the influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, the display brightness uniformity of the display product is ensured, and the display effect of the entire display product is improved.

[0115] At present, silicon-based OLED display devices are gradually applied to virtual reality (VR), augmented reality (AR), extended reality (XR) equipment, mixed reality (MR) equipment and other near-eye display fields, so that users can experience real feelings in a virtual reality world, have a super strong simulation system, and realize human-computer interaction. Research shows that when the screen resolution is high enough, the human eye retina cannot distinguish the pixel points. The resolution (Pixels Per Inch, PPI) refers to the number of pixels per unit area, which can be referred to as pixel density. The higher the PPI value, the higher the density at which the display substrate can display a picture, and the more details the picture has. Therefore, in order to improve the display quality, greatly improving the PPI has become the research focus of various manufacturers. The silicon-based OLED is prepared by using a semiconductor process. With the increase of PPI, the crosstalk and interference between sub-pixels gradually increase, which reduces the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0116] The exemplary embodiments of the present disclosure provide a display substrate, comprising a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit comprising at least a first transistor, a second transistor, a third transistor and a fourth transistor, a first electrode of the first transistor being coupled with a data signal line, a second electrode of the first transistor being coupled with a gate electrode of the third transistor, a first electrode of the second transistor being coupled with a first power supply line, a second electrode of the second transistor being coupled with a first electrode of the third transistor, a first electrode of the fourth transistor being coupled with a second power supply line, a second electrode of the fourth transistor being coupled with a second electrode of the third transistor, the first power supply line being configured to provide a first power supply signal to the pixel driving circuit, the second power supply line being configured to provide a second power supply signal to the pixel driving circuit, a voltage of the first power supply signal being greater than a voltage of the second power supply signal; the second transistor and the fourth transistor are respectively disposed on two sides of the third transistor in a second direction, the second power supply line being in a shape of a straight line or a broken line extending along a first direction and being disposed on a side of the fourth transistor away from the third transistor, the first direction and the second direction intersecting; in at least one sub-pixel, the pixel driving circuit further comprises a first shielding electrode and a second shielding electrode, the first shielding electrode and the second shielding electrode are respectively disposed on two sides of the fourth transistor in the first direction and are respectively connected with the second power supply line, the first shielding electrode, the second shielding electrode and the second power supply line forming a first shielding structure surrounding the fourth transistor on three sides.

[0117] In the exemplary embodiments, the first power supply line is in a shape of a straight line or a broken line extending along the first direction and is disposed on a side of the third transistor away from the fourth transistor; in at least one sub-pixel, the pixel driving circuit further comprises a third shielding electrode and a fourth shielding electrode, the third shielding electrode and the fourth shielding electrode are respectively disposed on two sides of the third transistor in the first direction and are respectively connected with the first power supply line, the third shielding electrode, the fourth shielding electrode and the first power supply line forming a second shielding structure surrounding the third transistor on four sides.

[0118] In an exemplary embodiment, the third transistor includes at least a third active region, and the fourth transistor includes at least a fourth active region; the first lateral electrode or the second lateral electrode has a first distance from the third active region, and has a second distance from the fourth active region, the first distance being less than the second distance; the first distance is a distance between an edge of the first lateral electrode or the second lateral electrode close to a side of the third active region and an edge of the third active region close to the first lateral electrode or the second lateral electrode, and the second distance is a distance between an edge of the first lateral electrode or the second lateral electrode close to a side of the fourth active region and an edge of the fourth active region close to the first lateral electrode or the second lateral electrode.

[0119] In an exemplary embodiment, in at least one unit row, pixel driving circuits in adjacent sub-pixels are symmetrically arranged relative to a first center line, and in at least one unit column, pixel driving circuits in adjacent sub-pixels are symmetrically arranged relative to a second center line, the first center line being a straight line located between adjacent pixel rows and extending along the first direction, and the second center line being a straight line located between adjacent pixel columns and extending along the second direction.

[0120] The technical solutions of the display substrate of the present disclosure are described below through exemplary embodiments.

[0121] FIG. 6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the pixel driving circuit structure of 12 sub-pixels in 2 pixel rows (Mth pixel row and (M+1)th pixel row) and 6 pixel columns (Nth pixel column to (N+5)th pixel column). In a plane parallel to the display substrate, the display substrate can include a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, the plurality of sub-pixels in a pixel row can be arranged in sequence along a first direction X, the plurality of sub-pixels in a pixel column can be arranged in sequence along a second direction Y, the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array, and the first direction X and the second direction Y intersect.

[0122] In an example embodiment, the at least one sub-pixel can include a pixel driving circuit, the at least one pixel driving circuit can include at least a first transistor T1 as a source driving transistor, a second transistor T2 as a threshold voltage compensation transistor, a third transistor T3 as a driving transistor, and a fourth transistor T4 as a reset transistor. A first electrode of the first transistor T1 is coupled with a data signal line, a second electrode of the first transistor T1 is coupled with a gate electrode of the third transistor T3, a first electrode of the second transistor T2 is coupled with a first power supply line 81, a second electrode of the second transistor T2 is coupled with a first electrode of the third transistor T3, a first electrode of the fourth transistor T4 is coupled with a second power supply line 82, and a second electrode of the fourth transistor T4 is coupled with a second electrode of the third transistor T3. The data signal line is configured to provide a data signal to the pixel driving circuit, the first power supply line 81 is configured to provide a first power supply signal to the pixel driving circuit, and the second power supply line 82 is configured to provide a second power supply signal to the pixel driving circuit. A voltage of the first power supply signal can be greater than a voltage of the second power supply signal.

[0123] In an example embodiment, in the at least one sub-pixel, the second transistor T2 can be disposed on one side of the first direction X of the first transistor T1 or on the opposite side of the first direction X of the first transistor T1, the first transistor T1 and the second transistor T2 can be disposed on one side of the second direction Y of the third transistor T3, and the fourth transistor T4 can be disposed on the other side of the second direction Y of the third transistor T3, i.e., the second transistor T2 and the fourth transistor T4 can be disposed on two sides of the second direction Y of the third transistor T3, respectively. For example, in the Mth pixel row, the first transistor T1 and the second transistor T2 can be disposed on the opposite side of the second direction Y of the third transistor T3, and the fourth transistor T4 can be disposed on one side of the second direction Y of the third transistor T3. For another example, in the M+1th pixel row, the first transistor T1 and the second transistor T2 can be disposed on one side of the second direction Y of the third transistor T3, and the fourth transistor T4 can be disposed on the opposite side of the second direction Y of the third transistor T3.

[0124] In an example embodiment, the display substrate can include at least a first center line O1 and a second center line O2, the first center line O1 can be a straight line located between adjacent pixel rows and extending along the first direction X, and the second center line O2 can be a straight line located between adjacent pixel columns and extending along the second direction Y. In the at least one pixel row, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in adjacent sub-pixels can be substantially mirror-symmetrical with respect to the first center line O1. In the at least one pixel column, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in adjacent sub-pixels can be substantially mirror-symmetrical with respect to the second center line O2.

[0125] In an exemplary embodiment, four sub-pixels defined by two pixel rows and two pixel columns can be the minimum repeating unit of the display substrate. In the minimum repeating unit, the pixel driving circuit in the four sub-pixels is mirror-symmetrical up and down and mirror-symmetrical left and right.

[0126] In an exemplary embodiment, the first transistor T1 can include at least a first gate electrode 21. In at least one pixel row, two first gate electrodes 21 of part of adjacent sub-pixels can be an integral structure connected to each other.

[0127] In an exemplary embodiment, the second transistor T2 can include at least a second gate electrode 22. In at least one pixel row, two second gate electrodes 22 of part of adjacent sub-pixels can be an integral structure connected to each other.

[0128] In an exemplary embodiment, the fourth transistor T4 can include at least a fourth active region 14 and a fourth gate electrode 24. In at least one pixel row, two fourth active regions in part of adjacent sub-pixels can be an integral structure connected to each other.

[0129] In an exemplary embodiment, the display substrate can further include a first scan signal line 31, a second scan signal line 32, and a third scan signal line, the first scan signal line 31 being connected to the first gate electrode 21 of the first transistor T1, the second scan signal line 32 being connected to the second gate electrode 22 of the second transistor T2, and the third scan signal line being connected to the fourth gate electrode 24 of the fourth transistor T4. The first scan signal line 31 is configured to provide a write switch signal to the pixel driving circuit, the second scan signal line 32 is configured to provide a display switch signal to the pixel driving circuit, and the third scan signal line is configured to provide a display reset signal to the pixel driving circuit. The first scan signal line 31, the second scan signal line 32, and the third scan signal line can have a shape of a straight line or a polyline extending along the first direction X, the first scan signal line 31 and the second scan signal line 32 can be disposed on the same side of the third transistor T3 in the second direction Y, the third scan signal line can be disposed on the other side of the third transistor T3 in the second direction Y, and the second scan signal line 32 can be disposed on the side of the first scan signal line 31 away from the third transistor T3.

[0130] In an exemplary embodiment, the first power supply line 81 can have a shape of a straight line or a polyline extending along the first direction X and can be disposed on the side of the third transistor T3 away from the fourth transistor T4. The second power supply line 82 can have a shape of a straight line or a polyline extending along the first direction X and can be disposed on the side of the fourth transistor T4 away from the third transistor T3.

[0131] In the exemplary embodiment, the pixel driving circuit in the at least one sub-pixel can further include a first shielding electrode 71, a second shielding electrode 72, a third shielding electrode 73, and a fourth shielding electrode 74. The first shielding electrode 71 and the second shielding electrode 72 can be respectively disposed on two sides of the fourth transistor T4 in the first direction X and connected with the second power supply line 82, and the first shielding electrode 71, the second shielding electrode 72, and the second power supply line 82 form a first shielding structure surrounding the fourth transistor T4 on three sides, which is configured to shield the fourth transistor T4 and the third node N3 in the sub-pixel.

[0132] In the exemplary embodiment, the third shielding electrode 73 and the fourth shielding electrode 74 can be respectively disposed on two sides of the third transistor T3 in the first direction X and respectively connected with the first power supply line 81, and the third shielding electrode 73, the fourth shielding electrode 74, and the first power supply line 81 form a second shielding structure surrounding the third transistor T3 on four sides, which is configured to shield the driving transistor and the first node N1 in the sub-pixel.

[0133] In the exemplary embodiment, the first shielding electrode 71 can be disposed between part of the adjacent fourth gate electrodes 24. The shape of the first shielding electrode 71 can be a strip shape extending along the second direction Y, the first end of the first shielding electrode 71 is connected with the second power supply line 82, and the second end of the first shielding electrode 71 extends along the second direction Y or the opposite direction of the second direction Y and is connected with the first electrode of the fourth transistor T4.

[0134] In the exemplary embodiment, the pixel driving circuit can further include a third node electrode 45, the second electrode of the third transistor T3 can be connected with the second electrode of the fourth transistor T4 through the third node electrode 45, and the second shielding electrode 72 can be disposed between part of the adjacent third node electrodes 45. The shape of the second shielding electrode 72 can be a strip shape extending along the second direction Y, the first end of the second shielding electrode 72 is connected with the second power supply line 82, and the second end of the second shielding electrode 72 extends along the second direction Y or the opposite direction of the second direction Y.

[0135] In the example embodiment, the first shielding electrode 71 can have a first electrode length F1, the second shielding electrode 72 can have a second electrode length F2, and the ratio of the first electrode length F1 to the second electrode length F2 can be 0.95 to 1.05. Here, the first electrode length F1 can be the distance between the edge of the first shielding electrode 71 away from the second power line 82 and the edge of the second power line 82 close to the first shielding electrode 71, the second electrode length F2 can be the distance between the edge of the second shielding electrode 72 away from the second power line 82 and the edge of the second power line 82 close to the second shielding electrode 72, and the first electrode length F1 and the second electrode length F2 can be the dimensions in the second direction Y.

[0136] In the example embodiment, the third shielding electrode 73 can include at least a first vertical electrode 73-1 and a first horizontal electrode 73-2, and the fourth shielding electrode 74 can include at least a second vertical electrode 74-1 and a second horizontal electrode 74-2. The first vertical electrode 73-1 and the second vertical electrode 74-1 can have a shape of a strip extending along the second direction Y, and the first horizontal electrode 73-2 and the second horizontal electrode 74-2 can have a shape of a strip extending along the first direction X.

[0137] In the example embodiment, the first end of the first vertical electrode 73-1 is connected to the first power line 81, the second end of the first vertical electrode 73-1 extends in the direction close to the fourth transistor T4 along the second direction Y and is then connected to the first end of the first horizontal electrode 73-2, and the second end of the first horizontal electrode 73-2 extends in the direction close to the second vertical electrode 74-1 along the first direction X. The first end of the second vertical electrode 74-1 is connected to the first power line 81, the second end of the second vertical electrode 74-1 extends in the direction close to the fourth transistor T4 along the second direction Y and is then connected to the first end of the second horizontal electrode 74-2, and the second end of the second horizontal electrode 74-2 extends in the direction close to the first vertical electrode 73-1 along the first direction X.

[0138] In the example embodiment, the first vertical electrode 73-1 can be disposed between the gate electrodes of two third transistors T3 adjacent to each other, and the first horizontal electrode 73-2 can be disposed between the third transistor T3 and the fourth transistor T4. In at least one pixel row, some adjacent sub-pixels can share the same first vertical electrode 73-1, and one first vertical electrode 73-1 and two first horizontal electrodes 73-2 in two sub-pixels can be an integrated structure connected to each other, forming a "T" shape.

[0139] In the example embodiment, the pixel driving circuit can further include a first node electrode 43, and the second electrode of the first transistor T1 can be connected to the gate electrode of the third transistor T3 through the first node electrode 43. A second vertical electrode 74-1 can be arranged between part of two adjacent first node electrodes 43, and a second horizontal electrode 74-2 can be arranged between the third transistor T3 and the fourth transistor T4. In at least one pixel row, part of adjacent sub-pixels can share the same second vertical electrode 74-1, and one second vertical electrode 74-1 and two second horizontal electrodes 74-2 in two sub-pixels can be an integrated structure connected to each other, forming a “T” shape.

[0140] In the example embodiment, the third transistor T3 can include at least a third active region 13. In at least one sub-pixel, the first horizontal electrode 73-2 can have a first distance A1 from the third active region 13, and the first horizontal electrode 73-2 can have a second distance A2 from the fourth active region 14, and the first distance A1 can be less than the second distance A2. Wherein, the first distance A1 can be the distance between the edge of the first horizontal electrode 73-2 close to the third active region 13 and the edge of the third active region 13 close to the first horizontal electrode 73-2, and the second distance A2 can be the distance between the edge of the first horizontal electrode 73-2 close to the fourth active region 14 and the edge of the fourth active region 14 close to the first horizontal electrode 73-2.

[0141] In the example embodiment, in at least one sub-pixel, the first horizontal electrode 73-2 can have a first shielding length B1, the second horizontal electrode 74-2 can have a second shielding length B2, the first vertical electrode 73-1 and the second vertical electrode 74-1 can have a third shielding length B3, and the ratio of the sum of the first shielding length B1 and the second shielding length B2 to the third shielding length B3 can be greater than or equal to 0.6. Wherein, the first shielding length B1 can be the distance between the end of the first horizontal electrode 73-2 away from the first vertical electrode 73-1 and the first vertical electrode 73-1, the second shielding length B2 can be the distance between the end of the second horizontal electrode 74-2 away from the second vertical electrode 74-1 and the second vertical electrode 74-1, and the third shielding length B3 can be the distance between the edge of the first vertical electrode 73-1 close to the second vertical electrode 74-1 and the edge of the second vertical electrode 74-1 close to the first vertical electrode 73-1.

[0142] In an example embodiment, the third node electrode 45 can include a first sub-electrode 45-1, a second sub-electrode 45-2, and a third sub-electrode 45-3. The first sub-electrode 45-1 and the third sub-electrode 45-3 can have a shape of a strip extending along the first direction X, and the second sub-electrode 45-2 can have a shape of a strip extending along the second direction Y. The two ends of the second sub-electrode 45-2 are connected to the first sub-electrode 45-1 and the third sub-electrode 45-3 respectively, forming a "C" shape. The first sub-electrode 45-1 is connected to the second electrode of the third transistor T3, and the third sub-electrode 45-3 is connected to the second electrode of the fourth transistor T4.

[0143] In an example embodiment, the orthographic projection of the third sub-electrode 45-3 on the silicon substrate can at least partially overlap with the orthographic projection of the fourth gate electrode 24 on the silicon substrate.

[0144] In an example embodiment, the third node electrode 45 can further include a fourth sub-electrode 45-4. The fourth sub-electrode 45-4 can have a shape of a strip extending along the first direction X, and can be arranged on the side of the second sub-electrode 45-2 away from the third sub-electrode 45-3 and connected to the second sub-electrode 45-2.

[0145] In an example embodiment, the third sub-electrode 45-3 can have a first extension length L1, and the fourth sub-electrode 45-4 can have a second extension length L2. The first extension length L1 can be greater than the second extension length L2. The first extension length L1 can be the distance between the end of the third sub-electrode 45-3 away from the second sub-electrode 45-2 and the second sub-electrode 45-2, and the second extension length L2 can be the distance between the end of the fourth sub-electrode 45-4 away from the second sub-electrode 45-2 and the second sub-electrode 45-2.

[0146] In an example embodiment, the pixel driving circuit can further include a first capacitor. The first capacitor can include at least a first plate and a second plate. The gate electrode of the third transistor T3 serves as the first plate, and the orthographic projection of the second plate on the display substrate plane at least partially overlaps with the first plate. The second plate can be provided with a second plate connecting block 120-1 arranged on the side of the second plate close to the first node electrode 43 and connected to the second plate. The second plate connecting block 120-1 has a block shape, the first node electrode 43 has a "C" shape, and the second plate connecting block 120-1 and the first node electrode 43 form an interdigital structure.

[0147] In the at least one unit row, the pixel driving circuit and the plurality of signal lines in the adjacent sub-pixels can be substantially symmetrically arranged relative to the first center line O1. In the at least one unit column, the pixel driving circuit and the plurality of signal lines in the adjacent sub-pixels can be substantially symmetrically arranged relative to the second center line O2.

[0148] The preparation process of the display device is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal materials, inorganic materials or transparent conductive materials, and includes deposition of a film layer, coating of an organic material on the film layer, mask exposure and development and the like for organic materials. The deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, the coating can use any one or more of spraying, spin coating and inkjet printing, and the etching can use any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "film" refers to a film of a certain material on a substrate by deposition, coating or other processes. If the "film" does not need to be patterned during the entire preparation process, the "film" can also be referred to as a "layer". If the "film" needs to be patterned during the entire preparation process, it is referred to as a "film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display device. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0149] In the exemplary embodiments, taking 12 sub-pixels in 2 pixel rows (Mth pixel row and M+1th pixel row) and 6 pixel columns (Nth pixel column to N+5th pixel column) as an example, the preparation process of the display substrate can include the following steps.

[0150] (1) Forming N-well region, P-well region and active region pattern on the silicon substrate, as shown in FIG. 7.

[0151] In the exemplary embodiments, the silicon substrate can be a P-type silicon substrate, which can serve as a channel region of an N-type transistor. In some possible implementations, the silicon substrate can be an N-type silicon material, which can serve as a channel region of a P-type transistor, which is not limited in the present disclosure.

[0152] In the example embodiment, a photoresist pattern including an opening region can be formed by coating a photoresist on a P-type silicon substrate, exposing and developing, the photoresist in the opening region is removed, exposing the surface of the P-type silicon substrate, n-type doping ions are implanted in the opening region by ion implantation, the remaining photoresist is stripped, an N-well (NW) region 10A is formed on the P-type silicon substrate, and a P-well (PW) region 10B is formed outside the N-well region 10A. Subsequently, an active region pattern is formed on the silicon substrate on which the aforementioned pattern is formed.

[0153] In the example embodiment, the N-well region 10A is configured to form P-type transistors and P-type devices, and the P-well region 10B (outside the N-well region 10A) is configured to form N-type transistors and N-type devices.

[0154] In the example embodiment, the n-type doping ions can be phosphorus or arsenic ion implantation agents, and the depth and doping concentration of ion implantation can be achieved by controlling the implantation energy and dose. The process of forming the N-well region can also include an annealing process, so that the ion implantation agent diffuses in the P-type silicon substrate to form a stable N-well structure.

[0155] In the example embodiment, in at least one sub-pixel, the N-well region 10A and the P-well region 10B can have a rectangular shape, and the N-well region 10A and the P-well region 10B can be arranged in sequence along the second direction Y. For example, in a plurality of sub-pixels in the Mth pixel row, the P-well region 10B can be arranged on one side of the N-well region 10A in the second direction Y. For another example, in a plurality of sub-pixels in the (M+1)th pixel row, the N-well region 10A can be arranged on one side of the P-well region 10B in the second direction Y.

[0156] In the example embodiment, in one pixel row, the N-well regions 10A of a plurality of sub-pixels can be an integrated structure connected to each other, and the P-well regions 10B of a plurality of sub-pixels can be an integrated structure connected to each other.

[0157] In the example embodiment, the N-well regions 10A and the P-well regions 10B of adjacent pixel rows can be mirror symmetrical with respect to the first center line O1. For example, the N-well regions 10A in the Mth pixel row and the (M+1)th pixel row can be mirror symmetrical with respect to the first center line O1. For another example, the P-well regions 10B in the Mth pixel row and the (M+1)th pixel row can be mirror symmetrical with respect to the first center line O1.

[0158] In an example embodiment, the two N-well regions 10A of the partially adjacent pixel rows can be an integral structure connected to each other, and the two P-well regions 10B of the partially adjacent pixel rows can be an integral structure connected to each other. For example, the two N-well regions 10A in the M-1th pixel row and the Mth pixel row can be an integral structure connected to each other, and the two N-well regions 10A in the M+1th pixel row and the M+2th pixel row can be an integral structure connected to each other. For another example, the two P-well regions 10B in the Mth pixel row and the M+1th pixel row can be an integral structure connected to each other.

[0159] By setting the N-well region 10A and the P-well region 10B of the adjacent pixel rows to be mirror-symmetrical relative to the first center line O1, the present disclosure can achieve that the first transistor T1, the second transistor T2, and the third transistor T3 in the adjacent pixel rows can share the same N-well region 10A, and the fourth transistor T4 in the adjacent pixel rows can share the same P-well region 10B, which can effectively reduce the layout space of the N-well region and the P-well region, reduce the occupied area of the pixel driving circuit, and be conducive to realizing high resolution.

[0160] In an example embodiment, the Active Area (AA) pattern of each sub-pixel in the display substrate can at least include a first active area 11, a second active area 12, a third active area 13, and a fourth active area 14.

[0161] In an example embodiment, the shape of the first active area 11 can be a strip shape extending along the second direction Y, and the first active area 11 can be arranged in the region where the N-well region 10A is located. The first active area 11 can serve as the active area of the first transistor T1.

[0162] In an example embodiment, the shape of the second active area 12 can be a strip shape extending along the second direction Y, and the second active area 12 can be arranged in the region where the N-well region 10A is located. The second active area 12 can serve as the active area of the second transistor T2.

[0163] In an example embodiment, the shape of the third active area 13 can be a strip shape extending along the second direction Y, and the third active area 13 can be arranged in the region where the N-well region 10A is located. The third active area 13 can serve as the active area of the third transistor T3.

[0164] In an example embodiment, the shape of the fourth active area 14 can be a strip shape extending along the first direction X, and the fourth active area 14 can be arranged in the region where the P-well region 10B is located. The fourth active area 14 can serve as the active area of the fourth transistor T4.

[0165] In the exemplary embodiments, in at least one sub-pixel, the first active region 11 can be disposed on one side of the second active region 12 in the first direction, or the first active region 11 can be disposed on the side opposite to the second active region 12 in the first direction. For example, in the Nth pixel column, the N+2th pixel column, and the N+4th pixel column, the first active region 11 can be disposed on one side of the second active region 12 in the first direction. For another example, in the N+1th pixel column, the N+3th pixel column, and the N+5th pixel column, the first active region 11 can be disposed on the side opposite to the second active region 12 in the first direction.

[0166] In the exemplary embodiments, in at least one sub-pixel, the second active region 12 and the fourth active region 14 can be respectively disposed on both sides of the third active region 13 in the second direction Y. For example, in the Mth pixel row, the first active region 11 and the second active region 12 can be disposed on the side opposite to the third active region 13 in the second direction Y, and the fourth active region 14 can be disposed on one side of the third active region 13 in the second direction Y. For another example, in the M+1th pixel row, the first active region 11 and the second active region 12 can be disposed on one side of the third active region 13 in the second direction Y, and the fourth active region 14 can be disposed on the side opposite to the third active region 13 in the second direction Y.

[0167] In the exemplary embodiments, the active region pattern can further include a first power supply region 15 and a second power supply region 16.

[0168] In the exemplary embodiments, the first power supply region 15 can have a block shape (e.g., a rectangular shape), and can be disposed in the region where the N-well region 10A is located. The first power supply region 15 is configured to be connected to a first power supply line formed later.

[0169] In the exemplary embodiments, in the first direction X, the first power supply region 15 can be disposed between some adjacent pixel columns. For example, the first power supply region 15 can be disposed between the Nth pixel column and the N+1th pixel column. For another example, the first power supply region 15 can be disposed between the N+2th pixel column and the N+3th pixel column. For another example, the first power supply region 15 can be disposed between the N+4th pixel column and the N+5th pixel column. In the second direction Y, the first power supply region 15 can be disposed at a position close to the P-well region 10B in the N-well region 10A.

[0170] In the exemplary embodiments, the second power supply region 16 can have a block shape (e.g., a rectangular shape), and can be disposed in the region where the P-well region 10B is located. The second power supply region 16 is configured to be connected to a second power supply line formed later.

[0171] In an exemplary embodiment, in the first direction X, the second power supply regions 16 can be disposed between partially adjacent pixel columns. For example, the second power supply regions 16 can be disposed between the Nth pixel column and the N+1th pixel column, between the N+2th pixel column and the N+3th pixel column, and between the N+4th pixel column and the N+5th pixel column, respectively. In the second direction Y, the second power supply regions 16 can be disposed between partially adjacent pixel rows. For example, the second power supply regions 16 can be disposed between the Mth pixel row and the M+1th pixel row.

[0172] In an exemplary embodiment, the active region patterns of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the first to fourth active regions 11 to 14, the first power supply region 15, and the second power supply region 16 in the M-1th pixel row and the Mth pixel row can be mirror-symmetrical with respect to the first center line O1. For another example, the first to fourth active regions 11 to 14, the first power supply region 15, and the second power supply region 16 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1. For still another example, the first to fourth active regions 11 to 14, the first power supply region 15, and the second power supply region 16 in the M+1th pixel row and the M+2th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0173] In an exemplary embodiment, the active region patterns of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the first to fourth active regions 11 to 14, the first power supply region 15, and the second power supply region 16 in the Nth pixel column and the N+1th pixel column can be mirror-symmetrical with respect to the second center line O2. For another example, the first to fourth active regions 11 to 14, the first power supply region 15, and the second power supply region 16 in the N+1th pixel column and the N+2th pixel column can be mirror-symmetrical with respect to the second center line O2. For still another example, the first to fourth active regions 11 to 14, the first power supply region 15, and the second power supply region 16 in the N+2th pixel column and the N+3th pixel column can be mirror-symmetrical with respect to the second center line O2.

[0174] In an exemplary embodiment, the active region of each transistor can include a source region, a drain region, and a channel region between the source region and the drain region.

[0175] In the exemplary embodiments, in at least one sub-pixel, the first source region 11-1 of the first active region can be located on the side of the first channel region of the first active region away from the third active region 13, and the first drain region 11-2 of the first active region can be located on the side of the first channel region of the first active region close to the third active region 13. The second source region 12-1 of the second active region can be located on the side of the second channel region of the second active region away from the third active region 13, and the second drain region 12-2 of the second active region can be located on the side of the second channel region of the second active region close to the third active region 13. The third source region 13-1 of the third active region can be located on the side of the third channel region of the third active region close to the second active region 12, and the third drain region 13-2 of the third active region can be located on the side of the third channel region of the third active region away from the second active region 12. The fourth source region 14-1 of the fourth active region and the fourth drain region 14-2 of the fourth active region can be located on both sides of the fourth channel region of the fourth active region in the first direction X.

[0176] In the exemplary embodiments, in at least one sub-pixel, the second drain region 12-2 of the second active region and the third source region 13-1 of the third active region can be connected to each other, and the second drain region 12-2 of the second active region can serve as the third source region 13-1 of the third active region.

[0177] In the exemplary embodiments, in at least one sub-pixel, the second active region 12 and the third active region 13 can be an integrated structure connected to each other.

[0178] In the exemplary embodiments, in at least one pixel column, the first active regions 11 in adjacent sub-pixels can be an integrated structure connected to each other, and the first active regions 11 of the two sub-pixels can share the same first source region 11-1. For example, the two sub-pixels in the M-1th pixel row and the Mth pixel row can share the same first source region 11-1. For another example, the two sub-pixels in the M+1th pixel row and the M+2th pixel row can share the same first source region 11-1. The present disclosure can effectively reduce the longitudinal wiring space, reduce the number of vias, and reduce the occupied area of the pixel driving circuit by setting the first transistors T1 of adjacent pixel rows in a mirror image and sharing the first electrode of the first transistors T1, which is conducive to achieving high resolution.

[0179] In the example embodiment, in at least one pixel column, the second active regions 12 in adjacent sub-pixels can be a unitary structure connected to each other, and the second active regions 12 of the two sub-pixels can share the same second source region 12-1. For example, the two sub-pixels in the Mth pixel row and the (M+1)th pixel row can share the same second source region 12-1. For another example, the two sub-pixels in the (M+1)th pixel row and the (M+2)th pixel row can share the same second source region 12-1. The disclosure can effectively reduce the longitudinal wiring space, reduce the number of vias, and reduce the occupied area of the pixel driving circuit by setting the second transistors T2 of the adjacent pixel rows to be mirror set and sharing the first pole of the second transistors T2, which is conducive to achieving high resolution.

[0180] In the example embodiment, in at least one pixel row, the fourth active regions 14 in part of adjacent sub-pixels can be a unitary structure connected to each other, and the fourth active regions 14 of the two sub-pixels can share the same fourth source region 14-1. For example, the two sub-pixels in the (N+1)th pixel column and the (N+2)th pixel column can share the same fourth source region 14-1. For another example, the two sub-pixels in the (N+3)th pixel column and the (N+4)th pixel column can share the same fourth source region 14-1. The disclosure can effectively reduce the horizontal wiring space, reduce the number of vias, and reduce the occupied area of the pixel driving circuit by setting the fourth transistors T4 of part of the adjacent pixel columns to be mirror set and sharing the first pole of the fourth transistors T4, which is conducive to achieving high resolution.

[0181] In the example embodiment, since the first active regions 11 in the adjacent pixel rows are mirror set, the second active regions 12 in the adjacent pixel rows are mirror set and are a unitary structure connected to each other, and the second active regions 12 and the third active regions 13 in each sub-pixel are a unitary structure connected to each other, the first transistors T1, the second transistors T2, and the third transistors T3 in the adjacent pixel rows can be set to share the same N-well region 10A, that is, the same type of transistors share the same type of substrate region, which can effectively reduce the layout space of the N-well region, reduce the occupied area of the pixel driving circuit, and be conducive to achieving high resolution.

[0182] In the example embodiment, since the fourth active regions 14 in the adjacent pixel rows are mirror set, and the fourth active regions 14 in part of the adjacent pixel columns are mirror set and are a unitary structure connected to each other, the fourth transistors T4 in the adjacent pixel rows can be set to share the same P-well region 10B, that is, the same type of transistors share the same type of substrate region, which can effectively reduce the layout space of the second substrate region, reduce the occupied area of the pixel driving circuit, and be conducive to achieving high resolution.

[0183] (2) forming a gate conductive layer pattern. In an exemplary embodiment, forming the gate conductive layer pattern can include: sequentially depositing a first insulating thin film and a polysilicon thin film on the silicon substrate on which the aforementioned pattern is formed, patterning the polysilicon thin film by a patterning process to form a first insulating layer covering the active region pattern and a polysilicon layer pattern disposed on the first insulating layer, and then doping the polysilicon layer to form the gate conductive layer pattern, as shown in FIGS. 8A and 8B, which is a schematic diagram of the gate conductive layer in FIG. 8A.

[0184] In an exemplary embodiment, the gate conductive layer pattern of each sub-pixel in the display substrate can at least include: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, and a first plate 110.

[0185] In an exemplary embodiment, the shape of the first plate 110 can be rectangular, and the orthographic projection of the first plate 110 on the silicon substrate at least partially overlaps with the orthographic projection of the third active region on the silicon substrate. The first plate 110 can serve as the gate electrode of the third transistor T3 on one hand and as one plate of the first capacitor on the other hand.

[0186] In an exemplary embodiment, the first plate 110 can be provided with a first plate connecting block 110-1. The shape of the first plate connecting block 110-1 can be block-shaped (such as rectangular), which can be disposed on one side of the first direction X of the first plate 110 or the opposite side of the first direction X and connected with the first plate 110. For example, the first plate connecting block 110-1 in the Nth pixel column, the N+2th pixel column, and the N+4th pixel column can be disposed on one side of the first direction X of the first plate 110. For another example, the first plate connecting block 110-1 in the N+1th pixel column, the N+3th pixel column, and the N+5th pixel column can be disposed on the opposite side of the first direction X of the first plate 110.

[0187] In an exemplary embodiment, in at least one sub-pixel, the first plate 110 and the first plate connecting block 110-1 can be an integrated structure connected with each other.

[0188] In an exemplary embodiment, the first plate connecting blocks 110-1 in adjacent unit columns can be disposed facing each other, and two first plate connecting blocks 110-1 can be disposed between two first plates 110 in adjacent unit columns, which can reduce the occupied area of the pixel driving circuit and facilitate the realization of high resolution.

[0189] In an exemplary embodiment, the shape of the first gate electrode 21 can be block-shaped (such as rectangular), and the corner of the rectangular shape can be provided with a chamfer or a groove. The orthographic projection of the first gate electrode 21 on the silicon substrate at least partially overlaps with the orthographic projection of the first active region on the silicon substrate, and the first gate electrode 21 can serve as the gate electrode of the first transistor T1.

[0190] In an example embodiment, the second gate electrode 22 can have a block shape (e.g., a rectangular shape), and a normal projection of the second gate electrode 22 on the silicon substrate at least partially overlaps with a normal projection of the second active region on the silicon substrate, and the second gate electrode 22 can serve as a gate electrode of the second transistor T2.

[0191] In an example embodiment, the fourth gate electrode 24 can have a block shape (e.g., a rectangular shape), and a normal projection of the fourth gate electrode 24 on the silicon substrate at least partially overlaps with a normal projection of the fourth active region 14 on the silicon substrate, and the fourth gate electrode 24 can serve as a gate electrode of the fourth transistor T4.

[0192] In an example embodiment, the fourth gate electrode 24 can be provided with a fourth gate connecting block 24-1. The fourth gate connecting block 24-1 can have a block shape (e.g., a rectangular shape), can be disposed on a side of the fourth gate electrode 24 away from the first plate 110, and can be connected with the fourth gate electrode 24.

[0193] In an example embodiment, the gate conductive layer patterns of adjacent pixel rows can be mirror symmetrical with respect to the first center line O1. For example, the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, and the first plate 110 in the M-1th pixel row and the Mth pixel row can be mirror symmetrical with respect to the first center line O1. For another example, the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, and the first plate 110 in the Mth pixel row and the M+1th pixel row can be mirror symmetrical with respect to the first center line O1. For another example, the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, and the first plate 110 in the M+1th pixel row and the M+2th pixel row can be mirror symmetrical with respect to the first center line O1.

[0194] In an example embodiment, the gate conductive layer patterns of adjacent pixel columns can be mirror symmetrical with respect to the second center line O2. For example, the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, and the first plate 110 in the Nth pixel column and the N+1th pixel column can be mirror symmetrical with respect to the second center line O2. For another example, the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, and the first plate 110 in the N+1th pixel column and the N+2th pixel column can be mirror symmetrical with respect to the second center line O2. For another example, the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, and the first plate 110 in the N+2th pixel column and the N+3th pixel column can be mirror symmetrical with respect to the second center line O2.

[0195] In the example embodiment, in at least one unit row, the first gate electrodes 21 of part of the adjacent sub-pixels can be an integral structure connected to each other. For example, the first gate electrodes 21 in the Nth pixel column and the N+1th pixel column can be an integral structure connected to each other. For another example, the first gate electrodes 21 in the N+2th pixel column and the N+3th pixel column can be an integral structure connected to each other. For another example, the first gate electrodes 21 in the N+4th pixel column and the N+5th pixel column can be an integral structure connected to each other. The present disclosure can reduce the distance between the two adjacent first active regions by setting the first gate electrodes of the adjacent pixel columns as an integral structure connected to each other, can effectively reduce the horizontal wiring space, can reduce the number of vias, can reduce the area occupied by the pixel driving circuit, and is conducive to realizing high resolution.

[0196] In the example embodiment, in at least one unit row, the second gate electrodes 22 of part of the adjacent sub-pixels can be an integral structure connected to each other. For example, the second gate electrodes 22 in the N+1th pixel column and the N+2th pixel column can be an integral structure connected to each other. For another example, the second gate electrodes 22 in the N+3th pixel column and the N+4th pixel column can be an integral structure connected to each other. The present disclosure can reduce the distance between the two adjacent second active regions by setting the second gate electrodes of the adjacent pixel columns as an integral structure connected to each other, can effectively reduce the horizontal wiring space, can reduce the number of vias, can reduce the area occupied by the pixel driving circuit, and is conducive to realizing high resolution.

[0197] (3) Forming an N-type doped (SN) region pattern. In the example embodiment, forming the N-type doped region pattern can include: coating a photoresist on the silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, the photoresist in the plurality of opening regions being removed, and forming an N-type doped pattern in the opening regions by a doping process, as shown in FIGS. 9A and 9B, FIG. 9B is a schematic view of the N-type doped pattern in FIG. 9A.

[0198] In the example embodiment, the N-type doped pattern of each sub-pixel in the display substrate can include an N-type doped region 20A.

[0199] In the example embodiment, in at least one sub-pixel, the N-type doped region 20A can be in a rectangular shape, can be located in the region where the P-well region 10B is located, and the orthographic projection of the N-type doped region 20A on the silicon substrate can contain the orthographic projection of the fourth active region on the silicon substrate, so that the fourth active region forms a fourth channel region, a fourth source region and a fourth drain region.

[0200] In the example embodiment, in one pixel row, the N-type doped regions 20A of a plurality of sub-pixels can be an integral structure connected to each other.

[0201] In an example embodiment, the N-type doped regions 20A of adjacent pixel rows can be mirror symmetrical with respect to the first center line O1. For example, the N-type doped regions 20A in the Mth pixel row and the (M+1)th pixel row can be mirror symmetrical with respect to the first center line O1.

[0202] In an example embodiment, the two N-type doped regions 20A of partially adjacent pixel rows can be an integral structure connected to each other. For example, the two N-type doped regions 20A in the Mth pixel row and the (M+1)th pixel row can be an integral structure connected to each other.

[0203] In an example embodiment, the N-type doped pattern can further include N-type protrusions 20A-1 and N-type openings 20A-2.

[0204] In an example embodiment, the N-type protrusions 20A-1 can be rectangular in shape, can be arranged at a side of the N-type doped regions 20A close to the first power supply region 15, and connected to the N-type doped regions 20A. In the first direction X, the N-type protrusions 20A-1 can be arranged between partially adjacent pixel columns. For example, the N-type protrusions 20A-1 can be arranged between the Nth pixel column and the (N+1)th pixel column. For another example, the N-type protrusions 20A-1 can be arranged between the (N+2)th pixel column and the (N+3)th pixel column. For another example, the N-type protrusions 20A-1 can be arranged between the (N+4)th pixel column and the (N+5)th pixel column.

[0205] In an example embodiment, the orthographic projection of the N-type protrusions 20A-1 on the silicon substrate can contain the orthographic projection of the first power supply region 15 on the silicon substrate, i.e., the first power supply region 15 is N-type doped.

[0206] In an example embodiment, the N-type openings 20A-2 can be rectangular in shape. In the first direction X, the N-type openings 20A-2 can be arranged between partially adjacent pixel columns, and in the second direction Y, the N-type openings 20A-2 can be arranged between partially adjacent pixel rows, and the area where the N-type openings 20A-2 are located is not doped. For example, the N-type openings 20A-2 can be arranged between the Nth pixel column and the (N+1)th pixel column. For another example, the N-type openings 20A-2 can be arranged between the (N+2)th pixel column and the (N+3)th pixel column. For another example, the N-type openings 20A-2 can be arranged between the (N+4)th pixel column and the (N+5)th pixel column.

[0207] In an example embodiment, the orthographic projection of the N-type openings 20A-2 on the silicon substrate can contain the orthographic projection of the second power supply region 16 on the silicon substrate, i.e., the second power supply region 16 is not N-type doped.

[0208] (4) Forming a P-type doped (SP) region pattern. In an example embodiment, forming the P-type doped region pattern can include: coating a photoresist on the silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, the photoresist in the plurality of opening regions being removed, and forming a P-type doped pattern in the opening regions by a doping process, as shown in FIGS. 10A and 10B, which is a schematic view of the P-type doped pattern in FIG. 10A.

[0209] In an example embodiment, the P-type doped pattern of each sub-pixel in the display substrate can include a P-type doped region 20B.

[0210] In an example embodiment, in at least one sub-pixel, the P-type doped region 20B can have a rectangular shape, can be located in the region where the N-well region 10A is located, and a normal projection of the P-type doped region 20B on the silicon substrate can contain normal projections of the first to third active regions on the silicon substrate, so that the first active region forms a first channel region, a first source region and a second drain region, the second active region forms a second channel region, a second source region and a second drain region, and the third active region forms a third channel region, a third source region and a third drain region.

[0211] In an example embodiment, in one pixel row, the P-type doped regions 20B of the plurality of sub-pixels can be an integrated structure connected to each other.

[0212] In an example embodiment, the P-type doped regions 20B of adjacent pixel rows can be mirror symmetrical with respect to the first center line O1. For example, the P-type doped regions 20B in the Mth pixel row and the (M+1)th pixel row can be mirror symmetrical with respect to the first center line O1.

[0213] In an example embodiment, the P-type doped pattern can further include a P-type doped block 20B-1 and a P-type groove 20B-2.

[0214] In an example embodiment, the P-type doped block 20B-1 can have a rectangular shape. In the first direction X, the P-type doped block 20B-1 can be arranged between part of adjacent pixel columns, and in the second direction Y, the P-type doped block 20B-1 can be arranged between part of adjacent pixel rows. For example, in the first direction X, the P-type doped block 20B-1 can be arranged between the Nth pixel column and the (N+1)th pixel column, between the (N+2)th pixel column and the (N+3)th pixel column, and between the (N+4)th pixel column and the (N+5)th pixel column, respectively. For another example, in the second direction Y, the P-type doped block 20B-1 can be arranged between the Mth pixel row and the (M+1)th pixel row.

[0215] In an example embodiment, a normal projection of the P-type doped block 20B-1 on the silicon substrate can contain a normal projection of the second power supply region 16 on the silicon substrate, i.e., the second power supply region 16 is P-type doped.

[0216] In an example embodiment, the orthographic projection of the P-type doped block 20B-1 on the silicon substrate can be located within the orthographic projection of the N-type opening 20A-2 on the silicon substrate.

[0217] In an example embodiment, the P-type recess 20B-2 can be rectangular in shape. In the first direction X, the P-type recess 20B-2 can be disposed between partially adjacent pixel columns, and in the second direction Y, the P-type recess 20B-2 can be disposed on the side of the P-type doped region 20B close to the N-type doped region 20A. For example, the P-type recess 20B-2 can be disposed between the Nth pixel column and the N+1th pixel column. For another example, the P-type recess 20B-2 can be disposed between the N+2th pixel column and the N+3th pixel column. For yet another example, the P-type recess 20B-2 can be disposed between the N+4th pixel column and the N+5th pixel column.

[0218] In an example embodiment, the orthographic projection of the P-type recess 20B-2 on the silicon substrate can contain the orthographic projection of the first power supply region 15 on the silicon substrate, that is, the first power supply region 15 is not doped by the P-type.

[0219] (5) Forming a second insulating layer pattern. In an example embodiment, forming the second insulating layer pattern can include: depositing a second insulating thin film on the silicon substrate on which the aforementioned patterns are formed, and patterning the second insulating thin film by a patterning process to form a second insulating layer covering the gate conductive layer pattern, the second insulating layer being provided with a plurality of vias, as shown in FIG. 11.

[0220] In an example embodiment, the plurality of vias in each sub-pixel in the display substrate can at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, and an eleventh via V11.

[0221] In an example embodiment, the orthographic projection of the first via V1 on the silicon substrate can be located within the orthographic projection of the first source region of the first active region on the silicon substrate, the first insulating layer and the second insulating layer in the first via V1 are etched away to expose the surface of the first source region, and the first via V1 is configured to allow the subsequently formed first connecting electrode to connect with the first source region through the via.

[0222] In an example embodiment, since the first active regions of adjacent sub-pixels in one pixel column are an integral structure connected with each other, and two sub-pixels share the first source region, adjacent sub-pixels in one pixel column can share the same first via V1, which can effectively reduce the number of vias, not only can reduce the occupied area of the pixel driving circuit, which is conducive to realizing high resolution, but also can reduce the process difficulty and improve the yield.

[0223] In an example embodiment, the orthogonal projection of the second via V2 on the silicon substrate can be located within the orthogonal projection of the second source region of the second active region on the silicon substrate, the first insulating layer and the second insulating layer within the second via V2 are etched away to expose the surface of the second source region, and the second via V2 is configured to enable a subsequently formed second connection electrode to connect with the second source region through the via.

[0224] In an example embodiment, since the second active regions of adjacent sub-pixels in one pixel column are an integrated structure connected with each other, two sub-pixels share the second source region, thus the adjacent sub-pixels in one pixel column can share the same second via V2, which can effectively reduce the number of vias, not only can reduce the area occupied by the pixel driving circuit, which is conducive to realizing high resolution, but also can reduce the process difficulty and improve the yield.

[0225] In an example embodiment, the orthogonal projection of the first via V1 and the second via V2 on the silicon substrate at least partially overlaps with the orthogonal projection of the first center line O1 on the silicon substrate.

[0226] In an example embodiment, in at least one pixel row, the plurality of first vias V1 and the plurality of second vias V2 can be located on the same straight line extending along the first direction X, which not only helps to improve the process uniformity, but also helps to increase the wiring space of the subsequently formed first scan signal line and the second scan signal line.

[0227] In an example embodiment, the orthogonal projection of the third via V3 on the silicon substrate can be located within the orthogonal projection of the first drain region of the first active region on the silicon substrate, the first insulating layer and the second insulating layer within the third via V3 are etched away to expose the surface of the first drain region, and the third via V3 is configured to enable a subsequently formed first node electrode to connect with the first drain region through the via.

[0228] In an example embodiment, the orthogonal projection of the fourth via V4 on the silicon substrate can be located within the orthogonal projection of the second drain region of the second active region (also the third source region of the third active region) on the silicon substrate, the first insulating layer and the second insulating layer within the fourth via V4 are etched away to expose the surface of the second drain region (also the third source region), and the fourth via V4 is configured to enable a subsequently formed second plate to connect with the second drain region (also the third source region) through the via.

[0229] In an example embodiment, the orthogonal projection of the fifth via V5 on the silicon substrate can be located within the orthogonal projection of the third drain region of the third active region on the silicon substrate, the first insulating layer and the second insulating layer within the fifth via V5 are etched away to expose the surface of the third drain region, and the fifth via V5 is configured to enable a subsequently formed third node electrode to connect with the third drain region through the via.

[0230] In the example embodiment, the orthogonal projection of the sixth via V6 on the silicon substrate can be located within the orthogonal projection of the fourth source region of the fourth active region on the silicon substrate, the first insulating layer and the second insulating layer within the sixth via V6 are etched away to expose the surface of the fourth source region, and the sixth via V6 is configured to enable the sixth connection electrode formed subsequently to connect with the fourth source region through the via.

[0231] In the example embodiment, since the fourth active regions of the part of the adjacent sub-pixels in one pixel row are an integral structure connected with each other, the fourth source regions are shared by two sub-pixels, thus the part of the adjacent sub-pixels in one pixel column can share the same sixth via V6, which can effectively reduce the number of vias, not only can reduce the occupied area of the pixel driving circuit, but also can facilitate the realization of high resolution, and can reduce the process difficulty and improve the yield.

[0232] In the example embodiment, the orthogonal projection of the seventh via V7 on the silicon substrate can be located within the orthogonal projection of the fourth drain region of the fourth active region on the silicon substrate, the first insulating layer and the second insulating layer within the seventh via V7 are etched away to expose the surface of the fourth drain region, and the seventh via V7 is configured to enable the third node electrode formed subsequently to connect with the fourth drain region through the via.

[0233] In the example embodiment, the orthogonal projection of the eighth via V8 on the silicon substrate can be located within the orthogonal projection of the first gate electrode 21 on the silicon substrate, the second insulating layer within the eighth via V8 is etched away to expose the surface of the first gate electrode 21, and the eighth via V8 is configured to enable the first scan signal line formed subsequently to connect with the first gate electrode 21 through the via.

[0234] In the example embodiment, since the first gate electrodes 21 of the part of the adjacent sub-pixels in one pixel row are an integral structure connected with each other, the part of the adjacent sub-pixels in one pixel row can share the same eighth via V8, which can effectively reduce the number of vias, not only can reduce the occupied area of the pixel driving circuit, but also can facilitate the realization of high resolution, and can reduce the process difficulty and improve the yield.

[0235] In the example embodiment, the orthogonal projection of the ninth via V9 on the silicon substrate can be located within the orthogonal projection of the second gate electrode 22 on the silicon substrate, the second insulating layer within the ninth via V9 is etched away to expose the surface of the second gate electrode 22, and the ninth via V9 is configured to enable the second scan signal line formed subsequently to connect with the second gate electrode 22 through the via.

[0236] In the example embodiment, since the second gate electrodes 22 of the part of the adjacent sub-pixels in one pixel row are an integral structure connected to each other, the part of the adjacent sub-pixels in one pixel row can share the same ninth via V9, which can effectively reduce the number of vias, reduce the area occupied by the pixel driving circuit, facilitate the realization of high resolution, reduce the process difficulty, and improve the yield.

[0237] In the example embodiment, the orthographic projection of the tenth via V10 on the silicon substrate can be located within the orthographic projection of the first plate connecting block 110-1 of the first plate 110 on the silicon substrate. The second insulating layer in the tenth via V10 is etched away to expose the surface of the first plate connecting block 110-1. The tenth via V10 is configured to connect the first node electrode formed subsequently therethrough with the first plate connecting block 110-1.

[0238] In the example embodiment, the orthographic projection of the eleventh via V11 on the silicon substrate can be located within the orthographic projection of the fourth gate connecting block 24-1 of the fourth gate electrode 24 on the silicon substrate. The second insulating layer in the eleventh via V11 is etched away to expose the surface of the fourth gate connecting block 24-1. The eleventh via V11 is configured to connect the fourth connecting electrode formed subsequently therethrough with the fourth gate connecting block 24-1.

[0239] In the example embodiment, the plurality of vias on the second insulating layer can further include a twelfth via V12 and a thirteenth via V13.

[0240] In the example embodiment, the orthographic projection of the twelfth via V12 on the silicon substrate can be located within the orthographic projection of the first power supply area 15 on the silicon substrate. The first insulating layer and the second insulating layer in the twelfth via V12 are etched away to expose the surface of the first power supply area 15. The twelfth via V12 is configured to connect the second shielding electrode formed subsequently therethrough with the first power supply area 15.

[0241] In the example embodiment, the orthographic projection of the thirteenth via V13 on the silicon substrate can be located within the orthographic projection of the second power supply area 16 on the silicon substrate. The first insulating layer and the second insulating layer in the thirteenth via V13 are etched away to expose the surface of the second power supply area 16. The thirteenth via V13 is configured to connect the second power supply line formed subsequently therethrough with the second power supply area 16.

[0242] In the example embodiment, one or more of the first via V1 to the thirteenth via V13 can adopt a plurality of via structures to reduce the contact resistance and improve the connection reliability.

[0243] (6) forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern can include: depositing a first conductive thin film on the silicon substrate on which the aforementioned pattern is formed, patterning the first conductive thin film through a patterning process, and forming the first conductive layer pattern on the second insulating layer. In an exemplary embodiment, the first conductive layer can be referred to as a Metal 1 (M1) layer.

[0244] In an exemplary embodiment, the first conductive layer pattern in each sub-pixel in the display substrate can include at least: a first scan signal line 31, a second scan signal line 32, a first connection electrode 41, a second connection electrode 42, a first node electrode 43, a fourth connection electrode 44, a third node electrode 45, a first shield electrode 71, a third shield electrode 73, a fourth shield electrode 74, a second shield electrode 72, a first power supply line 81, a second power supply line 82, and a second plate 120.

[0245] In an exemplary embodiment, the first scan signal line 31 can be in a straight line shape with a main body portion extending along the first direction X, can be located on a side of the first plate 110 away from the fourth gate electrode 24, and can be connected to the first gate electrode 21 of each sub-pixel through an eighth via V8, thereby achieving connection of the first scan signal line 31 to the gate electrode of the first transistor T1 in each sub-pixel, and the first scan signal line 31 can control turning on or off of the first transistor T1.

[0246] In an exemplary embodiment, the second scan signal line 32 can be in a straight line shape with a main body portion extending along the first direction X, can be located on a side of the first scan signal line 31 away from the first plate 110, and can be connected to the second gate electrode 22 of each sub-pixel through a ninth via V9, thereby achieving connection of the second scan signal line 32 to the gate electrode of the second transistor T2 in each sub-pixel, and the second scan signal line 32 can control turning on or off of the second transistor T2.

[0247] In an exemplary embodiment, the orthographic projection of the first scan signal line 31 on the silicon substrate at least partially overlaps the orthographic projection of the first gate electrode 21 and the second gate electrode 22 on the silicon substrate, and the orthographic projection of the second scan signal line 32 on the silicon substrate at least partially overlaps the orthographic projection of the first gate electrode 21 and the second gate electrode 22 on the silicon substrate.

[0248] In an example embodiment, the second plate 120 can be rectangular in shape, and the corners or edges of the rectangular shape can be provided with chamfers or grooves. The second plate 120 has a normal projection on the silicon substrate that at least partially overlaps the normal projection of the first plate 110 on the silicon substrate. The second plate 120 is connected to the second drain region (also the third source region) through the fourth via V4 to form a second node N2 of the pixel driving circuit, and the second plate 120 has the potential of the second node N2. In an example embodiment, the second plate 120 can serve as one plate of the first capacitor.

[0249] In an example embodiment, the first power supply line 81 can be linear in shape with a main body extending along the first direction X, and can be arranged on the side of the third transistor T3 away from the fourth transistor T4, specifically between the first scan signal line 31 and the second plate 12.

[0250] In an example embodiment, in at least one sub-pixel, the normal projection of the first power supply line 81 on the silicon substrate at least partially overlaps the normal projection of the first gate electrode 21 and the second gate electrode 22 on the silicon substrate.

[0251] In an example embodiment, the second power supply line 82 can be linear in shape with a main body extending along the first direction X, and can be arranged on the side of the fourth transistor T4 away from the third transistor T3, specifically between two fourth gate electrodes 24 of adjacent pixel rows. The second power supply line 82 can be connected to a plurality of second power supply regions 16 through a plurality of thirteenth vias V13, so that the second power supply line 82 writes the second power supply signal into the second power supply region 16. Since the second power supply region 16 is located in the P-well region 10B, the second power supply line 82 writes the second power supply signal (negative voltage) into the P-well region 10B, which not only increases the anode dynamic range and improves the contrast of the display device, but also provides better signal isolation effect, reduces signal crosstalk and interference, and improves the stability and reliability of the circuit.

[0252] In an example embodiment, the normal projection of the second power supply line 82 on the silicon substrate at least partially overlaps the normal projection of the first center line O1 on the silicon substrate.

[0253] In an example embodiment, the first connection electrode 41 can be strip-shaped in shape extending along the first direction X, and can be arranged on the side of the second scan signal line 32 away from the first plate 110. The first connection electrode 41 can be connected to the first source region through the first via V1, and the first connection electrode 41 is configured to be connected to the eleventh connection electrode formed subsequently.

[0254] In the example embodiment, since adjacent sub-pixels in one pixel column share the first source region and the first via V1, the adjacent sub-pixels in one pixel column can share the same first connection electrode 41, effectively reducing the number of connection electrodes, reducing the occupied area of the pixel driving circuit, and facilitating the realization of high resolution.

[0255] In the example embodiment, in at least one sub-pixel, the orthographic projection of the first connection electrode 41 on the silicon substrate at least partially overlaps the orthographic projection of the first center line O1 on the silicon substrate.

[0256] In the example embodiment, the second connection electrode 42 can be in the shape of a strip extending along the first direction X and can be arranged on the side of the second scan signal line 32 away from the first plate 110. The second connection electrode 42 can be connected to the second source region through the second via V2, and the second connection electrode 42 is configured to be connected to the twelfth connection electrode formed subsequently.

[0257] In the example embodiment, since adjacent sub-pixels in one pixel column share the second source region and the second via V2, the adjacent sub-pixels in one pixel column can share the same second connection electrode 42, effectively reducing the number of connection electrodes, reducing the occupied area of the pixel driving circuit, and facilitating the realization of high resolution.

[0258] In the example embodiment, in at least one sub-pixel, the orthographic projection of the second connection electrode 42 on the silicon substrate at least partially overlaps the orthographic projection of the first center line O1 on the silicon substrate.

[0259] In the example embodiment, in at least one pixel row, the plurality of first connection electrodes 41 and the plurality of second connection electrodes 42 can be located on the same straight line extending along the first direction X, which is conducive to improving process uniformity and facilitating the increase of wiring space for the first scan signal line and the second scan signal line.

[0260] In the example embodiment, the first node electrode 43 can be in the shape of a "C" letter, the first end of the first node electrode 43 is connected to the first drain region through the third via V3, and the second end of the first node electrode 43 is connected to the first plate connection block 110-1 through the tenth via V10. Since the first plate connection block 110-1 is connected to the first plate 110, the first plate 110 serves as the gate electrode of the third transistor T3, the first node electrode 43 realizes the mutual connection between the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first plate, and forms the first node N1 of the pixel driving circuit, and thus the first plate 110 has the potential of the first node N1.

[0261] In the example embodiment, the first plate 110 has the potential of the first node N1, and the second plate 120 has the potential of the second node N2, so that the first plate 110 and the second plate 120 form a first sub-capacitance of the first capacitance.

[0262] In the example embodiment, the second plate 120 can be provided with a second plate connecting block 120-1. The second plate connecting block 120-1 can have a block shape (e.g., a rectangular shape) and can be arranged on the side of the second plate 120 close to the first node electrode 43. The first end of the second plate connecting block 120-1 is connected to the second plate 120, and the second end of the second plate connecting block 120-1 extends toward the side close to the first node electrode 43. The first node electrode 43 can have a straight side and a recessed side, the straight side being the side of the first node electrode 43 away from the second plate 120, and the recessed side being the side of the first node electrode 43 close to the second plate 120, so that the first node electrode 43 and the second plate connecting block 120-1 form an interdigital structure, and a large parasitic capacitance is formed between the second plate connecting block 120-1 and the first node electrode 43.

[0263] In the example embodiment, the first node electrode 43 has the potential of the first node N1, and the second plate connecting block 120-1 has the potential of the second node N2, so that the parasitic capacitance and the first sub-capacitance are in parallel, which can effectively increase the capacity of the first capacitance and avoid crosstalk and flicker.

[0264] In the example embodiment, the first node electrode 43 can include a fifth sub-electrode 43-5, a sixth sub-electrode 43-6, and a seventh sub-electrode 43-7 connected in sequence. The fifth sub-electrode 43-5 and the seventh sub-electrode 43-7 can have a strip shape extending along the first direction X, and the sixth sub-electrode 43-6 can have a strip shape extending along the second direction Y. The sixth sub-electrode 43-6 has two ends connected to the fifth sub-electrode 43-5 and the seventh sub-electrode 43-7, respectively, forming a "C" shape. The fifth sub-electrode 43-5 is connected to the first drain region through a third via V3, and the seventh sub-electrode 43-7 is connected to the first plate connecting block 110-1 through a tenth via V10.

[0265] In an example embodiment, in the first direction X, the seventh sub-electrode 43-7 and the second plate 120 can have a first electrode spacing g1, and the second plate connecting block 120-1 and the sixth sub-electrode 43-6 can have a second electrode spacing g2. The first electrode spacing g1 can be a distance between an edge of the seventh sub-electrode 43-7 close to the second plate 120 and an edge of the second plate 120 close to the seventh sub-electrode 43-7, the second electrode spacing g2 can be a distance between an edge of the second plate connecting block 120-1 close to the sixth sub-electrode 43-6 and an edge of the sixth sub-electrode 43-6 close to the second plate connecting block 120-1, and the first electrode spacing g1 and the second electrode spacing g2 can be dimensions in the first direction X.

[0266] In an example embodiment, the second electrode spacing g2 can be greater than the first electrode spacing g1 to increase the parasitic capacitance of the interdigital structure.

[0267] In an example embodiment, in the first direction X, the seventh sub-electrode 43-7 can have a third extension length L3. The third extension length L3 can be a distance between an edge of the seventh sub-electrode 43-7 away from the sixth sub-electrode 43-6 and an edge of the sixth sub-electrode 43-6 close to the seventh sub-electrode 43-7, and the third extension length L3 can be a dimension in the first direction X.

[0268] In an example embodiment, the seventh sub-electrode 43-7 can include a first region and a second region, a normal projection of the first region on the silicon substrate at least partially overlaps a normal projection of the third active region on the silicon substrate, and a normal projection of the second region on the silicon substrate does not overlap a normal projection of the third active region on the silicon substrate, the first region can have a fourth extension length L4, the second region can have a fifth extension length L5, the fourth extension length L4 and the fifth extension length L5 can be dimensions in the first direction X, and the fourth extension length L4 and the fifth extension length L5 can be equal to the third extension length L3.

[0269] In an example embodiment, the fifth extension length L5 can be less than the fourth extension length L4, and the fifth extension length L5 can be greater than 0.5 times the fourth extension length L4, while increasing the parasitic capacitance, the tenth via (gate via) does not affect the third active region.

[0270] In an example embodiment, the fourth connection electrode 44 can have a shape of a strip extending along the first direction X, the fourth connection electrode 44 is connected to the fourth gate connecting block 24-1 through the eleventh via V11, and the fourth connection electrode 44 is configured to be connected to a fourteenth connection electrode formed subsequently.

[0271] In an exemplary embodiment, the third node electrode 45 can be C-shaped. The first end of the third node electrode 45 is connected to the third drain region via a fifth via V5, and the second end of the third node electrode 45 is connected to the fourth drain region via a seventh via V7. In an exemplary embodiment, the third node electrode 45 enables the connection between the second electrode of the third transistor T2 and the second electrode of the fourth transistor T4, forming the third node N3 of the pixel driving circuit.

[0272] In an exemplary embodiment, the "C"-shaped third node electrode 45 may include a first sub-electrode 45-1, a second sub-electrode 45-2, and a third sub-electrode 45-3 connected sequentially. The first sub-electrode 45-1 and the third sub-electrode 45-3 may be strip-shaped extending along a first direction X, and the second sub-electrode 45-2 may be strip-shaped extending along a second direction Y. The two ends of the second sub-electrode 45-2 are respectively connected to the first sub-electrode 45-1 and the third sub-electrode 45-3 to form a "C" shape. The first sub-electrode 45-1 is connected to the third drain region through a fifth via V5, and the third sub-electrode 45-3 is connected to the fourth drain region through a seventh via V7.

[0273] In an exemplary embodiment, the orthographic projection of the third sub-electrode 45-3 onto the silicon substrate may at least partially overlap with the orthographic projection of the fourth gate electrode 24 onto the silicon substrate.

[0274] In an exemplary embodiment, the third node electrode 45 may further include a fourth sub-electrode 45-4. The fourth sub-electrode 45-4 may be a strip shape extending along the first direction X, and may be disposed on the side of the second sub-electrode 45-2 away from the third sub-electrode 45-3, and connected to the second sub-electrode 45-2, wherein the third sub-electrode 45-3 and the fourth sub-electrode 45-4 are located on the same straight line extending along the first direction X.

[0275] In an exemplary embodiment, the third sub-electrode 45-3 may have a first extension length L1, and the fourth sub-electrode 45-4 may have a second extension length L2. The first extension length L1 may be greater than the second extension length L2. The first extension length L1 may be the distance between the end of the third sub-electrode 45-3 away from the second sub-electrode 45-2 and the second sub-electrode 45-2. The second extension length L2 may be the distance between the end of the fourth sub-electrode 45-4 away from the second sub-electrode 45-2 and the second sub-electrode 45-2.

[0276] In an exemplary embodiment, the first shielding electrode 71 can have a strip shape extending along the second direction Y, can be arranged between the fourth gate electrodes 24 adjacent in the first direction X, a first end of the first shielding electrode 71 can be connected to the second power supply line 82, and a second end of the first shielding electrode 71 can extend toward the third transistor T3 in the second direction Y and then be connected to the fourth source region through the sixth via V6, so that the second power supply line 82 writes the second power supply signal to the first electrode of the fourth transistor T4.

[0277] In an exemplary embodiment, since the fourth active regions of the adjacent sub-pixels in a pixel row are integrated structures connected to each other, the fourth source region and the sixth via V6 are shared by two sub-pixels, and thus the first shielding electrode 71 can be shared by the adjacent sub-pixels in a pixel row, and one first shielding electrode 71 can be arranged in every two pixel columns, i.e., the first shielding electrodes 71 adjacent in the first direction X can be spaced apart by two sub-pixels. For example, the first shielding electrode 71 can be arranged between the fourth gate electrodes 24 of the N+1th pixel column and the N+2th pixel column. For another example, the first shielding electrode 71 can be arranged between the fourth gate electrodes 24 of the N+3th pixel column and the N+4th pixel column.

[0278] In an exemplary embodiment, the first shielding electrode 71 and the second power supply line 82 can be integrated structures connected to each other in at least one sub-pixel.

[0279] In an exemplary embodiment, in at least one pixel row, the second power supply line 82 and the first shielding electrode 71 can be integrated structures connected to each other.

[0280] In an exemplary embodiment, in at least one pixel column, the first shielding electrode 71 and the second power supply line 82 can be integrated structures connected to each other in the adjacent sub-pixels.

[0281] In an exemplary embodiment, the second shielding electrode 72 can have a strip shape extending along the second direction Y, can be arranged between the third node electrodes 45 adjacent in the first direction X, a first end of the second shielding electrode 72 can be connected to the second power supply line 82, and a second end of the second shielding electrode 72 can extend toward the third transistor T3 in the second direction Y.

[0282] In an exemplary embodiment, two adjacent sub-pixels in one pixel row can share one second shielding electrode 72, and one second shielding electrode 72 can be arranged between every two pixel columns, i.e., two adjacent second shielding electrodes 72 in the first direction X can be spaced apart by two sub-pixels. For example, the second shielding electrode 72 can be arranged between the third node electrodes 45 of the Nth pixel column and the N+1th pixel column. For another example, the second shielding electrode 72 can be arranged between the third node electrodes 45 of the N+2th pixel column and the N+3th pixel column. For another example, the second shielding electrode 72 can be arranged between the third node electrodes 45 of the N+4th pixel column and the N+5th pixel column.

[0283] In an exemplary embodiment, the second shielding electrode 72 and the second power supply line 82 in at least one sub-pixel can be an integrated structure connected to each other.

[0284] In an exemplary embodiment, in at least one pixel row, one second power supply line 82 and a plurality of second shielding electrodes 72 can be an integrated structure connected to each other.

[0285] In an exemplary embodiment, in at least one pixel column, two second shielding electrodes 72 in adjacent sub-pixels and one second power supply line 82 can be an integrated structure connected to each other.

[0286] In an exemplary embodiment, the first shielding electrode 71 can have a first electrode length F1, and the second shielding electrode 72 can have a second electrode length F2. The ratio of the first electrode length F1 to the second electrode length F2 can be 0.95 to 1.05. The first electrode length F1 can be the distance between the edge of the first shielding electrode 71 away from the second power supply line 82 and the edge of the second power supply line 82 close to the first shielding electrode 71, and the second electrode length F2 can be the distance between the edge of the second shielding electrode 72 away from the second power supply line 82 and the edge of the second power supply line 82 close to the second shielding electrode 72. The first electrode length F1 and the second electrode length F2 can be the dimensions in the second direction Y.

[0287] In the example embodiment, since the first shielding electrode 71 is arranged between part of the adjacent fourth gate electrodes 24 in one pixel row, the second shielding electrode 72 is arranged between part of the adjacent third node electrodes 45 in one pixel row, and the first shielding electrode 71 and the second shielding electrode 72 are both connected with the second power supply line 82, the first shielding electrode 71, the second shielding electrode 72 and the second power supply line in one sub-pixel can form a first shielding structure surrounding the fourth transistor T4 in three directions, and the first shielding structure has the potential of the second power supply line, which can effectively shield the fourth transistor T4 and the third node N3 in the sub-pixel, can effectively reduce the mutual interference between the adjacent fourth transistors T4 and the third nodes N3, improve the reset performance and working stability of the fourth transistor T4, and improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0288] In the example embodiment, since the third node is configured to be connected with the anode through the plurality of connection electrodes, the second shielding electrode arranged between the adjacent third node electrodes can also effectively shield the crosstalk between the adjacent anodes and improve the output stability. The pixel driving circuit of the present disclosure can effectively improve the dynamic range of the anode and the brightness of the OLED by adopting the N-type fourth transistor T4 and the fourth transistor T4 having a good isolation structure.

[0289] In the example embodiment, the third shielding electrode 73 can include at least a first vertical electrode 73-1 and a first horizontal electrode 73-2, and the fourth shielding electrode 74 can include at least a second vertical electrode 74-1 and a second horizontal electrode 74-2. The shapes of the first vertical electrode 73-1 and the second vertical electrode 74-1 can be strip shapes extending along the second direction Y, the first vertical electrode 73-1 can be arranged on the side of the second plate 120 away from the first node electrode 43, and the second vertical electrode 74-1 can be arranged on the side of the first node electrode 43 away from the first plate 110. The shapes of the first horizontal electrode 73-2 and the second horizontal electrode 74-2 can be strip shapes extending along the first direction X, and the first horizontal electrode 73-2 and the second horizontal electrode 74-2 can both be arranged between the third transistor T3 and the fourth transistor T3.

[0290] In the example embodiment, the first end of the first vertical electrode 73-1 is connected with the first power supply line 81, the second end of the first vertical electrode 73-1 extends along the second direction Y towards the fourth gate electrode 24, and then is connected with the first end of the first horizontal electrode 73-2, the second end of the first horizontal electrode 73-2 extends along the first direction X towards the second vertical electrode 74-1. The first end of the second vertical electrode 74-1 is connected with the first power supply line 81, the second end of the second vertical electrode 74-1 extends along the second direction Y towards the fourth gate electrode 24, and then is connected with the first end of the second horizontal electrode 74-2, the second end of the second horizontal electrode 74-2 extends along the first direction X towards the first vertical electrode 73-1. In this way, the first horizontal electrode 73-2, the first vertical electrode 73-1, the first power supply line 81, the second vertical electrode 74-1 and the second horizontal electrode 74-2 connected in sequence form a second shielding structure substantially surrounding the third transistor T3 in four directions, and the second shielding structure surrounding the third transistor T3 has the potential of the first power supply line.

[0291] In the example embodiment, in at least one pixel row, part of the adjacent sub-pixels can share the same first vertical electrode 73-1, i.e. the first vertical electrode 73-1 can be arranged between the adjacent two first plates 110 (gate electrodes of the third transistor T3), and the first vertical electrode 73-1 and the two first horizontal electrodes 73-2 in the two sub-pixels can be an integrated structure connected with each other, forming a "T" shape. For example, the third shielding electrodes 73 of the two sub-pixels in the N+1th pixel column and the N+2th pixel column can share the same first vertical electrode 73-1, forming a "T" shape, and the shared first vertical electrode 73-1 can be arranged between the adjacent two first plates 110. For another example, the third shielding electrodes 73 of the two sub-pixels in the N+3th pixel column and the N+4th pixel column can share the same first vertical electrode 73-1, forming a "T" shape, and the shared first vertical electrode 73-1 can be arranged between the adjacent two first plates 110.

[0292] In the example embodiments, in at least one pixel row, the fourth shielding electrodes 74 of two adjacent sub-pixels can share the same second vertical electrode 74-1, i.e., the second vertical electrode 74-1 can be arranged between the two adjacent first node electrodes 43, and the second vertical electrode 74-1 and the two second horizontal electrodes 74-2 in the two sub-pixels can be an integrated structure connected to each other, forming another "T" shape. For example, the fourth shielding electrodes 74 of two sub-pixels in the Nth pixel column and the N+1th pixel column can share the same second vertical electrode 74-1, forming another "T" shape, and the shared second vertical electrode 74-1 can be arranged between the two adjacent first node electrodes 43. For another example, the fourth shielding electrodes 74 of two sub-pixels in the N+2th pixel column and the N+3th pixel column can share the same second vertical electrode 74-1, forming another "T" shape, and the shared second vertical electrode 74-1 can be arranged between the two adjacent first node electrodes 43. For another example, the fourth shielding electrodes 74 of two sub-pixels in the N+4th pixel column and the N+5th pixel column can share the same second vertical electrode 74-1, forming another "T" shape, and the shared second vertical electrode 74-1 can be arranged between the two adjacent first node electrodes 43.

[0293] The present disclosure can effectively reduce the horizontal layout space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit by arranging the first vertical electrode 73-1 shared by some adjacent sub-pixels and the second vertical electrode 74-1 shared by some adjacent sub-pixels, which is conducive to achieving high resolution.

[0294] In the example embodiments, the first conductive layer patterns of adjacent pixel columns are mirror-symmetrical, so the distance between adjacent first plates (the gate electrodes of the third transistors T3) is small, and the distance between adjacent first node electrodes (the first nodes N1 of the pixel driving circuits) is small. The present disclosure can effectively shield the mutual interference between adjacent driving transistors and the mutual interference between adjacent first nodes by arranging the first vertical electrodes between adjacent first plates and the second vertical electrodes between adjacent first node electrodes, and the first vertical electrodes and the second vertical electrodes having a constant potential can effectively improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0295] The present disclosure can effectively shield the driving transistors in the sub-pixels and improve the output stability of the driving transistors, and can effectively reduce the mutual interference between adjacent pixel driving circuits and effectively improve the uniformity and stability of the output current or voltage of the pixel driving circuit by arranging the third shielding electrode, the fourth shielding electrode, and the first power line to form a second shielding structure substantially surrounding the third transistor T3 on four sides, the second shielding structure substantially surrounds the third transistor T3 once, and the second shielding structure has the potential of the first power line.

[0296] In the example embodiment, since the two first lateral electrodes 73-2 in the partially adjacent sub-pixels are in an integrated structure connected to each other, and the two second lateral electrodes 74-2 in the partially adjacent sub-pixels are in an integrated structure connected to each other, the two first lateral electrodes 73-2 in the integrated structure and the two second lateral electrodes 74-2 in the integrated structure form a lateral shielding structure between the third transistor T3 and the fourth transistor T4, i.e., the lateral shielding structure with the potential of the first power line is arranged to isolate the third transistor T3 and the fourth transistor T4, which can effectively shield the mutual interference between the third transistor T3 and the fourth transistor T4, and improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0297] In the example embodiment, in at least one sub-pixel, the first lateral electrode 73-2 and the third active region 13 can have a first distance A1, and the first lateral electrode 73-2 and the fourth active region 14 can have a second distance A2. The first distance A1 can be the distance between the edge of the first lateral electrode 73-2 close to the third active region 13 and the edge of the third active region 13 close to the first lateral electrode 73-2. The second distance A2 can be the distance between the edge of the first lateral electrode 73-2 close to the fourth active region 14 and the edge of the fourth active region 14 close to the first lateral electrode 73-2. Alternatively, the second lateral electrode 74-2 and the third active region 13 can have a first distance A1, and the second lateral electrode 74-2 and the fourth active region 14 can have a second distance A2. The first distance A1 can be the distance between the edge of the second lateral electrode 74-2 close to the third active region 13 and the edge of the third active region 13 close to the second lateral electrode 74-2. The second distance A2 can be the distance between the edge of the second lateral electrode 74-2 close to the fourth active region 14 and the edge of the fourth active region 14 close to the second lateral electrode 74-2.

[0298] In the example embodiment, the first distance A1 can be smaller than the second distance A2, i.e., the first lateral electrode 73-2 or the second lateral electrode 74-2 is closer to the active region of the third transistor T3 (P-type transistor), so as to avoid the first power signal in the first lateral electrode 73-2 or the second lateral electrode 74-2 affecting the fourth transistor T4 (N-type transistor).

[0299] In the example embodiment, in at least one of the sub-pixels, the first lateral electrode 73-2 can have a first shielding length B1, the second lateral electrode 74-2 can have a second shielding length B2, and the third shielding length B3 can be between the first vertical electrode 73-1 and the second vertical electrode 74-1, and the ratio of the sum of the first shielding length B1 and the second shielding length B2 to the third shielding length B3 can be greater than or equal to 0.6. Wherein the first shielding length B1 can be the distance between the end of the first lateral electrode 73-2 away from the first vertical electrode 73-1 and the first vertical electrode 73-1, the second shielding length B2 can be the distance between the end of the second lateral electrode 74-2 away from the second vertical electrode 74-1 and the second vertical electrode 74-1, and the third shielding length B3 can be the distance between the edge of the first vertical electrode 73-1 close to the second vertical electrode 74-1 and the edge of the second vertical electrode 74-1 close to the first vertical electrode 73-1.

[0300] In the example embodiment, the second vertical electrode 74-1 in the fourth shielding electrode 74 can also be connected to the first power supply area 15 through the twelfth via V12. Since the first power supply area 15 is located in the N-well region 10A, the fourth shielding electrode 74 writes the first power supply signal into the N-well region 10A, which not only can provide better current driving capability and response speed to meet the operation requirements of the pixel driving circuit, but also can improve the overall efficiency of the pixel driving circuit.

[0301] In the example embodiment, the first conductive layer pattern of adjacent pixel rows can be mirror symmetrical with respect to the first center line O1, and the first conductive layer pattern of adjacent pixel columns can be mirror symmetrical with respect to the second center line O2.

[0302] (7) Forming a third insulating layer pattern. In the example embodiment, forming the third insulating layer pattern can include: depositing a third insulating thin film on the silicon substrate on which the aforementioned patterns are formed, and patterning the third insulating thin film by a patterning process to form a third insulating layer covering the first conductive layer pattern, and the third insulating layer is provided with a plurality of vias, as shown in FIG. 13.

[0303] In the example embodiment, the plurality of vias in each sub-pixel in the display substrate can include: a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26, a twenty-seventh via V27, a twenty-eighth via V28, and a twenty-ninth via V29.

[0304] In an example embodiment, a normal projection of the twenty-first via V21 on the silicon substrate can be located within a range of a normal projection of the first connection electrode 41 on the silicon substrate, the third insulating layer within the twenty-first via V21 is etched away, exposing a surface of the first connection electrode 41, and the twenty-first via V21 is configured to enable a subsequent formed eleventh connection electrode to connect with the first connection electrode 41 through the via.

[0305] In an example embodiment, a normal projection of the twenty-first via V21 on the silicon substrate at least partially overlaps with a normal projection of the first center line O1 on the silicon substrate.

[0306] In an example embodiment, a normal projection of the twenty-second via V22 on the silicon substrate can be located within a range of a normal projection of the second connection electrode 42 on the silicon substrate, the third insulating layer within the twenty-second via V22 is etched away, exposing a surface of the second connection electrode 42, and the twenty-second via V22 is configured to enable a subsequent formed twelfth connection electrode to connect with the second connection electrode 42 through the via.

[0307] In an example embodiment, a normal projection of the twenty-second via V22 on the silicon substrate at least partially overlaps with a normal projection of the first center line O1 on the silicon substrate.

[0308] In an example embodiment, in at least one pixel row, a plurality of the twenty-first vias V21 and a plurality of the twenty-second vias V22 can be located on a same straight line extending along the first direction X.

[0309] In an example embodiment, a normal projection of the twenty-third via V23 on the silicon substrate can be located within a range of a normal projection of the first node electrode 43 on the silicon substrate, the third insulating layer within the twenty-third via V23 is etched away, exposing a surface of the first node electrode 43, and the twenty-third via V23 is configured to enable a subsequent formed third plate to connect with the first node electrode 43 through the via.

[0310] In an example embodiment, a normal projection of the twenty-fourth via V24 on the silicon substrate can be located within a range of a normal projection of the fourth connection electrode 44 on the silicon substrate, the third insulating layer within the twenty-fourth via V24 is etched away, exposing a surface of the fourth connection electrode 44, and the twenty-fourth via V24 is configured to enable a subsequent formed fourteenth connection electrode to connect with the fourth connection electrode 44 through the via.

[0311] In an example embodiment, the orthogonal projection of the twenty-fifth via V25 on the silicon substrate can be located within the orthogonal projection of a third sub-electrode 45-3 in the third node electrode 45 on the silicon substrate, the third insulating layer within the twenty-fifth via V25 is etched away to expose the surface of the third sub-electrode 45-3, and the twenty-fifth via V25 is configured to enable a fifteenth connecting electrode formed subsequently to connect with the third sub-electrode 45-3 through the via.

[0312] In an example embodiment, the orthogonal projection of the twenty-sixth via V26 on the silicon substrate can be located within the orthogonal projection of the first shielding electrode 71 on the silicon substrate, the third insulating layer within the twenty-sixth via V26 is etched away to expose the surface of the first shielding electrode 71, and the twenty-sixth via V26 is configured to enable a second connecting line formed subsequently to connect with the first shielding electrode 71 through the via.

[0313] In an example embodiment, due to the fact that part of the adjacent sub-pixels in a pixel row share the same first shielding electrode 71, part of the adjacent sub-pixels in a pixel column can share the same twenty-sixth via V26. In an example embodiment, there can be multiple twenty-sixth vias V26 to reduce the contact resistance and improve the connection reliability.

[0314] In an example embodiment, the orthogonal projection of the twenty-seventh via V27 on the silicon substrate can be located within the orthogonal projection of the first power line 81 on the silicon substrate, the third insulating layer within the twenty-seventh via V27 is etched away to expose the surface of the first power line 81, and the twenty-seventh via V27 is configured to enable a twelfth connecting electrode formed subsequently to connect with the first power line 81 through the via.

[0315] In an example embodiment, the orthogonal projection of the twenty-eighth via V28 on the silicon substrate can be located within the orthogonal projection of the second power line 82 on the silicon substrate, the third insulating layer within the twenty-eighth via V28 is etched away to expose the surface of the second power line 82, and the twenty-eighth via V28 is configured to enable a first connecting line formed subsequently to connect with the second power line 82 through the via.

[0316] In an example embodiment, the orthogonal projection of the twenty-ninth via V29 on the silicon substrate can be located within the orthogonal projection of the second plate 120 on the silicon substrate, the third insulating layer within the twenty-ninth via V29 is etched away to expose the surface of the second plate 120, and the twenty-ninth via V29 is configured to enable a thirteenth connecting electrode formed subsequently to connect with the second plate 120 through the via.

[0317] (8) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: depositing a second conductive thin film on the silicon substrate on which the aforementioned pattern is formed, patterning the second conductive thin film through a patterning process, and forming the second conductive layer pattern on the third insulating layer. In an exemplary embodiment, the second conductive layer can be referred to as a second metal (Metal2) layer.

[0318] In an exemplary embodiment, the second conductive layer pattern in each sub-pixel in the display substrate can include at least: an eleventh connection electrode 51, a twelfth connection electrode 52, a thirteenth connection electrode 53, a fourteenth connection electrode 54, a fifteenth connection electrode 55, and a third plate 130.

[0319] In an exemplary embodiment, the third plate 130 can have a rectangular shape, a corner of the rectangular shape can be provided with a chamfer or a groove, a normal projection of the third plate 130 on the silicon substrate at least partially overlaps a normal projection of the second plate 120 on the silicon substrate, and the third plate 130 can be connected to the first node electrode 43 through a twenty-third via V23. Since the first node electrode 43 realizes the interconnection between the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first plate, and forms a first node N1 of a pixel driving circuit, the third plate 130 has a potential of the first node N1, and the third plate 130 can serve as one plate of a first capacitor.

[0320] In an exemplary embodiment, since the third plate 130 has the potential of the first node N1 and the second plate 120 has the potential of the second node N2, the third plate 130 and the second plate 120 constitute a second sub-capacitor of the first capacitor.

[0321] In an exemplary embodiment, the eleventh connection electrode 51 can have a strip shape extending along the first direction X, can be disposed on a side of the second scan signal line 32 away from the third plate 130, can be connected to the first connection electrode 41 through a twenty-first via V21, and can be configured to be connected to a subsequently formed twenty-first connection electrode.

[0322] In an exemplary embodiment, in at least one sub-pixel, a normal projection of the eleventh connection electrode 51 on the silicon substrate at least partially overlaps a normal projection of the first center line O1 on the silicon substrate, and adjacent sub-pixels in one pixel column can share the same eleventh connection electrode 51.

[0323] In an exemplary embodiment, the twelfth connection electrode 52 can have an "L" shape, a first end of the twelfth connection electrode 52 can be connected to the second connection electrode 42 through a twenty-second via V22, a second end of the twelfth connection electrode 52 can be connected to the first power supply line 81 through a twenty-seventh via V27, and the twelfth connection electrode 52 can be configured to be connected to a third connection line to be formed later.

[0324] In an exemplary embodiment, the twelfth connection electrodes 52 of adjacent sub-pixels in one pixel column can be integrated structures connected to each other.

[0325] In an exemplary embodiment, the thirteenth connection electrode 53 can have a bar shape extending along the first direction X, can be disposed between the twelfth connection electrode 52 and the third plate 130, can be connected to the second plate 120 through a twenty-ninth via V29, and can be configured to be connected to a fourth plate to be formed later.

[0326] In an exemplary embodiment, the fourteenth connection electrode 54 can have a bar shape extending along the first direction X, can be connected to the fourth connection electrode 44 through a twenty-fourth via V24, and can be configured to be connected to a third scan signal line to be formed later.

[0327] In an exemplary embodiment, the fifteenth connection electrode 55 can have a bar shape extending along the first direction X, can be connected to the third sub-electrode 45-3 through a twenty-fifth via V25, and can be configured to be connected to a twenty-second connection electrode to be formed later.

[0328] In an exemplary embodiment, the second conductive layer pattern can further include a first connection line 91 and a second connection line 92.

[0329] In an exemplary embodiment, the first connection line 91 can have a straight line shape or a polygonal line shape in which a main body portion extends along the first direction X, can be disposed between two fourth gate electrodes 24 of adjacent pixel rows, and can be connected to the second power supply line 82 through a twenty-eighth via V28.

[0330] In the example embodiment, the second connection line 92 can be in a straight line shape or a broken line shape extending along the second direction Y, can be arranged between two fourth gate electrodes 24 of adjacent pixel columns, and can be connected with the first connection line 91, thereby realizing the interconnection between the second power supply line 82 extending along the first direction X and the first connection line 91 and the second connection line 92 extending along the second direction Y, forming a different-layer mesh interconnection structure transmitting the second power supply signal on the display substrate, and forming a same-layer mesh interconnection structure transmitting the second power supply signal on the display substrate. This can effectively reduce the resistance of the second power supply line, reduce the voltage drop of the second power supply signal, effectively improve the uniformity of the second power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0331] In the example embodiment, the two first connection lines 91 and the two second connection lines 92 in the same-layer mesh interconnection structure transmitting the second power supply signal can surround two sub-pixels (the intersection region of two pixel rows and one pixel column), which can effectively reduce the signal interference between the sub-pixels.

[0332] In the example embodiment, the orthographic projection of the first connection line 91 on the silicon substrate at least partially overlaps the orthographic projection of the first center line O1 on the silicon substrate, and the orthographic projection of the second connection line 92 on the silicon substrate at least partially overlaps the orthographic projection of the second center line O2 on the silicon substrate. Since the first connection line 91 is arranged between adjacent pixel rows, and the second connection line 92 is arranged between adjacent pixel columns, the first connection line 91 and the second connection line 92 having a constant potential can effectively shield the pixel driving circuit in the sub-pixel, improve the output stability of the pixel driving circuit, and effectively reduce the mutual interference between the pixel driving circuits in the sub-pixel, effectively improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0333] In the example embodiment, in at least one sub-pixel, the first connection line 91 and the second connection line 92 can be an integrated structure connected with each other.

[0334] In the example embodiment, in at least one pixel row, the first connection line 91 and the second connection line 92 can be an integrated structure connected with each other.

[0335] In the example embodiment, in at least one pixel column, the two second connection lines 92 in adjacent sub-pixels can be an integrated structure connected with each other.

[0336] In the example embodiment, part of the second connection line 92 is further connected with the first shielding electrode 71 through the twenty-sixth via hole V26.

[0337] In an example embodiment, the second conductive layer pattern of adjacent pixel rows can be mirror-symmetrical relative to the first center line O1, and the second conductive layer pattern of adjacent pixel columns can be mirror-symmetrical relative to the second center line O2.

[0338] (9) Forming a fourth insulating layer and a third conductive layer pattern. In an example embodiment, forming the fourth insulating layer and the third conductive layer pattern can include sequentially depositing a fourth insulating thin film and a third conductive thin film on the silicon substrate on which the aforementioned patterns are formed, patterning the third conductive thin film by a patterning process, forming the fourth insulating layer covering the second conductive layer pattern, and the third conductive layer pattern disposed on the fourth insulating layer, as shown in FIGS. 15A and 15B, FIG. 15B is a schematic diagram of the third conductive layer in FIG. 15A. In an example embodiment, the third conductive layer can be referred to as a Metal-Insulator-Metal (MIM) layer.

[0339] In an example embodiment, the third conductive layer pattern in each sub-pixel can include at least a fourth plate 140.

[0340] In an example embodiment, the fourth plate 140 can have a rectangular shape, and the corner of the rectangular shape can be provided with a chamfer or a groove, which can be disposed between the thirteenth connection electrode 53 and the fifteenth connection electrode 55. The orthographic projection of the fourth plate 140 on the silicon substrate at least partially overlaps the orthographic projection of the third plate 130 on the silicon substrate, and the fourth plate 140 is configured as one plate of a first capacitor.

[0341] In an example embodiment, the fourth conductive layer pattern of adjacent pixel rows can be mirror-symmetrical relative to the first center line O1, and the fourth plate 140 of adjacent pixel columns can be mirror-symmetrical relative to the second center line O2.

[0342] (10) Forming a fifth insulating layer pattern. In an example embodiment, forming the fifth insulating layer pattern can include depositing a fifth insulating thin film on the silicon substrate on which the aforementioned patterns are formed, patterning the fifth insulating thin film by a patterning process, forming the fifth insulating layer covering the third conductive layer pattern, and the fifth insulating layer being provided with a plurality of vias, as shown in FIG. 16.

[0343] In an example embodiment, the plurality of vias in each sub-pixel of the display substrate can include a thirty-first via V31, a thirty-second via V32, a thirty-third via V33, a thirty-fourth via V34, a thirty-fifth via V35, and a thirty-sixth via V36.

[0344] In an example embodiment, the orthogonal projection of the thirty-first via V31 on the silicon substrate can be located within the range of the orthogonal projection of the eleventh connecting electrode 51 on the silicon substrate, the fourth insulating layer and the fifth insulating layer within the thirty-first via V31 are etched away, exposing the surface of the eleventh connecting electrode 51, and the thirty-first via V31 is configured to enable the twenty-first connecting electrode formed subsequently to connect with the eleventh connecting electrode 51 through the via.

[0345] In an example embodiment, the orthogonal projection of the thirty-first via V31 on the silicon substrate at least partially overlaps with the orthogonal projection of the first center line O1 on the silicon substrate.

[0346] In an example embodiment, the orthogonal projection of the thirty-second via V32 on the silicon substrate can be located within the range of the orthogonal projection of the twelfth connecting electrode 52 on the silicon substrate, the fourth insulating layer and the fifth insulating layer within the thirty-second via V32 are etched away, exposing the surface of the twelfth connecting electrode 52, and the thirty-second via V32 is configured to enable the third connecting line formed subsequently to connect with the twelfth connecting electrode 52 through the via.

[0347] In an example embodiment, the orthogonal projection of the thirty-third via V33 on the silicon substrate is located within the range of the orthogonal projection of the thirteenth connecting electrode 53 on the silicon substrate, the fourth insulating layer and the fifth insulating layer within the thirty-third via V33 are etched away, exposing the surface of the thirteenth connecting electrode 53, and the thirty-third via V33 is configured to enable the fourth plate formed subsequently to connect with the thirteenth connecting electrode 53 through the via.

[0348] In an example embodiment, the orthogonal projection of the thirty-fourth via V34 on the silicon substrate is located within the range of the orthogonal projection of the fourteenth connecting electrode 54 on the silicon substrate, the fourth insulating layer and the fifth insulating layer within the thirty-fourth via V34 are etched away, exposing the surface of the fourteenth connecting electrode 54, and the thirty-fourth via V34 is configured to enable the third scanning signal line formed subsequently to connect with the fourteenth connecting electrode 54 through the via.

[0349] In an example embodiment, the orthogonal projection of the thirty-fifth via V35 on the silicon substrate is located within the range of the orthogonal projection of the fifteenth connecting electrode 55 on the silicon substrate, the fourth insulating layer and the fifth insulating layer within the thirty-fifth via V35 are etched away, exposing the surface of the fifteenth connecting electrode 55, and the thirty-fifth via V35 is configured to enable the twenty-second connecting electrode formed subsequently to connect with the fifteenth connecting electrode 55 through the via.

[0350] In an example embodiment, the orthogonal projection of the thirty-sixth via V36 on the silicon substrate is within the range of the orthogonal projection of the fourth plate 140 on the silicon substrate, the fifth insulating layer in the thirty-sixth via V36 is etched to expose the surface of the fourth plate 140, and the thirty-sixth via V36 is configured to connect the fifth plate formed subsequently to the fourth plate 140 through the via. In an example embodiment, the thirty-sixth via V36 can be multiple, and the multiple vias can be arranged in sequence along the second direction Y to reduce the contact resistance and improve the connection reliability.

[0351] (11) Forming a fourth conductive layer pattern. In an example embodiment, forming the fourth conductive layer pattern can include: depositing a fourth conductive thin film on the silicon substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film through a patterning process to form the fourth conductive layer pattern on the fifth insulating layer, as shown in FIGS. 17A and 17B, which is a schematic diagram of the fourth conductive layer in FIG. 17A. In an example embodiment, the fourth conductive layer can be referred to as a third metal (Metal3) layer.

[0352] In an example embodiment, the fourth conductive layer pattern in each sub-pixel in the display substrate can include at least: a third scan signal line 33, a twenty-first connection electrode 61, a twenty-second connection electrode 62, a third connection line 93, a fourth connection line 94, and a fifth plate 150.

[0353] In an example embodiment, the third scan signal line 33 can have a shape of a straight line with a main body portion extending along the first direction X, can be located on the side of the third plate 130 away from the first scan signal line 31, and the third scan signal line 33 can be connected to the fourteenth connection electrode 54 through the thirty-fourth via V34. Since the fourteenth connection electrode 54 is connected to the fourth connection electrode 44 through the via, the fourth connection electrode 44 is connected to the fourth gate connection block 24-1 through the via, and the fourth gate connection block 24-1 is connected to the fourth gate electrode 24, the third scan signal line 33 is connected to the gate electrode of the fourth transistor T4 in each sub-pixel, and the third scan signal line 33 can control the conduction or disconnection of the fourth transistor T4.

[0354] In an example embodiment, the two third scan signal lines 33 in adjacent pixel rows can have a signal line spacing D1, and the signal line spacing D1 can be greater than or equal to 1 μm, which can significantly reduce the crosstalk between the third scan signal lines 33,

[0355] In the example embodiment, the fifth plate 150 can be rectangular in shape, and the corners of the rectangular shape can be chamfered or recessed. The fifth plate 150 has a projection on the silicon substrate that at least partially overlaps the projection of the fourth plate 140 on the silicon substrate. The fifth plate 150 is connected to the thirteenth connection electrode 53 via the thirty-third via V33 and connected to the fourth plate 140 via the thirty-sixth via V36. Since the thirteenth connection electrode 53 is connected to the second plate 120 via a via, the fourth plate 140 and the fifth plate 150 have the potential of the second node N2, and the fifth plate 150 can serve as one plate of the second capacitor.

[0356] In the example embodiment, since the third plate 130 has the potential of the first node N1 and the fourth plate 140 has the potential of the second node N2, the third plate 130 and the fourth plate 140 form a third sub-capacitor of the first capacitor.

[0357] In the example embodiment, the first capacitor includes the first plate 110, the second plate 120, the third plate 130, and the fourth plate 140 stacked one on top of another. The first plate 110 and the third plate 130 have the potential of the first node N1, and the second plate 120 and the fourth plate 140 have the potential of the second node N2. The first plate 110 and the second plate 120 form a first sub-capacitor, the second plate 120 and the third plate 130 form a second sub-capacitor, and the third plate 130 and the fourth plate 140 form a third sub-capacitor. The first sub-capacitor, the second sub-capacitor, and the third sub-capacitor are connected in parallel to form the first capacitor.

[0358] The present disclosure forms the first sub-capacitor, the second sub-capacitor, and the third sub-capacitor using the gate conductive layer, the first conductive layer, the second conductive layer, and the third conductive layer, respectively. The first sub-capacitor, the second sub-capacitor, and the third sub-capacitor are connected in parallel to form the first capacitor of the MIM capacitor structure. This maximizes the capacitance of the first capacitor, ensures the stability of the output current of the pixel driving circuit, ensures the stability of the OLED brightness, and can avoid crosstalk and flicker and other malfunctions. The structure of the first capacitor of the present disclosure is simple and the layout is reasonable. In the case of ensuring the capacitance, the occupied area of the capacitor plate can be effectively reduced, which is conducive to improving the resolution.

[0359] In the example embodiment, the twenty-first connection electrode 61 can be in the shape of a strip extending along the first direction X and can be disposed on the side of the second scan signal line 32 away from the fifth plate 150. The twenty-first connection electrode 61 can be connected to the eleventh connection electrode 51 via the thirty-first via V31, and the twenty-first connection electrode 61 is configured to be connected to the data signal line formed later.

[0360] In the example embodiment, in at least one of the sub-pixels, the orthogonal projection of the twenty-first connection electrode 61 on the silicon substrate at least partially overlaps with the orthogonal projection of the first center line O1 on the silicon substrate, and adjacent sub-pixels in one pixel column can share the same twenty-first connection electrode 61.

[0361] In the example embodiment, the twenty-second connection electrode 62 can be in the shape of a strip extending along the first direction X, can be arranged between the third scan signal line 33 and the fifth plate 150, and the twenty-second connection electrode 62 is connected to the fifteenth connection electrode 55 through the thirty-fifth via V35. The twenty-second connection electrode 62 is configured to be connected to the plate connection electrode formed subsequently.

[0362] In the example embodiment, the third connection line 93 can be in the shape of a straight line with the main body part extending along the first direction X, can be arranged between the first scan signal line 31 and the fifth plate 150, and the third connection line 93 can be connected to the twelfth connection electrode 52 through the thirty-second via V32. Since the twelfth connection electrode 52 is connected to the first power supply line 81 through the via, the third connection line 93 has the potential of the first power supply line.

[0363] In the example embodiment, the fourth connection line 94 can be in the shape of a straight line with the main body part extending along the second direction Y. In the first direction X, the fourth connection line 94 can be arranged between two fifth plates 150 of adjacent pixel columns. In the second direction Y, the fourth connection line 94 can be arranged between the third connection line 93 and the third scan signal line 33.

[0364] In the example embodiment, one end of the fourth connection line 94 away from the third scan signal line 33 is connected to the third connection line 93, thus realizing the interconnection between the third connection line 93 extending along the first direction X and the fourth connection line 94 extending along the second direction Y. The third connection line 93 and the fourth connection line 94 form a first layer meshed communication structure on the display substrate to transmit the first power supply signal, which not only can effectively reduce the resistance of the first power supply line and reduce the voltage drop of the first power supply signal, but also can effectively improve the uniformity of the first power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0365] In the example embodiment, the orthogonal projection of the third connection line 93 on the silicon substrate at least partially overlaps with the orthogonal projection of the first power supply line 81 on the silicon substrate, forming a double-layer power supply line transmitting the first power supply signal, and the first power supply line 81 extending along the first direction X and the fourth connection line 94 extending along the second direction Y can form a different-layer meshed communication structure transmitting the first power supply signal on the display substrate, which can further reduce the resistance of the first power supply line, further reduce the voltage drop of the first power supply signal, further improve the uniformity of the first power supply signal in the display substrate, further improve the display uniformity, and further improve the display quality and display performance.

[0366] In the example embodiment, the third connection line 93 and the fourth connection line 94 in at least one sub-pixel can be an integrated structure connected to each other.

[0367] In the example embodiment, the third connection line 93 and the fourth connection line 94 in at least one sub-pixel can be an integrated structure connected to each other.

[0368] In the example embodiment, the third connection line 93 and the fourth connection line 94 in at least one sub-pixel can be an integrated structure connected to each other.

[0369] In the example embodiment, the third connection line 93 and the fourth connection line 94 in at least one sub-pixel can be an integrated structure connected to each other.

[0370] (12) Forming the sixth insulating layer and the fifth conductive layer pattern. In the example embodiment, forming the sixth insulating layer and the fifth conductive layer pattern can include: sequentially depositing a sixth insulating film and a fifth conductive film on the silicon substrate on which the aforementioned patterns are formed, patterning the fifth conductive film by a patterning process, forming the sixth insulating layer covering the fourth conductive layer pattern, and forming the fifth conductive layer pattern on the sixth insulating layer, as shown in FIGS. 18A and 18B, FIG. 18B being a schematic view of the fifth conductive layer in FIG. 18A. In the example embodiment, the fifth conductive layer can be referred to as a top plate (CTOP) layer.

[0371] In the example embodiment, the fifth conductive layer pattern in each sub-pixel can at least include a sixth plate 160.

[0372] In the example embodiment, the sixth plate 160 can be rectangular in shape, and the corner of the rectangular shape can be provided with a chamfer or a groove, which can be arranged between the twenty-second connection electrode 62 and the third connection line 93. The orthogonal projection of the sixth plate 160 on the silicon substrate at least partially overlaps with the orthogonal projection of the fifth plate 150 on the silicon substrate, and the sixth plate 160 can serve as one plate of the second capacitor.

[0373] In the example embodiment, the fifth conductive layer pattern of the adjacent pixel rows can be mirror symmetrical relative to the first center line O1, and the fifth conductive layer of the adjacent pixel columns can be mirror symmetrical relative to the second center line O2.

[0374] (13) Forming a seventh insulating layer pattern. In the example embodiment, forming the seventh insulating layer pattern can include: depositing a seventh insulating thin film on the silicon substrate on which the aforementioned patterns are formed, patterning the seventh insulating thin film by a patterning process, forming a seventh insulating layer covering the fifth conductive layer pattern, and the seventh insulating layer being provided with a plurality of vias, as shown in FIG. 19.

[0375] In the example embodiment, the plurality of vias in each sub-pixel can include: a forty-first via V41, a forty-second via V42, a forty-third via V43, and a forty-fourth via V44.

[0376] In the example embodiment, the orthogonal projection of the forty-first via V41 on the silicon substrate is within the range of the orthogonal projection of the twenty-first connecting electrode 61 on the silicon substrate, the seventh insulating layer and the sixth insulating layer in the forty-first via V41 are etched away, exposing the surface of the twenty-first connecting electrode 61, and the forty-first via V41 is configured to allow the subsequently formed data connecting block to connect with the twenty-first connecting electrode 61 through the via.

[0377] In the example embodiment, the orthogonal projection of the forty-second via V42 on the silicon substrate is within the range of the orthogonal projection of the twenty-second connecting electrode 62 on the silicon substrate, the seventh insulating layer and the sixth insulating layer in the forty-second via V42 are etched away, exposing the surface of the twenty-second connecting electrode 62, and the forty-second via V42 is configured to allow the subsequently formed plate connecting electrode to connect with the twenty-second connecting electrode 62 through the via.

[0378] In the example embodiment, the orthogonal projection of the forty-third via V43 on the silicon substrate is within the range of the orthogonal projection of the sixth plate 160 on the silicon substrate, the seventh insulating layer in the forty-third via V43 is etched away, exposing the surface of the sixth plate 160, and the forty-third via V43 is configured to allow the subsequently formed plate connecting electrode to connect with the sixth plate 160 through the via. In the example embodiment, the forty-third via V43 can be multiple, and the multiple vias can be sequentially arranged along the second direction Y to reduce the contact resistance and improve the connection reliability.

[0379] In the example embodiment, the orthogonal projection of the forty-fourth via V44 on the silicon substrate is located within the range of the orthogonal projection of the third connection line 93 on the silicon substrate, the seventh insulating layer and the sixth insulating layer in the forty-fourth via V44 are etched away to expose the surface of the third connection line 93, and the forty-fourth via V44 is configured to enable the twenty-third connection electrode formed subsequently to connect with the third connection line 93 through the via.

[0380] (14) Forming a sixth conductive layer pattern. In the example embodiment, forming the sixth conductive layer pattern can include: depositing a sixth conductive thin film on the silicon substrate on which the aforementioned patterns are formed, and patterning the sixth conductive thin film through a patterning process to form the sixth conductive layer pattern on the seventh insulating layer, as shown in FIGS. 20A and 20B, which is a schematic diagram of the sixth conductive layer in FIG. 20A. In the example embodiment, the sixth conductive layer can be referred to as a fourth metal (Metal4) layer.

[0381] In the example embodiment, the sixth conductive layer pattern in each sub-pixel can at least include: the twenty-third connection electrode 63, the data signal line 83, and the plate connection electrode 170.

[0382] In the example embodiment, the shape of the twenty-third connection electrode 63 can be block-shaped (e.g., rectangular), the twenty-third connection electrode 63 is connected with the third connection line 93 through the forty-fourth via V44, and the twenty-third connection electrode 63 is configured to be connected with the fifth connection line formed subsequently.

[0383] In the example embodiment, the shape of the data signal line 83 can be a straight line or a polyline extending along the second direction Y, and the data signal line 83 can be arranged between two plate connection electrodes 170 of adjacent pixel columns. The data signal line 83 can be provided with a data connection block 83-1, the shape of the data connection block 83-1 can be a strip extending along the first direction X, the first end of the data connection block 83-1 is connected with the data signal line 83, and the second end of the data connection block 83-1 extends along the first direction X and is connected with the twenty-first connection electrode 61 through the forty-first via V41. Since the twenty-first connection electrode 61 is connected with the eleventh connection electrode 51 through a via, the eleventh connection electrode 51 is connected with the first connection electrode 41 through a via, and the first connection electrode 41 is connected with the first source electrode region through a via, the data signal line 83 can write a data signal to the first electrode of the first transistor T1.

[0384] In the example embodiment, the orthogonal projection of the data connection block 83-1 on the silicon substrate at least partially overlaps with the orthogonal projection of the first center line O1 on the silicon substrate, and adjacent sub-pixels in one pixel column can share the same data connection block 83-1, which effectively reduces the number of connection electrodes, reduces the occupied area of the pixel driving circuit, and is conducive to achieving high resolution.

[0385] In the example embodiment, the data signal line 83 and the data connection block 83-1 in at least one pixel column can be an integrated structure connected to each other.

[0386] In the example embodiment, since the first source region, the first connection electrode 41, the eleventh connection electrode 51, the twenty-first connection electrode 61 and the data connection block 83-1 are shared by adjacent sub-pixels in one pixel column, the two first transistors T1 of adjacent sub-pixels in one pixel column are written with the same data signal.

[0387] In the example embodiment, the orthogonal projection of the data signal line 83 on the silicon substrate at least partially overlaps with the orthogonal projection of the fourth connection line 94 on the silicon substrate, and the fourth connection line 94 with a constant potential can shield the influence of the jump voltage in the data signal line 83 on the key nodes of the pixel driving circuit.

[0388] In the example embodiment, the orthogonal projection of the data signal line 83 on the silicon substrate does not overlap with the orthogonal projection of the plurality of plates on the silicon substrate, which can reduce the parasitic capacitance between the data signal line and each plate, avoid the influence of the corresponding electrodes in the pixel driving circuit on the data voltage of the data signal line, improve the anti-interference ability of the data signal line, and maximize the display quality.

[0389] In the example embodiment, the shape of the plate connection electrode 170 can be block-shaped (such as rectangular), which can be arranged between the third scan signal line 33 and the third connection line 93. The orthogonal projection of the plate connection electrode 170 on the silicon substrate at least partially overlaps with the orthogonal projection of the sixth plate 160 on the silicon substrate. The plate connection electrode 170 is connected to the twenty-second connection electrode 62 through the forty-second via V42 and connected to the sixth plate 160 through the forty-third via V43. Since the twenty-second connection electrode 62 is connected to the fifteenth connection electrode 55 through a via, the fifteenth connection electrode 55 is connected to the third node electrode 45 through a via, and the third node electrode 45 realizes the connection between the second electrode of the third transistor T2 and the second electrode of the fourth transistor T4, forming the third node N3 of the pixel driving circuit, the sixth plate 160 and the plate connection electrode 170 have the potential of the third node N3.

[0390] In the example embodiment, since the fifth plate 150 has the potential of the second node N2 and the sixth plate 160 has the potential of the third node N3, the fifth plate 150 and the sixth plate 160 form the second capacitor.

[0391] In the example embodiment, the sixth conductive layer pattern of adjacent pixel rows can be mirror-symmetrical relative to the first center line O1, and the sixth conductive layer pattern of adjacent pixel columns can be mirror-symmetrical relative to the second center line O2.

[0392] (15) Forming an eighth insulating layer pattern. In an exemplary embodiment, forming the eighth insulating layer pattern can include: depositing an eighth insulating thin film on the silicon substrate on which the aforementioned patterns are formed, patterning the eighth insulating thin film through a patterning process, forming the eighth insulating layer covering the sixth conductive layer pattern, the eighth insulating layer being provided with a plurality of vias, as shown in FIG. 21.

[0393] In an exemplary embodiment, the plurality of vias in each sub-pixel can include: a fifty-first via V51 and a fifty-second via V52.

[0394] In an exemplary embodiment, the fifty-first via V51 has a projection on the silicon substrate within the range of the orthogonal projection of the twenty-third connecting electrode 63 on the silicon substrate, the eighth insulating layer in the fifty-first via V51 is etched away, exposing the surface of the twenty-third connecting electrode 63, and the fifty-first via V51 is configured to allow the fifth connecting line formed subsequently to pass through the via and connect with the twenty-third connecting electrode 63.

[0395] In an exemplary embodiment, the fifty-second via V52 has a projection on the silicon substrate within the range of the orthogonal projection of the plate connecting electrode 170 on the silicon substrate, the eighth insulating layer in the fifty-second via V52 is etched away, exposing the surface of the plate connecting electrode 170, and the fifty-second via V52 is configured to allow the anode connecting electrode formed subsequently to pass through the via and connect with the plate connecting electrode 170.

[0396] (16) Forming a seventh conductive layer pattern. In an exemplary embodiment, forming the seventh conductive layer pattern can include: sequentially depositing a seventh conductive thin film on the silicon substrate on which the aforementioned patterns are formed, patterning the seventh conductive thin film through a patterning process, forming the seventh conductive layer pattern disposed on the eighth insulating layer, as shown in FIGS. 22A and 22B, FIG. 22B being a schematic diagram of the seventh conductive layer in FIG. 22A. In an exemplary embodiment, the seventh conductive layer can be referred to as a fifth metal (Metal 5) layer or a second metal connecting (TM2) layer.

[0397] In an exemplary embodiment, the seventh conductive layer in each sub-pixel can at least include: an anode connecting electrode 84, a fifth connecting line 95, and a sixth connecting line 96.

[0398] In an example embodiment, the anode connecting electrode 84 can be in a strip shape extending along the second direction Y, the anode connecting electrode 84 can be connected with the plate connecting electrode 170 through the fifty-second via V52, and the anode connecting electrode 84 is configured to be connected with the subsequently formed anode. Since the plate connecting electrode 170 has the potential of the third node N3, the connection of the subsequently formed anode with the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4 (the third node N3 of the pixel driving circuit) can be achieved, and the current output by the pixel driving circuit can be provided to the anode.

[0399] In an example embodiment, the fifth connecting line 95 can be in a straight line shape with the main body part extending along the first direction X, can be arranged between the second scan signal line 32 and the plate connecting electrode 170, and the fifth connecting line 95 is connected with the twenty-third connecting electrode 63 through the fifty-first via V51.

[0400] In an example embodiment, the sixth connecting line 96 can be in a straight line shape with the main body part extending along the second direction Y, can be arranged between two plate connecting electrodes 170 of adjacent pixel columns, and is connected with the fifth connecting line 95.

[0401] In an example embodiment, since the twenty-third connecting electrode 63 is connected with the third connecting line 93 through the via, the third connecting line 93 is connected with the twelfth connecting electrode 52 through the via, and the twelfth connecting electrode 52 is connected with the first power supply line 81 through the via, the fifth connecting line 95 and the sixth connecting line 96 have the potential of the first power supply line, the mutual connection between the fifth connecting line 95 extending along the first direction X and the sixth connecting line 96 extending along the second direction Y is achieved, the fifth connecting line 95 and the sixth connecting line 96 form a second layer meshed communication structure transmitting the first power supply signal on the display substrate, which not only can effectively reduce the resistance of the first power supply line and reduce the voltage drop of the first power supply signal, but also can effectively improve the uniformity of the first power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0402] In the example embodiment, the orthogonal projection of the fifth connection line 95 on the silicon substrate at least partially overlaps with the orthogonal projection of the first power supply line 81 and the third connection line 93 on the silicon substrate, forming a three-layer power supply line transmitting the first power supply signal. The first power supply line 81 extending along the first direction X and the sixth connection line 96 extending along the second direction Y can form another layer-by-layer meshed communication structure transmitting the first power supply signal on the display substrate. The third connection line 93 extending along the first direction X and the sixth connection line 96 extending along the second direction Y can form another layer-by-layer meshed communication structure transmitting the first power supply signal on the display substrate. The resistance of the first power supply line can be further reduced, the voltage drop of the first power supply signal can be further reduced, the uniformity of the first power supply signal in the display substrate can be further improved, the display uniformity can be further improved, and the display quality and display performance can be further improved.

[0403] In the example embodiment, in at least one sub-pixel, the fifth connection line 95 and the sixth connection line 96 can be an integrated structure connected to each other.

[0404] In the example embodiment, the fifth connection line 95 and the sixth connection line 96 in one pixel row can be an integrated structure connected to each other.

[0405] In the example embodiment, in at least one pixel column, the sixth connection lines 96 in adjacent sub-pixels can be an integrated structure connected to each other.

[0406] In the example embodiment, the orthogonal projection of the sixth connection line 96 on the silicon substrate at least partially overlaps with the orthogonal projection of the data signal line 83 on the silicon substrate. The sixth connection line 96 with a constant potential can shield the influence of the jump voltage in the data signal line 83 on the key nodes of the pixel driving circuit.

[0407] In the example embodiment, the fourth connection line 94 and the sixth connection line 96 are arranged below and above the data signal line 83 in the direction perpendicular to the silicon substrate, respectively, which can shield the influence of the jump voltage in the data signal line 83 on the key nodes of the pixel driving circuit from the top and bottom directions.

[0408] In the example embodiment, the seventh conductive layer can further include a seventh connection line 97. The seventh connection line 97 can be in the shape of a straight line with a main body extending along the first direction X, and can be arranged between two third scan signal lines 33 in adjacent pixel rows.

[0409] In the example embodiment, the seventh connection line 97 is connected with the plurality of sixth connection lines 96, so that the seventh connection line 97 has the potential of the first power supply line, and the interconnection between the seventh connection line 97 extending along the first direction X and the sixth connection line 96 extending along the second direction Y is realized, and the seventh connection line 97 and the sixth connection line 96 form a second layer meshed communication structure for transmitting the first power supply signal on the display substrate, which can further reduce the resistance of the first power supply line, further reduce the voltage drop of the first power supply signal, further improve the uniformity of the first power supply signal in the display substrate, further improve the display uniformity, and further improve the display quality and display performance.

[0410] In the example embodiment, the fifth connection line 95, the sixth connection line 96 and the seventh connection line 97 in at least one sub-pixel can be an integrated structure.

[0411] In the example embodiment, the seventh connection line 97, the two fifth connection lines 95 and the plurality of sixth connection lines 96 of the adjacent pixel rows can be an integrated structure.

[0412] In the example embodiment, the two horizontal power supply lines (the fifth connection line 95 and the seventh connection line 97) and the two vertical power supply lines (the sixth connection line 96) in the second layer meshed communication structure for transmitting the first power supply signal can surround one sub-pixel, which can minimize the signal interference between the sub-pixels.

[0413] In the example embodiment, the seventh conductive layer pattern of the adjacent pixel rows can be mirror-symmetrical relative to the first center line O1, and the seventh conductive layer pattern of the adjacent pixel columns can be mirror-symmetrical relative to the second center line O2.

[0414] In the example embodiment, the subsequent preparation process can include forming an anode, a pixel definition layer, an organic light-emitting layer, a cathode, a first encapsulation layer, a color film structure layer and a second encapsulation layer, and the like, which will not be described here.

[0415] In the example embodiment, the first to eighth insulating layers can be made of silicon oxide SiOx, silicon nitride SiNx or silicon oxynitride SiON, and can be a single-layer structure or a multi-layer composite structure. The first to fifth metal layers can be made of metal materials such as silver (Ag), copper (Cu), aluminum (Al) or molybdenum (Mo), or can be made of alloy materials composed of metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and the alloy materials can be a single-layer structure or a multi-layer composite structure, such as a composite structure composed of a Mo layer, a Cu layer and a Mo layer. In the example embodiment, the planar shape of the via can be rectangular, circular or elliptical, and the sizes of the plurality of vias can be the same or different, which is not limited in the present disclosure.

[0416] FIG. 23 is a structural schematic diagram of the first capacitor and the second capacitor according to an exemplary embodiment of the present disclosure. As shown in FIG. 23, the first capacitor and the second capacitor are a stacked structure, and the second capacitor is arranged on a side of the first capacitor away from the silicon substrate. The first capacitor can include the first electrode plate 110, the second electrode plate 120, the third electrode plate 130, and the fourth electrode plate 140 stacked, and the second capacitor can include the fifth electrode plate 150 and the sixth electrode plate 160 stacked.

[0417] In an exemplary embodiment, the display substrate can at least include: a silicon substrate 101, a first insulating layer 201 arranged on the silicon substrate 101, a gate conductive layer arranged on a side of the first insulating layer 201 away from the silicon substrate 101, a second insulating layer 202 arranged on a side of the gate conductive layer away from the silicon substrate 101, a first conductive layer (Metal 1) arranged on a side of the second insulating layer 202 away from the silicon substrate 101, a third insulating layer 203 arranged on a side of the first conductive layer away from the silicon substrate 101, a second conductive layer (Metal 2) arranged on a side of the third insulating layer 203 away from the silicon substrate 101, a fourth insulating layer 204 arranged on a side of the second conductive layer away from the silicon substrate 101, a third conductive layer (MIM) arranged on a side of the fourth insulating layer 204 away from the silicon substrate 101, a fifth insulating layer 205 arranged on a side of the third conductive layer away from the silicon substrate 101, a fourth conductive layer (Metal 3) arranged on a side of the fifth insulating layer 205 away from the silicon substrate 101, a sixth insulating layer 206 arranged on a side of the fourth conductive layer away from the silicon substrate 101, a fifth conductive layer (CTOP) arranged on a side of the sixth insulating layer 206 away from the silicon substrate 101, a seventh insulating layer 207 arranged on a side of the fifth conductive layer away from the silicon substrate 101, a sixth conductive layer (Metal 4) arranged on a side of the seventh insulating layer 207 away from the silicon substrate 101, an eighth insulating layer 208 arranged on a side of the sixth conductive layer away from the silicon substrate 101, and a seventh conductive layer (Metal 5) arranged on a side of the eighth insulating layer 208 away from the silicon substrate 101.

[0418] In an exemplary embodiment, the gate conductive layer can at least include the first electrode plate 110, the first conductive layer can at least include the second electrode plate 120, the second conductive layer can at least include the third electrode plate 130, the third conductive layer can at least include the fourth electrode plate 140, the fourth conductive layer can at least include the fifth electrode plate 150, the fifth conductive layer can at least include the sixth electrode plate 160, the sixth conductive layer can at least include the electrode plate connecting electrode 170, and the seventh conductive layer can at least include the anode connecting electrode 84.

[0419] In the example embodiment, the first plate 110 serves as the gate electrode of the third transistor T3, and thus the first plate 110 has the potential of the first node N1. The second plate 120 is connected to the second electrode of the second transistor T2 and the first electrode of the third transistor T3, and thus the second plate 120 has the potential of the second node N2. The third plate 130 is connected to the first plate 110 through the first node electrode 43, and thus the third plate 130 has the potential of the first node N1. The fourth plate 140 is connected to the fifth plate 150 through a via, and the fifth plate 150 is connected to the second plate 120 through the thirteenth connection electrode 53, and thus the fourth plate 140 and the fifth plate 150 have the potential of the second node N2. The sixth plate 160 is connected to the plate connection electrode 170 through a via, and the plate connection electrode 170 is connected to the second electrode of the third transistor T2 and the second electrode of the fourth transistor T4 through a plurality of connection electrodes, and thus the sixth plate 160 and the plate connection electrode 170 have the potential of the third node N3. In this way, the first plate 110 and the second plate 120 form a first sub-capacitor of the first capacitor, the second plate 120 and the third plate 130 form a second sub-capacitor of the first capacitor, the third plate 130 and the fourth plate 140 form a third sub-capacitor of the first capacitor, the first sub-capacitor, the second sub-capacitor, and the third sub-capacitor in parallel form the first capacitor of the pixel driving circuit, the fifth plate 150 and the sixth plate 160 form the second capacitor of the pixel driving circuit, and the second capacitor is arranged on the side of the first capacitor away from the silicon substrate.

[0420] In the example embodiment, since the first capacitor and the second capacitor are both flat-plate capacitor structures, only one insulating layer is arranged between the first plate 110 and the second plate 120, only one insulating layer is arranged between the second plate 120 and the third plate 130, only one insulating layer is arranged between the third plate 130 and the fourth plate 140, and only one insulating layer is arranged between the fifth plate 150 and the sixth plate 160, and thus the capacity of the first capacitor and the second capacitor can be effectively guaranteed, the arrangement of the pixel driving circuit can be more compact under the premise of meeting the design requirements, and the resolution of the display device can be improved.

[0421] In the example embodiment, the capacity of the first capacitor and the second capacitor can be further increased by increasing the number of conductive layers, which is not limited in the present disclosure.

[0422] In the example embodiment, subsequent manufacturing processes can include forming an anode, a pixel definition layer, an organic light-emitting layer, a cathode, a first encapsulation layer, a color filter structure layer, and a second encapsulation layer, which are not described here.

[0423] The display substrate provided by the example embodiments of the present disclosure can effectively shield the fourth transistor T4 and the third node N3 in the sub-pixel by setting the first shielding structure surrounding the fourth transistor T4 in three directions and the first shielding structure having the potential of the second power supply line, can effectively reduce the mutual interference between the adjacent fourth transistor T4 and the third node N3, improve the reset performance and working stability of the fourth transistor T4, and improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0424] The display substrate provided by the example embodiments of the present disclosure can effectively shield the fourth transistor T4 and the third node N3 in the sub-pixel by setting the first shielding structure surrounding the fourth transistor T4 in three directions and the first shielding structure having the potential of the second power supply line, can effectively reduce the mutual interference between the adjacent fourth transistor T4 and the third node N3, improve the reset performance and working stability of the fourth transistor T4, and improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0425] The display substrate provided by the example embodiments of the present disclosure can effectively shield the fourth transistor T4 and the third node N3 in the sub-pixel by setting the first shielding structure surrounding the fourth transistor T4 in three directions and the first shielding structure having the potential of the second power supply line, can effectively reduce the mutual interference between the adjacent fourth transistor T4 and the third node N3, improve the reset performance and working stability of the fourth transistor T4, and improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0426] The display substrate provided by the example embodiments of the present disclosure can effectively shield the fourth transistor T4 and the third node N3 in the sub-pixel by setting the first shielding structure surrounding the fourth transistor T4 in three directions and the first shielding structure having the potential of the second power supply line, can effectively reduce the mutual interference between the adjacent fourth transistor T4 and the third node N3, improve the reset performance and working stability of the fourth transistor T4, and improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0427] The display substrate provided by the example embodiments of the present disclosure can effectively shield the fourth transistor T4 and the third node N3 in the sub-pixel by setting the first shielding structure surrounding the fourth transistor T4 in three directions and the first shielding structure having the potential of the second power supply line, can effectively reduce the mutual interference between the adjacent fourth transistor T4 and the third node N3, improve the reset performance and working stability of the fourth transistor T4, and improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0428] The present disclosure improves the uniformity and symmetry of the pixel driving circuit by mirroring the pixel driving circuit of the adjacent pixel rows relative to the first center line and mirroring the pixel driving circuit of the adjacent pixel columns relative to the second center line, which not only realizes the uniformity design of the process and the coupling capacitance, but also realizes the uniformity design of the current distribution, effectively improves the display stability and uniformity, and effectively improves the display effect and display quality.

[0429] The present disclosure mirrors the first transistor T1 of the adjacent pixel rows and shares the first electrode of the first transistor T1, mirrors the second transistor T2 of the adjacent pixel rows and shares the first electrode of the second transistor T2, and mirrors the fourth transistor T4 of the adjacent pixel columns and shares the first electrode of the fourth transistor T4, which can effectively reduce the horizontal and vertical wiring space, reduce the number of vias, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution.

[0430] The present disclosure can effectively reduce the layout space of the substrate area and the occupied area of the pixel driving circuit by sharing the same type of substrate area for the same type of transistor, which is conducive to the realization of high resolution.

[0431] The present disclosure forms a first capacitor, a second capacitor and a third capacitor by using a gate conductive layer, a first conductive layer, a second conductive layer and a third conductive layer, respectively, and forms a first capacitor of MIM capacitor structure by using the first capacitor, the second capacitor and the third capacitor in parallel structure, which maximizes the capacitance value of the first capacitor, ensures the stability of the output current of the pixel driving circuit, ensures the stability and display uniformity of OLED brightness, and reduces the risk of display defects such as screen flashing. The structure of the first capacitor of the present disclosure is simple and reasonable in layout, which can effectively reduce the occupied area of the capacitor plate under the condition of ensuring the capacitance value, and is conducive to improving the resolution.

[0432] The present disclosure sets the first capacitor and the second capacitor in a flat plate capacitor structure, and the first capacitor and the second capacitor are stacked, which not only solves the problem of capacitor area limitation, but also superimposes the parasitic capacitance generated by the stacked structure to the capacitor itself, reduces the influence of parasitic capacitance, has gain on the capacitance value, ensures the stability and uniformity of the output current of the pixel driving circuit, and makes the arrangement of the pixel driving circuit more compact under the premise of meeting the design requirements, which is helpful to improve the resolution of the display device.

[0433] The fourth connection line and the sixth connection line can shield the influence of the jump voltage in the data signal line on the key nodes of the pixel driving circuit from the top and bottom directions. The data signal line does not overlap with the plurality of polar plates, which can reduce the parasitic capacitance between the data signal line and each polar plate, avoid the influence of the corresponding electrode in the pixel driving circuit on the data voltage of the data signal line, improve the anti-interference ability of the data signal line, and maximize the display quality.

[0434] The layout of the pixel driving circuit is optimized by the above structural design, the layout space is optimized, the resistance of the power supply trace is significantly reduced, the crosstalk to the key nodes of the pixel driving circuit is significantly reduced, the proportion of trace defects is significantly reduced, the product yield is significantly improved, the occupied area of the pixel driving circuit is effectively reduced, and the display substrate can meet the display with a resolution of 4K*4K and a refresh frequency of 60Hz to 120Hz. The stability and smoothness of the display picture are better, the dizziness in VR application and the screen door effect in AR application can be effectively reduced, the sense of immersion is effectively increased, and the user experience is effectively improved.

[0435] The preparation process of the display substrate is based on a 0.11-micron integrated circuit process, which can be well compatible with the existing preparation process, has simple process implementation, is easy to implement, has high production efficiency, low production cost, and high yield.

[0436] In example embodiments, the display substrate of the present disclosure can be applied to display devices with pixel driving circuits, such as Micro OLED micro display, OLED display, quantum dot display (QLED), light-emitting diode micro display (Micro LED or Mini LED), or quantum dot light-emitting diode micro display (QDLED), etc., which are not limited herein.

[0437] In example embodiments, the pixel driving circuit of the display substrate of the present disclosure can be applied to product types including but not limited to integrated silicon-based, glass-based, printed circuit board (PCB)-based, etc. substrate materials, amorphous silicon (a-Si), low-temperature polysilicon (LTPS), low-temperature polysilicon oxide (LTPO), oxide semiconductor materials represented by indium gallium zinc oxide (IGZO), thin film transistors (TFT) with back channel etching structure (BCE), etching stop layer structure (ESL), top gate structure (Top Gate), dual gate structure (Dual Gate), etc., metal oxide semiconductor (MOS), diode (Diode), etc.

[0438] The structure of the display device and the preparation process thereof in the exemplary embodiments of the present disclosure are merely exemplary, and the corresponding structure can be changed, and the patterning process can be increased or reduced, which is not limited herein.

[0439] The exemplary embodiments of the present disclosure also provide a preparation method of a display substrate for preparing the aforementioned display substrate. In the exemplary embodiments, the display substrate includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns; and the preparation method can include:

[0440] forming a pixel driving circuit in at least one sub-pixel, the pixel driving circuit including at least a first transistor, a second transistor, a third transistor, and a fourth transistor, a first electrode of the first transistor being coupled with a data signal line, a second electrode of the first transistor being coupled with a gate electrode of the third transistor, a first electrode of the second transistor being coupled with a first power supply line, a second electrode of the second transistor being coupled with a first electrode of the third transistor, a first electrode of the fourth transistor being coupled with a second power supply line, a second electrode of the fourth transistor being coupled with a second electrode of the third transistor, the first power supply line being configured to provide a first power supply signal to the pixel driving circuit, the second power supply line being configured to provide a second power supply signal to the pixel driving circuit, a voltage of the first power supply signal being greater than a voltage of the second power supply signal; the second transistor and the fourth transistor being respectively disposed on two sides of the third transistor in a second direction, the second power supply line being in a shape of a straight line or a broken line extending along a first direction and being disposed on a side of the fourth transistor away from the third transistor, the first direction and the second direction intersecting; in at least one sub-pixel, the pixel driving circuit further including a first shielding electrode and a second shielding electrode, the first shielding electrode and the second shielding electrode being respectively disposed on two sides of the fourth transistor in the first direction and being respectively connected with the second power supply line, the first shielding electrode, the second shielding electrode, and the second power supply line forming a first shielding structure surrounding the fourth transistor on three sides.

[0441] The exemplary embodiments of the present disclosure also provide a display device including the aforementioned display substrate. The display device of the present disclosure can be used in virtual reality devices, augmented display devices, extended reality devices, mixed reality devices, sights, range finders, and the like, and can also be used in products or components having display functions, including but not limited to mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigation devices, or any product or component having display functions.

[0442] While the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in order to elucidate the embodiments of the present disclosure and it should be understood that the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure.

Claims

1. A display substrate comprising a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit comprising at least a first transistor, a second transistor, a third transistor, and a fourth transistor, a first electrode of the first transistor coupled to a data signal line, a second electrode of the first transistor coupled to a gate electrode of the third transistor, a first electrode of the second transistor coupled to a first power supply line, a second electrode of the second transistor coupled to a first electrode of the third transistor, a first electrode of the fourth transistor coupled to a second power supply line, a second electrode of the fourth transistor coupled to a second electrode of the third transistor, the first power supply line configured to provide a first power supply signal to the pixel driving circuit, the second power supply line configured to provide a second power supply signal to the pixel driving circuit. The second power line is in a linear or zigzag shape extending along a first direction and is arranged on a side of the fourth transistor away from the third transistor, and the data signal line is in a linear or zigzag shape extending along a second direction, the first direction and the second direction intersecting each other. In at least one of the sub-pixels, the pixel driving circuit further comprises a first shielding electrode and a second shielding electrode, the first shielding electrode and the second shielding electrode are arranged on two sides of the fourth transistor in the first direction respectively, and are connected with the second power line respectively, the first shielding electrode, the second shielding electrode and the second power line form a first shielding structure surrounding the fourth transistor on three sides; the first shielding electrode has a first electrode length, the second shielding electrode has a second electrode length, and the ratio of the first electrode length to the second electrode length is 0.95 to 1.05, the first electrode length and the second electrode length are the dimensions in the second direction. 2.The display substrate of claim 1, wherein, The fourth transistor comprises at least a fourth gate electrode; the first shielding electrode is arranged between two adjacent fourth gate electrodes in the first direction; a first end of the first shielding electrode is connected with the second power line, and a second end of the first shielding electrode is connected with a first electrode of the fourth transistor after extending along the second direction or the opposite direction of the second direction. 3.The display substrate of claim 1, wherein, The second electrode of the third transistor is connected with the second electrode of the fourth transistor through a third node electrode; the second shielding electrode is arranged between two adjacent third node electrodes in the first direction; a first end of the second shielding electrode is connected with the second power line, and a second end of the second shielding electrode extends along the second direction or the opposite direction of the second direction. 4.The display substrate of claim 3, wherein, The third node electrode comprises at least a first sub-electrode, a second sub-electrode and a third sub-electrode, the first sub-electrode and the third sub-electrode are in a strip shape extending along the first direction, and the second sub-electrode is in a strip shape extending along the second direction, two ends of the second sub-electrode are connected with the first sub-electrode and the third sub-electrode respectively, forming a "C" shape; the first sub-electrode is connected with the second electrode of the third transistor, the third sub-electrode is connected with the second electrode of the fourth transistor, and the orthographic projection of the third sub-electrode on the display substrate plane at least partially overlaps with the fourth gate electrode of the fourth transistor. 5.The display substrate of claim 4, wherein, The third node electrode further comprises a fourth sub-electrode, which is in the shape of a strip extending along the first direction, is arranged on the side of the second sub-electrode away from the third sub-electrode, and is connected with the second sub-electrode; the third sub-electrode has a first extension length, and the fourth sub-electrode has a second extension length, the first extension length is greater than the second extension length, the first extension length is the distance between the end of the third sub-electrode away from the second sub-electrode and the second sub-electrode, and the second extension length is the distance between the end of the fourth sub-electrode away from the second sub-electrode and the second sub-electrode. 6.The display substrate of claim 1, wherein, The first power supply line is in the shape of a straight line or a broken line extending along the first direction, and is arranged on the side of the third transistor away from the fourth transistor; in at least one sub-pixel, the pixel driving circuit further comprises a third shielding electrode and a fourth shielding electrode, the third shielding electrode and the fourth shielding electrode are arranged on the two sides of the third transistor in the first direction respectively, and are connected with the first power supply line respectively, the third shielding electrode, the fourth shielding electrode and the first power supply line form a second shielding structure surrounding the third transistor on four sides. 7.The display substrate of claim 6, wherein, The third shielding electrode comprises at least a first vertical electrode and a first horizontal electrode, a first end of the first vertical electrode is connected with the first power supply line, a second end of the first vertical electrode extends towards the fourth transistor, and then is connected with a first end of the first horizontal electrode, a second end of the first horizontal electrode extends towards the fourth shielding electrode; The fourth shielding electrode comprises at least a second vertical electrode and a second horizontal electrode, a first end of the second vertical electrode is connected with the first power supply line, a second end of the second vertical electrode extends towards the fourth transistor, and then is connected with a first end of the second horizontal electrode, a second end of the second horizontal electrode extends towards the third shielding electrode. 8.The display substrate of claim 7, wherein, The first vertical electrode is arranged between the gate electrodes of two adjacent third transistors in the first direction, and the first horizontal electrode is arranged between the third transistor and the fourth transistor. 9.The display substrate of claim 7, wherein, The second electrode of the first transistor is connected with the gate electrode of the third transistor through a first node electrode; the second vertical electrode is arranged between two adjacent first node electrodes in the first direction, and the second horizontal electrode is arranged between the third transistor and the fourth transistor. 10.The display substrate of claim 7, wherein, In at least one pixel row, part of the adjacent sub-pixels share the same first vertical electrode, one first vertical electrode and two first horizontal electrodes in two sub-pixels form an integral structure connected with each other, and form a "T" shape. 11.The display substrate of claim 7, wherein, In at least one pixel row, part of the adjacent sub-pixels share the same second vertical electrode, one second vertical electrode and two second horizontal electrodes in two sub-pixels form an integral structure connected with each other, and form a "T" shape. 12.The display substrate of claim 7, wherein, The third transistor comprises at least a third active region, and the fourth transistor comprises at least a fourth active region; the first lateral electrode or the second lateral electrode has a first distance from the third active region, and has a second distance from the fourth active region, the first distance being smaller than the second distance; the first distance is a distance between an edge of the first lateral electrode or the second lateral electrode close to the third active region and an edge of the third active region close to the first lateral electrode or the second lateral electrode, and the second distance is a distance between an edge of the first lateral electrode or the second lateral electrode close to the fourth active region and an edge of the fourth active region close to the first lateral electrode or the second lateral electrode. 13.The display substrate of claim 7, wherein, In at least one of the sub-pixels, the first lateral electrode has a first shielding length, the second lateral electrode has a second shielding length, and the first vertical electrode and the second vertical electrode have a third shielding length, and a ratio of a sum of the first shielding length and the second shielding length to the third shielding length is greater than or equal to 0.6; wherein the first shielding length is a distance between an end of the first lateral electrode away from the first vertical electrode and the first vertical electrode, the second shielding length is a distance between an end of the second lateral electrode away from the second vertical electrode and the second vertical electrode, and the third shielding length is a distance between an edge of the first vertical electrode close to the second vertical electrode and an edge of the second vertical electrode close to the first vertical electrode. 14.The display substrate of claim 1, wherein, The pixel driving circuit further comprises a first node electrode and a first capacitor, and a second electrode of the first transistor is connected to a gate electrode of the third transistor through the first node electrode; the first capacitor comprises at least a first plate and a second plate, the gate electrode of the third transistor serving as the first plate, and a normal projection of the second plate on a display substrate plane at least partially overlaps a normal projection of the first plate on the display substrate plane, a second plate connecting block is arranged on the second plate, the second plate connecting block is arranged on a side of the second plate close to the first node electrode and connected to the second plate, the second plate connecting block is in a block shape, the first node electrode is in a "C" shape, and the second plate connecting block and the first node electrode form an interdigital structure. 15.The display substrate of claim 14, wherein, The first node electrode comprises at least a fifth sub-electrode, a sixth sub-electrode and a seventh sub-electrode, the fifth sub-electrode and the seventh sub-electrode are in a strip shape extending along the first direction, and the sixth sub-electrode is in a strip shape extending along the second direction, and two ends of the sixth sub-electrode are connected to the fifth sub-electrode and the seventh sub-electrode respectively. The seventh sub-electrode and the second plate have a first electrode interval, the second plate connecting block and the sixth sub-electrode have a second electrode interval, the first electrode interval and the second electrode interval are dimensions in the first direction; the second electrode interval is greater than the first electrode interval. 16.The display substrate of claim 14, wherein, The third transistor at least includes a third active region; the seventh sub-electrode includes a first region and a second region, a normal projection of the first region on a display substrate plane at least partially overlaps a normal projection of the third active region on the display substrate plane, a normal projection of the second region on the display substrate plane does not overlap the normal projection of the third active region on the display substrate plane; the first region has a fourth extension length, the second region has a fifth extension length, the fourth extension length and the fifth extension length are dimensions in the first direction; the fifth extension length is less than the fourth extension length, and the fifth extension length is greater than 0.5 times the fourth extension length.

17. The display substrate according to any one of claims 1 to 16, wherein, In at least one unit row, pixel driving circuits in adjacent sub-pixels are symmetrically arranged relative to a first center line, and in at least one unit column, pixel driving circuits in adjacent sub-pixels are symmetrically arranged relative to a second center line, the first center line is a straight line located between adjacent pixel rows and extending along the first direction, and the second center line is a straight line located between adjacent pixel columns and extending along the second direction. 18.The display substrate of claim 17, wherein, The first transistor at least includes a first gate electrode, and the second transistor at least includes a second gate electrode; in at least one unit row, the first gate electrodes of some adjacent sub-pixels are an integral structure connected to each other, and the second gate electrodes of some adjacent sub-pixels are an integral structure connected to each other.

19. A display device, wherein, The display substrate includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns; the preparation method includes:

20. A method for manufacturing a display substrate, wherein, The display substrate includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns; the preparation method includes: A pixel driving circuit is formed in at least one sub-pixel, the pixel driving circuit at least includes a first transistor, a second transistor, a third transistor and a fourth transistor, a first electrode of the first transistor is coupled with a data signal line, a second electrode of the first transistor is coupled with a gate electrode of the third transistor, a first electrode of the second transistor is coupled with a first power supply line, a second electrode of the second transistor is coupled with a first electrode of the third transistor, a first electrode of the fourth transistor is coupled with a second power supply line, a second electrode of the fourth transistor is coupled with a second electrode of the third transistor, the first power supply line is configured to provide a first power supply signal to the pixel driving circuit, the second power supply line is configured to provide a second power supply signal to the pixel driving circuit; a shape of the second power supply line is linear or zigzag along a first direction, and the second power supply line is arranged on a side of the fourth transistor away from the third transistor, a shape of the data signal line is linear or zigzag along a second direction, the first direction and the second direction intersect; in at least one sub-pixel, the pixel driving circuit further includes a first shielding electrode and a second shielding electrode, the first shielding electrode and the second shielding electrode are arranged on two sides of the fourth transistor in the first direction respectively, and are connected with the second power supply line respectively, the first shielding electrode, the second shielding electrode and the second power supply line form a first shielding structure which surrounds the fourth transistor on three sides; the first shielding electrode has a first electrode length, the second shielding electrode has a second electrode length, a ratio of the first electrode length to the second electrode length is 0.95 to 1.05, and the first electrode length and the second electrode length are dimensions in the second direction.

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