Substrate processing method for improving imaging quality of infrared focal plane hybrid integrated chip

Abstract

The present invention belongs to the technical field of substrate processing. Disclosed is a substrate processing method for improving the imaging quality of an infrared focal plane hybrid integrated chip. The infrared focal plane hybrid integrated chip is fabricated from an array die and a silicon readout integrated circuit by means of flip-chip bonding using indium bumps; and an epitaxial layer, a substrate / epitaxial layer interface and a substrate are sequentially arranged above the indium bumps along a first direction. The method comprises the following steps: step S1, thinning a substrate, and performing an adhesive and wax removal treatment; step S2, forming a protective layer on an electrode of a silicon readout integrated circuit; step S3, adhering a treated die and a dummy wafer to a glass substrate, and removing the thinned substrate by means of a chemico-mechanical polishing treatment; and step S4, removing, by means of a chemical polishing treatment, the portion of the epitaxial layer that is close to the substrate / epitaxial layer interface and has a set thickness, and performing cleaning. The technical solution has the following beneficial effects: a tellurium-zinc-cadmium substrate is removed by means of chemico-mechanical polishing, thereby reducing the loss rate and overcoming the problem of uneven corrosion; and an epitaxial material close to the substrate / epitaxial layer interface is removed by means of chemical polishing, thereby improving the imaging quality.

Description

Substrate processing method for improving imaging quality of infrared focal plane hybrid chip TECHNICAL FIELD

[0001] The present application relates to the technical field of substrate processing, and particularly relates to a substrate processing method for improving imaging quality of an infrared focal plane hybrid chip. BACKGROUND

[0002] Referring to FIG. 1 and FIG. 2, an infrared focal plane detector hybrid chip is prepared by flip-chip interconnection of an infrared focal plane array chip and a silicon readout circuit 7 through an indium column 6. In order to improve the reliability of the indium column 6, a filling glue 4 is usually filled between the electrode 5 of the chip and the silicon readout circuit 7, and is subjected to temperature curing. The infrared focal plane array chip is prepared by tellurium-zinc-cadmium substrate epitaxy technology, and the substrate 1 has a thickness of hundreds of microns. After the sample chip is thinned through a substrate back surface thinning process, a certain thickness of the tellurium-zinc-cadmium substrate 1 is reserved, and then the substrate is subjected to etching using a substrate selective etching liquid and cleaning, so as to achieve the purpose of completely removing the substrate 1.

[0003] In the prior art, referring to FIG. 5 and FIG. 6, the substrate selective etching process may cause uneven etching. When the detector assembly is imaged, the etching lines are easily shown in the level diagram, which affects the imaging quality. If the etching is too severe, the detector assembly may be invalid. The HgCdTe (mercury cadmium telluride) wafer of the infrared focal plane manufacturing technology has inherent growth defects on the surface. The HgCdTe surface has wave-like ripples due to convection. The substrate etching cannot remove the ripple morphology at the interface. The components mutually diffuse between the substrate 1 and the epitaxial layer 2, and the epitaxial material near the substrate epitaxial interface 3 has a high impurity concentration and mismatch dislocation. SUMMARY

[0004] The present application aims to provide a substrate processing method for improving imaging quality of an infrared focal plane hybrid chip, and solve the above technical problems.

[0005] The present application aims to provide a substrate processing method for improving imaging quality of an infrared focal plane hybrid chip, and solve the above technical problems.

[0006] The infrared focal plane hybrid chip is prepared by flip-chip interconnection of an array chip and a silicon readout circuit through an indium column. An epitaxial layer, a substrate epitaxial interface and a substrate are sequentially arranged above the indium column along a first direction, and the method comprises the following steps.

[0007] S1, thinning the substrate and performing a degumming and dewaxing treatment to obtain a thinned substrate;

[0008] S2, forming a protective layer on the electrode of the silicon readout circuit to obtain a treated chip;

[0009] Step S3, the processed chip and a partner chip are adhered to the glass substrate, and the thinned substrate is removed by chemical mechanical polishing treatment;

[0010] Step S4, the epitaxial layer with a set thickness near the epitaxial interface of the substrate is removed by chemical polishing treatment and cleaning.

[0011] Preferably, the thinned substrate in step S1 is a cadmium zinc telluride substrate, and the thickness of the thinned substrate is 10-15 μm.

[0012] Preferably, step S2 comprises coating photoresist on the electrode and baking for 15 min to form the protective layer.

[0013] Preferably, the processed chip and the partner chip are adhered to the glass substrate by paraffin in step S3, the partner chip has the same thickness as the processed chip, and the partner chip is made of cadmium zinc telluride material.

[0014] Preferably, the chemical mechanical polishing treatment in step S3 comprises,

[0015] The first polishing is performed by using alumina with a first particle size and sodium hypochlorite solution in a first time period, and the second polishing is performed by using silica sol with a second particle size and hydrogen peroxide solution in a second time period.

[0016] Preferably, the first time period is 3 min, the first particle size is 0.3 μm, the second time period is 30 min, and the second particle size is 50 nm.

[0017] Preferably, the chemical polishing treatment in step S4 is to remove the epitaxial layer by using bromine-based alcohol solution with a first concentration.

[0018] Preferably, the first concentration is 0.1%-0.5%, and the epitaxial layer is made of mercury cadmium telluride material.

[0019] Preferably, the set thickness in step S4 is 2-3 μm.

[0020] Preferably, the surface roughness of the array chip is less than 1 nm.

[0021] The present application has the following beneficial effects: the cadmium zinc telluride substrate is removed by chemical mechanical polishing instead of substrate etching process, the loss rate is reduced, the problem of uneven etching is solved, the epitaxial material near the epitaxial interface of the substrate is removed by chemical polishing, and the imaging quality is improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] Fig. 1 is a flow of substrate removal in the prior art;

[0023] Fig. 2 is a structure diagram of a hybrid chip of an infrared focal plane detector in the prior art;

[0024] Fig. 3 is a step diagram of the substrate processing method of the present application for improving the imaging quality of an infrared focal plane hybrid chip;

[0025] Fig. 4 is a substrate processing flow chart of an embodiment of the present application;

[0026] Fig. 5 is a microscope photograph of a chip surface processed using the prior art;

[0027] Fig. 6 is a micrograph of a chip surface processed using the prior art;

[0028] Fig. 7 is a microscope photograph of a chip surface processed using the present application;

[0029] Fig. 8 is a micrograph of a chip surface processed using the present application.

[0030] In the drawings: 1, substrate; 2, epitaxial layer; 3, substrate epitaxial interface; 4, filling glue; 5, electrode; 6, indium column; 7, silicon readout circuit. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0032] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0033] The present application will be further described below with reference to the drawings and specific embodiments, but is not limited by the embodiments.

[0034] A substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip, as shown in Figs. 1 and 3, comprises,

[0035] The infrared focal plane hybrid chip is prepared by flip-chip interconnection of an array chip and a silicon readout circuit 7, and the epitaxial layer 2, the substrate epitaxial interface 3 and the substrate 1 are sequentially arranged above the indium column 6 along a first direction (arrow A), comprising the following steps,

[0036] Step S1, thinning the substrate 1 and performing a de-gluing and de-waxing treatment to obtain a thinned substrate;

[0037] Step S2, forming a protective layer on the electrode 5 of the silicon readout circuit 7 to obtain a processed chip;

[0038] Step S3, the processed chip and the accompanying chip are adhered to the glass substrate, and the thinned substrate is removed by chemical mechanical polishing treatment;

[0039] Step S4, the epitaxial layer 2 with a set thickness near the epitaxial interface 3 of the substrate is removed by chemical polishing treatment and cleaned.

[0040] Specifically, the present application provides a substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip. The tellurium-zinc-cadmium substrate is removed by chemical mechanical polishing instead of a substrate etching process, reducing the loss rate and solving the problem of uneven etching caused by the traditional substrate etching process. The epitaxial material near the epitaxial interface of the substrate is removed by chemical polishing, improving the imaging quality.

[0041] The purpose of thinning the substrate 1 is to reduce its thickness to improve the sensitivity and imaging quality of the infrared sensor. After the thickness of the substrate 1 is thinned to a certain extent, it can better transmit infrared light and reduce the attenuation of the infrared signal. The degreasing and wax removal process removes the residues on the surface of the substrate 1, which plays a cleaning role.

[0042] Forming a protective layer on the electrode 5 of the silicon readout circuit 7 can prevent damage to the electrode 5 during subsequent processing, protect the electrode 5 from chemical treatment or mechanical operation, and help improve the stability and reliability of the final chip.

[0043] Chemical mechanical polishing is used to remove the substrate 1, replacing the substrate etching process, reducing the loss rate of the chip substrate etching removal process, and solving the problem of uneven etching. The epitaxial layer 2 with a set thickness is removed by chemical polishing to improve the imaging quality, obtain a flat and low roughness surface, reduce the surface reflectivity, and improve the backside transmittance of the back-illuminated infrared detector.

[0044] In a more preferred embodiment, the thinned substrate in step S1 is a tellurium-zinc-cadmium substrate, and the thickness of the thinned substrate is 10-15 μm.

[0045] Specifically, the tellurium-zinc-cadmium substrate is thinned to a target thickness of 10-15 μm using a backside thinning process, ensuring that the performance of the detector is in the best state and improving the imaging clarity and overall efficiency of the detector.

[0046] Thinning the tellurium-zinc-cadmium substrate can reduce the absorption and scattering of infrared light by the substrate, improving the light transmittance of the infrared focal plane hybrid chip. The thinned substrate can effectively reduce the loss in the optical path and improve the overall efficiency of the optical system.

[0047] The thinner substrate 1 can better match the thermal management system of the readout circuit, reducing the impact of heat accumulation on the performance of the detector.

[0048] The thinned substrate 1 can reduce the signal propagation time in the substrate 1, improve the response speed of the detector and real-time imaging capability.

[0049] In subsequent processing steps such as chemical mechanical polishing and chemical polishing treatment, the amount of material removed is reduced, the processing difficulty is reduced, and a more flat and smooth surface is obtained.

[0050] In a preferred embodiment, step S2 includes applying a photoresist on the electrode 5 and baking for 15 minutes to form a protective layer.

[0051] Specifically, the photoresist layer protects the electrode 5 from chemical corrosion, physical wear and high temperature environment in subsequent processing steps. A good photoresist protective layer can reduce defects such as contamination, missing or irregular shape on the surface of the electrode 5 in subsequent deposition or etching process, improve the processing precision of the infrared focal plane hybrid chip, and thus improve the quality of the final imaging.

[0052] The protective layer helps to maintain the structure and shape of the electrode 5, avoiding damage to the electrode 5 when removing the substrate 1 and removing the epitaxial layer 2, thereby improving the precision and consistency of the processing process.

[0053] The protective layer can improve the adhesion of the electrode to other materials such as glass substrate, ensuring the reliability and stability of the final chip.

[0054] After forming the protective layer, the process of removing the substrate 1 and the epitaxial layer 2 can be simplified, as the electrode area is effectively isolated, reducing unnecessary interference and damage.

[0055] In a preferred embodiment, in step S3, the processed chip and the dummy chip are bonded to the glass substrate by paraffin wax, the dummy chip has the same thickness as the processed chip, and the dummy chip is made of tellurium-zinc-cadmium material.

[0056] Specifically, paraffin wax is used as a temporary adhesive to fix the position of the dummy chip and the chip on the substrate.

[0057] The dummy chip provides necessary mechanical support during chip processing to prevent deformation or damage of the chip during subsequent processing steps. The same thickness ensures the consistency of mechanical support, thereby avoiding stress concentration problems caused by thickness differences.

[0058] The dummy chip is made of a substrate material with the same thermal expansion coefficient as the chip material to reduce stress and deformation caused by temperature changes, thereby improving imaging quality.

[0059] In a preferred embodiment, the chemical mechanical polishing treatment in step S3 includes,

[0060] The first polishing is performed using alumina of a first particle size and sodium hypochlorite solution for a first time period, and the second polishing is performed using silica sol of a second particle size and hydrogen peroxide solution for a second time period;

[0061] The first time period is 3 min, the first particle size is 0.3 μm, the second time period is 30 min, and the second particle size is 50 nm.

[0062] Specifically, the first step of rough polishing is performed using alumina of a particle size of 0.3 μm and sodium hypochlorite solution, and the polishing time is 3 min. Then, the second step of fine polishing is performed using silica sol of a particle size of 50 nm and hydrogen peroxide solution, and the polishing time is 30 min, until the mirror surface is smooth and scratch-free.

[0063] The alumina particles of a particle size of 0.3 μm are relatively large, which can effectively remove large surface defects and irregular surface roughness, so as to reduce the macro-unevenness and obvious scratches on the material surface.

[0064] The silica sol of a particle size of 50 nm is very fine, which can effectively remove the small surface defects and fine scratches left in the rough polishing stage. The fine particle size polishing material can achieve higher smoothness, so that the surface reaches the mirror level. The surface quality is gradually improved from macro to micro. The rough polishing removes large-scale irregularities, and the fine polishing ensures the removal of small defects, so that the mirror effect of high smoothness is finally achieved.

[0065] In a preferred embodiment, the chemical polishing treatment in step S4 is to remove the epitaxial layer 2 by using a bromine-based alcohol solution of a first concentration;

[0066] The first concentration is 0.1% to 0.5%, and the epitaxial layer 2 is made of tellurium-cadmium-mercury material;

[0067] The thickness set in step S4 is 2 μm to 3 μm.

[0068] Specifically, by precisely controlling the concentration of bromine-based alcohol, the removal rate and effect can be finely adjusted, the thickness of the removed epitaxial layer 2 is controlled, and the performance and morphology of the substrate are preserved. The selective corrosion characteristics of bromine-based alcohol make it suitable for processing tellurium-zinc-cadmium material without affecting other materials.

[0069] The chemical polishing can effectively remove surface defects and unevenness, ensure the smoothness of the epitaxial layer 2, and thus improve the imaging quality of the infrared focal plane hybrid chip. The improvement of the surface smoothness helps to reduce image distortion and enhance the accuracy of imaging.

[0070] Through precise chemical polishing control, 2 μm to 3 μm of unnecessary epitaxial material can be uniformly removed, and the consistency of the required thickness is ensured.

[0071] The selective solubility of the bromoalcohol facilitates removal of the epitaxial layer 2 without damaging the substrate, thus preserving the original characteristics and properties of the substrate. This selective removal facilitates maintaining the overall performance of the final device.

[0072] In a preferred embodiment, the surface roughness of the array chip is less than 1 nm.

[0073] Specifically, the surface roughness directly affects the optical uniformity of the chip. Higher surface roughness can cause scattering and interference of light, thus affecting the imaging clarity and sensitivity of the infrared detector. In an infrared focal plane hybrid chip, the surface roughness affects the quality of electrical contact. Surface unevenness can cause poor contact, affecting signal transmission and electrical performance of the detector.

[0074] A surface roughness of less than 1 nm helps to reduce light scattering and interference, thus improving imaging quality. A smoother surface can ensure that light passes through the chip in a more consistent manner, improving detection accuracy and image clarity.

[0075] A smooth surface can improve the response speed of the detector and the stability of the signal, as a small surface roughness can reduce signal noise and improve signal quality.

[0076] Chemical mechanical polishing technology is used to process the surface of the substrate to obtain the desired ultra-low surface roughness. Surface irregularities are removed through a combination of chemical and mechanical action to achieve an extremely smooth surface. Chemical reactions help dissolve and remove surface materials, while mechanical polishing physically grinds the surface.

[0077] Through chemical mechanical polishing and chemical polishing, a flat, low-roughness surface of less than 1 nm is obtained, reducing surface reflectivity and improving the backside transmittance of the back-illuminated infrared detector.

[0078] Referring to FIG. 4, the array chip is used as a sample chip for substrate processing, and the specific steps are as follows:

[0079] First, the back of the substrate is thinned to reserve a thickness of 10-15 μm of the CdZnTe substrate;

[0080] Then, glue is applied to the electrodes 5 around the array chip for protection;

[0081] Second, the CdZnTe substrate is completely removed by CMP (chemical mechanical polishing);

[0082] Then, the epitaxial layer 2 of 2-3 μm thickness is removed by CP (chemical polishing);

[0083] Finally, it is cleaned thoroughly.

[0084] Specifically, the glue coating of the array chip peripheral electrode 5 can prevent the electrode 5 from being damaged in the subsequent polishing process. Protecting the electrode 5 is the key to ensuring the reliability of electrical connection, preventing the electrode 5 from being damaged and affecting the working performance of the final chip.

[0085] CMP can uniformly remove the substrate material, reduce surface roughness, and eliminate surface defects that may affect the imaging quality. Through precise chemical mechanical polishing, the substrate surface is smooth, which helps to improve the clarity of the infrared image.

[0086] When removing 2-3 μm of the epitaxial layer, chemical polishing can remove surface unevenness and stress release layer, thereby improving the flatness and consistency of the chip. This flatness directly affects the imaging performance of the focal plane array, reducing image distortion and aberration.

[0087] The final cleaning process removes chemical residues and small particles generated during processing, ensuring that the chip surface is free of contamination.

[0088] Further specifically, during processing, the electrode 5 is coated with glue to effectively protect the array chip from damage when removing the substrate 1.

[0089] By removing the substrate 1 by CMP and the epitaxial layer 2 by CP, the flatness and quality of the chip surface can be improved, and the loss rate of the chip substrate etching and removal process can be reduced.

[0090] By precisely controlling the concentration of bromine-based alcohol, the removal rate and effect can be finely adjusted, and the thickness of the epitaxial layer 2 can be controlled. The selective etching properties of bromine-based alcohol make it suitable for processing cadmium zinc telluride materials without affecting other materials. Removing excess substrate 1 and epitaxial layer 2 helps to optimize the optoelectronic performance of the chip, especially in optoelectronic devices.

[0091] Reducing material thickness and unnecessary layers helps to improve the stability and long-term reliability of the chip, improve the imaging quality, and improve the back surface transmittance of the back-illuminated infrared detector.

[0092] Avoiding the uneven etching phenomenon that occurs in the substrate selective etching process does not affect the imaging quality, removes the epitaxial material near the substrate epitaxial interface 3, and avoids high impurity concentration and mismatch dislocations.

[0093] Figure 6a shows the etching residual hole defects under high magnification, Figure 6b shows the macroscopic ripple steps of the mercury tellurium cadmium epitaxial layer under high magnification, and Figures 6c and 6d correspond to Figures 6a and 6b, respectively: Hole defects and ripple step topography patterns taken by a white light profiler.

[0094] Figure 7 is a mirror inspection graph of the chip surface processed by the application, and Figures 8a', 8b' show the mirror-finished chip surface under high magnification, and Figures 8c', 8d' show the roughness below 1nm under white light profilometer.

[0095] In summary, the application provides a substrate processing method for improving the imaging quality of infrared focal plane hybrid chips. The chemical mechanical polishing process is used to replace the substrate etching process to remove tellurium zinc cadmium, thereby reducing the loss rate of the chip substrate etching removal process and solving the problem of uneven etching. The chemical polishing is used to remove 2-3μm of the epitaxial layer close to the interface, thereby improving the imaging quality and improving the back surface transmittance of the back-illuminated infrared detector.

[0096] The above description is merely preferred embodiments of the application, and is not intended to limit the embodiments and protection scope of the application. It should be noted that, for those skilled in the art, any equivalent replacements and obvious changes made according to the content of the specification and drawings should be included in the protection scope of the application.

Claims

1. A substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip, characterized by, The infrared focal plane hybrid chip is prepared by flip interconnection of array chip and silicon readout circuit (7) through indium column (6), and epitaxial layer (2), substrate epitaxial interface (3) and substrate (1) are sequentially arranged above the indium column (6) along the first direction, comprising the following steps, Step S1, thinning the substrate (1) and carrying out degumming and dewaxing treatment to obtain a thinned substrate; Step S2, forming a protective layer on the electrode (5) of the silicon readout circuit (7) to obtain a treated chip; Step S3, bonding the treated chip and a partner chip on a glass substrate, and removing the thinned substrate by chemical mechanical polishing treatment; Step S4, removing the epitaxial layer (2) with a set thickness close to the substrate epitaxial interface (3) by chemical polishing treatment and cleaning.

2. The substrate processing method for improving the imaging quality of an infrared hybrid focal plane chip according to claim 1, wherein The thinned substrate in step S1 is a cadmium zinc telluride substrate, and the thickness of the thinned substrate is 10-15 μm.

3. The substrate processing method for improving the imaging quality of an infrared hybrid focal plane array chip according to claim 1, wherein Step S2 includes coating photoresist on the electrode (5) and baking for 15 min to form the protective layer.

4. The substrate processing method for improving the imaging quality of an infrared hybrid focal plane array chip according to claim 1, wherein In step S3, the treated chip and the partner chip are bonded on the glass substrate by paraffin wax, the partner chip has the same thickness as the treated chip, and the partner chip is made of cadmium zinc telluride material.

5. The substrate processing method for improving the imaging quality of an infrared hybrid focal plane array chip according to claim 1, wherein The chemical mechanical polishing treatment in step S3 includes, First polishing is performed using aluminum oxide with a first particle size and sodium hypochlorite solution for a first time period, and then second polishing is performed using silica sol with a second particle size and hydrogen peroxide solution for a second time period.

6. The substrate processing method for improving the imaging quality of an infrared hybrid focal plane array chip according to claim 5, wherein The first time period is 3 min, the first particle size is 0.3 μm, the second time period is 30 min, and the second particle size is 50 nm.

7. The substrate processing method for improving the imaging quality of an infrared hybrid focal plane array chip according to claim 1, wherein The chemical polishing treatment in step S4 is to remove the epitaxial layer (2) using a bromine-based alcohol solution with a first concentration.

8. The substrate processing method for improving the imaging quality of an infrared hybrid focal plane array chip according to claim 7, wherein The first concentration is 0.1%-0.5%, and the epitaxial layer (2) is made of mercury cadmium telluride material.

9. The substrate processing method for improving the imaging quality of an infrared hybrid focal plane array chip according to claim 1, wherein The set thickness in step S4 is 2-3 μm.

10. The substrate processing method for improving the imaging quality of an infrared hybrid focal plane array chip according to claim 1, wherein The surface roughness of the array chip is less than 1 nm.

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