Switched capacitor circuit and electronic device

Abstract

Embodiments of the present application relate to the technical field of electronics, and provide a switched capacitor circuit and an electronic device, used for reducing the turn-on loss of switched capacitor circuits. The switched capacitor circuit comprises two-phase SFIPS circuits, and a plurality of auxiliary circuits are added between the two-phase SFIPS circuits. Within the dead time of the switched capacitor circuit, a voltage of a key node in one-phase SFIPS circuit can be transferred or clamped to a key node in the other-phase SFIPS circuit by means of the auxiliary circuits, so as to reduce voltage differences between two ends of transistors in the two-phase SFIPS circuits, thereby reducing a surge current of the transistors at a turn-on moment, and reducing the turn-on loss of the switched capacitor circuit.

Description

Switched capacitor circuit and electronic device

[0001] The present application claims priority to the Chinese Patent Application No. 202411292756.8, filed on September 13, 2024, and entitled “Switched capacitor circuit and electronic device”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of electronic technology, and in particular to a switched capacitor circuit and an electronic device. BACKGROUND

[0003] Electronic devices such as mobile phones, watches, tablets, etc. achieve wired or wireless fast charging by outputting a high voltage of 2 times (or 4 times) the battery voltage through a power adapter or a wireless charging circuit, and then reducing the high voltage to 1 / 2 (or 1 / 4) voltage through a switched capacitor circuit (SC) in the electronic device to charge the battery. In this way, under the same power, using high voltage to transmit power can reduce the transmission current and reduce line loss. In addition, the switched capacitor circuit SC has the characteristics of open-loop high efficiency, and combined with the charging protocol control, the adapter or the wireless charging circuit can adjust the voltage or the current, so that the entire electronic device charging system is efficient and reduces heat consumption, thereby realizing super-fast charging.

[0004] Currently, the turn-on loss of the switched capacitor circuit itself is an important reason for limiting the efficiency of the switched capacitor circuit. SUMMARY

[0005] The present application provides a switched capacitor circuit and an electronic device comprising the same, for reducing the turn-on loss of the switched capacitor circuit.

[0006] In a first aspect, the present application provides a switched-capacitor circuit, comprising at least one switched-capacitor group; the switched-capacitor group comprises a first auxiliary circuit, a second auxiliary circuit, and a first-phase switched-capacitor sub-circuit and a second-phase switched-capacitor sub-circuit which are coupled in parallel between an input terminal and an output terminal. The first-phase switched-capacitor sub-circuit and the second-phase switched-capacitor sub-circuit can be, for example, a single first interleaved second stage (SFIPS) circuit. The first-phase switched-capacitor sub-circuit and the second-phase switched-capacitor sub-circuit each comprise a first capacitor, a first-stage switch network, and a switched-capacitor network, wherein the switched-capacitor network comprises a second capacitor, a third capacitor, and a second-stage switch network; the first-stage switch network is coupled to the input terminal and the first capacitor, and is configured to adjust the on-off state between the first capacitor and the input terminal; the second-stage switch network is coupled to the first capacitor, the second capacitor, and the third capacitor, and is configured to adjust the series-parallel relationship among the first capacitor, the second capacitor, and the third capacitor. The first auxiliary circuit is coupled between a first node and a second node, and is configured to convert the voltage of the first node and the voltage of the second node during a period when the first-phase switched-capacitor sub-circuit and the second-phase switched-capacitor sub-circuit are both off; the first node is coupled to the negative electrode of the first capacitor of the first-phase switched-capacitor sub-circuit, and the second node is coupled to the negative electrode of the first capacitor of the second-phase switched-capacitor sub-circuit. The second auxiliary circuit is coupled between a third node and a fourth node, and is configured to convert the voltage of the third node and the voltage of the fourth node during a period when the first-phase switched-capacitor sub-circuit and the second-phase switched-capacitor sub-circuit are both off; the third node is coupled to the negative electrode of the second capacitor of the first-phase switched-capacitor sub-circuit and the negative electrode of the third capacitor of the second-phase switched-capacitor sub-circuit, and the fourth node is coupled to the negative electrode of the third capacitor of the first-phase switched-capacitor sub-circuit and the negative electrode of the second capacitor of the second-phase switched-capacitor sub-circuit.

[0007] The switch capacitor circuit provided by the embodiments of the present application has the first-phase switch capacitor sub-circuit and the second-phase switch capacitor sub-circuit connected in parallel in an opposite phase, so that when the switch capacitor circuit works in the first state, the voltage of the first node is 2 times of the output voltage 2Vvo, and the voltage of the second node is 0. When the switch capacitor circuit works in the second state, the voltage of the first node is 0, and the voltage of the second node is 2 times of the output voltage 2Vvo. By arranging the first auxiliary circuit in the switch capacitor circuit, the voltage conversion of the first node and the second node can be realized to pull down 2Vvo and pull up 0. For example, when the voltage of the first node is 2Vvo and the voltage of the second node is 0, after the voltage conversion of the first node and the second node, the voltage of the first node becomes less than 2Vvo, and the voltage of the second node becomes greater than 0. By changing the voltages of the first node and the second node, the voltage difference of some transistors in the first-stage switch network and the second-stage switch network can be changed, so that the "shock" current of the some transistors in the instant of turning on can be reduced. Similarly, when the switch capacitor circuit works in the first state, the voltage of the third node is the output voltage Vvo, and the voltage of the fourth node is 0. When the switch capacitor circuit works in the second state, the voltage of the third node is 0, and the voltage of the fourth node is the output voltage Vvo. By arranging the second auxiliary circuit in the switch capacitor circuit, the voltage conversion of the third node and the fourth node can be realized to pull down Vvo and pull up 0. By changing the voltages of the third node and the fourth node, the voltage difference of some transistors in the second-stage switch network can be changed, so that the "shock" current of the some transistors in the instant of turning on can be reduced. With the cooperation of the first auxiliary circuit and the second auxiliary circuit, the "shock" current of some or all transistors in the instant of turning on of the switch capacitor circuit can be reduced, the turn-on loss of the switch capacitor circuit can be reduced, and the efficiency and frequency of the switch capacitor circuit can be improved. After the frequency of the switch capacitor circuit is improved, the requirement for the capacitance value of the capacitor in the switch capacitor circuit can be reduced, and the area occupied by the switch capacitor circuit can be reduced. Moreover, after the voltage conversion of the third node and the fourth node, the voltage change rate (dv / dt) of the third node and the fourth node can be reduced, and the electromagnetic interference can be effectively reduced. In addition, the third node is coupled with the first-phase switch capacitor sub-circuit and the second-phase switch capacitor sub-circuit respectively, and the fourth node is coupled with the first-phase switch capacitor sub-circuit and the second-phase switch capacitor sub-circuit respectively. That is, the first-phase switch capacitor sub-circuit and the second-phase switch capacitor sub-circuit share the second auxiliary circuit, and the structure of the switch capacitor circuit can be simplified.

[0008] In a possible implementation, the first auxiliary circuit includes a first inductor, a fourth capacitor, a second inductor, and a fifth capacitor; the first inductor, the fourth capacitor, the second inductor, and the fifth capacitor are coupled in series between the first node and the second node; and the second inductor is further coupled to the reference ground voltage terminal at one end of the fourth capacitor. The first auxiliary circuit includes only capacitors and inductors, and does not need to change the transistor topology of the switched-capacitor circuit, and is easy to implement.

[0009] In a possible implementation, the first auxiliary circuit includes a bidirectional switch circuit; and the bidirectional switch circuit is coupled between the first node and the second node. The second auxiliary circuit includes only the bidirectional switch circuit, and does not include capacitors and inductors, and is simple in process and easy to implement.

[0010] In a possible implementation, the first auxiliary circuit includes a first switch transistor, a second switch transistor, and a third inductor; the first switch transistor, the third inductor, and the second switch transistor are coupled in series between the first node and the second node. The first auxiliary circuit with this structure can realize zero-voltage turn-on of the transistor in the switched-capacitor circuit, greatly reduce the turn-on loss of the switched-capacitor circuit, and improve the efficiency and frequency of the switched-capacitor circuit.

[0011] In a possible implementation, the first auxiliary circuit further includes a third switch transistor and a fourth switch transistor; the third switch transistor is coupled between one end of the third inductor toward the first switch transistor and the reference ground voltage terminal; and the fourth switch transistor is coupled between one end of the third inductor toward the second switch transistor and the reference ground voltage terminal. The first auxiliary circuit with this structure can realize zero-voltage turn-on of the transistor in the switched-capacitor circuit, and can simplify the structure of the first auxiliary circuit.

[0012] In a possible implementation, the switched-capacitor circuit includes a plurality of switched-capacitor groups; and the plurality of switched-capacitor groups are coupled in parallel between the input terminal and the output terminal. By arranging a plurality of groups of first-phase switched-capacitor sub-circuits and second-phase switched-capacitor sub-circuits that are connected in opposite phases, the ripple of the charging voltage can be reduced, and the stability of the charging voltage can be improved.

[0013] In a possible implementation, the second-stage switch network includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; a first electrode of the first transistor is coupled with a negative electrode of a first capacitor, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of a second capacitor respectively; a second electrode of the second transistor is coupled with the output terminal and a first electrode of the third transistor respectively; a second electrode of the third transistor is coupled with a negative electrode of the second capacitor and a first electrode of the fourth transistor respectively; a second electrode of the fourth transistor is coupled with the reference ground voltage terminal; a first electrode of the fifth transistor is coupled with a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of a third capacitor respectively; a second electrode of the sixth transistor is coupled with the output terminal and a first electrode of the seventh transistor respectively; a second electrode of the seventh transistor is coupled with a negative electrode of the third capacitor and a first electrode of the eighth transistor respectively; and a second electrode of the eighth transistor is coupled with the reference ground voltage terminal.

[0014] In a possible implementation, the seventh transistor in the first-phase switch capacitor sub-circuit and the third transistor in the second-phase switch capacitor sub-circuit are the same transistor. And / or, the eighth transistor in the first-phase switch capacitor sub-circuit and the fourth transistor in the second-phase switch capacitor sub-circuit are the same transistor. In this topology, the number of transistors in the switch capacitor circuit can be reduced, and the area occupied by the switch capacitor circuit can be reduced.

[0015] In a possible implementation, the first-phase switch capacitor sub-circuit and the second-phase switch capacitor sub-circuit each include a multi-stage (N-stage) switch capacitor network coupled in series, and the switch capacitor circuit further includes a plurality of second auxiliary circuits; the plurality of second auxiliary circuits are coupled with the multi-stage switch capacitor network one by one. By arranging the multi-stage (N-stage) switch capacitor network in each phase switch capacitor sub-circuit, the ratio of the input voltage and the output voltage at the input terminal Vvi:Vvo can be 2 N+1 :1, so as to achieve a high conversion ratio and meet different use requirements. On this basis, the second auxiliary circuit is coupled with each stage of the switch capacitor network, so as to reduce the "impact" current of the transistor in each stage of the switch capacitor network at the moment of turning on, so as to reduce the turn-on loss of the transistor.

[0016] In a possible implementation, the second switch network in each stage of the switch capacitor network respectively includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; in each stage of the switch capacitor network, a first electrode of the fourth transistor is coupled with a second electrode of the third transistor, and a second electrode of the fourth transistor is coupled with a reference ground voltage terminal; a first electrode of the eighth transistor is coupled with a second electrode of the seventh transistor, and a second electrode of the eighth transistor is coupled with the reference ground voltage terminal; in the first stage of the switch capacitor network, a first electrode of the first transistor is coupled with a negative electrode of a first capacitor, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of a second capacitor respectively; a first electrode of the fifth transistor is coupled with a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of a third capacitor respectively; in the switch capacitor network except the first stage, a first electrode of the first transistor is coupled with a second electrode of the second transistor in the previous stage of the switch capacitor network, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of the second capacitor respectively; a first electrode of the fifth transistor is coupled with a second electrode of the sixth transistor in the previous stage of the switch capacitor network, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of the third capacitor respectively; in the last stage of the switch capacitor network, a second electrode of the second transistor, a first electrode of the third transistor, a second electrode of the sixth transistor and a first electrode of the seventh transistor are all coupled with an output terminal; in the switch capacitor network except the last stage, a second electrode of the second transistor is coupled with a first electrode of the seventh transistor, and a second electrode of the sixth transistor is coupled with a first electrode of the third transistor. This is a simple topology structure.

[0017] In a possible implementation, the seventh transistor in the last stage of the switch capacitor network in the first phase switch capacitor sub-circuit and the third transistor in the last stage of the switch capacitor network in the second phase switch capacitor sub-circuit are the same transistor. And / or, the eighth transistor in the last stage of the switch capacitor network in the first phase switch capacitor sub-circuit and the fourth transistor in the last stage of the switch capacitor network in the second phase switch capacitor sub-circuit are the same transistor. In this topology, the number of transistors in the switch capacitor circuit can be reduced, and the area occupied by the switch capacitor circuit can be reduced.

[0018] In a possible implementation, the first stage switch network includes a ninth transistor and a tenth transistor; a first electrode of the ninth transistor is coupled with an input terminal, and a second electrode of the ninth transistor is coupled with a positive electrode of a first capacitor and a first electrode of a fifth transistor respectively; a first electrode of the tenth transistor is coupled with a negative electrode of the first capacitor and a first electrode of the first transistor respectively, and a second electrode of the tenth transistor is coupled with a reference ground voltage terminal. This is a simple topology structure.

[0019] In a second aspect, the application provides a switched-capacitor circuit, comprising: a first phase switched-capacitor sub-circuit, a second phase switched-capacitor sub-circuit, a third phase switched-capacitor sub-circuit and a fourth phase switched-capacitor sub-circuit coupled in parallel between an input terminal and an output terminal; the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are 180° out of phase, the first phase switched-capacitor sub-circuit and the third phase switched-capacitor sub-circuit are 90° out of phase, and the third phase switched-capacitor sub-circuit and the fourth phase switched-capacitor sub-circuit are 180° out of phase; the first phase switched-capacitor sub-circuit, the second phase switched-capacitor sub-circuit, the third phase switched-capacitor sub-circuit and the fourth phase switched-capacitor sub-circuit each comprise a first capacitor, a first-stage switch network and a switched-capacitor network, the switched-capacitor network comprising a second capacitor, a third capacitor and a second-stage switch network; the first-stage switch network is coupled to the input terminal and the first capacitor, and is configured to adjust the connection between the first capacitor and the input terminal; the second-stage switch network is coupled to the first capacitor, the second capacitor and the third capacitor, and is configured to adjust the series-parallel connection among the first capacitor, the second capacitor and the third capacitor; a first bidirectional switch circuit is coupled between a fifth node and a sixth node, and is configured to clamp the voltage of the sixth node to the voltage of the fifth node when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off; the fifth node is coupled to the negative electrode of the second capacitor of the first phase switched-capacitor sub-circuit and the negative electrode of the third capacitor of the second phase switched-capacitor sub-circuit, and the sixth node is coupled to the negative electrode of the third capacitor of the third phase switched-capacitor sub-circuit and the negative electrode of the second capacitor of the fourth phase switched-capacitor sub-circuit.

[0020] The switched-capacitor circuit provided by the application sets the first bidirectional switch circuit between the fifth node and the sixth node, and when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off, the third phase switched-capacitor sub-circuit and the fourth phase switched-capacitor sub-circuit work normally. At this time, the voltage of the sixth node can be clamped to the voltage of the fifth node by the first bidirectional switch circuit, and the voltage difference between the two ends of some transistors in the second-stage switch network of the first phase switched-capacitor sub-circuit and the second-stage switch network of the second phase switched-capacitor sub-circuit can be reduced by changing the voltage of the fifth node, so as to reduce the “shock” current of the transistors at the moment of turning on and reduce the turn-on loss of the transistors. Moreover, the first bidirectional switch circuit has a simple structure and simple process, and is easy to implement.

[0021] In a possible implementation, the switch capacitor circuit further includes a second bidirectional switch circuit. The second bidirectional switch circuit is coupled between the seventh node and the eighth node, and is configured to clamp the voltage of the eighth node to the voltage of the seventh node during a period when both the first-phase switch capacitor sub-circuit and the second-phase switch capacitor sub-circuit are turned off. The seventh node is coupled to the negative electrode of the third capacitor of the first-phase switch capacitor sub-circuit and the negative electrode of the second capacitor of the second-phase switch capacitor sub-circuit respectively, and the eighth node is coupled to the negative electrode of the second capacitor of the third-phase switch capacitor sub-circuit and the negative electrode of the third capacitor of the fourth-phase switch capacitor sub-circuit respectively. By arranging the second bidirectional switch circuit in the switch capacitor circuit, the voltage difference between two ends of some transistors in the second-stage switch network of the first-phase switch capacitor sub-circuit and the second-stage switch network of the second-phase switch capacitor sub-circuit can be reduced, so as to reduce the “shock” current of the transistors at the moment of turning on and reduce the turn-on loss of the transistors.

[0022] In a possible implementation, the switch capacitor circuit further includes a third bidirectional switch circuit. The third bidirectional switch circuit is coupled between the ninth node and the tenth node, and is configured to clamp the voltage of the tenth node to the voltage of the ninth node during a period when both the first-phase switch capacitor sub-circuit and the second-phase switch capacitor sub-circuit are turned off. The ninth node is coupled to the negative electrode of the first capacitor of the first-phase switch capacitor sub-circuit, and the tenth node is coupled to the negative electrode of the first capacitor of the third-phase switch capacitor sub-circuit. By arranging the third bidirectional switch circuit between the ninth node and the tenth node, the third-phase switch capacitor sub-circuit can normally work when both the first-phase switch capacitor sub-circuit and the second-phase switch capacitor sub-circuit are turned off. At this time, the voltage of the tenth node can be clamped to the voltage of the ninth node by the third bidirectional switch circuit, and the voltage difference between two ends of the transistors in the first-stage switch network of the first-phase switch capacitor sub-circuit can be reduced by changing the voltage of the ninth node, so as to reduce the “shock” current of the transistors at the moment of turning on and reduce the turn-on loss of the transistors. In addition, the third bidirectional switch circuit has a simple structure, a simple process, and is easy to implement.

[0023] In a possible implementation, the switched-capacitor circuit further includes: a fourth bidirectional switch circuit. The fourth bidirectional switch circuit is coupled between the eleventh node and the twelfth node, and is configured to clamp the voltage of the twelfth node to the voltage of the eleventh node in a period when both the first-phase switched-capacitor subcircuit and the second-phase switched-capacitor subcircuit are off. The eleventh node is coupled to the negative electrode of the first capacitor of the second-phase switched-capacitor subcircuit, and the twelfth node is coupled to the negative electrode of the first capacitor of the fourth-phase switched-capacitor subcircuit. By arranging the fourth bidirectional switch circuit between the eleventh node and the twelfth node, the fourth-phase switched-capacitor subcircuit can normally work when both the first-phase switched-capacitor subcircuit and the second-phase switched-capacitor subcircuit are off. At this time, the voltage of the twelfth node can be clamped to the voltage of the eleventh node by the fourth bidirectional switch circuit, and the voltage difference between the two ends of a transistor in the first-stage switch network of the second-phase switched-capacitor subcircuit can be reduced by changing the voltage of the eleventh node, so as to reduce the "impact" current of the transistor at the moment of turning on and reduce the turn-on loss of the transistor. Moreover, the fourth bidirectional switch circuit has a simple structure, simple process, and is easy to implement.

[0024] In a possible implementation, each phase switched-capacitor subcircuit includes a multi-stage (N-stage) switched-capacitor network coupled in series, and the switched-capacitor circuit includes a plurality of first bidirectional switch circuits; the plurality of first bidirectional switch circuits are coupled to the multi-stage switched-capacitor network in a one-to-one correspondence. By arranging the multi-stage (N-stage) switched-capacitor network in each phase switched-capacitor subcircuit, the ratio of the input voltage to the output voltage Vvi:Vvo of the input end can be 2 N+1 :1, so as to achieve a high conversion ratio and meet different use requirements.

[0025] In a possible implementation, the second-stage switch network includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the first electrode of the first transistor is coupled to the negative electrode of the first capacitor, and the second electrode of the first transistor is coupled to the first electrode of the second transistor and the positive electrode of the second capacitor; the second electrode of the second transistor is coupled to the output end and the first electrode of the third transistor; the second electrode of the third transistor is coupled to the negative electrode of the second capacitor and the first electrode of the fourth transistor; the second electrode of the fourth transistor is coupled to the reference ground voltage terminal; the first electrode of the fifth transistor is coupled to the positive electrode of the first capacitor, and the second electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the positive electrode of the third capacitor; the second electrode of the sixth transistor is coupled to the output end and the first electrode of the seventh transistor; the second electrode of the seventh transistor is coupled to the negative electrode of the third capacitor and the first electrode of the eighth transistor; and the second electrode of the eighth transistor is coupled to the reference ground voltage terminal. This is a simple topology.

[0026] In a possible implementation, the seventh transistor in the first-phase switched-capacitor sub-circuit and the third transistor in the second-phase switched-capacitor sub-circuit are the same transistor; or, the eighth transistor in the first-phase switched-capacitor sub-circuit and the fourth transistor in the second-phase switched-capacitor sub-circuit are the same transistor. In this topology, the number of transistors in the switched-capacitor circuit can be reduced, and the area occupied by the switched-capacitor circuit can be reduced.

[0027] In a possible implementation, the seventh transistor in the third-phase switched-capacitor sub-circuit and the third transistor in the fourth-phase switched-capacitor sub-circuit are the same transistor; or, the eighth transistor in the third-phase switched-capacitor sub-circuit and the fourth transistor in the fourth-phase switched-capacitor sub-circuit are the same transistor. In this topology, the number of transistors in the switched-capacitor circuit can be reduced, and the area occupied by the switched-capacitor circuit can be reduced.

[0028] In a possible implementation, the second-stage switching network in each switched-capacitor network includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; in each switched-capacitor network, the first electrode of the fourth transistor is coupled to the second electrode of the third transistor, and the second electrode of the fourth transistor is coupled to a reference ground voltage terminal; the first electrode of the eighth transistor is coupled to the second electrode of the seventh transistor, and the second electrode of the eighth transistor is coupled to the reference ground voltage terminal; in the first-stage switched-capacitor network, the first electrode of the first transistor is coupled to the negative electrode of a first capacitor, and the second electrode of the first transistor is coupled to the first electrode of the second transistor and the positive electrode of a second capacitor; the first electrode of the fifth transistor is coupled to the positive electrode of the first capacitor, and the second electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the positive electrode of a third capacitor; in the switched-capacitor network other than the first stage, the first electrode of the first transistor is coupled to the second electrode of the second transistor in the previous-stage switched-capacitor network, and the second electrode of the first transistor is coupled to the first electrode of the second transistor and the positive electrode of the second capacitor; the first electrode of the fifth transistor is coupled to the second electrode of the sixth transistor in the previous-stage switched-capacitor network, and the second electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the positive electrode of the third capacitor; in the last-stage switched-capacitor network, the second electrode of the second transistor, the first electrode of the third transistor, the second electrode of the sixth transistor, and the first electrode of the seventh transistor are all coupled to an output terminal; in the switched-capacitor network other than the last stage, the second electrode of the second transistor is coupled to the first electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled to the first electrode of the third transistor. This is a simple topology.

[0029] In a possible implementation, the seventh transistor of the last-stage switched-capacitor network in the first-phase switched-capacitor sub-circuit and the third transistor of the last-stage switched-capacitor network in the second-phase switched-capacitor sub-circuit are the same transistor. And / or, the eighth transistor of the last-stage switched-capacitor network in the first-phase switched-capacitor sub-circuit and the fourth transistor of the last-stage switched-capacitor network in the second-phase switched-capacitor sub-circuit are the same transistor. In this topology, the number of transistors in the switched-capacitor circuit can be reduced, and the area occupied by the switched-capacitor circuit can be reduced.

[0030] In a possible implementation, the seventh transistor of the last-stage switched-capacitor network in the third-phase switched-capacitor sub-circuit and the third transistor of the last-stage switched-capacitor network in the fourth-phase switched-capacitor sub-circuit are the same transistor. And / or, the eighth transistor of the last-stage switched-capacitor network in the third-phase switched-capacitor sub-circuit and the fourth transistor of the last-stage switched-capacitor network in the fourth-phase switched-capacitor sub-circuit are the same transistor. In this topology, the number of transistors in the switched-capacitor circuit can be reduced, and the area occupied by the switched-capacitor circuit can be reduced.

[0031] In a possible implementation, the first-stage switching network includes a ninth transistor and a tenth transistor; the first electrode of the ninth transistor is coupled to the input terminal, and the second electrode of the ninth transistor is coupled to the positive electrode of the first capacitor and the first electrode of the fifth transistor respectively; the first electrode of the tenth transistor is coupled to the negative electrode of the first capacitor and the first electrode of the first transistor respectively, and the second electrode of the tenth transistor is coupled to the reference ground voltage terminal. This is a simple topology structure.

[0032] In a third aspect, the embodiment of the present application provides a switched-capacitor circuit, which comprises: a first phase switched-capacitor sub-circuit, a second phase switched-capacitor sub-circuit, a third phase switched-capacitor sub-circuit and a fourth phase switched-capacitor sub-circuit coupled in parallel between an input terminal and an output terminal; the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are 180° out of phase, the first phase switched-capacitor sub-circuit and the third phase switched-capacitor sub-circuit are 90° out of phase, and the third phase switched-capacitor sub-circuit and the fourth phase switched-capacitor sub-circuit are 180° out of phase; the first phase switched-capacitor sub-circuit, the second phase switched-capacitor sub-circuit, the third phase switched-capacitor sub-circuit and the fourth phase switched-capacitor sub-circuit each comprise a first capacitor, a first-stage switch network and a switched-capacitor network, and the switched-capacitor network comprises a second capacitor, a third capacitor and a second-stage switch network; the first-stage switch network is coupled with the input terminal and the first capacitor, and is configured to adjust the on-off state between the first capacitor and the input terminal; the second-stage switch network is coupled with the first capacitor, the second capacitor and the third capacitor, and is configured to adjust the series-parallel connection relationship among the first capacitor, the second capacitor and the third capacitor. A bidirectional switch circuit is coupled between a ninth node and a tenth node, and is configured to clamp the voltage of the tenth node to the ninth node during a period when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off; the ninth node is coupled with the negative electrode of the first capacitor of the first phase switched-capacitor sub-circuit, and the tenth node is coupled with the negative electrode of the first capacitor of the third phase switched-capacitor sub-circuit. By arranging the bidirectional switch circuit between the ninth node and the tenth node, the third phase switched-capacitor sub-circuit can normally work when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off. At this time, the voltage of the tenth node can be clamped to the ninth node by the third bidirectional switch circuit, and the voltage difference between the two ends of the transistor in the first-stage switch network of the first phase switched-capacitor sub-circuit can be reduced by changing the voltage of the ninth node, so as to reduce the “shock” current of the transistor at the moment of turning on and reduce the turn-on loss of the transistor. Moreover, the bidirectional switch circuit has a simple structure and simple process, and is easy to implement.

[0033] In a fourth aspect, the embodiment of the present application provides a switched capacitor circuit, which comprises: a first capacitor and a first switch network; the first capacitor is coupled with the first switch network, and the first switch network is configured to adjust the on-off between the first capacitor and an input terminal; a first switch capacitor network coupled in series in multiple stages, each stage of the first switch capacitor network comprising a second capacitor and a second switch network; the second switch network is coupled with the second capacitor and the first switch network respectively, and is configured to adjust the series-parallel connection between the second capacitor and the first capacitor; each stage of the first switch capacitor network further comprises a thirteenth node coupled with the negative electrode of the second capacitor; a second switch capacitor network coupled in series in multiple stages, each stage of the second switch capacitor network comprising a third capacitor and a third switch network; the third switch network is coupled with the third capacitor and the first switch network respectively, and is configured to adjust the series-parallel connection between the third capacitor and the first capacitor; each stage of the second switch capacitor network further comprises a fourteenth node coupled with the negative electrode of the third capacitor; a plurality of auxiliary circuits, each of which is coupled with a thirteenth node and a fourteenth node respectively, and is configured to convert the voltage of the thirteenth node and the voltage of the fourteenth node in a period when the first switch network, the second switch network and the third switch network are all turned off.

[0034] The switched capacitor circuit provided by the embodiment of the present application comprises a first switch capacitor network coupled in series in multiple stages (N stages) and a second switch capacitor network coupled in series in multiple stages (N stages), and can realize the ratio Vvi:Vvo of the input voltage and the output voltage of the input terminal as 2 N+1 :1, so as to realize high conversion ratio and meet different use requirements. On this basis, the auxiliary circuit is correspondingly coupled between each stage of the first switch capacitor network and the second switch capacitor network, so as to reduce the "impact" current of the transistor in each stage of the first switch capacitor network and the second switch capacitor network at the turn-on moment, so as to reduce the turn-on loss of the transistor.

[0035] In a fifth aspect, the embodiment of the present application provides an electronic device comprising the switched capacitor circuit of any one of the first aspect to the fourth aspect and a battery, wherein the switched capacitor circuit is coupled with the battery. BRIEF DESCRIPTION OF DRAWINGS

[0036] FIG. 1 is an architecture diagram of an electronic device provided by the embodiment of the present application;

[0037] FIG. 2 is a connection relationship diagram of a switched capacitor circuit provided by the embodiment of the present application;

[0038] FIG. 3 is a topology diagram of a switched capacitor circuit provided by the embodiment of the present application;

[0039] FIG. 4A is an intermediate modal diagram of a switched capacitor circuit provided by the embodiment of the present application;

[0040] Fig. 4B is an equivalent diagram of one intermediate mode of the switched-capacitor circuit provided in the embodiments of the present application;

[0041] Fig. 5A is another intermediate mode diagram of a switched-capacitor circuit provided in the embodiments of the present application;

[0042] Fig. 5B is an equivalent diagram of another intermediate mode of the switched-capacitor circuit provided in the embodiments of the present application;

[0043] Fig. 6A and Fig. 6B are architecture diagrams of a switched-capacitor circuit provided in the embodiments of the present application;

[0044] Fig. 7A is a topological schematic diagram of a second auxiliary circuit provided in the embodiments of the present application;

[0045] Fig. 7B is a diagram of a circuit control signal and corresponding current-voltage waveforms provided in the embodiments of the present application;

[0046] Fig. 7C is a topological schematic diagram of a resonant network provided in the embodiments of the present application;

[0047] Fig. 8 is a topological schematic diagram of another second auxiliary circuit provided in the embodiments of the present application;

[0048] Fig. 9A is a topological schematic diagram of yet another second auxiliary circuit provided in the embodiments of the present application;

[0049] Fig. 9B is a diagram of a circuit control signal and corresponding current-voltage waveforms provided in the embodiments of the present application;

[0050] Fig. 10A is a topological schematic diagram of yet another second auxiliary circuit provided in the embodiments of the present application;

[0051] Fig. 10B is a diagram of another circuit control signal and corresponding current-voltage waveforms provided in the embodiments of the present application;

[0052] Fig. 11A and Fig. 11B are topological schematic diagrams of a switched-capacitor circuit provided in the embodiments of the present application;

[0053] Fig. 12A is an architecture diagram of another switched-capacitor circuit provided in the embodiments of the present application;

[0054] Fig. 12B is a topological schematic diagram of another switched-capacitor circuit provided in the embodiments of the present application;

[0055] Fig. 12C is a topological schematic diagram of another switched-capacitor circuit provided in the embodiments of the present application;

[0056] Fig. 13 is a topological schematic diagram of yet another switched-capacitor circuit provided in the embodiments of the present application;

[0057] FIG. 14A and FIG. 14B are schematic diagrams of another topology of a switched-capacitor circuit according to embodiments of the present application;

[0058] FIG. 15A and FIG. 15B are schematic diagrams of another topology of a switched-capacitor circuit according to embodiments of the present application;

[0059] FIG. 16A and FIG. 16B are schematic diagrams of another topology of a switched-capacitor circuit according to embodiments of the present application;

[0060] FIG. 17 is a schematic diagram of another topology of a switched-capacitor circuit according to embodiments of the present application. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0062] Hereinafter, the terms "second", "first", and the like are only used for description convenience, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "second", "first", and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0063] In addition, in the embodiments of the present application, the orientation terms such as "upper", "lower", "left", "right", and the like can include but not limited to the orientation defined by the relative placement of the components in the drawings. It should be understood that these directional terms can be relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the placement of the components in the drawings.

[0064] In the embodiments of the present application, unless otherwise explicitly specified and limited, the term "connection" should be understood in a broad sense, for example, "connection" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through an intermediate medium. In addition, the term "coupling" can be direct electrical connection, or indirect electrical connection through an intermediate medium. The term "contact" can be direct contact, or indirect contact through an intermediate medium.

[0065] In the embodiments of the present application, "and / or" describes the association relationship between the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it.

[0066] Embodiments of the present application provide an electronic device, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial electronic product. The consumer electronic product is, for example, a mobile phone, a pad, a notebook computer, an e-book reader, a personal computer (PC), a personal digital assistant (PDA), a desktop display, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, a drone, and the like. The home electronic product is, for example, a smart door lock, a television, a refrigerator, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), and the like. The vehicle-mounted electronic product is, for example, a vehicle-mounted navigator, a vehicle-mounted DVD, and the like. The financial electronic product is, for example, an ATM machine, a self-service electronic device, and the like.

[0067] Embodiments of the present application do not specially limit the specific form of the electronic device, and the following embodiments are exemplarily described by taking a mobile phone as an example.

[0068] FIG. 1 is an architecture diagram of an electronic device provided by an embodiment of the present application.

[0069] The electronic device 100 provided by an embodiment of the present application, as shown in FIG. 1, can include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 01, an antenna 02, a mobile communication module 150, a wireless communication module 160, an audio module 170, a loudspeaker 170A, a receiver 170B, a microphone 170C, a headset interface 170D, a sensor module 180, a camera 193, and a display screen 194, and the like.

[0070] It can be understood that the structure shown in the embodiments of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 can include more or fewer components than those shown, or combine certain components, or split certain components, or different arrangement of components. The components shown can be implemented in hardware, software, or a combination of software and hardware.

[0071] The wireless communication function of the electronic device 100 can be realized by the antenna 01, the antenna 02, the mobile communication module 150, the wireless communication module 160, the modem processor, and the baseband processor, and the like.

[0072] The processor 110 can include one or more processing units, for example, the processor 110 can include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc.

[0073] The electronic device 100 implements a display function through a GPU, a display screen 194, and an application processor, etc. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering.

[0074] The electronic device 100 can implement a shooting function through an ISP, a camera 193, a video codec, a GPU, a display screen 194, and an application processor, etc.

[0075] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function.

[0076] The internal memory 121 can be used to store one or more computer programs including instructions. The processor 110 can cause the electronic device 100 to perform the methods provided in some embodiments of the present application, as well as various functional applications and data processing, etc., by running the above-mentioned instructions stored in the internal memory 121.

[0077] The electronic device 100 can implement an audio function through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, and an application processor, etc. For example, music playing, recording, etc.

[0078] The sensor module 180 can include a pressure sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, etc.

[0079] The power management module 141 is configured to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives the input of the battery 142 and / or the charging management module 140, and supplies power for the processor 110, the internal memory 121, the display screen 194, the camera 193, the wireless communication module 160 and the like. The power management module 141 can also be configured to monitor the battery capacity, the battery cycle number, the battery health status (leakage, impedance) and the like. In some other embodiments, the power management module 141 can also be arranged in the processor 110. In some other embodiments, the power management module 141 and the charging management module 140 can also be arranged in the same device.

[0080] The charging management module 140 is configured to receive the charging input from the charger. The charger can be a wireless charger or a wired charger (or an adapter). In some embodiments of the wired charging, the charging management module 140 can receive the charging input of the wired charger through the USB interface 130. In some embodiments of the wireless charging, the charging management module 140 can receive the wireless charging input through the wireless charging coil of the electronic device 100.

[0081] FIG. 2 is a schematic diagram of a connection relationship of a switched capacitor circuit according to an embodiment of the present application.

[0082] As shown in FIG. 2, the charging management module 140 can be connected to the USB interface 130 by an over voltage protection (OVP) protection circuit 131. When the OVP protection circuit 131 detects that the voltage connected to the USB interface 130 is too high (exceeding a threshold voltage), the charging management module 140 can be actively disconnected from the USB interface 130. For example, as shown in FIG. 2, the charging management module 140 is connected to the wireless charging coil 132 through a receive integrated circuit (Rx IC) 133. In order to realize the normal charging or the fast charging of the battery, as shown in FIG. 2, the charging management module 140 can include a switched capacitor converter (SC) for fast charging of the battery and a step-down converter (BUCK) for normal charging of the battery. The switched capacitor converter SC and the BUCK are connected to the USB interface 130 through the OVP protection circuit 131, and are connected to the wireless charging coil 132 through the Rx IC 133.

[0083] The processor 110 or the charging management module 140 can detect, according to the charging protocol, that the step-down conversion circuit BUCK or the switched-capacitor circuit SC is charging the battery, and generally the switched-capacitor circuit SC and the step-down conversion circuit BUCK are step-down conversion circuits with a fixed step-down ratio. For example, when the charging protocol detects that the voltage at the input side of the switched-capacitor circuit SC and the step-down conversion circuit BUCK is 5V, the step-down conversion circuit BUCK is controlled to convert the voltage of 5V to a voltage slightly higher than the voltage of the battery, and then charge the battery. Alternatively, when the charging protocol detects that the voltage at the input side of the switched-capacitor circuit SC and the step-down conversion circuit BUCK is 20V, it is determined that this is a fast charging scenario, and then the switched-capacitor circuit SC is controlled to convert the voltage of 20V to a voltage near the voltage of the battery, and then charge the battery.

[0084] When the battery voltage or capacity rises to a certain stage, or the heat consumption is too large, the charging power needs to be controlled to be switched down to a lower charging power (for example, 40W). The voltage output by the switched-capacitor circuit SC of the adapter or the wireless charger will drop to about 10V. At this time, in order to maintain the original charging current and maintain fast charging, the charging protocol will control the switched-capacitor circuit SC to convert the input voltage of 10V to about 5V in a 2:1 step-down mode to continue charging the battery. Of course, when the charging protocol controls the adapter or the wireless charger to further reduce the voltage, the switched-capacitor circuit SC needs to be further switched to a step-down mode to ensure that the output voltage is continuously maintained at about 5V, thereby ensuring the effect of fast charging.

[0085] That is, the switched-capacitor circuit SC can receive an input voltage through an input terminal and provide an output voltage through an output terminal. The input voltage can be a voltage provided from a charger outside the electronic device 100, or a voltage provided from any node in the power network inside the electronic device 100. The switched-capacitor circuit SC can generate an output voltage with a certain ratio to the input voltage, and output to the outside of the system or any node in the power network inside the system.

[0086] FIG. 3 is a topological schematic diagram of a switched-capacitor circuit provided in an embodiment of the present application.

[0087] In some embodiments, as shown in FIG. 3, the switched-capacitor circuit SC includes a first capacitor Cf1, a second capacitor Cf2, a third capacitor Cf3, a first-stage switch network 10, and a second-stage switch network 20. The first-stage switch network 10 includes a first switch network, and the second-stage switch network 20 includes a second switch network 21 and a third switch network 22.

[0088] The first capacitor Cf1 is coupled with the first stage switch network 10 (i.e. the first switch network) for adjusting the on-off between the first capacitor Cf1 and the input terminal VI. The second switch network 21 is coupled with the second capacitor Cf2 and the first stage switch network 10 respectively, for adjusting the series-parallel between the second capacitor Cf2 and the first capacitor Cf1. The third switch network 22 is coupled with the third capacitor Cf3 and the first stage switch network 10 respectively, for adjusting the series-parallel between the third capacitor Cf3 and the first capacitor Cf1. The second switch network 21 and the third switch network 22 are coupled with the output terminal VO for outputting the reduced charging voltage.

[0089] For example, the second switch network 21 includes a first transistor Q1, a second transistor Q2, a third transistor Q3 and a fourth transistor Q4, the third switch network 22 includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7 and an eighth transistor Q8, and the first stage switch network 10 includes a ninth transistor Q9 and a tenth transistor Q10.

[0090] The first pole of the first transistor Q1 is coupled with the negative pole of the first capacitor Cf1, and the second pole of the first transistor Q1 is coupled with the first pole of the second transistor Q2 and the positive pole of the second capacitor Cf2 respectively. The second pole of the second transistor Q2 is coupled with the output terminal VO and the first pole of the third transistor Q3 respectively. The second pole of the third transistor Q3 is coupled with the negative pole of the second capacitor Cf2 and the first pole of the fourth transistor Q4 respectively. The second pole of the fourth transistor Q4 is coupled with the reference ground voltage terminal GND.

[0091] The first pole of the fifth transistor Q5 is coupled with the positive pole of the first capacitor Cf1, and the second pole of the fifth transistor Q5 is coupled with the first pole of the sixth transistor Q6 and the positive pole of the third capacitor Cf3 respectively. The second pole of the sixth transistor Q6 is coupled with the output terminal VO and the first pole of the seventh transistor Q7 respectively. The second pole of the seventh transistor Q7 is coupled with the negative pole of the third capacitor Cf3 and the first pole of the eighth transistor Q8 respectively. The second pole of the eighth transistor Q8 is coupled with the reference ground voltage terminal GND.

[0092] The first pole of the ninth transistor Q9 is coupled with the input terminal VI, and the second pole of the ninth transistor Q9 is coupled with the positive pole of the first capacitor Cf1 and the first pole of the fifth transistor Q5 respectively. The first pole of the tenth transistor Q10 is coupled with the negative pole of the first capacitor Cf1 and the first pole of the first transistor Q1 respectively, and the second pole of the tenth transistor Q10 is coupled with the reference ground voltage terminal GND.

[0093] The first transistor Q1 to the tenth transistor Q10 each include a control electrode, and under the control of the control electrode, the switch can switch the first electrode and the second electrode between the on state and the off state. In the embodiments of the present application, the transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET). In addition, in the example shown in FIG. 3, only one transistor is shown at each position of the transistor, and it can be understood that two or more transistors in parallel can be used at each position of the transistor to reduce the resistance when the switch is on. In the embodiments of the present application, the transistor is divided into two types: a negative (N) type transistor and a positive (P) type transistor. The transistor includes a source, a drain, and a gate, and the on state or the off state of the transistor can be controlled by controlling the level of the gate of the transistor. When the transistor is on, the source and the drain are on, and an on current is generated. When the levels of the gates of the transistors are different, the size of the on current generated between the source and the drain is also different. When the transistor is off, the source and the drain are not on, and no current is generated. In the embodiments of the present application, the gate of the transistor is also referred to as the control electrode, the source is referred to as the first electrode, and the drain is referred to as the second electrode; or the gate is referred to as the control electrode, the drain is referred to as the first electrode, and the source is referred to as the second electrode. In addition, the N type transistor is on when the level of the control electrode is high, the first electrode and the second electrode are on, and the on current is generated between the first electrode and the second electrode. The N type transistor is off when the level of the control electrode is low, the first electrode and the second electrode are not on, and no current is generated. The P type transistor is on when the level of the control electrode is low, the first electrode and the second electrode are on, and the on current is generated. The P type transistor is off when the level of the control electrode is high, the first electrode and the second electrode are not on, and no current is generated. The transistors used in the following schemes can be referred to the description herein.

[0094] FIG. 4A is a middle mode diagram of a switched capacitor circuit provided by an embodiment of the present application, and FIG. 4B is an equivalent diagram of a middle mode of a switched capacitor circuit provided by an embodiment of the present application.

[0095] As shown in FIG. 4A, in the first mode, the first transistor Q1, the third transistor Q3, the sixth transistor Q6, the eighth transistor Q8, and the ninth transistor Q9 are controlled to be on, and the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5, the seventh transistor Q7, and the tenth transistor Q10 are controlled to be off, and the capacitors are connected to form the equivalent circuit shown in FIG. 4B.

[0096] In the 4:1 step-down mode, in the first time period of a cycle, as shown in Fig. 4A, the first switch network 10 connects the input terminal VI to the positive terminal of the first capacitor Cf1. The second switch network 21 connects the negative terminal of the first capacitor Cf1 to the positive terminal of the second capacitor Cf2, and connects the negative terminal of the second capacitor Cf2 to the output terminal VO. The third switch network 22 connects the negative terminal of the third capacitor Cf3 to the reference ground voltage terminal GND, and connects the positive terminal of the third capacitor Cf3 to the output terminal VO. The capacitors are connected to form the equivalent circuit as shown in Fig. 4B, in which the first capacitor Cf1 and the second capacitor Cf2 are connected in series, and the first capacitor Cf1 and the second capacitor Cf2 are connected in parallel with the third capacitor Cf3 and the output terminal VO respectively. When the system is stable, Vvi = Vcf1 + Vcf2 + Vvo, and Vcf3 = Vvo, where Vvi is the input voltage, Vcf1 is the voltage across the first capacitor Cf1, Vcf2 is the voltage across the second capacitor Cf2, Vcf3 is the voltage across the third capacitor Cf3, and Vvo is the output voltage.

[0097] Fig. 5A is another intermediate mode diagram of a switched capacitor circuit according to an embodiment of the present application, and Fig. 5B is an equivalent circuit of the switched capacitor circuit according to an embodiment of the present application.

[0098] As shown in Fig. 5A, in the second mode, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5, the seventh transistor Q7 and the tenth transistor Q10 are turned on, and the first transistor Q1, the third transistor Q3, the sixth transistor Q6, the eighth transistor Q8 and the ninth transistor Q9 are turned off. The capacitors are connected to form the equivalent circuit as shown in Fig. 5B.

[0099] In the second time period of a cycle, as shown in Fig. 5A, the first switch network 10 connects the negative terminal of the first capacitor Cf1 to the reference ground voltage terminal GND. The second switch network 21 connects the positive terminal of the second capacitor Cf2 to the output terminal VO, and connects the negative terminal of the second capacitor Cf2 to the reference ground voltage terminal GND. The third switch network 22 connects the positive terminal of the third capacitor Cf3 to the positive terminal of the first capacitor Cf1, and connects the negative terminal of the third capacitor Cf3 to the output terminal VO. The capacitors are connected to form the equivalent circuit as shown in Fig. 5B, in which the first capacitor Cf1 and the third capacitor Cf3 are connected in series, and the first capacitor Cf1 and the third capacitor Cf3 are connected in parallel with the second capacitor Cf2 and the output terminal VO respectively. When the system is stable, Vcf2 = Vvo, and Vcf1 = Vcf2 + Vvo.

[0100] In summary, Vvi=4Vvo, Vcf1=2Vvo, Vcf2=Vvo, Vcf3=Vvo, thus a 4:1 voltage ratio conversion can be achieved. That is, since the input voltage Vvi is four times the output voltage Vvo, a 4:1 voltage conversion ratio can be achieved when the switch capacitor circuit SC shown in FIG. 3 operates in the mode shown in FIG. 4A and FIG. 5A. At this time, the voltage Vcf1 of the first capacitor Cf1 is twice the output voltage Vvo, and each of the voltage Vcf2 of the second capacitor Cf2 and the voltage Vcf3 of the third capacitor Cf3 is equal to the output voltage Vvo.

[0101] Therefore, the first capacitor Cf1, the second capacitor Cf2, and the third capacitor Cf3 all have lower voltage stress. Since the effective capacitance of a capacitor is greatly affected by the DC bias voltage, lower voltage stress means less number of capacitors required, and thus the single board area of the switch capacitor circuit SC shown in FIG. 3 is smaller.

[0102] Since the principle of the switch capacitor is the mutual charging and discharging between the capacitors, the turn-off current of any transistor in the switch capacitor circuit SC shown in FIG. 3 is small (the "surge" current tail has approached zero current), and the turn-off loss is small. However, there is a large "surge" current at the turn-on moment of any transistor in the switch capacitor circuit SC, resulting in a large turn-on loss, and the turn-on loss of the transistor is a major reason for limiting the efficiency of the switch capacitor circuit SC.

[0103] For example, taking the fourth transistor Q4 as an example, in the first mode, the node A coupled to the first pole of the fourth transistor Q4 is in series with the output terminal VO, and the voltage of the node A is equal to the voltage of the output terminal VO. In the second mode, the fourth transistor Q4 needs to be turned on, and at the moment when the fourth transistor Q4 is turned on, the voltage of the first pole of the fourth transistor Q4 is equal to the voltage of the output terminal VO, and the voltage of the second pole of the fourth transistor Q4 is equal to the voltage of the reference ground terminal GND. There is a large voltage difference between the first pole and the second pole of the fourth transistor Q4, resulting in a large "surge" current at the turn-on moment of the fourth transistor Q4, thereby causing a large turn-on loss.

[0104] FIG. 6A and FIG. 6B are architecture diagrams of a switch capacitor circuit provided in an embodiment of the present application.

[0105] The embodiment of the present application provides a kind of switched capacitor circuit, as shown in Figure 6A, switched capacitor circuit SC includes switched capacitor group;Switched capacitor group includes first phase switched capacitor subcircuit SC1 and second phase switched capacitor subcircuit SC2, first phase switched capacitor subcircuit SC1 and second phase switched capacitor subcircuit SC2 staggered parallel coupling between input terminal VI and output terminal VO between.The example, first phase switched capacitor subcircuit SC1 and second phase switched capacitor subcircuit SC2 parallel coupling between input terminal VI and output terminal VO, the phase of first phase switched capacitor subcircuit SC1 and second phase switched capacitor subcircuit SC2 staggered 180°.That is, at the same time, the transistor of second stage switch network 20A in first phase switched capacitor subcircuit SC1 and the transistor of second stage switch network 20B in second phase switched capacitor subcircuit SC2 are completely different.For example, first phase switched capacitor subcircuit SC1 enters the first mode shown in Figure 4A, and second phase switched capacitor subcircuit SC2 enters the second mode shown in Figure 5A.First phase switched capacitor subcircuit SC1 enters the second mode shown in Figure 5A, and second phase switched capacitor subcircuit SC2 enters the first mode shown in Figure 4A.

[0106] The example, first phase switched capacitor subcircuit SC1 and second phase switched capacitor subcircuit SC2 are identical with the structure of the switched capacitor circuit SC shown in Figure 3.For example, first phase switched capacitor subcircuit SC1 and second phase switched capacitor subcircuit SC2 are single first interleaved second stage (SFIPS) circuit.

[0107] For example, first phase switched capacitor subcircuit SC1 includes first switched capacitor network 1A and second switched capacitor network 2A, first switched capacitor network 1A includes first capacitor Cf1A and first stage switch network 10A, and second switched capacitor network 2A includes second capacitor Cf2A, third capacitor Cf3A and second stage switch network 20A;First stage switch network 10A is coupled with input terminal VI and second stage switch network 20A respectively, and second stage switch network 20A is coupled with output terminal VO.Second capacitor Cf1A is coupled with first stage switch network 10A, and first stage switch network 10A is used to adjust the on-off between first capacitor Cf1A and input terminal VI.Second stage switch network 20A is coupled with first capacitor Cf1A, second capacitor Cf2A and third capacitor Cf3A respectively, and second stage switch network 20A is used to adjust the series-parallel relationship between third capacitor Cf3A, second capacitor Cf2A and first capacitor Cf1A.First stage switch network 10A includes the above-mentioned first switch network, for example, and second stage switch network 20A includes the above-mentioned second switch network 21 and third switch network 22.

[0108] The second-phase switched-capacitor sub-circuit SC2 also includes a first switched-capacitor network IB and a second switched-capacitor network 2B. The first switched-capacitor network IB includes a first capacitor CfIB and a first-stage switch network 10B, and the second switched-capacitor network 2B includes a second capacitor Cf2B, a third capacitor Cf3B, and a second-stage switch network 20B. The first-stage switch network 10B is coupled to the input terminal VI and the second-stage switch network 20B, respectively, and the second-stage switch network 20B is coupled to the output terminal VO. The first capacitor CfIB is coupled to the first-stage switch network 10B, which is configured to adjust the connection and disconnection between the first capacitor CfIB and the input terminal VI. The second-stage switch network 20B is coupled to the first capacitor CfIB, the second capacitor Cf2B, and the third capacitor Cf3B, respectively, and is configured to adjust the series-parallel connection among the third capacitor Cf3A, the second capacitor Cf2B, and the first capacitor CfIB. The first-stage switch network 10B includes, for example, the first switch network described above, and the second-stage switch network 20B includes, for example, the second switch network 21 and the third switch network 22 described above.

[0109] In some embodiments, as shown in FIG. 6A, the second-stage switch network 20A of the first-phase switched-capacitor sub-circuit SC1 includes a first transistor Q1A, a second transistor Q2A, a third transistor Q3A, a fourth transistor Q4A, a fifth transistor Q5A, a sixth transistor Q6A, a seventh transistor Q7A, and an eighth transistor Q8A, and the first-stage switch network 10A includes a ninth transistor Q9A and a tenth transistor Q10A. The connection relationship of each transistor can refer to the description about FIG. 3 above.

[0110] The second-stage switch network 20B of the second-phase switched-capacitor sub-circuit SC2 includes a first transistor Q1B, a second transistor Q2B, a third transistor Q3B, a fourth transistor Q4B, a fifth transistor Q5B, a sixth transistor Q6B, a seventh transistor Q7B, and an eighth transistor Q8B, and the first-stage switch network 10B includes a ninth transistor Q9B and a tenth transistor Q10B. The connection relationship of each transistor can refer to the description about FIG. 3 above.

[0111] In other embodiments, as shown in FIG. 6B, the seventh transistor Q7A in the first-phase switched-capacitor sub-circuit SC1 and the third transistor Q3B in the second-phase switched-capacitor sub-circuit SC2 are the same transistor.

[0112] Alternatively, the eighth transistor Q8A in the first-phase switched-capacitor sub-circuit SC1 and the fourth transistor Q4B in the second-phase switched-capacitor sub-circuit SC2 are the same transistor.

[0113] Alternatively, the seventh transistor Q7B in the second phase switched-capacitor sub-circuit SC2 and the third transistor Q3A in the first phase switched-capacitor sub-circuit SC1 are the same transistor.

[0114] Alternatively, the eighth transistor Q8B in the second phase switched-capacitor sub-circuit SC2 and the fourth transistor Q4A in the first phase switched-capacitor sub-circuit SC1 are the same transistor.

[0115] In this topology, the number of transistors in the switched-capacitor circuit SC can be reduced, and the area occupied by the switched-capacitor circuit SC can be reduced.

[0116] The transistors in the first phase switched-capacitor sub-circuit SC1 and the second phase switched-capacitor sub-circuit SC2 in the interleaved parallel connection are in a complementary relationship, which can be understood as a corresponding relationship between conduction and shutdown. For example, the ninth transistor Q9A in the first phase switched-capacitor sub-circuit SC1 is turned on, and the ninth transistor Q9B in the second phase switched-capacitor sub-circuit SC2 is turned off.

[0117] In some embodiments, as shown in FIG. 6A, the switched-capacitor circuit SC further includes a second auxiliary circuit 32.

[0118] The second auxiliary circuit 32 is coupled between the third node A3 and the fourth node A4, and is configured to convert the voltage of the third node A3 and the voltage of the fourth node A4 during a period when both the first phase switched-capacitor sub-circuit SC1 and the second phase switched-capacitor sub-circuit SC2 are turned off. The third node A3 is coupled to the negative electrode of the second capacitor Cf2A of the first phase switched-capacitor sub-circuit SC1 and the negative electrode of the third capacitor Cf3B of the second phase switched-capacitor sub-circuit SC2, respectively. The fourth node A4 is coupled to the negative electrode of the third capacitor Cf3A of the first phase switched-capacitor sub-circuit and the negative electrode of the second capacitor Cf2B of the second phase switched-capacitor sub-circuit SC2, respectively.

[0119] The above-mentioned "conversion" can be understood as changing the voltage of the node, changing the high voltage in the two nodes to the low voltage, and changing the low voltage in the two nodes to the high voltage. For example, the voltage of the third node A3 can be transferred to the fourth node A4, or the voltage of the fourth node A4 can be transferred to the third node A3. Depending on the architecture of the auxiliary circuit, the principle of voltage conversion between nodes is different.

[0120] The switch capacitor circuit SC provided by the embodiments of the present application has the first-phase switch capacitor sub-circuit SC1 and the second-phase switch capacitor sub-circuit SC2 connected in parallel with a phase difference of 180°, so that when the switch capacitor circuit works in the first state, the voltage of the third node is the output voltage Vvo and the voltage of the fourth node is 0. When the switch capacitor circuit works in the second state, the voltage of the third node is 0 and the voltage of the fourth node is the output voltage Vvo. By setting the second auxiliary circuit 32 in the switch capacitor circuit SC, the voltage conversion of the third node A3 and the fourth node A4 can be realized to realize the pull-down of Vvo and the pull-up of 0. For example, when the voltage of the third node A3 is Vvo and the voltage of the fourth node A4 is 0, after the voltage conversion of the third node A3 and the fourth node A4, the voltage of the third node A3 becomes less than Vvo and the voltage of the fourth node A4 becomes greater than 0. By changing the voltages of the third node A3 and the fourth node A4, the voltage difference across some transistors in the second-stage switch network 20A and the second-stage switch network 20B can be changed, so that the "shock" current of the some transistors in the opening moment is reduced, the opening loss of the switch capacitor circuit SC is reduced, and the efficiency and frequency of the switch capacitor circuit SC are improved. After the frequency of the switch capacitor circuit SC is improved, the requirement for the capacitance value of the capacitor in the switch capacitor circuit SC can be reduced, and the area occupied by the switch capacitor circuit SC can be reduced. Moreover, after the voltages of the third node A3 and the fourth node A4 are converted, the voltage change rate (dv / dt) of the third node A3 and the fourth node A4 can be reduced, and the electromagnetic interference can be effectively reduced. In addition, the third node A3 is coupled with the first-phase switch capacitor sub-circuit SC1 and the second-phase switch capacitor sub-circuit SC2 respectively, and the fourth node A4 is coupled with the first-phase switch capacitor sub-circuit SC1 and the second-phase switch capacitor sub-circuit SC2 respectively. That is, the first-phase switch capacitor sub-circuit SC1 and the second-phase switch capacitor sub-circuit SC2 share the second auxiliary circuit 32, so that the structure of the switch capacitor circuit SC can be simplified.

[0121] In some embodiments, the first auxiliary circuit 31 is configured to exchange the voltage of the third node A3 and the voltage of the fourth node A4 during the dead time period of the switch capacitor circuit SC.

[0122] FIG. 7A is a topological schematic diagram of a second auxiliary circuit 32 provided by the embodiments of the present application, FIG. 7B is a schematic diagram of a circuit control signal and the corresponding current and voltage waveform provided by the embodiments of the present application, and FIG. 7C is a topological schematic diagram of a resonant network provided by the embodiments of the present application.

[0123] In some embodiments, as shown in FIG. 7A, the second auxiliary circuit 32 includes a first switch tube T1, a second switch tube T2, a third inductor L3, a third switch tube T3, and a fourth switch tube T4. The first switch tube T1, the third inductor L3, and the second switch tube T2 are coupled in series between a third node A3 and a fourth node A4 in sequence.

[0124] The first switch tube T1 and the second switch tube T2 can be a P-type transistor, an N-type transistor, an insulated gate bipolar transistor (IGBT), a mlos controlled (MCT), a gate turn-off thyristor (GTO), a bipolar junction transistor (BJT), a gallium nitride (GaN) device, or the like.

[0125] One end of the first switch tube T1 is coupled to the third node A3, the other end of the first switch tube T1 is coupled to one end of the third inductor L3, the other end of the third inductor L3 is coupled to one end of the second switch tube T2, and the other end of the second switch tube T2 is coupled to the fourth node A4.

[0126] The third switch tube T3 and the fourth switch tube T4 can be a P-type transistor, an N-type transistor, an IGBT, an MCT, a GTO, a BJT, a diode, or the like.

[0127] The third switch tube T3 is coupled between one end of the third inductor L3 toward the first switch tube T1 and a reference ground voltage terminal GND, and the fourth switch tube T4 is coupled between one end of the third inductor L3 toward the second switch tube T2 and the reference ground voltage terminal GND.

[0128] As shown in FIG. 7B, during the t0-t1 period, the first phase switching capacitor sub-circuit SC1 enters the first mode shown in FIG. 4A, and the first transistor Q1A, the third transistor Q3A, the sixth transistor Q6A, the eighth transistor Q8A, and the ninth transistor Q9A are turned on. The second phase switching capacitor sub-circuit SC2 enters the second mode shown in FIG. 5A, and the second transistor Q2B, the fourth transistor Q4B, the fifth transistor Q5B, the seventh transistor Q7B, and the tenth transistor Q10B are turned on. The voltage of the third node A3 is Vvo, and the voltage of the fourth node A4 is 0. The second switch tube T2 and the third switch tube T3 are turned on, the voltage across the third inductor L3 is 0, and the current flowing through the third inductor L3 is 0.

[0129] In the period of t1-t2, the first phase switching capacitor sub-circuit SC1 and the second phase switching capacitor sub-circuit SC2 enter the dead zone period, all the transistors in the first phase switching capacitor sub-circuit SC1 and the second phase switching capacitor sub-circuit SC2 are in the off state, and the first switch T1 and the second switch T2 are turned on, as shown in FIG. 7C, so that the third inductor L3, the parasitic capacitance Coss of the fourth transistor Q4A and the parasitic capacitance Coss of the eighth transistor Q8B form a resonance network. If the dead zone period is exactly equal to half of the resonance period of the above resonance network, the inductor current iL will start to resonate from 0 and return to 0 again, at which time the voltage of the parasitic capacitance Coss of the fourth transistor Q4A and the parasitic capacitance Coss of the eighth transistor Q8B are exchanged, and the voltages of the third node A3 and the fourth node A4 are exchanged. The voltage of the third node A3 decreases from Vvo to 0, and the voltage of the fourth node A4 increases from 0 to Vvo.

[0130] At the moment t2, the first phase switching capacitor sub-circuit SC1 enters the second mode shown in FIG. 5A, and the second transistor Q2A, the fourth transistor Q4A, the fifth transistor Q5A, the seventh transistor Q7A and the tenth transistor Q10A of the first phase switching capacitor sub-circuit SC1 are turned on. The second phase switching capacitor sub-circuit SC2 enters the first mode shown in FIG. 4A, and the first transistor Q1B, the third transistor Q3B, the sixth transistor Q6B, the eighth transistor Q8B and the ninth transistor Q9B of the second phase switching capacitor sub-circuit SC2 are turned on.

[0131] The voltage of the third node A3 decreases from Vvo to 0, which can make the second transistor Q2A and the fourth transistor Q4A of the first phase switching capacitor sub-circuit SC1 achieve zero-voltage switching (ZVS), and the sixth transistor Q6B and the eighth transistor Q8B of the second phase switching capacitor sub-circuit SC2 achieve zero-voltage switching. The voltage of the fourth node A4 increases from 0 to Vvo, which can make the seventh transistor Q7A of the first phase switching capacitor sub-circuit SC1 and the third transistor Q3B of the second phase switching capacitor sub-circuit SC2 achieve zero-voltage switching.

[0132] In the period of t2-t3, the first phase switching capacitor sub-circuit SC1 enters the second mode shown in FIG. 5A, and the second transistor Q2A, the fourth transistor Q4A, the fifth transistor Q5A, the seventh transistor Q7A and the tenth transistor Q10A. The second phase switching capacitor sub-circuit SC2 enters the first mode shown in FIG. 4A, and the first transistor Q1B, the third transistor Q3B, the sixth transistor Q6B, the eighth transistor Q8B and the ninth transistor Q9B are turned on. The voltage of the third node A3 is 0, and the voltage of the fourth node A4 is Vvo. The first switch T1 and the fourth switch T4 are turned on, the voltage across the third inductor L3 is 0, and the current flowing through the third inductor L3 is 0.

[0133] In the period of t3-t4, all the transistors in the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are in the off state, and the first switch T1 and the second switch T2 are in the on state, as shown in FIG. 7C, so that the third inductor L3, the parasitic capacitance Coss of the fourth transistor Q4A and the parasitic capacitance Coss of the eighth transistor Q8B form a resonance network. If the dead time period is equal to half of the resonance period of the resonance network, the inductor current iL will start from 0, resonate and return to 0, at which time the voltage of the parasitic capacitance Coss of the fourth transistor Q4A and the parasitic capacitance Coss of the eighth transistor Q8B are exchanged, and the voltage of the third node A3 and the fourth node A4 are exchanged. The voltage of the third node A3 rises from 0 to Vvo, and the voltage of the fourth node A4 falls from Vvo to 0.

[0134] At the moment t4, the first phase switched capacitor sub-circuit SC1 enters the first mode shown in FIG. 4A, and the first transistor Q1A, the third transistor Q3A, the sixth transistor Q6A, the eighth transistor Q8A and the ninth transistor Q9A are turned on. The second phase switched capacitor sub-circuit SC2 enters the second mode shown in FIG. 5A, and the second transistor Q2B, the fourth transistor Q4B, the fifth transistor Q5B, the seventh transistor Q7B and the tenth transistor Q10B are turned on.

[0135] The voltage of the third node A3 rises from 0 to Vvo, so that the third transistor Q3A of the first phase switched capacitor sub-circuit SC1 and the seventh transistor Q7B of the second phase switched capacitor sub-circuit SC2 can be turned on with zero voltage. The voltage of the fourth node A4 falls from Vvo to 0, so that the sixth transistor Q6A and the eighth transistor Q8A of the first phase switched capacitor sub-circuit SC1 and the second transistor Q2B and the fourth transistor Q4B of the second phase switched capacitor sub-circuit SC2 can be turned on with zero voltage.

[0136] By setting the second auxiliary circuit 32 in the switched capacitor circuit SC, the zero voltage turn-on of some transistors in the second stage switching network 20A and the second stage switching network 20B can be realized, so as to reduce the “shock” current of some transistors at the moment of turn-on and reduce the turn-on loss of some transistors. In addition, the third switch T3 and the fourth switch T4 in the second auxiliary circuit 32 can function as a freewheeling device. When the current on the third inductor L3 is not resonated to 0, the current on the third inductor L3 can be freewheeled to the reference ground voltage terminal GND, so that the second auxiliary circuit 32 can still operate safely in the presence of errors.

[0137] FIG. 8 is a topological schematic diagram of another second auxiliary circuit 32 provided by an embodiment of the present application.

[0138] In some other embodiments, as shown in FIG. 8, the second auxiliary circuit 32 can also include only the first switch tube T1, the second switch tube T2, and the third inductor L3, and not include the third switch tube T3 and the fourth switch tube T4.

[0139] The principle of the second auxiliary circuit 32 shown in FIG. 8 is the same as that of the second auxiliary circuit 32 shown in FIG. 7A, and reference can be made to the above description.

[0140] FIG. 9A is a schematic diagram of another topology of a second auxiliary circuit provided by embodiments of the present application, and FIG. 9B is a schematic diagram of another circuit control signal and corresponding current and voltage waveforms provided by embodiments of the present application.

[0141] In some other embodiments, as shown in FIG. 9A, the second auxiliary circuit 32 includes the first inductor L1, the fourth capacitor C4, the second inductor L2, and the fifth capacitor C5. The first inductor L1, the fourth capacitor C4, the second inductor L2, and the fifth capacitor C5 are coupled in series between the third node A3 and the fourth node A4, and one end of the second inductor L2 towards the fourth capacitor C4 is further coupled with the reference ground voltage terminal GND.

[0142] As shown in FIG. 9B, in the period of t0-t1, the first phase switched capacitor sub-circuit SC1 enters the first mode shown in FIG. 4A, and the first transistor Q1A, the third transistor Q3A, the sixth transistor Q6A, the eighth transistor Q8A, and the ninth transistor Q9A are turned on. The second phase switched capacitor sub-circuit SC2 enters the second mode shown in FIG. 5A, and the second transistor Q2B, the fourth transistor Q4B, the fifth transistor Q5B, the seventh transistor Q7B, and the tenth transistor Q10B are turned on. The voltage at the third node A3 is Vvo, and the voltage at the fourth node A4 is 0.

[0143] In the period of t1-t2, the dead zone period is entered, and all the transistors in the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are turned off, and the first inductor L1 forms a resonance network with the fourth capacitor C4 and the reference ground voltage terminal GND. The voltage at the third node A3 and the reference ground voltage terminal GND are communicated, the voltage at the third node A3 decreases from Vvo to 0, and the voltage at the fourth node A4 remains unchanged at 0.

[0144] At the time t2, the first phase switched capacitor sub-circuit SC1 enters the second mode shown in FIG. 5A, and the second phase switched capacitor sub-circuit SC2 enters the first mode shown in FIG. 4A. The voltage at the third node A3 decreases from Vvo to 0, which can reduce the voltage difference across the second transistor Q2A and the fourth transistor Q4A of the first phase switched capacitor sub-circuit SC1.

[0145] In the period of t2-t3, the first phase switched capacitor sub-circuit SC1 enters the second mode shown in Fig. 5A, and the second phase switched capacitor sub-circuit SC2 enters the first mode shown in Fig. 4A. The voltage of the third node A3 is 0, and the voltage of the fourth node A4 is Vvo.

[0146] In the period of t3-t4, a dead zone period is entered, all the transistors in the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are in the off state, and the second inductor L2 forms a resonance network with the fifth capacitor C5 and the reference ground voltage terminal GND. The voltage of the fourth node A4 and the reference ground voltage terminal GND are communicated, the voltage of the fourth node A4 decreases from Vvo to 0, and the voltage of the third node A3 remains unchanged, still being 0.

[0147] At the moment t4, the first phase switched capacitor sub-circuit SC1 enters the first mode shown in Fig. 4A, and the second phase switched capacitor sub-circuit SC2 enters the second mode shown in Fig. 5A. The voltage of the fourth node A4 decreases from Vvo to 0, which can reduce the voltage difference between the second transistor Q2B and the fourth transistor Q4B of the second phase switched capacitor sub-circuit SC2.

[0148] The second auxiliary circuit 32 only includes capacitors and inductors, and does not need to change the transistor topology of the switched capacitor circuit SC, and is easy to implement.

[0149] Fig. 10A is a schematic diagram of another topology of a second auxiliary circuit provided in an embodiment of the present application, and Fig. 10B is a schematic diagram of another circuit control signal and corresponding current and voltage waveforms provided in an embodiment of the present application.

[0150] In some other embodiments, the second auxiliary circuit 32 is used to communicate the third node A3 and the fourth node A4 in the dead zone period of the switched capacitor circuit SC, and realize the mutual conversion of the voltages of the third node A3 and the fourth node A4.

[0151] For example, as shown in Fig. 10A, the second auxiliary circuit 32 includes a bidirectional switch circuit M, and the bidirectional switch circuit M is coupled between the third node A3 and the fourth node A4.

[0152] The bidirectional switch circuit M includes two transistors in series, for example, or the bidirectional switch circuit M includes a bidirectional switch circuit tube.

[0153] As shown in Fig. 10B, in the period of t0-t1, the first phase switched capacitor sub-circuit SC1 enters the first mode shown in Fig. 4A, and the second phase switched capacitor sub-circuit SC2 enters the second mode shown in Fig. 5A. The voltage of the third node A3 is Vvo, and the voltage of the fourth node A4 is 0.

[0154] In the period of t1-t2, all the transistors in the first phase switched-capacitor sub-circuit SC1 and the second phase switched-capacitor sub-circuit SC2 are in the off state, and the bidirectional switch circuit M is in the on state. The voltages of the third node A3 and the fourth node A4 are interchanged, the voltage of the third node A3 decreases from Vvo to 0.5Vvo, and the voltage of the fourth node A4 increases from 0 to 0.5Vvo.

[0155] At the moment of t2, the first phase switched-capacitor sub-circuit SC1 enters the second mode shown in Fig. 5A, and the second phase switched-capacitor sub-circuit SC2 enters the first mode shown in Fig. 4A. The voltage of the third node A3 decreases from Vvo to 0.5Vvo, which can reduce the voltage difference between the second transistor Q2A and the fourth transistor Q4A in the first phase switched-capacitor sub-circuit SC1. The voltage of the fourth node A4 increases from 0 to 0.5Vvo, which can reduce the voltage difference between the seventh transistor Q7A in the first phase switched-capacitor sub-circuit SC1 and the third transistor Q3B in the second phase switched-capacitor sub-circuit SC2.

[0156] In the period of t2-t3, the first phase switched-capacitor sub-circuit SC1 enters the second mode shown in Fig. 5A, and the second phase switched-capacitor sub-circuit SC2 enters the first mode shown in Fig. 4A. The voltage of the third node A3 is 0, and the voltage of the fourth node A4 is Vvo. In the period of t3-t4, all the transistors in the first phase switched-capacitor sub-circuit SC1 and the second phase switched-capacitor sub-circuit SC2 are in the off state, and the bidirectional switch circuit M is in the on state. The voltages of the third node A3 and the fourth node A4 are interchanged, the voltage of the third node A3 increases from 0 to 0.5Vvo, and the voltage of the fourth node A4 decreases from Vvo to 0.5Vvo.

[0157] At the moment of t4, the first phase switched-capacitor sub-circuit SC1 enters the first mode shown in Fig. 4A, and the second phase switched-capacitor sub-circuit SC2 enters the second mode shown in Fig. 5A. The voltage of the third node A3 increases from 0 to 0.5Vvo, which can reduce the voltage difference between the third transistor Q3A in the first phase switched-capacitor sub-circuit SC1 and the seventh transistor Q7B in the second phase switched-capacitor sub-circuit SC2. The voltage of the fourth node A4 decreases from Vvo to 0.5Vvo, which can reduce the voltage difference between the sixth transistor Q6A and the eighth transistor Q8A in the first phase switched-capacitor sub-circuit SC1 and between the second transistor Q2B and the fourth transistor Q4B in the second phase switched-capacitor sub-circuit SC2.

[0158] The second auxiliary circuit 32 only includes the bidirectional switch circuit M, and does not include a capacitor and an inductor, so the process is simple and easy to implement.

[0159] In other embodiments, as shown in Fig. 6A, the switched-capacitor circuit SC includes the first auxiliary circuit 31.

[0160] The first auxiliary circuit 31 is coupled between the first node Al and the second node A2, and is configured to convert the voltage of the first node Al and the voltage of the second node A2 during the period when both the first phase switched-capacitor sub-circuit SCI and the second phase switched-capacitor sub-circuit SC2 are off (e.g. the dead zone period as referred to in the art). The first node Al is coupled to the negative terminal of the first capacitor Cf1A of the first phase switched-capacitor sub-circuit SCI, and the second node A2 is coupled to the negative terminal of the first capacitor Cf1B of the second phase switched-capacitor sub-circuit SC2.

[0161] The structure and principle of the first auxiliary circuit 31 can refer to the above description of the second auxiliary circuit 32, and the main difference is that the second auxiliary circuit 32 is coupled between the third node A3 and the fourth node A4, while the first auxiliary circuit 31 is coupled between the first node Al and the second node A2.

[0162] During the period of t0-t1, the first phase switched-capacitor sub-circuit SCI enters the first mode shown in FIG. 4A, and the first transistor Q1A, the third transistor Q3A, the sixth transistor Q6A, the eighth transistor Q8A and the ninth transistor Q9A are turned on. The second phase switched-capacitor sub-circuit SC2 enters the second mode shown in FIG. 5A, and the second transistor Q2B, the fourth transistor Q4B, the fifth transistor Q5B, the seventh transistor Q7B and the tenth transistor Q10B are turned on. As shown in FIG. 7B, the voltage of the first node Al is 2Vvo, and the voltage of the second node A2 is 0.

[0163] During the period of t1-t2, the dead zone period is entered, and all the transistors in the first phase switched-capacitor sub-circuit SCI and the second phase switched-capacitor sub-circuit SC2 are in the off state, the first auxiliary circuit 31 is turned on, and the voltages of the first node Al and the second node A2 are exchanged with each other. As shown in FIG. 7B, the voltage of the first node Al decreases from 2Vvo to 0, and the voltage of the second node A2 increases from 0 to 2Vvo.

[0164] At time t2, the first phase switched-capacitor sub-circuit SCI enters the second mode shown in FIG. 5A, and the second transistor Q2A, the fourth transistor Q4A, the fifth transistor Q5A, the seventh transistor Q7A and the tenth transistor Q10A of the first phase switched-capacitor sub-circuit SCI are turned on. The second phase switched-capacitor sub-circuit SC2 enters the first mode shown in FIG. 4A, and the first transistor Q1B, the third transistor Q3B, the sixth transistor Q6B, the eighth transistor Q8B and the ninth transistor Q9B of the second phase switched-capacitor sub-circuit SC2 are turned on.

[0165] The voltage of the first node Al decreases from 2Vvo to 0, which can make the fifth transistor Q5A and the tenth transistor Q10A of the first-phase switched-capacitor sub-circuit SC1 realize zero-voltage turn-on. The voltage of the second node A2 increases from 0 to 2Vvo, which can make the ninth transistor Q9B and the first transistor Q1B of the second-phase switched-capacitor sub-circuit SC2 realize zero-voltage turn-on.

[0166] In the t2-t3 period, the first-phase switched-capacitor sub-circuit SC1 enters the second mode shown in FIG. 5A, and the second transistor Q2A, the fourth transistor Q4A, the fifth transistor Q5A, the seventh transistor Q7A and the tenth transistor Q10A are turned on. The second-phase switched-capacitor sub-circuit SC2 enters the first mode shown in FIG. 4A, and the first transistor Q1B, the third transistor Q3B, the sixth transistor Q6B, the eighth transistor Q8B and the ninth transistor Q9B are turned on. As shown in FIG. 7B, the voltage of the first node Al is 0, and the voltage of the second node A2 is 2Vvo.

[0167] In the t3-t4 period, the dead zone period is entered, all the transistors in the first-phase switched-capacitor sub-circuit SC1 and the second-phase switched-capacitor sub-circuit SC2 are turned off, the first auxiliary circuit 31 is turned on, and the voltages of the first node Al and the second node A2 are exchanged. As shown in FIG. 7B, the voltage of the first node Al increases from 0 to 2Vvo, and the voltage of the second node A2 decreases from 2Vvo to 0.

[0168] At the t4 moment, the first-phase switched-capacitor sub-circuit SC1 enters the first mode shown in FIG. 4A, and the first transistor Q1A, the third transistor Q3A, the sixth transistor Q6A, the eighth transistor Q8A and the ninth transistor Q9A are turned on. The second-phase switched-capacitor sub-circuit SC2 enters the second mode shown in FIG. 5A, and the second transistor Q2B, the fourth transistor Q4B, the fifth transistor Q5B, the seventh transistor Q7B and the tenth transistor Q10B are turned on.

[0169] The voltage of the first node Al increases from 0 to 2Vvo, which can make the ninth transistor Q9A and the first transistor Q1A of the first-phase switched-capacitor sub-circuit SC1 realize zero-voltage turn-on. The voltage of the second node A2 decreases from 2Vvo to 0, which can make the tenth transistor Q10B and the fifth transistor Q5B of the second-phase switched-capacitor sub-circuit SC2 realize zero-voltage turn-on.

[0170] By setting the first auxiliary circuit 31 in the switched capacitor circuit SC, the "shock" current of the transistors in the first stage switching network 10A and part of the transistors in the second stage switching network 20A in the first phase switched capacitor sub-circuit SC1 at the moment of turning on can be reduced, and the "shock" current of the transistors in the first stage switching network 10B and part of the transistors in the second stage switching network 20B in the second phase switched capacitor sub-circuit SC2 at the moment of turning on can be reduced.

[0171] In the case that the switched capacitor circuit SC simultaneously includes the first auxiliary circuit 31 and the second auxiliary circuit 32, the "shock" current of all the transistors in the first phase switched capacitor sub-circuit SC1 at the moment of turning on can be reduced, and the "shock" current of all the transistors in the second phase switched capacitor sub-circuit SC2 at the moment of turning on can be reduced, further reducing the turn-on loss of the switched capacitor circuit SC, improving the overall efficiency of the switched capacitor circuit SC, and making the electronic device have a faster charging experience or a lower heat generation.

[0172] FIGS. 11A and 11B are schematic diagrams of a topology of a switched capacitor circuit provided by an embodiment of the present application.

[0173] In some embodiments, as shown in FIG. 11A, the switched capacitor circuit includes a plurality of switched capacitor groups coupled in parallel between the input terminal VI and the output terminal VO, and each switched capacitor group includes the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2. In FIG. 11A, two groups of the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are taken as an example for illustration.

[0174] The first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 in the same switched capacitor group are 180° out of phase, the first phase switched capacitor sub-circuit SC1 in different switched capacitor groups are 180° / n out of phase, and the second phase switched capacitor sub-circuit SC2 in different groups are 180° / n out of phase.

[0175] For example, in FIG. 11A, the phase of the first phase switched capacitor sub-circuit SC1 in the left switched capacitor group is 0°, and the phase of the second phase switched capacitor sub-circuit SC2 is 180°. The phase of the first phase switched capacitor sub-circuit SC1 in the right switched capacitor group is 90°, and the phase of the second phase switched capacitor sub-circuit SC2 is 270°.

[0176] For example, a driving period of one switch capacitor group is T, and the driving timing of different switch capacitor groups does not affect each other. The phase of the first phase switch capacitor sub-circuit SC1 in the right switch capacitor group is 180° / n out of phase with the phase of the first phase switch capacitor sub-circuit SC1 in the left switch capacitor group. Then, the driving timing of each transistor of the first phase switch capacitor sub-circuit SC1 in the right switch capacitor group is delayed by ((180° / n) / 360°)*T compared with the driving timing of each transistor of the first phase switch capacitor sub-circuit SC1 in the left switch capacitor group. The phase of the first phase switch capacitor sub-circuit SC1 in the right switch capacitor group is 90° out of phase with the phase of the first phase switch capacitor sub-circuit SC1 in the left switch capacitor group. Then, the driving timing of each transistor of the first phase switch capacitor sub-circuit SC1 in the right switch capacitor group is delayed by 1 / 4T compared with the driving timing of each transistor of the first phase switch capacitor sub-circuit SC1 in the left switch capacitor group.

[0177] Alternatively, for example, as shown in FIG. 11B, the first phase switch capacitor sub-circuit SC1 in the left group operates at a 180° phase, and the first phase switch capacitor sub-circuit SC1 in the right group operates at a 270° phase. The second phase switch capacitor sub-circuit SC2 in the left group operates at a 0° phase, and the second phase switch capacitor sub-circuit SC2 in the right group operates at a 90° phase.

[0178] Each group of the first phase switch capacitor sub-circuit SC1 and the second phase switch capacitor sub-circuit SC2 is correspondingly coupled with a group of the first auxiliary circuit 31 and the second auxiliary circuit 32, or alternatively, the switch capacitor circuit SC includes a plurality of parallel structures shown in FIG. 6A or FIG. 6B.

[0179] By arranging a plurality of groups of the first phase switch capacitor sub-circuit SC1 and the second phase switch capacitor sub-circuit SC2 that are connected in parallel and out of phase in the switch capacitor circuit SC, the ripple of the charging voltage can be reduced, and the stability of the charging voltage can be improved.

[0180] FIG. 12A is a structural diagram of another switch capacitor circuit provided by the embodiments of the present application, and FIG. 12B and FIG. 12C are topological schematic diagrams of another switch capacitor circuit provided by the embodiments of the present application.

[0181] In some embodiments, as shown in FIG. 12A, the first phase switch capacitor sub-circuit SC1 includes a plurality of (for example, N) second switch capacitor networks 2A that are connected in series, and the second phase switch capacitor sub-circuit SC2 includes a plurality of (for example, N) second switch capacitor networks 2B that are connected in series. The switch capacitor circuit SC includes a plurality of second auxiliary circuits 32, and the plurality of second auxiliary circuits 32 are correspondingly coupled with the plurality of second switch capacitor networks 2A and 2B. One second auxiliary circuit 32 is coupled between the third node A3 of each second switch capacitor network 2A and the fourth node A4 of the second switch network 21B.

[0182] For example, the third node A3 is taken as an example, in FIG. 12A, the third node A3 (1) The third node A3 represents the first-stage second switched-capacitor network 2A. The third node A3 (N-1) The third node A3 represents the (N-1)th-stage second switched-capacitor network 2A. The third node A3 (N) The third node A3 represents the Nth-stage second switched-capacitor network 2A. Other labels are also in this manner.

[0183] In some embodiments, as shown in FIG. 12B, the first-stage switching network 10A includes a ninth transistor Q9A and a tenth transistor Q10A. The second-stage switching network 20A in each stage of the second switched-capacitor network 2A includes a first transistor Q1A, a second transistor Q2A, a third transistor Q3A, a fourth transistor Q4A, a fifth transistor Q5A, a sixth transistor Q6A, a seventh transistor Q7A, and an eighth transistor Q8A.

[0184] The first electrode of the ninth transistor Q9A is coupled to the input terminal VI, and the second electrode of the ninth transistor Q9A is coupled to the positive electrode of the first capacitor Cf1A and the first electrode of the fifth transistor Q5A, respectively. The first electrode of the tenth transistor Q10A is coupled to the negative electrode of the first capacitor Cf1A and the first electrode of the first transistor Q1A, respectively, and the second electrode of the tenth transistor Q10A is coupled to the reference ground voltage terminal GND.

[0185] In each stage of the second switched-capacitor network 2A, the first electrode of the fourth transistor Q4A is coupled to the second electrode of the third transistor Q3A, and the second electrode of the fourth transistor Q4A is coupled to the reference ground voltage terminal GND. The first electrode of the eighth transistor Q8A is coupled to the second electrode of the seventh transistor Q7A, and the second electrode of the eighth transistor Q8A is coupled to the reference ground voltage terminal.

[0186] In the first-stage second switched-capacitor network 2A, a first electrode of the first transistor Q1A is coupled to a negative electrode of the first capacitor Cf1A, and a second electrode of the first transistor Q1A is coupled to a first electrode of the second transistor Q2A and a positive electrode of the second capacitor Cf2A, respectively. In the fifth transistor Q5A, a first electrode is coupled to a positive electrode of the first capacitor Cf1A, and a second electrode is coupled to a first electrode of the sixth transistor Q6A and a positive electrode of the third capacitor Cf3A, respectively. In the second-stage second switched-capacitor network 2A other than the first stage, a first electrode of the first transistor Q1A is coupled to a second electrode of the second transistor Q2A in the second-stage second switched-capacitor network 2A of the previous stage, and a second electrode of the first transistor Q1A is coupled to a first electrode of the second transistor Q2A and a positive electrode of the second capacitor Cf2A, respectively. In the fifth transistor Q5A, a first electrode is coupled to a second electrode of the sixth transistor Q6A in the second-stage second switched-capacitor network 2A of the previous stage, and a second electrode is coupled to a first electrode of the sixth transistor Q6A and a positive electrode of the third capacitor Cf3A, respectively.

[0187] In the last-stage second switched-capacitor network 2A, a second electrode of the second transistor Q2A, a first electrode of the third transistor Q3A, a second electrode of the sixth transistor Q6A, and a first electrode of the seventh transistor Q7A are all coupled to the output terminal VO. In the second-stage second switched-capacitor network 2A other than the last stage, a second electrode of the second transistor Q2A is coupled to a first electrode of the seventh transistor Q7A, and a second electrode of the sixth transistor Q6A is coupled to a first electrode of the third transistor Q3A.

[0188] For example, taking the first transistor Q1 as an example, the first transistor Q1A1 represents the first transistor Q1A in the first-stage second switched-capacitor network 2A, and the first transistor Q1AN represents the first transistor Q1A in the Nth-stage second switched-capacitor network 2A. The other notations are also in this manner.

[0189] In some embodiments, as shown in FIG. 12B, the first-stage switching network 10B in the second-phase second switched-capacitor sub-circuit SC2 includes the ninth transistor Q9B and the tenth transistor Q10B, and the second-stage switching network 20B in each stage of the second-stage second switched-capacitor network 2B includes the first transistor Q1B, the second transistor Q2B, the third transistor Q3B, the fourth transistor Q4B, the fifth transistor Q5B, the sixth transistor Q6B, the seventh transistor Q7B, and the eighth transistor Q8B. The connection relationship between the transistors can be referred to the above description about the first-stage switching network 10A and the second-stage switching network 20A in the first-phase second switched-capacitor sub-circuit SC1.

[0190] In some embodiments, as shown in FIG. 12C, the seventh transistor Q7AN in the seventh stage of the second stage switch network 20A in the first phase switch capacitor sub-circuit SC1 and the third transistor Q3BN in the seventh stage of the second stage switch network 20B in the second phase switch capacitor sub-circuit SC2 are the same transistor.

[0191] Alternatively, the eighth transistor Q8AN in the seventh stage of the second stage switch network 20A in the first phase switch capacitor sub-circuit SC1 and the fourth transistor Q4BN in the seventh stage of the second stage switch network 20B in the second phase switch capacitor sub-circuit SC2 are the same transistor.

[0192] Alternatively, the seventh transistor Q7BN in the seventh stage of the second stage switch network 20B in the second phase switch capacitor sub-circuit SC2 and the third transistor Q3AN in the seventh stage of the second stage switch network 20A in the first phase switch capacitor sub-circuit SC1 are the same transistor.

[0193] Alternatively, the eighth transistor Q8BN in the seventh stage of the second stage switch network 20B in the second phase switch capacitor sub-circuit SC2 and the fourth transistor Q4AN in the seventh stage of the second stage switch network 20A in the first phase switch capacitor sub-circuit SC1 are the same transistor.

[0194] In this topology, the number of transistors in the switch capacitor circuit SC can be reduced, and the area occupied by the switch capacitor circuit SC can be reduced.

[0195] By arranging the multi-stage (N-stage) second stage switch capacitor network 2A, 2B in each phase switch capacitor sub-circuit, the ratio of the input voltage and the output voltage of the input terminal VI can be 2 N+1 :1, so as to achieve a high conversion ratio and meet different use requirements. On this basis, the second auxiliary circuit 32 is coupled to each stage of the second stage switch capacitor network 2A, 2B, so as to reduce the “shock” current of the transistors in each stage of the second stage switch capacitor network 2A, 2B at the moment of turning on, so as to reduce the turn-on loss of the transistors.

[0196] In some embodiments, the switch capacitor circuit SC includes multiple groups of the first phase switch capacitor sub-circuit SC1 and the second phase switch capacitor sub-circuit SC2 shown in FIG. 12B or FIG. 12C, so as to reduce the ripple of the charging voltage and improve the stability of the charging voltage.

[0197] FIG. 13 is a schematic diagram of another topology of a switch capacitor circuit provided by the embodiments of the present application.

[0198] The embodiments of the present application also provide a switch capacitor circuit SC, which includes only one phase switch capacitor sub-circuit.

[0199] As shown in FIG. 13, the switched-capacitor circuit SC includes a first switched-capacitor network 1, a third switched-capacitor network 3 coupled in series with N stages, a fourth switched-capacitor network 4 coupled in series with N stages, and a plurality of auxiliary circuits 30.

[0200] The first switched-capacitor network 1 includes a first capacitor Cf1 and a first switch network 11, the first capacitor Cf1 being coupled with the first switch network 11, and the first switch network 11 being configured to adjust the on-off between the first capacitor Cf1 and an input terminal VI.

[0201] For example, the first switch network 11 includes a ninth transistor Q9 and a tenth transistor Q10, the first electrode of the ninth transistor Q9 being coupled with the input terminal VI, the second electrode of the ninth transistor Q9 being coupled with the positive electrode of the first capacitor Cf1 and the first electrode of a fifth transistor Q5 respectively. The first electrode of the tenth transistor Q10 is coupled with the negative electrode of the first capacitor Cf1 and the first electrode of a first transistor Q1 respectively, and the second electrode of the tenth transistor Q10 is coupled with a reference ground voltage terminal GND.

[0202] Each stage of the third switched-capacitor network 3 includes a second capacitor Cf2 and a second switch network 21, the second switch network 21 being coupled with the second capacitor Cf2 and the first switch network 11 respectively, and the second switch network 21 being configured to adjust the series-parallel connection between the second capacitor Cf2 and the first capacitor Cf1. Each stage of the third switched-capacitor network 3 further includes a thirteenth node A13 coupled with the negative electrode of the second capacitor Cf2.

[0203] Each stage of the fourth switched-capacitor network 4 includes a third capacitor Cf3 and a third switch network 22, the third switch network 22 being coupled with the third capacitor Cf3 and the first switch network 11 respectively, and the third switch network 22 being configured to adjust the series-parallel connection between the third capacitor Cf3 and the first capacitor Cf1. Each stage of the fourth switched-capacitor network 4 further includes a fourteenth node A14 coupled with the negative electrode of the third capacitor Cf3.

[0204] Each auxiliary circuit 30 is coupled with one thirteenth node A13 and one fourteenth node A14 respectively, and is configured to convert the voltage of the thirteenth node A13 and the voltage of the fourteenth node A14 during the period when the first switch network 11, the second switch network 21, and the third switch network 22 are all turned off.

[0205] The structure and principle of the auxiliary circuit 30 can refer to the description of the second auxiliary circuit 32 above, which will not be repeated here.

[0206] Taking the first transistor Q1 as an example, the first transistor Q11 represents the first transistor Q1 in the first stage of the third switched-capacitor network 3, and the first transistor Q1 Ndenotes the first transistor Q1 in the Nth stage of the third switched-capacitor network 3, and the other labels are in the same manner.

[0207] The first electrode of the ninth transistor Q9 is coupled with the input terminal VI, and the second electrode of the ninth transistor Q9 is coupled with the positive electrode of the first capacitor Cf1 and the first electrode of the fifth transistor Q51 respectively.

[0208] The first electrode of the tenth transistor Q10 is coupled with the negative electrode of the first capacitor Cf1 and the first electrode of the first transistor Q11 respectively, and the second electrode of the tenth transistor Q10 is coupled with the reference ground voltage terminal GND.

[0209] In the first stage of the second switched-capacitor network 2, the first electrode of the first transistor Q11 is coupled with the negative electrode of the first capacitor Cf1, and the second electrode of the first transistor Q11 is coupled with the first electrode of the second transistor Q21 and the positive electrode of the second capacitor Cf21 respectively. The second electrode of the second transistor Q21 is coupled with the first electrode of the first transistor Q11 in the adjacent stage of the second switched-capacitor network 2. The first electrode of the third transistor Q31 is coupled with the second electrode of the sixth transistor Q61, and the second electrode of the third transistor Q31 is coupled with the negative electrode of the second capacitor Cf21 and the first electrode of the fourth transistor Q41 respectively. The second electrode of the fourth transistor Q41 is coupled with the reference ground voltage terminal GND. The first electrode of the fifth transistor Q51 is coupled with the positive electrode of the first capacitor Cf1, and the second electrode of the fifth transistor Q51 is coupled with the first electrode of the sixth transistor Q61 and the positive electrode of the third capacitor Cf31 respectively. The second electrode of the sixth transistor Q61 is also coupled with the first electrode of the fifth transistor Q51 in the adjacent stage of the second switched-capacitor network 2. The first electrode of the seventh transistor Q71 is coupled with the second electrode of the second transistor Q21, and the second electrode of the seventh transistor Q71 is coupled with the negative electrode of the third capacitor Cf31 and the first electrode of the eighth transistor Q81 respectively. The second electrode of the eighth transistor Q81 is coupled with the reference ground voltage terminal GND.

[0210] In the second switched-capacitor network 2 of the other stages (M>1) except the first stage, the first electrode of the first transistor Q1 M is coupled with the second electrode of the second transistor Q2 M-1 of the upper stage, and the first electrode of the fifth transistor Q5 M is coupled with the second electrode of the sixth transistor Q6 M-1 of the upper stage. The coupling modes of the other transistors are the same as those in the first stage of the second switched-capacitor network 2.

[0211] In the last stage of the second switched-capacitor network 2, the second electrode of the second transistor Q2 N , the first electrode of the third transistor Q3 N , the second electrode of the sixth transistor Q6 N , and the first electrode of the seventh transistor Q7 NThe first poles of the first switch capacitor network and the second switch capacitor network are coupled with the output terminal VO.

[0212] The switch capacitor circuit SC provided by the embodiment of the present application comprises a third switch capacitor network 3 and a fourth switch capacitor network 4, which are coupled in series in multiple stages (N stages), and the ratio of the input voltage of the input terminal VI to the output voltage is 2 N+1 :1, so as to realize high conversion ratio and meet different use requirements. On this basis, the auxiliary circuit 30 is coupled between each of the third switch capacitor network 3 and the fourth switch capacitor network 4, so as to reduce the “shock” current of the transistor in each of the third switch capacitor network 3 and the fourth switch capacitor network 4 at the moment of turning on, and reduce the turn-on loss of the transistor.

[0213] FIGS. 14A and 14B are schematic diagrams of another switch capacitor circuit provided by the embodiment of the present application.

[0214] The embodiment of the present application further provides a switch capacitor circuit SC, as shown in FIG. 14A, which comprises a multi-phase switch capacitor sub-circuit and a first bidirectional switch circuit M1.

[0215] The multi-phase switch capacitor sub-circuit comprises, for example, a first-phase switch capacitor sub-circuit SC1, a second-phase switch capacitor sub-circuit SC2, a third-phase switch capacitor sub-circuit SC3 and a fourth-phase switch capacitor sub-circuit SC4, which are coupled in parallel between the input terminal VI and the output terminal VO. For example, the first-phase switch capacitor sub-circuit SC1 and the second-phase switch capacitor sub-circuit SC2 are out of phase by 180°, the first-phase switch capacitor sub-circuit SC1 and the third-phase switch capacitor sub-circuit SC3 are out of phase by 90°, and the third-phase switch capacitor sub-circuit SC3 and the fourth-phase switch capacitor sub-circuit SC4 are out of phase by 180°. For example, in FIG. 14A, the phase of the first-phase switch capacitor sub-circuit SC1 is 0°, the phase of the second-phase switch capacitor sub-circuit SC2 is 180°, the phase of the third-phase switch capacitor sub-circuit SC3 is 90°, and the phase of the fourth-phase switch capacitor sub-circuit SC4 is 270°. Of course, FIG. 14A is only an example and is not limited in any way.

[0216] For example, the first-phase switch capacitor sub-circuit SC1, the second-phase switch capacitor sub-circuit SC2, the third-phase switch capacitor sub-circuit SC3 and the fourth-phase switch capacitor sub-circuit SC4 are respectively the same as the structure of the switch capacitor circuit SC shown in FIG. 3.

[0217] In some embodiments, the first-phase switched-capacitor sub-circuit SC1 includes a first switched-capacitor network 1A and a second switched-capacitor network 2A, the first switched-capacitor network 1A includes a first capacitor Cf1A and a first-stage switch network 10A, and the second switched-capacitor network 2A includes a second capacitor Cf2A, a third capacitor Cf3A, and a second-stage switch network 20A. The first-stage switch network 10A is coupled to the input terminal VI and the second-stage switch network 20A, respectively, and the second-stage switch network 20A is coupled to the output terminal VO. The first capacitor Cf1A is coupled to the first-stage switch network 10A, and the first-stage switch network 10A is configured to adjust the connection between the first capacitor Cf1A and the input terminal VI. The second-stage switch network 20A is coupled to the first capacitor Cf1A, the second capacitor Cf2A, and the third capacitor Cf3A, respectively, and the second-stage switch network 20A is configured to adjust the series-parallel connection among the third capacitor Cf3A, the second capacitor Cf2A, and the first capacitor Cf1A. The first-stage switch network 10A includes, for example, the first switch network described above, and the second-stage switch network 20A includes, for example, the second switch network 21 and the third switch network 22 described above.

[0218] The second-phase switched-capacitor sub-circuit SC2 includes a first switched-capacitor network 1B and a second switched-capacitor network 2B, the first switched-capacitor network 1B includes a first capacitor Cf1B and a first-stage switch network 10B, and the second switched-capacitor network 2B includes a second capacitor Cf2B, a third capacitor Cf3B, and a second-stage switch network 20B. The first-stage switch network 10B is coupled to the input terminal VI and the second-stage switch network 20B, respectively, and the second-stage switch network 20B is coupled to the output terminal VO. The first capacitor Cf1B is coupled to the first-stage switch network 10B, and the first-stage switch network 10B is configured to adjust the connection between the first capacitor Cf1B and the input terminal VI. The second-stage switch network 20B is coupled to the first capacitor Cf1B, the second capacitor Cf2B, and the third capacitor Cf3B, respectively, and the second-stage switch network 20B is configured to adjust the series-parallel connection among the third capacitor Cf3B, the second capacitor Cf2B, and the first capacitor Cf1B. The first-stage switch network 10B includes, for example, the first switch network described above, and the second-stage switch network 20B includes, for example, the second switch network 21 and the third switch network 22 described above.

[0219] The third-phase switched-capacitor sub-circuit SC3 includes a first switched-capacitor network 1C and a second switched-capacitor network 2C, the first switched-capacitor network 1C includes a first capacitor Cf1C and a first-stage switch network 10C, and the second switched-capacitor network 2C includes a second capacitor Cf2C, a third capacitor Cf3C, and a second-stage switch network 20C; the first-stage switch network 10C is coupled with the input terminal VI and the second-stage switch network 20C respectively, and the second-stage switch network 20C is coupled with the output terminal VO. The first capacitor Cf1C is coupled with the first-stage switch network 10C, and the first-stage switch network 10C is configured to adjust the on-off relationship between the first capacitor Cf1C and the input terminal VI. The second-stage switch network 20C is coupled with the first capacitor Cf1C, the second capacitor Cf2C, and the third capacitor Cf3C respectively, and the second-stage switch network 20C is configured to adjust the series-parallel relationship among the third capacitor Cf3C, the second capacitor Cf2C, and the first capacitor Cf1C. The first-stage switch network 10C includes, for example, the first switch network described above, and the second-stage switch network 20C includes, for example, the second switch network 21 and the third switch network 22 described above.

[0220] The fourth-phase switched-capacitor sub-circuit SC4 includes a first switched-capacitor network 1D and a second switched-capacitor network 2D, the first switched-capacitor network 1D includes a first capacitor Cf1D and a first-stage switch network 10D, and the second switched-capacitor network 2D includes a second capacitor Cf2D, a third capacitor Cf3D, and a second-stage switch network 20D; the first-stage switch network 10D is coupled with the input terminal VI and the second-stage switch network 20D respectively, and the second-stage switch network 20D is coupled with the output terminal VO. The first capacitor Cf1D is coupled with the first-stage switch network 10D, and the first-stage switch network 10D is configured to adjust the on-off relationship between the first capacitor Cf1D and the input terminal VI. The second-stage switch network 20D is coupled with the first capacitor Cf1D, the second capacitor Cf2D, and the third capacitor Cf3D respectively, and the second-stage switch network 20D is configured to adjust the series-parallel relationship among the third capacitor Cf3D, the second capacitor Cf2D, and the first capacitor Cf1D. The first-stage switch network 10D includes, for example, the first switch network described above, and the second-stage switch network 20D includes, for example, the second switch network 21 and the third switch network 22 described above.

[0221] For example, as shown in FIG. 14A, the second-stage switch network 20A of the first-phase switched-capacitor sub-circuit SC1 includes a first transistor Q1A, a second transistor Q2A, a third transistor Q3A, a fourth transistor Q4A, a fifth transistor Q5A, a sixth transistor Q6A, a seventh transistor Q7A, and an eighth transistor Q8A, and the first-stage switch network 10A includes a ninth transistor Q9A and a tenth transistor Q10A. The connection relationship of each transistor can refer to the description about FIG. 3 above.

[0222] The second-stage switch network 20B of the second-phase switched-capacitor subcircuit SC2 includes a first transistor Q1B, a second transistor Q2B, a third transistor Q3B, a fourth transistor Q4B, a fifth transistor Q5B, a sixth transistor Q6B, a seventh transistor Q7B, and an eighth transistor Q8B, and the first-stage switch network 10B includes a ninth transistor Q9B and a tenth transistor Q10B. The connection relationship of each transistor can refer to the description of FIG. 3.

[0223] The second-stage switch network 20C of the third-phase switched-capacitor subcircuit SC3 includes a first transistor Q1C, a second transistor Q2C, a third transistor Q3C, a fourth transistor Q4C, a fifth transistor Q5C, a sixth transistor Q6C, a seventh transistor Q7C, and an eighth transistor Q8C, and the first-stage switch network 10C includes a ninth transistor Q9C and a tenth transistor Q10C. The connection relationship of each transistor can refer to the description of FIG. 3.

[0224] The second-stage switch network 20D of the fourth-phase switched-capacitor subcircuit SC4 includes a first transistor Q1D, a second transistor Q2D, a third transistor Q3D, a fourth transistor Q4D, a fifth transistor Q5D, a sixth transistor Q6D, a seventh transistor Q7D, and an eighth transistor Q8D, and the first-stage switch network 10D includes a ninth transistor Q9D and a tenth transistor Q10D. The connection relationship of each transistor can refer to the description of FIG. 3.

[0225] Alternatively, as shown in FIG. 14B, the seventh transistor Q7A in the first-phase switched-capacitor subcircuit SC1 and the third transistor Q3B in the second-phase switched-capacitor subcircuit SC2 are the same transistor. Alternatively, the eighth transistor Q8A in the first-phase switched-capacitor subcircuit SC1 and the fourth transistor Q4B in the second-phase switched-capacitor subcircuit SC2 are the same transistor.

[0226] Alternatively, the seventh transistor Q7B in the second-phase switched-capacitor subcircuit SC2 and the third transistor Q3A in the first-phase switched-capacitor subcircuit SC1 are the same transistor. Alternatively, the eighth transistor Q8B in the second-phase switched-capacitor subcircuit SC2 and the fourth transistor Q4A in the first-phase switched-capacitor subcircuit SC1 are the same transistor.

[0227] Alternatively, the seventh transistor Q7C in the third-phase switched-capacitor subcircuit SC3 and the third transistor Q3D in the fourth-phase switched-capacitor subcircuit SC4 are the same transistor. Alternatively, the eighth transistor Q8C in the third-phase switched-capacitor subcircuit SC3 and the fourth transistor Q4D in the fourth-phase switched-capacitor subcircuit SC4 are the same transistor.

[0228] Alternatively, the seventh transistor Q7D in the fourth phase switched-capacitor sub-circuit SC4 and the third transistor Q3C in the third phase switched-capacitor sub-circuit SC3 are the same transistor. Alternatively, the eighth transistor Q8D in the fourth phase switched-capacitor sub-circuit SC4 and the fourth transistor Q4C in the third phase switched-capacitor sub-circuit SC3 are the same transistor.

[0229] In this topology, the number of transistors in the switched-capacitor circuit SC can be reduced, and the area occupied by the switched-capacitor circuit SC can be reduced.

[0230] The negative terminal of the second capacitor Cf2 of the first phase switched-capacitor sub-circuit SC1 and the negative terminal of the third capacitor Cf3 of the second phase switched-capacitor sub-circuit SC2 are coupled to the fifth point A5, and the negative terminal of the third capacitor Cf3 of the third phase switched-capacitor sub-circuit SC3 and the negative terminal of the second capacitor Cf2 of the fourth phase switched-capacitor sub-circuit SC4 are coupled to the sixth point A6. The coupling positions of the fifth point A5 and the sixth point A6 in FIG. 14A are only one example, and the positions of the seventh point A7 and the eighth point A8 in FIG. 14A can also be used as the fifth point A5 and the sixth point A6.

[0231] The first bidirectional switch circuit M1 is connected between the fifth point A5 and the sixth point A6, and is used to clamp the voltage of the sixth point A6 to the fifth point A5 during the period when the first phase switched-capacitor sub-circuit SC1 and the second phase switched-capacitor sub-circuit SC2 are both turned off. The first bidirectional switch circuit M1 is also used to clamp the voltage of the fifth point A5 to the sixth point A6 during the period (dead zone period) when the third phase switched-capacitor sub-circuit SC3 and the fourth phase switched-capacitor sub-circuit SC4 are both turned off.

[0232] The first bidirectional switch circuit M1 can be, for example, a bidirectional switch circuit tube, or include two unidirectionally conductive transistors, and the embodiments of the present application do not limit this.

[0233] The third phase switched-capacitor sub-circuit SC3 and the first phase switched-capacitor sub-circuit SC1 are out of phase by 90°, and the fourth phase switched-capacitor sub-circuit SC4 and the second phase switched-capacitor sub-circuit SC2 are out of phase by 90°. During the period when the first phase switched-capacitor sub-circuit SC1 and the second phase switched-capacitor sub-circuit SC2 are both turned off, all the transistors in the first phase switched-capacitor sub-circuit SC1 and the second phase switched-capacitor sub-circuit SC2 are turned off, and the third phase switched-capacitor sub-circuit SC3 and the fourth phase switched-capacitor sub-circuit SC4 enter the first mode in FIG. 4A or the second mode in FIG. 5A.

[0234] When the third phase switched capacitor sub-circuit SC3 and the fourth phase switched capacitor sub-circuit SC4 enter the first mode in FIG. 4A, the eighth transistor Q8C of the third phase switched capacitor sub-circuit SC3 and the fourth transistor Q4D of the fourth phase switched capacitor sub-circuit SC4 are turned on, the first bidirectional switch circuit M1 is turned on, and the 0 voltage of the sixth point A6 is clamped to the fifth point A5. When the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 enter the first mode in FIG. 4A, the second transistor Q2A, the fourth transistor Q4A and the seventh transistor Q7A in the first phase switched capacitor sub-circuit SC1 and the eighth transistor Q8B, the sixth transistor Q6B and the third transistor Q3B in the second phase switched capacitor sub-circuit SC2 can realize zero voltage turn-on.

[0235] The switched capacitor circuit SC provided by the embodiment of the present application is provided with the first bidirectional switch circuit M1 between the fifth point A5 and the sixth point A6, and the third phase switched capacitor sub-circuit SC3 and the fourth phase switched capacitor sub-circuit SC4 normally work when the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are both turned off. At this time, the voltage of the sixth point A6 can be clamped to the fifth point A5 through the first bidirectional switch circuit M1, the voltage of the fifth point A5 is changed to reduce the voltage difference between the two ends of some transistors in the second stage switch network 20A in the first phase switched capacitor sub-circuit SC1 and the second stage switch network 20B in the second phase switched capacitor sub-circuit SC2, so as to reduce the "impact" current of the transistors at the moment of turn-on and reduce the turn-on loss of the transistors. Moreover, the first bidirectional switch circuit M1 has simple structure and simple process and is easy to realize.

[0236] In some embodiments, as shown in FIG. 14A, the switched capacitor circuit SC further comprises a second bidirectional switch circuit M2.

[0237] The second bidirectional switch circuit M2 is coupled between the seventh point A7 and the eighth point A8, and is used for clamping the voltage of the eighth point A8 to the seventh point A7 in the period when the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are both turned off. The seventh point A7 is coupled with the negative electrode of the third capacitor Cf3 of the first phase switched capacitor sub-circuit SC1 and the negative electrode of the second capacitor Cf2 of the second phase switched capacitor sub-circuit SC2 respectively, and the eighth point A8 is coupled with the negative electrode of the second capacitor Cf2 of the third phase switched capacitor sub-circuit SC3 and the negative electrode of the third capacitor Cf3 of the fourth phase switched capacitor sub-circuit SC4 respectively.

[0238] When the third phase switched capacitor sub-circuit SC3 and the fourth phase switched capacitor sub-circuit SC4 enter the second mode in FIG. 5A, the fourth transistor Q4C and the eighth transistor Q8D of the third phase switched capacitor sub-circuit SC3 are turned on, the second bidirectional switch circuit M2 is turned on, and the Vvo voltage of the eighth point A8 is clamped to the seventh point A7. When the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 enter the second mode in FIG. 5A, the eighth transistor Q8A, the sixth transistor Q6A and the third transistor Q3A in the first phase switched capacitor sub-circuit SC1 and the second transistor Q2B, the fourth transistor Q4B and the seventh transistor Q7B in the second phase switched capacitor sub-circuit SC2 can realize zero voltage turn-on.

[0239] By arranging the second bidirectional switch circuit M2 in the switched capacitor circuit SC, the voltage difference between the two ends of some transistors in the second stage switch network 20A in the first phase switched capacitor sub-circuit SC1 and the second stage switch network 20B in the second phase switched capacitor sub-circuit SC2 can be reduced, so as to reduce the "impact" current of the transistors at the turn-on moment and reduce the turn-on loss of the transistors.

[0240] FIGS. 15A and 15B are schematic diagrams of another switched capacitor circuit according to an embodiment of the present application.

[0241] The embodiment of the present application further provides a switched capacitor circuit SC, as shown in FIGS. 15A and 15B, which comprises a multi-phase switched capacitor sub-circuit and a third bidirectional switch circuit M3. The structure of the multi-phase switched capacitor sub-circuit can refer to the related description of FIGS. 14A and 14B.

[0242] The third bidirectional switch circuit M3 is coupled between the ninth point A9 and the tenth point A10, and is used for clamping the voltage of the tenth point A10 to the ninth point A9 in a period when the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are both turned off. The ninth point A9 is coupled with the negative electrode of the first capacitor Cf1 of the first phase switched capacitor sub-circuit SC1, and the tenth point A10 is coupled with the negative electrode of the first capacitor Cf1 of the third phase switched capacitor sub-circuit SC3.

[0243] When the third phase switched capacitor sub-circuit SC3 enters the first mode in FIG. 4A, the voltage of the tenth point A10 is the input voltage 2Vvo, the third bidirectional switch circuit M3 is turned on, 2Vvo of the tenth point A10 is clamped to the ninth point A9, and when the first phase switched capacitor sub-circuit SC1 enters the first mode in FIG. 4A, the ninth transistor Q9A and the first transistor Q1A can realize zero voltage turn-on.

[0244] When the third phase switched capacitor sub-circuit SC3 enters the second mode in FIG. 5A, the voltage of the tenth point A10 is 0, the third bidirectional switch circuit M3 is turned on, and 0 of the tenth point A10 is clamped to the ninth point A9. When the first phase switched capacitor sub-circuit SC1 enters the second mode in FIG. 5A, zero-voltage turn-on of the tenth transistor Q10A and the fifth transistor Q5A can be realized.

[0245] The switched capacitor circuit SC provided by the embodiment of the present application is configured with the third bidirectional switch circuit M3 between the ninth point A9 and the tenth point A10. In the case that the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are both turned off, the third phase switched capacitor sub-circuit SC3 normally works. At this time, the voltage of the tenth point A10 can be clamped to the ninth point A9 through the third bidirectional switch circuit M3. By changing the voltage of the ninth point A9, the voltage difference between the two ends of the transistor in the first stage switch network 10A in the first phase switched capacitor sub-circuit SC1 can be reduced, so as to reduce the "impact" current of the transistor at the moment of turn-on and reduce the turn-on loss of the transistor. Moreover, the third bidirectional switch circuit M3 has a simple structure and simple process, and is easy to implement.

[0246] In some embodiments, as shown in FIG. 15A, the switched capacitor circuit SC further comprises a fourth bidirectional switch circuit M4.

[0247] The fourth bidirectional switch circuit M4 is coupled between the eleventh point A11 and the twelfth point A12, and is configured to clamp the voltage of the twelfth point A12 to the eleventh point A11 in the period that the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are both turned off. The eleventh point A11 is coupled with the negative electrode of the first capacitor Cf1 of the second phase switched capacitor sub-circuit SC2, and the twelfth point A12 is coupled with the negative electrode of the first capacitor Cf1 of the fourth phase switched capacitor sub-circuit SC4.

[0248] When the fourth phase switched capacitor sub-circuit SC4 enters the first mode in FIG. 5A, the voltage of the twelfth point A12 is 2Vvo, the fourth bidirectional switch circuit M4 is turned on, and 2Vvo of the twelfth point A12 is clamped to the eleventh point A11. When the second phase switched capacitor sub-circuit SC2 enters the first mode in FIG. 4A, zero-voltage turn-on of the ninth transistor Q9B and the first transistor Q1B can be realized.

[0249] When the fourth phase switched capacitor sub-circuit SC4 enters the second mode in FIG. 5A, the voltage of the twelfth point A12 is 0, the fourth bidirectional switch circuit M4 is turned on, and 0 of the twelfth point A12 is clamped to the eleventh point A11. When the second phase switched capacitor sub-circuit SC2 enters the second mode in FIG. 5A, zero-voltage turn-on of the tenth transistor Q10B and the fifth transistor Q5B can be realized.

[0250] The switch capacitor circuit SC provided by the embodiment of the present application is provided with a fourth bidirectional switch circuit M4 between the eleventh point A11 and the twelfth point A12, and the fourth phase switch capacitor sub-circuit SC4 normally works in the case that the first phase switch capacitor sub-circuit SC1 and the second phase switch capacitor sub-circuit SC2 are both off. At this time, the voltage of the twelfth point A12 can be clamped to the eleventh point A11 through the fourth bidirectional switch circuit M4, and the voltage difference between the two ends of the transistor in the first stage switch network 10B in the second phase switch capacitor sub-circuit SC2 can be reduced by changing the voltage of the eleventh point A11, so as to reduce the "shock" current of the transistor at the moment of turning on and reduce the turn-on loss of the transistor. Moreover, the fourth bidirectional switch circuit M4 has a simple structure and simple process and is easy to implement.

[0251] FIG. 16A and FIG. 16B are schematic diagrams of another topology of a switch capacitor circuit provided by the embodiment of the present application.

[0252] In some embodiments, as shown in FIG. 16A and FIG. 16B, the switch capacitor circuit SC includes a multi-phase switch capacitor sub-circuit and one or more of the first bidirectional switch circuit M1, the second bidirectional switch circuit M2, the third bidirectional switch circuit M3 and the fourth bidirectional switch circuit M4. In FIG. 16A and FIG. 16B, the switch capacitor circuit SC is taken as an example including the first bidirectional switch circuit M1, the second bidirectional switch circuit M2, the third bidirectional switch circuit M3 and the fourth bidirectional switch circuit M4, so that each transistor in the switch capacitor circuit SC can realize zero-voltage turn-on, so as to reduce the "shock" current of the transistor at the moment of turning on and reduce the turn-on loss of the transistor.

[0253] FIG. 17 is an architectural diagram of another switch capacitor circuit provided by the embodiment of the present application.

[0254] In some embodiments, as shown in FIG. 17, each phase switch capacitor sub-circuit includes a plurality of (for example, N levels) second switch capacitor networks 2 coupled in series, the switch capacitor circuit SC includes a plurality of first bidirectional switch circuits M1 and / or a plurality of second bidirectional switch circuits M2, the plurality of first bidirectional switch circuits M1 are one-to-one coupled with the plurality of (for example, N levels) second switch capacitor networks 2, and the plurality of second bidirectional switch circuits M2 are one-to-one coupled with the plurality of (for example, N levels) second switch capacitor networks 2.

[0255] The coupling relationship between each first bidirectional switch circuit M1 and each level of second switch capacitor network 2A, 2B, 2C, 2D can refer to the related description about the coupling relationship between the first bidirectional switch circuit M1 and the second switch capacitor network 2A, 2B, 2C, 2D in FIG. 14A. The series connection mode of the second switch capacitor network 2 in each phase switch capacitor sub-circuit can refer to the related description about the series connection mode of the second switch capacitor network 2 in FIG. 12B and FIG. 12C.

[0256] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any change or replacement within the technical scope disclosed by the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A switched-capacitor circuit, characterized by, The switch capacitor circuit comprises at least one switch capacitor group; the switch capacitor group comprises a first auxiliary circuit, a second auxiliary circuit, and the first phase switch capacitor sub-circuit and the second phase switch capacitor sub-circuit which are coupled in parallel between an input end and an output end; The first phase switch capacitor sub-circuit and the second phase switch capacitor sub-circuit respectively comprise a first capacitor, a first stage switch network, and a switch capacitor network, the switch capacitor network comprising a second capacitor, a third capacitor, and a second stage switch network; the first stage switch network is coupled with the input end and the first capacitor respectively, and is used for adjusting the on-off of the first capacitor and the input end; The second stage switch network is coupled with the first capacitor, the second capacitor, and the third capacitor respectively, and is used for adjusting the series-parallel relationship among the first capacitor, the second capacitor, and the third capacitor; The first auxiliary circuit is coupled between a first node and a second node, and is used for converting the voltage of the first node and the voltage of the second node in a period when the first phase switch capacitor sub-circuit and the second phase switch capacitor sub-circuit are both off; the first node is coupled with the negative electrode of the first capacitor of the first phase switch capacitor sub-circuit, and the second node is coupled with the negative electrode of the first capacitor of the second phase switch capacitor sub-circuit; The second auxiliary circuit is coupled between a third node and a fourth node, and is used for converting the voltage of the third node and the voltage of the fourth node in a period when the first phase switch capacitor sub-circuit and the second phase switch capacitor sub-circuit are both off; the third node is coupled with the negative electrode of the second capacitor of the first phase switch capacitor sub-circuit and the negative electrode of the third capacitor of the second phase switch capacitor sub-circuit respectively, and the fourth node is coupled with the negative electrode of the third capacitor of the first phase switch capacitor sub-circuit and the negative electrode of the second capacitor of the second phase switch capacitor sub-circuit respectively.

2. The switched-capacitor circuit of claim 1, wherein, The first auxiliary circuit comprises a first inductor, a fourth capacitor, a second inductor, and a fifth capacitor; The first inductor, the fourth capacitor, the second inductor, and the fifth capacitor are coupled in series between the first node and the second node in sequence; one end of the second inductor towards the fourth capacitor is further coupled with a reference ground voltage end.

3. The switched-capacitor circuit of claim 1, wherein, The first auxiliary circuit comprises a bidirectional switch circuit; The bidirectional switch circuit is coupled between the first node and the second node.

4. The switched-capacitor circuit of claim 1, wherein, The first auxiliary circuit comprises a first switch tube, a second switch tube, and a third inductor; The first switch tube, the third inductor, and the second switch tube are coupled in series between the first node and the second node in sequence.

5. The switched-capacitor circuit of claim 4, wherein, The first auxiliary circuit further comprises a third switch tube and a fourth switch tube; The third switch tube is coupled between one end of the third inductor towards the first switch tube and a reference ground voltage end, and the fourth switch tube is coupled between one end of the third inductor towards the second switch tube and the reference ground voltage end.

6. The switched-capacitor circuit of any of claims 1-5, wherein, The switched-capacitor circuit comprises a plurality of the switched-capacitor groups, and the plurality of the switched-capacitor groups are coupled in parallel between the input terminal and the output terminal.

7. The switched-capacitor circuit of any of claims 1-6, wherein, The first-phase switched-capacitor sub-circuit and the second-phase switched-capacitor sub-circuit each comprise a plurality of the switched-capacitor networks coupled in series, and the switched-capacitor circuit further comprises a plurality of the second auxiliary circuits; the plurality of the second auxiliary circuits are coupled one-to-one with the plurality of the switched-capacitor networks.

8. The switched-capacitor circuit according to any one of claims 1-6, characterized in that, The second-stage switched network comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; a first electrode of the first transistor is coupled with a negative electrode of the first capacitor, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of the second capacitor respectively; a second electrode of the second transistor is coupled with the output terminal and a first electrode of the third transistor respectively; a second electrode of the third transistor is coupled with a negative electrode of the second capacitor and a first electrode of the fourth transistor respectively; a second electrode of the fourth transistor is coupled with a reference ground voltage terminal; a first electrode of the fifth transistor is coupled with a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of the third capacitor respectively; a second electrode of the sixth transistor is coupled with the output terminal and a first electrode of the seventh transistor respectively; a second electrode of the seventh transistor is coupled with a negative electrode of the third capacitor and a first electrode of the eighth transistor respectively; a second electrode of the eighth transistor is coupled with the reference ground voltage terminal; the seventh transistor in the first-phase switched-capacitor sub-circuit and the third transistor in the second-phase switched-capacitor sub-circuit are the same transistor; or, the eighth transistor in the first-phase switched-capacitor sub-circuit and the fourth transistor in the second-phase switched-capacitor sub-circuit are the same transistor.

9. The switched-capacitor circuit of claim 7, wherein, The second-stage switched network in each of the switched-capacitor networks comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; in each of the switched-capacitor networks, a first electrode of the fourth transistor is coupled with a second electrode of the third transistor, and a second electrode of the fourth transistor is coupled with a reference ground voltage terminal; a first electrode of the eighth transistor is coupled with a second electrode of the seventh transistor, and a second electrode of the eighth transistor is coupled with the reference ground voltage terminal; In the first stage of the switched-capacitor network, a first electrode of the first transistor is coupled to a negative electrode of the first capacitor, and a second electrode of the first transistor is coupled to a first electrode of the second transistor and a positive electrode of the second capacitor, respectively; a first electrode of the fifth transistor is coupled to a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled to a first electrode of the sixth transistor and a positive electrode of the third capacitor, respectively; in the switched-capacitor network except the first stage, the first electrode of the first transistor is coupled to a second electrode of the second transistor in the switched-capacitor network of the previous stage, and the second electrode of the first transistor is coupled to the first electrode of the second transistor and the positive electrode of the second capacitor, respectively; the first electrode of the fifth transistor is coupled to a second electrode of the sixth transistor in the switched-capacitor network of the previous stage, and the second electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the positive electrode of the third capacitor, respectively; In the last stage of the switched-capacitor network, the second electrode of the second transistor, the first electrode of the third transistor, the second electrode of the sixth transistor and the first electrode of the seventh transistor are all coupled to the output terminal; in the switched-capacitor network except the last stage, the second electrode of the second transistor is coupled to the first electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled to the first electrode of the third transistor; the seventh transistor of the last stage of the switched-capacitor network in the first phase switched-capacitor sub-circuit and the third transistor of the last stage of the switched-capacitor network in the second phase switched-capacitor sub-circuit are the same transistor; or, the eighth transistor of the last stage of the switched-capacitor network in the first phase switched-capacitor sub-circuit and the fourth transistor of the last stage of the switched-capacitor network in the second phase switched-capacitor sub-circuit are the same transistor.

10. A switched-capacitor circuit, characterized by The switched-capacitor circuit comprises: The first phase switched-capacitor sub-circuit, the second phase switched-capacitor sub-circuit, the third phase switched-capacitor sub-circuit and the fourth phase switched-capacitor sub-circuit are coupled in parallel between the input terminal and the output terminal; the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are out of phase by 180°, the first phase switched-capacitor sub-circuit and the third phase switched-capacitor sub-circuit are out of phase by 90°, and the third phase switched-capacitor sub-circuit and the fourth phase switched-capacitor sub-circuit are out of phase by 180°; The first phase switched-capacitor sub-circuit, the second phase switched-capacitor sub-circuit, the third phase switched-capacitor sub-circuit and the fourth phase switched-capacitor sub-circuit respectively comprise a first capacitor, a first-stage switch network and a switched-capacitor network, the switched-capacitor network comprising a second capacitor, a third capacitor and a second-stage switch network; the first-stage switch network is coupled with the input terminal and the first capacitor respectively, and is used for adjusting the on-off between the first capacitor and the input terminal; the second-stage switch network is coupled with the first capacitor, the second capacitor and the third capacitor respectively, and is used for adjusting the series-parallel relationship between the first capacitor, the second capacitor and the third capacitor; A first bidirectional switch circuit is coupled between a fifth node and a sixth node, and is used for clamping the voltage of the sixth node to the fifth node in a period when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off. The fifth node is coupled with the negative electrode of the second capacitor of the first phase switched-capacitor sub-circuit and the negative electrode of the third capacitor of the second phase switched-capacitor sub-circuit respectively, and the sixth node is coupled with the negative electrode of the third capacitor of the third phase switched-capacitor sub-circuit and the negative electrode of the second capacitor of the fourth phase switched-capacitor sub-circuit respectively.

11. The switched-capacitor circuit of claim 10, wherein, The switched-capacitor circuit further comprises a second bidirectional switch circuit; The second bidirectional switch circuit is coupled between a seventh node and an eighth node, and is used for clamping the voltage of the eighth node to the seventh node in a period when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off. The seventh node is coupled with the negative electrode of the third capacitor of the first phase switched-capacitor sub-circuit and the negative electrode of the second capacitor of the second phase switched-capacitor sub-circuit respectively, and the eighth node is coupled with the negative electrode of the second capacitor of the third phase switched-capacitor sub-circuit and the negative electrode of the third capacitor of the fourth phase switched-capacitor sub-circuit respectively.

12. The switched-capacitor circuit of claim 10 or 11, wherein, The switched-capacitor circuit further comprises a third bidirectional switch circuit; The third bidirectional switch circuit is coupled between a ninth node and a tenth node, and is used for clamping the voltage of the tenth node to the ninth node in a period when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off. The ninth node is coupled with the negative electrode of the first capacitor of the first phase switched-capacitor sub-circuit, and the tenth node is coupled with the negative electrode of the first capacitor of the third phase switched-capacitor sub-circuit.

13. The switched-capacitor circuit of any of claims 10-12, wherein, The switched-capacitor circuit further comprises a fourth bidirectional switch circuit; The fourth bidirectional switch circuit is coupled between an eleventh node and a twelfth node, and is used for clamping the voltage of the twelfth node to the eleventh node in a period when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off. The eleventh node is coupled with the negative electrode of the first capacitor of the second phase switched-capacitor sub-circuit, and the twelfth node is coupled with the negative electrode of the first capacitor of the fourth phase switched-capacitor sub-circuit.

14. The switched-capacitor circuit of any of claims 10-13, wherein, The switch capacitor circuit of each phase comprises the switch capacitor network of multiple stages connected in series, and the switch capacitor circuit comprises multiple first bidirectional switch circuits; the multiple first bidirectional switch circuits are one-to-one coupled with the multiple-stage switch capacitor network.

15. The switched-capacitor circuit of any of claims 10-13, wherein, The second-stage switch network comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; a first electrode of the first transistor is coupled with a negative electrode of the first capacitor, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of the second capacitor respectively; a second electrode of the second transistor is coupled with the output end and a first electrode of the third transistor respectively; a second electrode of the third transistor is coupled with a negative electrode of the second capacitor and a first electrode of the fourth transistor respectively; a second electrode of the fourth transistor is coupled with a reference ground voltage end; a first electrode of the fifth transistor is coupled with a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of the third capacitor respectively; a second electrode of the sixth transistor is coupled with the output end and a first electrode of the seventh transistor respectively; a second electrode of the seventh transistor is coupled with a negative electrode of the third capacitor and a first electrode of the eighth transistor respectively; a second electrode of the eighth transistor is coupled with the reference ground voltage end; the seventh transistor in the first-phase switch capacitor sub-circuit and the third transistor in the second-phase switch capacitor sub-circuit are the same transistor; or the eighth transistor in the first-phase switch capacitor sub-circuit and the fourth transistor in the second-phase switch capacitor sub-circuit are the same transistor.

16. The switch capacitor circuit of claim 14, wherein, the second-stage switch network in each stage of the switch capacitor network comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor respectively; in each stage of the switch capacitor network, a first electrode of the fourth transistor is coupled with a second electrode of the third transistor, and a second electrode of the fourth transistor is coupled with a reference ground voltage end; a first electrode of the eighth transistor is coupled with a second electrode of the seventh transistor, and a second electrode of the eighth transistor is coupled with the reference ground voltage end; In the first stage of the switched capacitor network, a first electrode of the first transistor is coupled with a negative electrode of the first capacitor, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of the second capacitor respectively; a first electrode of the fifth transistor is coupled with a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of the third capacitor respectively; in the switched capacitor network except the first stage, the first electrode of the first transistor is coupled with a second electrode of the second transistor in the switched capacitor network of the previous stage, and the second electrode of the first transistor is coupled with the first electrode of the second transistor and the positive electrode of the second capacitor respectively; the first electrode of the fifth transistor is coupled with a second electrode of the sixth transistor in the switched capacitor network of the previous stage, and the second electrode of the fifth transistor is coupled with the first electrode of the sixth transistor and the positive electrode of the third capacitor respectively; In the last stage of the switched capacitor network, the second electrode of the second transistor, the first electrode of the third transistor, the second electrode of the sixth transistor and the first electrode of the seventh transistor are all coupled with the output terminal; in the switched capacitor network except the last stage, the second electrode of the second transistor is coupled with the first electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled with the first electrode of the third transistor; The seventh transistor of the last stage of the switched capacitor network in the first phase switched capacitor sub-circuit and the third transistor of the last stage of the switched capacitor network in the second phase switched capacitor sub-circuit are the same transistor; or, the eighth transistor of the last stage of the switched capacitor network in the first phase switched capacitor sub-circuit and the fourth transistor of the last stage of the switched capacitor network in the second phase switched capacitor sub-circuit are the same transistor.

17. A switched-capacitor circuit, comprising: The switched capacitor circuit comprises: a first capacitor and a first switch network; the first capacitor is coupled with the first switch network, and the first switch network is used for adjusting the on-off between the first capacitor and an input terminal; a plurality of first switched capacitor networks coupled in series, each of the first switched capacitor networks comprising a second capacitor and a second switch network; the second switch network is coupled with the second capacitor and the first switch network respectively, and the second switch network is used for adjusting the series-parallel connection between the second capacitor and the first capacitor; each of the first switched capacitor networks further comprises a thirteenth node coupled with a negative electrode of the second capacitor; a plurality of second switched capacitor networks coupled in series, each of the second switched capacitor networks comprising a third capacitor and a third switch network; the third switch network is coupled with the third capacitor and the first switch network respectively, and the third switch network is used for adjusting the series-parallel connection between the third capacitor and the first capacitor; each of the second switched capacitor networks further comprises a fourteenth node coupled with a negative electrode of the third capacitor; a plurality of auxiliary circuits, each of the auxiliary circuits coupled with one of the thirteenth nodes and one of the fourteenth nodes, for converting the voltage of the thirteenth node and the voltage of the fourteenth node during a period when the first switch network, the second switch network and the third switch network are all turned off.

18. An electronic device, comprising: A battery comprising the switched capacitor circuit of any one of claims 1-17 coupled with the battery.

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