Semiconductor module and external component connection method

Abstract

The purpose of the present invention is to improve accuracy of laser welding for connecting an external component to a semiconductor module.　A semiconductor unit has a terminal holding part including a terminal that has a first surface fixed to a cooling part, protrudes to the outside from an end part in an A direction parallel to the first surface, and has a terminal surface that is parallel to the first surface. A cover (5) is provided with an upper surface covering part (5a), side surface covering parts (5b1, 5b2), and flat parts (5c1, 5c2). The upper surface covering part (5a) is provided with protrusions (5a1), (5a2), (5a3), (5a4), (5a5), (5a6), (5a7), and (5a8) that cover the upper surface of the semiconductor unit and extend upward in an outer peripheral part. The side surface covering parts (5b1, 5b2) cover the side surfaces of the semiconductor unit provided in a B direction that is parallel to the first surface of the upper surface covering part (5a) and orthogonal to the A direction. The flat parts (5c1), (5c2) extend from the lower ends of the side surface covering parts (5b1), (5b2) in the B direction on the surface of the cooling part and abut the cooling part.

Description

Semiconductor Module and External Component Connection Method

[0001] The present invention relates to a semiconductor module and an external component connection method.

[0002] In a semiconductor module, independent units are provided in a plurality of storage parts, terminals joined by laser welding protrude from the side surface, and protrusions are provided on the outer periphery (Patent Document 1). A plurality of independent modules are covered with an exterior case, and the exterior case is supported by a support plate having a plurality of fixing holes (Patent Document 2). The downward pressure from the side wall of the housing cover acting on the multilayer substrate pressed against the heat sink is dispersed by a filler (Patent Document 3). Pressure is applied to the flat laminated bus bar arranged in the power module to form a laminate (Patent Document 4).

[0003] Japanese Patent Application Laid-Open No. 2023-86353, Japanese Patent Application Laid-Open No. 2020-47656, Japanese Patent Application Laid-Open No. 2009-44152, Japanese Patent Application Laid-Open No. 2023-29342

[0004] An object of the present invention is to improve the accuracy of laser welding for connecting external components to a semiconductor module.

[0005] To solve the above problems, a semiconductor module is provided. The semiconductor module includes a cooling section, a semiconductor unit having a terminal holding section with a terminal having a terminal surface parallel to the first surface and a first surface fixed to the cooling section, with the terminal protruding outward from an end in a first direction parallel to the first surface, and having a terminal surface parallel to the first surface, a top cover section that covers the top surface of the semiconductor unit and has a projection extending upward on its outer circumference, a side cover section that covers the side surface of the semiconductor unit provided in a second direction parallel to the first surface of the top cover section and perpendicular to the first direction, and a flat section that extends from the lower end of the side cover section in the second direction and contacts the cooling section. Furthermore, to solve the above problems, a method for connecting external components is provided. The external component connection method includes a first step of preparing an external component and a semiconductor module having a cooling section, a semiconductor unit having a terminal holding section whose first surface is fixed to the cooling section and which includes a terminal that protrudes outward from an end in a first direction parallel to the first surface and has a terminal surface parallel to the first surface, a top cover section that covers the top surface of the semiconductor unit and has a projection extending upward on its outer circumference, a side cover section that covers the side of the semiconductor unit provided in a second direction parallel to the first surface of the top cover section and perpendicular to the first direction, and a flat section that extends from the lower end of the side cover section in the second direction and contacts the cooling section. The method also includes a first step of preparing an external component and a second step of fixing the semiconductor module by pressing the projection and the flat section against it, a third step of contacting the external component with the terminal surface of the terminal protruding from the semiconductor module with respect to the fixed semiconductor module and pressing the projection, the flat section and the external component together, and a fourth step of laser welding the external component to the terminal surface to connect the external component to the terminal.

[0006] One aspect of this invention is that it becomes possible to improve the accuracy of laser welding for connecting external components to semiconductor modules. The above and other objects, features and advantages of the present invention will become apparent from the following description in conjunction with the attached drawings illustrating preferred embodiments as examples of the present invention.

[0007] This is a diagram showing an example of the configuration of a semiconductor unit. This is a diagram showing an example of the configuration of a semiconductor unit. This is a diagram showing an example of the appearance of a semiconductor unit. This is a diagram showing an example of the process of mounting a semiconductor unit to the cooling section. This is a plan view of a semiconductor module. This is a diagram showing an example of the circuit configuration of a 3-level inverter. This is a diagram showing an example of the circuit configuration of a 2-level inverter. This is a plan view of the cover. This is a side view of the cover. This is a flowchart showing the method of connecting external components. This is a diagram showing the first connection state between the terminals of the semiconductor module and external components. This is a diagram showing the second connection state between the terminals of the semiconductor module and external components. This is a diagram showing a first example of the configuration of the terminal holding section. This is a diagram showing a second example of the configuration of the terminal holding section. This is a diagram showing a third example of the configuration of the terminal holding section. This is a diagram showing a fourth example of the configuration of the terminal holding section.

[0008] Hereinafter, this embodiment will be described with reference to the drawings. In this specification and in the drawings, elements having substantially the same function may be denoted by the same reference numerals, and redundant explanations may be omitted. In the following description, "front surface" and "top surface" refer to the surface facing upwards as viewed from the page. Similarly, "upwards" refers to the direction facing upwards as viewed from the page. "Back surface" and "bottom surface" refer to the surface facing downwards as viewed from the page. Similarly, "downwards" refers to the direction facing downwards as viewed from the page. "Front surface," "top surface," and "upwards" and "back surface," "bottom surface," and "downwards" are merely convenient expressions to specify the relative positional relationship and do not limit the technical concept of the present invention.

[0009] The configuration of the semiconductor module of this embodiment will be described with reference to Figures 1 to 5. Figures 1 and 2 show an example of the configuration of a semiconductor unit. Figure 3 shows an example of the external appearance of a semiconductor unit. The semiconductor unit 11a included in the semiconductor module of this embodiment comprises a first circuit board 1, a second circuit board 2, and a case 3. Figure 1 shows a plan view of the first circuit board 1, Figure 2 shows a plan view of the second circuit board 2, and Figure 3 shows the assembled semiconductor unit.

[0010] The first circuit board 1 may be an insulating circuit board including, for example, an insulating member and a conductive plate formed on the front surface of the insulating member. The second circuit board 2 may be a printed circuit board having a multilayer structure in which a plurality of conductive layers are arranged within an insulating layer and each layer is stacked via the insulating layer. The first circuit board 1 is mounted with, for example, semiconductor chip groups Q10, Q20, Q30, and Q40 that constitute a three-level inverter (power converter), and each of the semiconductor chip groups Q10, Q20, Q30, and Q40 includes a plurality of semiconductor chips. The second circuit board 2 is provided with control terminal groups g1 and g2.

[0011] Case 3 includes a storage area. The storage area of ​​Case 3 houses the first circuit board 1, the second circuit board 2, the semiconductor chip group Q10, Q20, Q30, Q40, and a sealing member (not shown) that seals the first circuit board 1, the second circuit board 2, and the semiconductor chip group Q10, Q20, Q30, Q40. Case 3 is integrally molded with a terminal holding portion 110a. The terminal holding portion 110a is provided in the direction A (first direction) and the opposite direction of direction A of the storage area, and external terminals are integrally provided on it. Furthermore, Case 3 is provided with control terminal holes through which control terminal groups g1 and g2 are inserted along the side of the storage area in direction A. Each control terminal hole may have a single control terminal inserted through it, or multiple control terminals may be inserted together.

[0012] Case 3 is integrally molded by injection molding using a thermoplastic resin. Examples of thermoplastic resins include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, acrylonitrile butadiene styrene resin, or liquid crystal polymer.

[0013] External terminals are connected to the first circuit board 1 in direction A, and these external terminals are connected to the conductive plate of the first circuit board 1 by laser welding or ultrasonic welding. Examples of external terminals include a positive terminal P, a negative terminal N, an intermediate terminal M, and an output terminal OUT.

[0014] The positive terminal P, negative terminal N, intermediate terminal M, and output terminal OUT are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy mainly composed of at least one of these. The surfaces of the positive terminal P, negative terminal N, intermediate terminal M, and output terminal OUT may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0015] On the other hand, the second circuit board 2, which is positioned above the first circuit board 1, includes a conductive pattern layer formed on an insulating layer. Figure 2 shows the conductive pattern layers 2a, 2b, 2c, and 2d formed on the insulating layer 21. Furthermore, control terminal groups g1 and g2, which include multiple control terminals, are mounted on the long side of the second circuit board 2.

[0016] The semiconductor unit 11a is formed by sandwiching a group of semiconductor chips Q10, Q20, Q30, and Q40 between a first circuit board 1 and a second circuit board 2, and is further provided in the housing area of ​​the case 3.

[0017] The structure of the semiconductor unit 11a includes a first circuit board 1, implant pins, and a second circuit board 2, which is a printed circuit board bonded to the implant pins, all housed in a storage area of ​​the case 3, and these components housed in the storage area are sealed by a sealing member. The positive terminal P, negative terminal N, intermediate terminal M, output terminal OUT, and control terminal groups g1 and g2 are sealed while exposed from the case 3. As the second circuit board 2, a polyimide film substrate or an epoxy film substrate with a conductive layer of Cu, Al, etc. can be used. As the implant pins, copper pins using Cu can be used. The implant pins of the second circuit board 2 may be treated with Ni plating or other treatments for purposes such as rust prevention.

[0018] The second circuit board 2 and the implant pins electrically connect the semiconductor chip group Q10, Q20, Q30, Q40 to each other, or between the semiconductor chip group Q10, Q20, Q30, Q40 and the first circuit board 1. The implant pins and the first circuit board 1 or the semiconductor chip group Q10, Q20, Q30, Q40 can be joined by a metal particle sintered body or a solder bonding layer. A semiconductor unit 11a with such a structure is manufactured by assembling the first circuit board 1, the semiconductor chip group Q10, Q20, Q30, Q40, the implant pins, and the second circuit board 2, placing them in the storage area of ​​the case 3, then placing the case 3 on a suitable mold, filling the mold with a sealing material, and heating and curing it. Examples of molding methods for such a sealing material include transfer molding, but are not limited to the specified molding method.

[0019] Figure 4 shows an example of the process for mounting semiconductor units to the cooling section. If three semiconductor units 11a, 11b, and 11c are included in the semiconductor module, the cooling section 4 is attached to the first surface of each of the semiconductor units 11a, 11b, and 11c. The first surface is parallel to the XY plane.

[0020] In this case, a thermally conductive adhesive member 4a is placed between the lower surface of semiconductor unit 11a and the upper surface of cooling unit 4, a thermally conductive adhesive member 4b is placed between the lower surface of semiconductor unit 11b and the upper surface of cooling unit 4, and a thermally conductive adhesive member 4c is placed between the lower surface of semiconductor unit 11c and the upper surface of cooling unit 4. Thus, semiconductor units 11a, 11b, and 11c are arranged in direction B (second direction) perpendicular to direction A with respect to the cooling unit 4. Holes h11, h12, h13, h14, h15, h16, h17, and h18 are formed at the long side ends of the cooling unit 4 for screw fixing to the cover described later.

[0021] The thermally conductive adhesive members 4a, 4b, and 4c are TIMs (Thermal Interface Materials). TIMs are a general term for various materials such as thermally conductive grease, thermal compounds, elastomer sheets, RTV (Room Temperature Vulcanization) rubber, gels, phase change materials, solder, and silver solder.

[0022] Furthermore, the cooling unit 4 is made of a material with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these materials. To improve corrosion resistance, the surface of the cooling unit 4 may be plated. Examples of plating materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The cooling unit 4 may also be, for example, a heat dissipation base equipped with heat dissipation fins, or a cooling device in which a coolant circulates inside.

[0023] Figure 5 is a plan view of the semiconductor module. The semiconductor module 10 has semiconductor units 11a, 11b, and 11c mounted on the cooling unit 4, and a cover 5 is attached to the upper surface of the semiconductor units 11a, 11b, and 11c. The cover 5 is molded from thermoplastic resin.

[0024] Examples of such resins include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin. The terminals of the semiconductor units 11a, 11b, and 11c are exposed from the cover 5. In this case, the positive terminal P, negative terminal N, intermediate terminal M, and output terminal OUT provided on the terminal holding portion 110a of the semiconductor unit 11a protrude outward from the end in direction A with the terminal surface parallel to the XY plane (first plane).

[0025] Furthermore, the positive terminal P, negative terminal N, intermediate terminal M, and output terminal OUT provided on the terminal holding portion 110b of the semiconductor unit 11b protrude outward from the end in direction A with their terminal surfaces parallel to the XY plane. In addition, the positive terminal P, negative terminal N, intermediate terminal M, and output terminal OUT provided on the terminal holding portion 110c of the semiconductor unit 11c protrude outward from the end in direction A with their terminal surfaces parallel to the XY plane.

[0026] Next, the configuration of the semiconductor chips and level inverters included in the semiconductor unit will be explained using Figures 6 and 7. The semiconductor chip groups Q10, Q20, Q30, and Q40 included in semiconductor units 11a, 11b, and 11c, respectively, may include power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) composed mainly of silicon carbide. The body diode of the power MOSFET may function as a FWD (Free Wheeling Diode). Such a semiconductor chip, for example, has an input electrode (drain electrode), which is the main electrode, on its back surface, and an output electrode (source electrode) and a control electrode (gate electrode), which are the main electrodes, on its front surface.

[0027] The semiconductor chip groups Q10, Q20, Q30, and Q40 may include switching elements mainly composed of silicon. The switching elements may be, for example, RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). An RC-IGBT is a semiconductor chip configured by connecting an IGBT and a FWD in antiparallel. Such a semiconductor chip has, for example, an input electrode (collector electrode), which is the main electrode, on its back surface, and an output electrode (emitter electrode) and a control electrode (gate electrode), which are the main electrodes, on its front surface.

[0028] Each of the semiconductor units 11a, 11b, and 11c included in the semiconductor module 10 is equipped with a three-level inverter or a two-level inverter composed of the semiconductor chips described above.

[0029] Figure 6 shows an example of a circuit configuration for a three-level inverter. The three-level inverter, which is a bidirectional switch type, includes a semiconductor chip Q1 on the upper arm, a semiconductor chip Q2 on the lower arm, a semiconductor chip Q3 on the upstream intermediate arm, a semiconductor chip Q4 on the downstream intermediate arm, a positive terminal P, a negative terminal N, an intermediate terminal M, and an output terminal OUT. For example, semiconductor chip Q1 is included in semiconductor chip group Q10, semiconductor chip Q2 is included in semiconductor chip group Q20, semiconductor chip Q3 is included in semiconductor chip group Q30, and semiconductor chip Q4 is included in semiconductor chip group Q40.

[0030] The semiconductor chip Q1 on the upper arm, the semiconductor chip Q2 on the lower arm, the semiconductor chip Q3 on the upstream intermediate arm, and the semiconductor chip Q4 on the downstream intermediate arm each have a MOSFET transistor and a body diode connected in antiparallel to the transistor.

[0031] The positive terminal P is connected to the drain electrode of the transistor on semiconductor chip Q1. The source electrode of the transistor on semiconductor chip Q1 is connected to the output terminal OUT and the drain electrode of the transistor on semiconductor chip Q2. The negative terminal N is connected to the source electrode of the transistor on semiconductor chip Q2. The intermediate terminal M is connected to the source electrode of the transistor on semiconductor chip Q3.

[0032] The source electrode of the transistor on semiconductor chip Q4 is connected to the drain electrode of the transistor on semiconductor chip Q3. The output terminal OUT, the source electrode of the transistor on semiconductor chip Q1, and the drain electrode of the transistor on semiconductor chip Q2 are connected to the drain electrode of the transistor on semiconductor chip Q4.

[0033] The gate electrodes of the transistors on semiconductor chips Q1, Q2, Q3, and Q4 are connected to gate terminals G1, G2, G3, and G4, respectively, which are input terminals for the switching operation drive signals. In addition, auxiliary source terminals S1, S2, S3, and S4 are connected to the source electrodes of semiconductor chips Q1, Q2, Q3, and Q4. The gate terminals G1, G2, G3, and G4 and the auxiliary source terminals S1, S2, S3, and S4 are included in either control terminal group g1 or control terminal group g2.

[0034] In a three-level inverter with this configuration, when the drive signals to gate terminals G1 and G3 are ON and the drive signals to gate terminals G2 and G4 are OFF, the output voltage from output terminal OUT is E / 2. When the drive signals to gate terminals G3 and G4 are ON and the drive signals to gate terminals G1 and G2 are OFF, the output voltage from output terminal OUT is 0. When the drive signals to gate terminals G2 and G4 are ON and the drive signals to gate terminals G1 and G3 are OFF, the output voltage from output terminal OUT is -E / 2.

[0035] Figure 7 shows an example of a circuit configuration for a two-level inverter. The two-level inverter comprises semiconductor chips Q1a and Q2a, a positive terminal P, a negative terminal N, and an output terminal OUT. For example, semiconductor chip Q1a is included in semiconductor chip group Q10 or semiconductor chip group Q30, and semiconductor chip Q2a is included in semiconductor chip group Q20 or semiconductor chip group Q40. Furthermore, semiconductor chip Q1a includes an IGBT 13a and a diode D11, and semiconductor chip Q2a includes an IGBT 13b and a diode D12.

[0036] The positive terminal P is connected to the collector electrode of IGBT 13a and the cathode of diode D11. The emitter electrode of IGBT 13a is connected to the anode of diode D11, the collector electrode of IGBT 13b, the cathode of diode D12, and the output terminal OUT. The negative terminal N is connected to the emitter electrode of IGBT 13b and the anode of diode D12. In addition, the gate electrodes of IGBTs 13a and 13b are connected to control terminals G11 and G12, which are included in control terminal group g1 or control terminal group g2, respectively.

[0037] Next, the structure of the cover 5 will be explained using Figures 8 and 9. Figure 8 is a plan view of the cover, and Figure 9 is a side view of the cover. Figure 9 is a view of the cover 5 from the Y-axis direction. The cover 5 comprises an upper covering portion 5a, side covering portions 5b1 and 5b2, and flat portions 5c1 and 5c2, and the upper covering portion 5a, side covering portions 5b1 and 5b2, and flat portions 5c1 and 5c2 are integrally molded.

[0038] The upper covering portion 5a covers the upper surfaces of the semiconductor units 11a, 11b, and 11c, and is provided with projections (bosses) 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, and 5a8 that extend upward relative to the outer periphery. The projections 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, and 5a8 are arranged symmetrically with respect to direction A and symmetrically with respect to direction B.

[0039] Furthermore, holes h21, h22, h23, h24, h25, h26, h27, and h28 are formed in the protrusions 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, and 5a8, respectively, for fixing the semiconductor module to the drive substrate. The area of ​​the upper surface of the protrusions 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, and 5a8 is, for example, 93.415 mm². ２ That is the case.

[0040] Mounting portions 51, 52, 53, 54, 55, 56, 57, and 58 for screw fixing to the cooling portion 4 are formed at the long side ends of the cover 5. The hole h51 of mounting portion 51 is screw-fixed to the hole h11 of the cooling portion 4, the hole h52 of mounting portion 52 is screw-fixed to the hole h12 of the cooling portion 4, the hole h53 of mounting portion 53 is screw-fixed to the hole h13 of the cooling portion 4, and the hole h54 of mounting portion 54 is screw-fixed to the hole h14 of the cooling portion 4.

[0041] Similarly, the hole h55 of the mounting portion 55 and the hole h15 of the cooling portion 4 are fixed with screws, the hole h56 of the mounting portion 56 and the hole h16 of the cooling portion 4 are fixed with screws, the hole h57 of the mounting portion 57 and the hole h17 of the cooling portion 4 are fixed with screws, and the hole h58 of the mounting portion 58 and the hole h18 of the cooling portion 4 are fixed with screws.

[0042] On the other hand, the side coverings 5b1 and 5b2 cover the sides of the semiconductor unit in the direction B, which is perpendicular to the direction A. The flat portion 5c1 extends from the lower end of the side covering 5b1 to the opposite side of the cooling portion 4 in the direction B and contacts the surface of the cooling portion 4. Similarly, the flat portion 5c2 extends from the lower end of the side covering 5b2 to the surface of the cooling portion 4 in the direction B and contacts the surface of the cooling portion 4. The area of ​​the flat portions 5c1 and 5c2 is larger than the area of ​​the upper surfaces of the protrusions 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, and 5a8.

[0043] Next, an external component connection method for connecting an external component to a terminal of a semiconductor module and the configuration of the semiconductor module to which the external component is connected will be described with reference to FIGS. 10 to 12. FIG. 10 is a flowchart showing the external component connection method. [First step P1] A semiconductor module 10 and an external component are prepared. [Second step P2] The protrusions 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, 5a8 and the flat portions 5c1, 5c2 of the semiconductor module 10 are pressed by a combining machine (prestress) to fix the semiconductor module 10.

[0044] [Third step P3] An external component is brought into contact with the terminal surface of a terminal (any one of the positive terminal P, negative terminal N, intermediate terminal M, and output terminal OUT) protruding from the semiconductor module 10 with respect to the fixed semiconductor module (10). Then, a main pressing is performed by the combining machine to press the protrusions 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, <5a8> and the flat portions 5c1, 5c2 and the external component.

[0045] [Fourth step P4] The external component is laser welded to the terminal surface of the semiconductor module 10 with respect to the main pressed semiconductor module and external component to connect the external component to the terminal of the semiconductor module 10.

[0046] FIG. 11 is a diagram showing a first connection state between a terminal of a semiconductor module and an external component. The semiconductor module 10 is a module including a three-level inverter, and the external component is a capacitor. In the first connection state, one terminal L1 of the capacitor C1 is laser welded to the positive terminal P protruding from the semiconductor module <10>, and the other terminal L2 of the capacitor C1 is laser welded to the intermediate terminal M protruding from the semiconductor module 10.

[0047] Also, one terminal L3 of the capacitor C2 is laser welded to the intermediate terminal M protruding from the semiconductor module 10, and the other terminal L4 of the capacitor C2 is laser welded to the negative terminal N protruding from the semiconductor module 10. Note that the terminal L2 and the terminal L<3> may be integral.

[0048] Figure 12 shows a second connection state between the terminals of a semiconductor module and an external component. The semiconductor module 10 is a module equipped with a two-level inverter, and the external component is a capacitor. In the second connection state, one terminal L5 of the capacitor C3 is laser-welded to the positive terminal P protruding from the semiconductor module 10, and the other terminal L6 of the capacitor C3 is laser-welded to the negative terminal N protruding from the semiconductor module 10.

[0049] In this case, when external components such as capacitors are laser-welded to terminals provided on a semiconductor module, as described above, prestressing is performed on the upper surface of the semiconductor module cover using an assembly machine to fix the semiconductor module in place. Then, permanent pressing is performed on both the semiconductor module and the external component to ensure close contact between the semiconductor module's terminals and the external component before laser welding is performed.

[0050] In this process, the semiconductor module is pressed down from above while laser welding is performed. However, if there is no flat surface on the top surface of the semiconductor module's cover, it is difficult to press the semiconductor module uniformly from above. Furthermore, even if there is a flat surface on the top surface of the cover, if the flat surface is not in the appropriate position relative to the top surface of the cover, the semiconductor module cannot be pressed uniformly. This results in a large height tolerance between the terminals and external components during laser welding, leading to a decrease in the accuracy of the laser welding.

[0051] In contrast, in the semiconductor module 10 of this embodiment, the upper covering portion 5a of the cover 5 has projections 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, and 5a8 extending upward on its outer circumference, and the side covering portions 5b1 and 5b2 of the cover 5 have flat portions 5c1 and 5c2 that contact the surface of the cooling portion 4, respectively.

[0052] Since the upper surfaces of the protrusions 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, and 5a8, as well as the flat portions 5c1 and 5c2, are flat surfaces, the assembly machine can press the semiconductor module 10 from above.

[0053] Furthermore, the protrusions 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, and 5a8 are arranged symmetrically in the direction A and symmetrically in the direction B. In addition, the flat portions 5c1 and 5c2 are located on both sides of the cover 5.

[0054] Thus, the protrusions 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, and 5a8 are arranged symmetrically in a plan view of the cover 5, and the flat portions 5c1 and 5c2 are also arranged symmetrically in a plan view of the cover 5.

[0055] Therefore, when the assembly machine presses the semiconductor module 10 from above, the semiconductor module 10 can be pressed uniformly, which reduces the height tolerance between the terminals and external components during laser welding, thereby improving the accuracy of laser welding.

[0056] Next, an example of the configuration of the terminal holding portion provided in the semiconductor module of this embodiment will be described with reference to Figures 13 to 16. The explanation will be based on the case where the semiconductor module contains one semiconductor unit. Furthermore, the projections and mounting portions provided on the cover 5 will not be shown.

[0057] Figure 13 shows a first example configuration of the terminal holding portion. The terminal holding portion of the semiconductor module 10a includes a single first terminal 111a1 and comprises a first terminal holding portion 111a provided at the end opposite to the direction A, and a second terminal holding portion 112 provided at the end in the direction A, which includes a single terminal 112a. For example, the first terminal 111a1 is a power terminal V, and the terminal 112a is an output terminal OUT.

[0058] Figure 14 shows a second example of the configuration of the terminal holding portion. The terminal holding portion of the semiconductor module 10b includes a plurality of terminals and comprises a first terminal holding portion 111b provided at the end opposite to the direction A, and a second terminal holding portion 112 including a terminal 112a provided at the end in the direction A.

[0059] The first terminal holding portion 111b includes a first terminal 111b1 and a second terminal 111b2, with the first terminal 111b1, the insulating member 6, and the second terminal 111b2 being stacked in order. For example, the first terminal 111b1 is a positive terminal P, and the second terminal 111b2 is a negative terminal N.

[0060] Figure 15 shows a third example of the configuration of the terminal holding portion. The terminal holding portion of the semiconductor module 10c includes a plurality of terminals and comprises a first terminal holding portion 111c provided at the end opposite to the direction A, and a second terminal holding portion 112 including a terminal 112a provided at the end in the direction A.

[0061] The first terminal holding portion 111c includes a first terminal 111c1 and a second terminal 111c2, and the first terminal 111c1 and the second terminal 111c2 are arranged in the B direction. For example, the first terminal 111c1 is a positive terminal P, and the second terminal 111c2 is a negative terminal N.

[0062] Figure 16 shows a fourth example of the configuration of the terminal holding portion. The terminal holding portion of the semiconductor module 10d includes a plurality of terminals and comprises a first terminal holding portion 111d provided at the end opposite to the direction A, and a second terminal holding portion 112 including a terminal 112a provided at the end in the direction A.

[0063] The first terminal holding portion 111d includes a first terminal 111d1, a second terminal 111d2, and a third terminal 111d3, with the first terminal 111d1 and the second terminal 111d2 arranged in the B direction. Furthermore, the first terminal 111d1 and the second terminal 111d2, the insulating member 6, and the third terminal 111d3 are stacked in order. For example, the first terminal 111d1 is a positive terminal P, the second terminal 111d2 is a negative terminal N, and the third terminal 111d3 is an intermediate terminal M.

[0064] While embodiments have been illustrated above, the configurations of each part shown in the embodiments can be replaced with others having similar functions. Furthermore, any other components or processes may be added. Moreover, any two or more configurations (features) from the embodiments described above may be combined. The above merely illustrates the principle of the present invention. Furthermore, numerous modifications and changes are possible for those skilled in the art, and the present invention is not limited to the exact configurations and applications shown and described above. All corresponding modifications and equivalents are considered to be within the scope of the present invention as defined by the appended claims and their equivalents.

[0065] 1 First circuit board 2 Second circuit board 3 Case 2a, 2b, 2c, 2d Conductive pattern layer 21 Insulating layer 10, 10a, 10b, 10c, 10d Semiconductor module 11a, 11b, 11c Semiconductor unit 110a, 110b, 110c Terminal holding part 4 Cooling part 4a, 4b, 4c Thermally conductive adhesive material (TIM) 12a, 12b, 12c, 12d MOSFET 13a, 13b IGBT 5 Cover 5a Top covering part 5a1, 5a2, 5a3, 5a4, 5a5, 5a6, 5a7, 5a8 Protrusion 51, 52, 53, 54, 55, 56, 57, 58 Mounting part 5b1, 5b2 Side covering part 5c1, 5c2 Flat section 6 Insulating members 111a, 111b, 111c, 111d First terminal holding section 111a1 First terminal (power terminal V) 111b1, 111c1, 111d1 First terminal (positive terminal P) 111b2, 111c2, 111d2 Second terminal (negative terminal N) 111d3 Third terminal (intermediate terminal M) 112 Second terminal holding section 112a Terminal (output terminal OUT) Q10, Q20, Q30, Q40 Semiconductor chip group g1, g2 Control terminal group P Positive terminal N Negative terminal M Intermediate terminal OUT Output terminal A First direction B Second direction h11, h12, h13, h14, h15, h16, h17, h18 Holes formed in the cooling section Q1, Q2, Q3, Q4, Q1a, Q2a Semiconductor chips D1, D2, D3, D4, D11, D12 Diodes C1, C2, C3 Capacitors G1, G2, G3, G4, G11, G12 Control terminals S1, S2, S3, S4 Auxiliary source terminals L1, L3, L5 One terminal of a capacitor L2, L4, L6 The other terminal of a capacitor h21, h22, h23, h24, h25, h26, h27, h28 Holes formed in the protrusions h51, h52, h53, h54, h55, h56, h57, h58 Holes formed in the mounting portion

Claims

1. A semiconductor module comprising: a cooling section; a semiconductor unit having a terminal holding section, the first surface of which is fixed to the cooling section, and which includes a terminal that protrudes outward from an end in a first direction parallel to the first surface and has a terminal surface parallel to the first surface; a top cover section that covers the upper surface of the semiconductor unit and has a projection extending upward on its outer circumference; a side cover section that covers the side surface of the semiconductor unit provided in a second direction parallel to the first surface of the top cover section and perpendicular to the first direction; and a flat section that extends from the lower end of the side cover section in the second direction and contacts the surface of the cooling section.

2. The semiconductor module according to claim 1, wherein a plurality of the semiconductor units are arranged in the second direction in the cooling section.

3. The semiconductor module according to claim 1, wherein the cover is provided with a mounting portion for inserting screws and screw-fixing the semiconductor unit to the cooling portion.

4. The semiconductor module according to claim 1, wherein the projection is provided with a hole for fixing the semiconductor module to a drive substrate.

5. The semiconductor module according to claim 1, wherein the plurality of protrusions are arranged symmetrically in the first direction.

6. The semiconductor module according to claim 1, wherein the plurality of protrusions are arranged symmetrically in the second direction.

7. The semiconductor module according to claim 1, wherein the terminals are laser-welded to external components.

8. The semiconductor module according to claim 1, wherein the terminal holding portion comprises a first terminal holding portion provided at the end in the first direction and including one or more terminals, and a second terminal holding portion provided at the end in the opposite direction to the first direction and including a single terminal.

9. The semiconductor module according to claim 8, wherein the first terminal holding portion includes at least one power terminal, and the second terminal holding portion includes an output terminal.

10. The semiconductor module according to claim 8, wherein the first terminal holding portion includes a first terminal and a second terminal, the first terminal, an insulating member, and the second terminal are stacked in order, and the second terminal holding portion includes an output terminal.

11. The semiconductor module according to claim 8, wherein the first terminal holding portion includes a first terminal and a second terminal, the first terminal and the second terminal are arranged in the second direction, and the second terminal holding portion includes an output terminal.

12. The semiconductor module according to claim 10 or 11, wherein the first terminal is a positive terminal and the second terminal is a negative terminal.

13. The semiconductor module according to claim 8, wherein the first terminal holding portion includes a first terminal, a second terminal, and a third terminal, the first terminal and the second terminal are arranged in the second direction, the first terminal and the second terminal, an insulating member, and the third terminal are stacked in order, and the second terminal holding portion includes an output terminal.

14. The semiconductor module according to claim 13, wherein the first terminal is a positive terminal, the second terminal is a negative terminal, and the third terminal is an intermediate terminal.

15. A semiconductor module having a cooling section, a terminal holding section having a terminal whose first surface is fixed to the cooling section and which protrudes outward from an end in a first direction parallel to the first surface and has a terminal surface parallel to the first surface, a cover having an upper surface cover section that covers the upper surface of the semiconductor unit and has a projection extending upward on its outer circumference, a side surface cover section that covers the side surface of the semiconductor unit provided in a second direction parallel to the first surface of the upper surface cover section and perpendicular to the first direction, and a flat section that extends from the lower end of the side surface cover section in the second direction and contacts the surface of the cooling section, and external components; a first step of preparing external components; a second step of fixing the semiconductor module by pressing the projection and the flat section against the fixed semiconductor module; a third step of contacting the terminal surface of the terminal protruding from the semiconductor module with the external components, and pressing the projection, the flat section and the external components against the fixed semiconductor module; a fourth step of laser welding the external components to the terminal surface to connect the external components to the terminals; A method for connecting external components.

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