Radio frequency switch

Abstract

This disclosure describes systems, methods, and apparatuses for an RF switch comprising one or more cells coupled in series between RF terminals. Each cell having a bridge of PIN diodes or three-terminal switches controlled by complementary drivers through a coupled inductor. A bypass inductor can be arranged across each bridge. The RF switch may include compensation capacitors to better achieve equal distribution of voltage over the switches when the RF switch is in the off state.

Description

Attorney Docket No. AE2024-020PCT TITLE: RADIO FREQUENCY SWITCH CLAIM OF PRIORITY UNDER 35 U.S.C. §120

[0001] The present Application for Patent claims priority to U.S. Provisional Patent Application No.63 / 693,587 entitled “RADIO FREQUENCY SWITCH” filed September 11, 2024 and assigned to the assignee hereof and hereby expressly incorporated by reference herein. FIELD OF THE DISCLOSURE

[0002] The present disclosure relates generally to power systems. Specifically, but without limitation, the present disclosure relates to impedance matching networks. BACKGROUND

[0003] In the context of plasma processing, manufacturers use plasma processing chambers that utilize power (e.g., radio frequency (RF) power) to generate a plasma. To achieve efficient power transfer between a generator and a plasma load, an impedance-matching network (“match network”) is often used to match the load impedance to a desired input impedance, typically (although not always) 50 ^. Plasma load impedance may vary depending on variables such as generator frequency, power, chamber pressure, gas composition, and plasma ignition. The match network accounts for these variations in load impedance by varying reactive elements (e.g., variable capacitors) to maintain the desired input impedance.

[0004] RF matching networks have long utilized variable vacuum capacitors, but solid-state matches (SSMs), which include discrete reactive elements such as capacitors and inductors that are switched in or out to alter the value of a reactive element in a SSM, are now anAttorney Docket No. AE2024-020PCT alternative technology that are gaining popularity, but there are challenges to achieving desired performance characteristics when using SSMs.Attorney Docket No. AE2024-020PCT BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Various objects and advantages and a more complete understanding of the present disclosure are apparent and more readily appreciated by referring to the following detailed description and to the appended claims when taken in conjunction with the accompanying drawings:

[0006] FIG.1 is a circuit diagram illustrating an RF switch incorporating a PIN diode as the switching element.

[0007] FIG.2 shows the state of a PIN diode in the forward biased state.

[0008] FIG.3 shows the state of a PIN diode at the start of reverse biasing the PIN diode.

[0009] FIG.4 shows the state of a PIN diode a short time after the start of reverse biasing the PIN diode.

[0010] FIG.5 shows the state of a PIN diode after a substantial amount of charge had been removed in the reverse biasing of the PIN diode.

[0011] FIG.6 shows an approximation to the state of the PIN diode after a substantial amount of charge had been removed in the reverse biasing of the PIN diode.

[0012] FIG.7A shows a switching circuit comprising multiple PIN diodes arranged in series within stacked bridges.

[0013] FIG.7B shows a cell of a switching circuit.

[0014] FIG.7C shows one or more cells of a switching circuit along with complementary drivers.

[0015] FIG.7D shows a switching circuit with an alternative topology.

[0016] FIG.8 shows a switching circuit comprising multiple three-terminal switches arranged in series within stacked bridges.Attorney Docket No. AE2024-020PCT

[0017] FIG.9 shows a schematic for analyzing the effects of parasitic capacitance on a switching circuit.

[0018] FIG.10 shows a switching circuit comprising multiple three-terminal switches along with compensation capacitors.

[0019] FIG.11 depicts processing components that may be used to control aspects disclosed herein.

[0020] FIG.12 shows a method of operating a switching circuit.

[0021] FIG.13 shows another method of operating a switching circuit.

[0022] FIG.14 shows another switching circuit coupled to an impedance element. DETAILED DESCRIPTION

[0023] Prior to describing the embodiments in detail, it is expedient to define certain terms as used in this disclosure.

[0024] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0025] As discussed above, solid-state matches (SSMs) are gaining popularity. An aspect of SSMs is that they may be switched more quickly than variable vacuum capacitors, and faster switching enables faster matching, which enables better process control.

[0026] In some circumstances, however, it may be difficult to design a SSM that may continuously switch reactive elements in and out of the SSM at a high rate. This difficulty may be dueAttorney Docket No. AE2024-020PCT to the power required to affect the switching at a high rate as well as dissipation in the switches during the time that it takes to turn the switches off.

[0027] Aspects of this disclosure relate to systems, methods, and apparatuses for an RF switch (or switching circuit), and more particularly for an RF switch that comprises a series arrangement of switches comprising coupled inductors to simultaneously provide high impedance to an RF signal applied to the switch while providing a low impedance path for current controlling the state of the switch. Each member of the series arrangement of switches may include a bridge formation of diodes having four terminals, where two of those terminals may be coupled to two of the inductors and the remaining two terminals may be coupled to one or more of the other bridge circuits. The coupled inductors may be driven by a pair of oppositely phased drivers.

[0028] These and other features, and characteristics of the present technology, as well as the methods of operation and functions of the related elements of structure and the combination of parts and economies of manufacture, will become more apparent upon consideration of the following description and the appended claims with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in the various figures. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the invention. As used in the specification and in the claims, the singular form of “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.Attorney Docket No. AE2024-020PCT

[0029] For the purposes of this disclosure, “high impedance” for an RF signal means a magnitude of impedance that is at least 100 times greater than a “low impedance” at the frequency of the applied RF signal. For example, at 13.56 MHz a magnitude of high impedance may be greater than 100 ^ and a magnitude of low impedance may be less than 1 ^, although in other embodiments, a magnitude of high impedance may be greater than 1000 ^ and a magnitude of low impedance may be less than 1 ^ (i.e., a 1000x difference).

[0030] As for a current used to control switching elements in this disclosure, “high” and “low” impedance depend on the frequency of the current. For example, at low frequency currents (e.g., ~DC), low impedance may be less than 5 ^^ yet for high frequency currents (e.g., up to 1 MHz), low impedance may be less than 10 ^. PIN Diodes

[0031] PIN diodes are electrical devices having an un-doped or lightly doped intrinsic (I) semiconductor region sandwiched between heavily doped regions, and having various applications, for instance, as switching devices in impedance matching networks, especially in radio frequency (RF) matching networks. The “PIN” designation derives from the three-part “sandwich” structure of this diode: a lightly doped intrinsic region (I) positioned between a heavily doped p-type semiconductor (P) and a heavily doped n-type semiconductor (N).

[0032] In general, PIN diodes obey conventional diode behavior at low frequency input signals, but for higher frequency input signals they operate as a resistor in the forward biased or ON-state, and as a capacitor in the reverse biased or OFF-state (or as a current-controlledAttorney Docket No. AE2024-020PCT resistor). As such, PIN diodes may be utilized in radio frequency (RF) applications, e.g., in attenuators and fast switches where high isolation and low loss are desired. RF applications typically see at least MHz frequencies for thick intrinsic layers and upwards through GHz frequencies for thinner PIN devices. For instance, 1-60 MHz are common impedance matching frequencies. In some circumstances, PIN diodes may be turned ON with a DC current that is a small fraction of the RF current being switched and turned OFF by reverse biasing the PIN diode. PIN diodes are attractive switches because they combine low ON-state resistance with low OFF-state losses. In some cases, a PIN diode driver circuit may be used to turn the PIN diode ON and OFF by conducting a DC current through the PIN diode and applying a reverse bias voltage across the PIN diode, respectively. This unique operation allows PIN diodes in a bridge configuration to be turned ON and OFF via current and / or voltage applied to two opposing nodes of a bridge circuit while passing or blocking RF current passing between another two opposing nodes of the bridge circuit as seen, for example, in FIG.7A (i.e., a four-terminal PIN diode bridge).

[0033] In some aspects, the techniques described herein relate to an apparatus including: a first driver; a second driver configured to provide an opposite polarity to the first driver; and a first cell including: a bridge configuration of first switching elements having a first node, a second node, a third node, and a fourth node, wherein the first and third nodes are coupled to the first and second driver through a first coupled inductor; wherein the second and fourth nodes are configured to pass alternating current between the second and fourth nodes when a first current is passed between the first and third nodes and wherein the second and fourth nodes are configured to block the alternating current when a second current is passed between the first and third nodes having an opposite polarity to the first current.Attorney Docket No. AE2024-020PCT

[0034] In some aspects, the techniques described herein relate to an apparatus, wherein the first switching elements are PIN diodes.

[0035] In some aspects, the techniques described herein relate to an apparatus, wherein after the second current has been applied for some time, the magnitude of the second current decreases towards zero and the drivers maintain a voltage between the first and third nodes.

[0036] In some aspects, the techniques described herein relate to an apparatus, wherein after the first current has been applied for some time, the magnitude of the first current decreases towards zero.

[0037] In some aspects, the techniques described herein relate to an apparatus, wherein the first switching elements are three-terminal devices.

[0038] In some aspects, the techniques described herein relate to an apparatus, further including an inductor coupled between the second and fourth nodes.

[0039] In some aspects, the techniques described herein relate to an apparatus, wherein the bridge configuration presents a variable impedance between the second and fourth nodes, and wherein the variable impedance is controlled by the polarity of the first and second currents or a polarity of a voltage applied between the first and third nodes.

[0040] In some aspects, the techniques described herein relate to an apparatus, wherein a first node of an impedance element is connected to the second node and an impedance between a second node of the impedance element and the fourth node is controlled by the polarity of the first and second currents or a polarity of a voltage applied between the first and third nodes.Attorney Docket No. AE2024-020PCT

[0041] In some aspects, the techniques described herein relate to an apparatus, wherein the impedance element is one of a resistor, a capacitor, or an inductor.

[0042] In some aspects, the techniques described herein relate to an apparatus, further including capacitors parallel to the switching elements to equalize voltages across the switching elements.

[0043] In some aspects, the techniques described herein relate to an apparatus, further including a second cell including a bridge configuration of second switching elements, and a first node, a second node, a third node, and a fourth node, wherein the second node of the second cell is coupled to the fourth node of the first cell, and

[0044] In some aspects, the techniques described herein relate to wherein the second cell further includes a second coupled inductor, wherein the first and third nodes of the second cell are coupled to the first and second drivers through the second coupled inductor.

[0045] In some aspects, the techniques described herein relate to an apparatus, wherein the first and second coupled inductors are cascaded.

[0046] In some aspects, the techniques described herein relate to an apparatus, wherein the first and second coupled inductors connect independently to the first and second drivers.

[0047] In some aspects, the techniques described herein relate to an apparatus, further including inductors connecting the second nodes of each bridge to the fourth node of the second bridge 16.Attorney Docket No. AE2024-020PCT

[0048] In some aspects, the techniques described herein relate to an apparatus, wherein the inductors connect between the second node and the fourth node of each bridge.

[0049] In some aspects, the techniques described herein relate to an apparatus, wherein the inductors connect the second node of each bridge to the fourth node of the second bridge.

[0050] In some aspects, the techniques described herein relate to an apparatus, wherein a first node of an impedance element is connected to the second node of the first bridge and an impedance between a second node of the impedance element and the fourth node of the second bridge is controlled by a polarity of the first and second currents or a polarity of a voltage applied between the first and third nodes of the bridges.

[0051] In some aspects, the techniques described herein relate to an apparatus, wherein the impedance element is one of a resistor, capacitor, or inductor.

[0052] In some aspects, the techniques described herein relate to an apparatus, further including capacitors parallel to the switching elements to equalize voltages across the switching elements.

[0053] In some aspects, the techniques described herein relate to an apparatus, further including N-1 additional cells, each cell including a bridge configuration of switching elements, and a first node, a second node, a third node, and a fourth node, wherein the second node of cell K is coupled to the fourth node of cell K-1 for K between 2 and N.

[0054] In some aspects, the techniques described herein relate to an apparatus, wherein cell K further includes a K-th coupled inductor wherein the first and third nodes of cell K are coupled to the first and second drivers through the K-th coupled inductor.Attorney Docket No. AE2024-020PCT

[0055] In some aspects, the techniques described herein relate to an apparatus, wherein the coupled inductors are cascaded, and the K-th coupled inductor is connected to the drivers through coupled inductors K+1, K+2, …, N.25.

[0056] In some aspects, the techniques described herein relate to an apparatus, further including inductors connecting the second nodes of each bridge to the fourth node of the N-th bridge.

[0057] In some aspects, the techniques described herein relate to an apparatus, wherein the inductors connect between the second node and the fourth node of each bridge.

[0058] In some aspects, the techniques described herein relate to an apparatus, wherein the inductors connect the second node of each bridge to the fourth node of the N-th bridge.

[0059] In some aspects, the techniques described herein relate to an apparatus, wherein a first node of an impedance element is connected to the second node of the first bridge and an impedance between a second node of the impedance element and the fourth node of the N- th bridge is controlled by a polarity of the first and second currents or a polarity of a voltage applied between the first and third nodes of the bridges.

[0060] In some aspects, the techniques described herein relate to an apparatus, wherein the impedance element is one of a resistor, capacitor, or inductor.

[0061] In some aspects, the techniques described herein relate to an apparatus, further including capacitors parallel to the switching elements to equalize voltages across the switching elements.Attorney Docket No. AE2024-020PCT

[0062] In some aspects, the techniques described herein relate to a method for operating a switch, the method including: providing a first cell between a first node and a second node, the first cell including a bridge of switching elements and four nodes, a first two of the four nodes for controlling a state of the switching elements, and a second two of the four nodes for passing alternating current between the first and second nodes as controlled by the state of the switching elements; and forming a current loop including a first driver, a coupled inductor, the first two of the four nodes of the bridge, and a second driver; wherein when a current in the current loop has a first polarity, a magnitude of an impedance presented to an AC current between the second two of the four nodes increases, and wherein when the current in the current loop has a second polarity, the magnitude of the impedance presented to the AC current between the second two of the four nodes decreases, wherein the second two of the four nodes include the switch nodes.

[0063] In some aspects, the techniques described herein relate to a non-transitory, tangible computer readable storage medium, encoded with processor readable instructions to perform a method for switching, the method including: sourcing a first current from a first driver; sinking the first current with a second driver; passing the first current through a coupled inductor and a bridge of switching elements and a first two nodes of the bridge of switching elements to increase a magnitude of an impedance presented to an AC current passing through the switching elements and a second two nodes in the bridge of switching elements.

[0064] In some aspects, the techniques described herein relate to a non-transitory, tangible computer readable storage medium, the method further including: passing the first current through a bypass inductor and the second two nodes in the bridge of switching elements toAttorney Docket No. AE2024-020PCT complete the discharge of one of the switching elements when another one of the switching elements reaches an OFF state first.

[0065] In some aspects, the techniques described herein relate to a non-transitory, tangible computer readable storage medium, the method further including: wherein the switching elements are PIN diodes and the alternating current has a frequency high enough to prevent depletion of an intrinsic region of the PIN diodes during a cycle of the alternating current.

[0066] In some aspects, the techniques described herein relate to a non-transitory, tangible computer readable medium, the method further including: sourcing a second current from the second driver; sinking the second current with the first driver; passing the second current through the coupled inductor and the bridge of switching elements and the first two nodes of the bridge of switching elements to decrease a magnitude of an impedance presented to the AC current passing through the switching elements and the second two nodes in the bridge of switching elements.

[0067] In some aspects, the techniques described herein relate to a non-transitory, tangible computer readable medium, the method further including adjusting the sourcing and sinking such that the disabling removes a capacitive element from a reactance seen by a load.

[0068] An aspect of the present disclosure relates to systems, methods, and apparatuses for an apparatus comprising: a first node; a second node; a first driver; a second driver configured to provide an opposite polarity to the first driver; and a first cell arranged between the first node and the second node. The first cell includes a bridge of switching elements having a third node, a fourth node, a fifth node, and a sixth node. The third node is coupled to theAttorney Docket No. AE2024-020PCT first node and the fourth node is coupled to the second node or to the second node through a second cell. A first inductor of a coupled inductor is coupled between the first driver and the third node and a second inductor of the coupled inductor is coupled between the second driver and the fifth node.

[0069] An aspect of the present disclosure relates to systems, methods, and apparatuses for an RF switch, and more particularly for an RF switch that comprises a series arrangement of switches using coupled inductors to simultaneously provide high impedance to the RF signal applied to the switch while providing a low impedance path for current controlling the state of the switch.

[0070] In some aspects, the techniques described herein relate to an apparatus including: switching elements, each comprising at least a common and an output terminal, arranged in a bridge configuration wherein common and output terminals are joined together at a first and a third terminal of the bridge; common terminals are joined at a second terminal of the bridge; output terminals are joined at a fourth terminal of the bridge; a first terminal of a bridge forming a first RF switch terminal; a third terminal of a bridge forming a second RF switch terminal; a first and a second terminal of a coupled inductor connected to the second and fourth terminals of a bridge, respectively; a driver connected to a third terminal of a coupled inductor and a complementary driver connected to a fourth terminals of a coupled inductor; and wherein the driver and complementary driver are configured to add and remove charge from the switching elements; and wherein the adding and removing of charge from the switches aids in turning the switches on and off; and wherein turning the switches on creates a low RF impedance between the first and second RF switch terminals;Attorney Docket No. AE2024-020PCT and wherein turning the switches off creates a high RF impedance between the first and second RF switch terminals.

[0071] Aspects may also be characterized as a method for operating an RF switch, the method including: connecting switching elements in a bridge configuration; using a first terminal of a bridge as a first RF switch terminal; using a third terminal of a bridge as a second RF switch terminal; connecting a first terminal of a coupled inductor to a second terminal of a bridge; connecting a second terminal of a coupled inductor to a fourth terminal of a bridge; connecting a driver to a third terminal of a coupled inductor; connecting a complementary driver to a fourth terminal of a coupled inductor; conducting a current from the driver output through the coupled inductor and through the bridge to the output of the complementary driver; using the current to either add or remove charge from the switches; wherein adding or removing charge from the switching elements aids in turning the switches on or off; and wherein turning the switches on creates a low RF impedance between the first and second RF switch terminals; and wherein turning the switches off creates a high RF impedance between the first and second RF switch terminals. Limited Switching Speeds and High Turn-off Losses

[0072] Given the desire to use a PIN diode as an RF switching element, FIG.1 shows one example of a PIN diode switching circuit controlled by a pair of sources, a pair of switches, and an inductor. This circuit 100 suffers from high RF losses when the PIN diode is turned off as well as limited switching speeds (e.g., around 1 kHz or less). In the ON state the PIN diode 102 presents a low impedance and capacitor 104 is connected between the terminals 106 and 108. In this state, a reactance of the capacitor 104 is seen by the rest of a circuit (notAttorney Docket No. AE2024-020PCT shown) coupled to the terminals 106 and 108 of the switching circuit 100. In the OFF state the PIN diode presents a high impedance at RF frequencies and thus (because the inductor 110 also presents a high impedance at RF frequencies) a high impedance is presented between the terminals 106 and 108 of the switching circuit 100, effectively disconnecting the capacitor 104 from the rest of the circuit. In some instances, capacitor 104 may be a reactance that is connected and disconnected between the terminals 106 and 108 and in other cases the capacitor 104 may be a blocking capacitor (blocking the voltage of the sources 116 and 118 from appearing between the terminals 106 and 108). The sources 116 and 118 along with corresponding switches 112 and 114, provide a low amplitude current for controlling a state of the PIN diode 102: source 118 and switch 114 in the ON state (switch 112 in the OFF state) forward bias the PIN diode 102 causing its ON state; and source 116 and switch 112 in the ON state (switch 114 in the OFF state) reverse bias the PIN diode 102 causing its OFF state.

[0073] To protect the control circuitry, including the sources 116 and 118 and the switches 112 and 114, from RF current between terminals 106 and 108, the inductor 110 is arranged between the capacitor 104, the PIN diode 102 and the switches 112 and 114. At the same time, the inductor 110 allows low-frequency current from sources 116 and 118 to control the PIN diode 102 state.

[0074] As concluded in the section “Analysis of PIN Diode Transition Turn-off Losses”, significant design improvements in terms of switching speed and energy consumption to discharge or combinations thereof can be achieved by using multiple smaller PIN diodes rather than one big PIN diode.Attorney Docket No. AE2024-020PCT

[0075] Yet, driving multiple series-connected PIN diodes may create a risk that, due to small differences in the PIN diodes, one of the series-connected diodes (or group of parallel PIN diodes) discharges before another PIN diode (or group of parallel PIN diodes), thus blocking the discharge current from completing discharge of the remaining PIN diodes.

[0076] Another approach to reducing losses is to reduce a voltage of the power supply used to discharge the PIN diode, but this approach may lead to longer turn-off times because the lower voltage may be less effective at clearing charge in the intrinsic region. Switching Circuit Design

[0077] An aspect of this disclosure addresses RF losses and reduces switching time in a PIN diode switching circuit by replacing a lone large PIN diode with multiple smaller series- connected PIN diodes arranged in one or more stacked bridges, the one or more bridges controlled via complementary drivers coupled to the one or more bridges via inductor pairs (or optionally coupled inductors) as seen in FIGs.7A, 7B, 7C, and 7D. Two or more ‘cells’ (see, e.g., a single cell shown in FIG. 7B) may be coupled in series to increase voltage- and / or current-carrying capacity, where FIG. 7A shows a non-limiting example of three cells. Each cell may include series-connected PIN diodes 720 in a bridge 710 configuration, coupled inductors 730 such as a pair of inductors or coupled inductors, and a bypass inductor 760. Within this switching circuit 700, the bridges 710 are denoted first bridge 710a, second bridge 710b, and third bridge 710c and are coupled in series between switching nodes 702 and 704 of the switching circuit 700. Details of the bridges 710 are shown within the cell details of FIG.7B for clarity.Attorney Docket No. AE2024-020PCT

[0078] This topology can present little inductance to the complementary drivers 740 and 750, which is achieved by connecting PIN diodes 720 in a bridge 710 configuration and charging and discharging the PIN diodes 720 via the complementary drivers 740 and 750 and coupled inductors 730. Coupled inductors may also be referred to as a balun or a transformer. Additionally, the coupled inductor 730 in each of the control current paths acts as an RF choke to prevent RF currents between switching node 702 and switching node 704 from reaching the drivers 740 and 750.

[0079] Additionally, an alternate current path through the bypass inductor 760 can be provided to prevent one PIN diode (or group of parallel connected PIN diodes) from blocking discharge currents to the remaining PIN diodes 720 should one PIN diode 720 reach the OFF state before the others.

[0080] It should be noted that the switching elements, in this example PIN diodes 720, may be replaced by groups of parallel switching elements, or in this example, groups of parallel connected PIN diodes. Additionally, one or more cells may be coupled in series to form the switching circuit 700. To this end, FIG.7C shows details of a first cell along with an optional second cell, both controlled by complementary drivers 740 and 750.

[0081] The switching circuit 700 can be used in various high frequency or RF switching applications, for instance, match networks. FIG. 14 shows an embodiment, where the switching circuit 700 is coupled in series with an impedance element 1460 (e.g., a capacitor, inductor, or resistor), and switching of the bridges causes a reactance component of an impedance attributable to the impedance element 1460 seen by a load to change. More specifically, a first node of the impedance element 146 is connected to the secondAttorney Docket No. AE2024-020PCT node 723 and an impedance between a second node of the impedance element 1460 and the fourth node 725 is controlled by the polarity of a current or voltage between the first and third nodes 722 and 724. BRIDGES

[0082] As seen in FIG. 7B, within each bridge 710 configuration, the PIN diodes 720 can be referred to as a first PIN diode 742, a second PIN diode 744, a third PIN diode 746, and a fourth PIN diode 748, and each bridge 710 comprises a first node 722, a second node 723, a third node 724, and a fourth node 725. A cathode node of the first PIN diode 742 is coupled to an anode node of the second PIN diode 744. A cathode node of the fourth PIN diode 748 is coupled to an anode node of the third PIN diode 746. An anode node of the first PIN diode 742 is coupled to an anode node of the fourth PIN diode 748. A cathode node of the second PIN diode 744 is coupled to a cathode node of the third PIN diode 746.

[0083] The first node 722 and the third node 724 are control nodes for each bridge 710 and are coupled to the complementary drivers 740 and 750 via coupled inductors 730 of the cell. Current is passed from one of the drivers 740 / 750 to the complementary driver 750 / 740 via the coupled inductors 730 and the first and second nodes 722 and 724 (i.e., a current loop is established through these elements). Depending on the direction of the current, it either adds or removes charge from the PIN diodes 720 thereby causing the PIN diodes 720 to enter an ON or an OFF state.

[0084] When the PIN diodes 720 of a bridge 710 are in the ON state, alternating current (e.g., RF current) may pass between the second node 723 and the fourth node 725—sometimes referred to as RF power nodes of a given bridge 710. In other words, and regardless of theAttorney Docket No. AE2024-020PCT number of cells, RF current may pass between the first and second switching nodes 702 and 704 of the switching circuit 700 as seen in FIG.7A. When the PIN diodes 720 of a bridge 710 are in the OFF state, RF current may be precluded from passing between the second node 723 and the fourth node 725, and thus RF current may not pass through the switching circuit 700. Thus, the second and fourth nodes 723 and 725 are input / output nodes for each bridge 710 and may be coupled to (1) the first switching node 702, (2) the second switching node 704, (3) an / or another bridge 710. For instance, in the first bridge 710a, the second node 723 is coupled to (or is) the first switching node 702, and the fourth node 725 is coupled to the second node 723 of the second bridge 710b. Similarly, in the second bridge 710b, the second node 723 is coupled to the fourth node 725 of the first bridge 710a, and the fourth node 725 is coupled to the second node 723 of the third bridge 710c. Also, in the third bridge 710c, the second node 723 is coupled to the fourth node 725 of the second bridge 710b, and the fourth node 725 is coupled to (or is) the second switching node 704. Given this ability to be controlled via the first and third nodes 722 and 724 and to pass or block RF current between the second and fourth nodes 723 and 725, these bridge configurations 710 of switching elements can be referred to as four-terminal PIN diode bridges.

[0085] Although this disclosure often describes PIN diodes as the switching elements in the bridges, other switching elements such as FETs, etc. can also be used. Accordingly, FIG. 7C shows a bridge 710 using more generalized switching elements 743, 745, 747, and 749.

[0086] Although the example of FIGs. 7A and 7B use PIN diodes for switching elements, other devices such as, but not limited to, field-effect transistors (FETs) (see for instance, FIG.8),Attorney Docket No. AE2024-020PCT MOSFETs, HEMTs, BJTs, micro-electromechanical systems switches (MEMS switches), and some Gallium Nitride (GaN) switches may also be used. COUPLED INDUCTORS

[0087] As shown in FIG.7B, a first inductor node 731 and a second inductor node 732 of coupled inductors 730 are connected to the first node 722 and the third node 724 of the bridge 710, respectively. A first driver 740 is coupled to a third inductor node 733 of the coupled inductors 730 and a complementary driver 750 is coupled to a fourth inductor node 734 of the coupled inductors 730. Where a single cell is used, or when speaking of a final cell in a switching circuit, the third and fourth inductor nodes 733 and 734 of the coupled inductors 730 would be directly coupled to the drivers 740 and 750, respectively. However, where two or more cells are used and when referring to any but the final cell in the switching circuit, the third and fourth inductor nodes 733 and 734 are coupled to coupled inductors of another cell (i.e., to the first and second inductor nodes 731 and 732 of another cell) as seen in FIG.7A. In some cases, instead of cascading the coupled inductors 730, as shown in FIG.7A, the third and fourth inductor nodes 733 and 734 of the coupled inductors 730 for each cell may connect independently to the complementary drivers 740 and 750 (e.g., see FIG.7D). The choice depends on how to handle the RF voltage and DC resistance of the coupled inductors 730. In higher voltage applications the cascade connection as shown in FIG. 7A may be used. In lower voltage applications, direct connections between the drivers 740, 750 and each of the coupled inductors 730 may be used (FIG.7D).

[0088] The coupled inductors 730, when implemented as a coupled inductor or mutual inductor, can be an electronic component featuring two or more windings sharing a commonAttorney Docket No. AE2024-020PCT magnetic core, and enabling energy transfer between the windings through electromagnetic induction. Coupling the windings of the coupled inductors 730 may allow faster ramping of the currents used to charge and discharge the PIN diodes 720. Such implementation can use a transformer, dual-winding inductor, mutual-winding inductor, or magnetically coupled coils.

[0089] Ideal coupled inductors would not present inductance to the complementary drivers 740 and 750 allowing PIN diode charge and discharge currents to establish quickly even with low driver 740 and 850 output voltages. Yet practically, the coupled inductors 730 present finite inductance to the complementary drivers 740 and 750, but this inductance may be orders of magnitude smaller than the inductance presented to the common mode RF when RF is applied between the switching nodes 702 and 704. BYPASS INDUCTORS

[0090] If one PIN diode 720 in a bridge 710 turns OFF before the others, it may be difficult to complete discharging the remaining PIN diodes 720 as they turn off. To address this, an optional bypass inductor 760 may be coupled between the second and fourth nodes 723 and 725 to provide an alternative current path to the complementary drivers 740 and 750; thus, allowing the complementary drivers 740 and 750 to extract all the charge from the remaining PIN diodes 720 being turned off in a given bridge 710. Also, and as shown in FIG. 7A, if multiple cells are used, the optional bypass inductor 760 may be coupled in series with an optional bypass inductor(s) 760 of another cell(s). Although the optional bypass inductors 760 are shown connected to each other, in other examples, such as lower voltage applications, each bypass inductor 760 may connect separately to the second nodeAttorney Docket No. AE2024-020PCT 723 of the corresponding bridge 710 in a respective cell and to the second switching node 704 as shown in FIG.7D. COMPLEMENTARY DRIVERS

[0091] The drivers 740 and 750 may be complementary meaning that they may provide the same magnitude of voltage or current, but in opposing polarities (i.e., one sources current while the other sinks current). For instance, for a switching circuit 700 able to handle 1500 V of RF voltage in the OFF state and having PIN diodes each with a 500 V rating, the complementary drivers 740 and 750 would put out 250 V, referenced to the second switching node 704, in opposing polarities when the PIN diodes 720 are reverse biased. The coupled inductors are shown connected in series in FIG.7A. However, and as noted earlier, each of the coupled inductors 730 may be connected between its corresponding bridge 710 and the complementary drivers 740 and 750 without intermediary coupled inductors 730 (see, e.g., FIG.7D). Resistors (not shown) may be placed in series between the coupled inductors 730 and the bridges 710 to ensure even current distribution when the PIN diodes 720 are forward biased.

[0092] As this discussion of the switching circuit 700 and variations thereof has shown, smaller series-connected PIN diodes may lead to reduced switching times, reduced energy expended to achieve turn-off or some combination of shortened switching times and less energy consumed compared to a design using a single higher voltage switching device such as a large PIN diode. Further, stacking bridges of PIN diodes may achieve a higher voltage rating. This holds true even when multiple PIN diodes are used in parallel to restore the on-state resistance to that of the single diode. The switching circuit 700 also illustrates theAttorney Docket No. AE2024-020PCT use of coupled inductors that may provide a high impedance magnitude for the applied RF as well as a low impedance magnitude path for driving the switching elements. The switching circuit 700 also illustrates the use of alternate current paths through bypass inductors 760 that may prevent one PIN diode (or group of parallel connected PIN diodes) from blocking the control current, which would otherwise prevent the discharge of one or more other PIN diode (or group of parallel connected PIN diodes). THREE-TERMINAL SWITCHING ELEMENTS

[0093] FIG. 8 shows three-terminal switching elements, such as field-effect transistors (FETs), instead of PIN diodes as the switching elements for the topology shown in FIGs.7A, 7B, and 7C. As in FIGs.7A, 7B, and 7C, the switching circuit 800 may comprise one of more cells coupled in a stacked bridge configuration where each cell includes coupled inductors 830, a bridge 810 configuration of switching elements 820, and a bypass inductor 860. Because three-terminal switching elements, such as FETs, MOSFETs, BJTs, etc. are used in this example, the complimentary drivers 840 and 850 are configured to provide current to charge and discharge a capacitance of the three-terminal switching elements 820. This example shows three cells, though any one or more cells can be implemented. For these devices the topology may provide the same benefits as described with reference to FIGs. 7A, 7B, and 7C, namely an alternative path for charging the switch 820 capacitance should one switch open before another. Similarly, coupled inductors 830 do not present a large inductance to the complementary drivers 840 and 850 so that the current to charge the device 820 capacitance (i.e., to turn the three-terminal devices 820 OFF) may be established quickly. Note that when going from the ON state to the OFF state, charge isAttorney Docket No. AE2024-020PCT removed from the intrinsic region of a PIN diode, but in the case of FETs and other three- terminal devices, charge is typically added to reach the OFF state.

[0094] Each three-terminal switching element 820 may have a common terminal (e.g., source or emitter), a control terminal (e.g., base or gate) and an output terminal (e.g., collector or drain). The three-terminal switching elements 820 may be arranged in series and arranged in bridge configurations 810 wherein common and output terminals are joined at a second terminal 823 and a fourth terminal 825 of the bridge 810. Common terminals are joined at a third terminal 824 of each bridge 810, and output terminals are joined at a first terminal 822 of each bridge. In addition, a second terminal 823 of a first bridge 810a forms a first switch node 802 and a fourth terminal 825 of the third bridge 810c forms a second switch node 804. As shown, a first terminal 831 and a second terminal 832 of the coupled inductors 830 are connected to the first terminal 822 and the third terminal 824 of each bridge 810, respectively. A first driver 840 is coupled to a third terminal 835 of coupled inductors 830 and a complementary driver 850 is coupled to a fourth terminal 836 of the same coupled inductors 830.

[0095] The three-terminal switching elements 820 are controlled using the control and common terminals and the device acts as a switch between the output and common terminals. The switching circuit 800 of FIG. 8 solves the problem of connecting switches (or groups of parallel switches) in series by preventing one switching element (or group of parallel connected switching elements) from blocking current thus preventing the charging of the output capacitance of other three-terminal switching elements 820 (or group of parallel connected three-terminal switching elements) while also presenting little inductance to the drivers 840 and 850. This can be achieved by connecting three-terminal switching elementsAttorney Docket No. AE2024-020PCT 820 in a bridge configuration 810 and using complementary drivers 840 and 850 driving the output capacitance of the three-terminal switching elements 820 in the bridges 810 through the coupled inductors 830. Where coupled or mutual inductors are implemented, these may also be described as a balun or a transformer.

[0096] Ideal coupled inductors 830 would not present inductance to the complementary drivers 840 and 850, allowing charge and discharge currents to establish quickly even with low driver 840 and 850 output voltages. Yet practically, the coupled inductors 830 present finite inductance to the complementary drivers 840 and 850, but this inductance may be orders of magnitude smaller than the inductance presented to the common mode RF when RF is applied between the first switch node 802 and the second switch node804 of switching circuit 800.

[0097] If one three-terminal switching element 820 in a bridge 810 turns OFF before the others, it may be difficult to complete charging the remaining three-terminal switching elements 820 as they turn off. To address this, an optional bypass inductor 860 may be coupled between the second and fourth nodes 823 and 825 to provide an alternative current path to the complementary drivers 840 and 850; thus, allowing the complementary drivers 840 and 850 to fully charge the output capacitance of the remaining three-terminal switches 820 being turned off in a given bridge 810. Also, where multiple cells are used, the optional bypass inductor 860 may be coupled in series with an optional bypass inductor(s) 860 of another cell(s). Although the optional bypass inductors 860 are shown connected to each other, in other examples, such as lower voltage applications, each bypass inductor 860 may connect separately to the second node 823 of the corresponding bridge 810 in a respectiveAttorney Docket No. AE2024-020PCT cell and to the second switch node 804 (similar to the topology shown for PIN diodes in FIG.7D).

[0098] In addition to the complementary drivers 840 and 850 for charging and discharging the output capacitance of the three-terminal switches 820, drivers 870 can be used to assist in turning the three-terminal switching elements 820 on and off. The drivers 870 are coupled to the gates and sources of the three-terminal switching elements 820. Parasitic Capacitance

[0099] The switching elements, whether PIN diodes, three-terminal switching elements, or other types of switches, often operate best when cooled. Cooling often involves physical contact between a heat sink and the switching elements. However, parasitic capacitance is formed between the switching element terminals and the heatsink. Usually, the heatsink is referenced to one of the switching nodes 702, 704, 802, or 804, and FIG.9 shows a circuit diagram useful in analyzing parasitic capacitance from the heatsink(s). The second switching node 904 is assumed to be ground and the analysis remains valid where the second switching node 904 is not ground, but the parasitic capacitances to ground are to switching node 904, as would happen if the heatsink and enclosure is connected to second switching node 904 rather than ground.

[0100] One goal of the analysis is to find the values of the compensation capacitors, Cc1, Cc2, … , Cc10 that produce the same voltage, ^^, over all the switching elements.

[0101] In FIG.9, the switches in the OFF state are replaced by capacitors ^^^^. ^^^^3represents the capacitance across each winding of the coupled inductors. Normally the inductors andAttorney Docket No. AE2024-020PCT coupled inductors at the RF frequency behave like small capacitors. If this is not the case, ^^^^3may be replaced by the equivalent negative capacitance corresponding to the inductance. ^^^^8corresponds to the capacitance across the inductors. As for the coupled inductors, if the impedance is still inductive at the RF frequency, ^^^^8may be replaced by the equivalent negative capacitance. ^^^^6corresponds to the capacitance to ground at the anode-to-cathode junction of (e.g., the PIN diodes of FIG. 7A) or the source-to-drain junction of the three-terminal switching elements of FIG. 8. ^^^^9corresponds to the capacitance of the anode-to-cathode or source-to-drain junctions of two bridges so, in most cases ^^^^9 ≈ 2^^^^6. ^^^^7 is essentially the sum of ^^^^9 and ^^^^8. ^^^^4 corresponds to thecapacitance to ground at the anode-to-anode junctions of FIG. 7 or the source-to-source junctions of FIG.8. ^^^^5corresponds to the capacitance to ground of the cathode-to-cathode junctions of FIG. 7 or the drain-to-drain junctions of FIG. 8. ^^^^1 is essentially ^^^^4 + ^^^^3and ^^^^2 is essentially ^^^^5 + ^^^^3. It is assumed that the outputs of complementary drivers740, 750, 840, 850, are essentially at ground potential. If this is not the case, ^^^^1and ^^^^2may be adjusted to account for driver source impedance.

[0102] Applying Kirchoff's current law at the nodes of FIG.9, gives: At node 1: 0 = v(n1)(Cc1 + 2Cd + Cp1 + Cp3) − v(n3)(Cc1 + Cd) − v(n4)Cp3At node 2: 0 = v(n2)(Cc2 + 2Cd + Cp2 + Cp3) − v(n3)(Cc2 + Cd) − v(n5)Cp3At node 3: 0 = −v(n1)(Cc1 + Cd) − v(n2)(Cc2 + Cd) + v(n3)(Cc1 + Cc2 + Cc3 +Cc4 + 4Cd + Cp7 + Cp8) − v(n4)(Cc3 + Cd) − v(n5)(Cc4 + Cd) − v(n6)Cp8At node 4: 0 = −v(n1)Cp3 − v(n3)(Cc3 + Cd) + v(n4)(Cp4 + Cc3 + ^^^^5 + 2Cd +2Cp3) − v(n6)(Cc5 + Cd)Attorney Docket No. AE2024-020PCT At node 5: 0 = −v(n2)Cp3 − v(n3)(Cc4 + Cd) + v(n5)(2Cp3 + Cp5 + Cc6 + Cc4 +2Cd) − v(n6)(Cc6 + Cd) − v(n8)Cp3At node 6: 0 = −v(n3)Cp8 − v(n4)(Cc5 + Cd) − v(n5)(Cc6 + Cd) + v(n6)(2Cp8 +Cp9 + Cc5 + Cc6 + Cc7 + Cc8 + 4Cd) − v(n7)(Cc7 + Cd) − v(n8)(Cc8 + Cd)At node 7: 0 = −v(n4)Cp3 − v(n6)(Cc7 + Cd) + v(n7)(Cp3 + Cp4 + Cc7 + Cc9 +2Cd) − v(n9)(Cc9 + Cd)At node 8: 0 = −v(n5)Cp3 − v(n6)(Cc8 + Cd) + v(n8)(Cp3 + Cp5 + Cc8 + Cc10 +2Cd) − v(n9)(Cc10 + Cd)

[0103] There are 8 equations and 10 unknowns. Two variables may be eliminated by noting that the voltage drop over both ^^^^3and ^^^^4is ^^ and the current through ^^^^3and ^^^^4sum together at node 3. Thus, only the sum of ^^^^3and ^^^^4matter, not their values so one sets ^^^^4 = ^^^^3. Similarly, the voltage drop over both ^^^^7 and ^^^^8 is ^^ and the current through^^^^7and ^^^^8sum together at node 6. Thus, only the sum of ^^^^7and ^^^^8matter, not their values, so one sets ^^^^8 = ^^^^7.

[0104] Setting the node voltages to the required values, i.e., v(n1) = v(n2) = ^^, v(n3) = 2^^,v(n4) = v(n5) = 3^^, v(n6) = 4^^, and v(n7) = v(n8) = 5^^, and solving forCc1, Cc2, … , Cc10 yields:Cc1 = Cp1 − 2Cp3Cc2 = Cp2 − 2Cp3Cc3 = 0.5(Cp1 + Cp2) − 2Cp3 + Cp7 − Cp8Cc4 = Cc3Cc5 = 0.5(Cp1 + Cp2) − 2 Cp3 + 3 Cp4 + Cp7 − Cp8Attorney Docket No. AE2024-020PCT Cc6 = 0.5(Cp1 + Cp2) − 2Cp3 + 3Cp5 + Cp7 − Cp8Cc7 = 0.5(Cp1 + Cp2) − 2Cp3 + 1.5Cp4 + 1.5Cp5 + Cp7 − Cp8 + 2Cp9Cc8 = Cc7Cc9 = 0.5(Cp1 + Cp2) + 6.5Cp4 + 1.5Cp5 + Cp7 − Cp8 + 2Cp9Cc10 = 0.5(Cp1 + Cp2) + 1.5Cp4 + 6.5Cp5 + Cp7 − Cp8 + 2Cp9

[0105] To ensure that Cc1, Cc2, … , Cc10 are all positive, ^^^^1 and ^^^^2 should satisfy:Cp1 > 2Cp3+2Cp8 − 4Cp9)The above requirements may be satisfied by adding capacitance parallel to the parasitic capacitances ^^^^1and ^^^^2. The effective capacitance between node 9 and ground is Cp8 / 3 + (Cc9 + Cc10 + 2Cd) / 6 + Cp6. The added capacitive elements can be referredto as compensation capacitors

[0106] To illustrate the result of adding the compensation capacitors, consider the circuit of FIG. 8in which each switch is three parallel MOSFETS with the device capacitance, ^^^^ = 24pF.

[0107] The drain pad of the device is about 5.8 by 6.4 mm. Assuming that the device is mounted on 5 mm thick alumina and if the capacitance increases by 50 % due to fringing, the drainAttorney Docket No. AE2024-020PCT pad capacitance is approximately 1 pF. For 3 devices in parallel and accounting for some additional capacitance, we estimate the capacitance to ground at the node where the drains join, ^^^^^^^^ = ^^^^5 = 7.2 pF.

[0108] The gate and source pads of the device are about 2.2 by 1.2 mm resulting in a pad capacitance of about 0.14 pF per device assuming a capacitance increase of 50 % due to fringing. Where the 6 sources of the devices join and accounting for some additional capacitance, we estimate this capacitance to be ^^^^^^^^ = ^^^^4 = 1.2 pF.

[0109] Where the three sources and drains join we may expect about 4.2 pF giving ^^^^^^^^ = ^^^^6 =4.2 pF.

[0110] Assume the capacitance of each winding of the coupled inductors as well as the inductor capacitances are 3 pF. Thus ^^^^3 = ^^^^8 = 3 pF.

[0111] Let Cp1equal the sum of Cssgthe coupled inductor winding capacitance Cp3and an additional capacitor Ce. Then for Cc1to be positive we need Cc1 = Cp1 − 2Cp3 = Cssg + Cp3 + Ce − 2Cp3 = Cssg + Ce − Cp3 = 1.2 + Ce − 3⇒ ^^^^ ≥ 3 − 1.2 = 0.8 pF.

[0112] With the information above the compensation capacitors, Cc1, Cc2, … , Cc10, may becalculated giving: ^^^^ = 1.8 pF^^^^1 = 0Cc2 = 4.2 pF^^^^3 = ^^^^4 = 10.5 pF^^^^5 = 14.1 pFAttorney Docket No. AE2024-020PCT ^^^^6 = 32.1 pF^^^^7 = ^^^^8 = 39.9 pF^^^^9 = 51.9 pF^^^^10 = 81.9 pFand the off-state capacitance of the switching circuit (capacitance between the switch terminals with the devices OFF) is approximately 51.5 pF.

[0113] FIG. 10 shows a switching circuit 1000 with compensation capacitors to seek equal distribution of the applied RF voltage over the switching elements. Switching circuit 1000 is essentially switching circuit 800 of FIG. 8 with compensation capacitors Cc1, Cc2, … , Cc10 and ^^^^ added. As shown above, in addition to Cc1, Cc2, … , Cc10, ^^^^, 1080,can be added to ensure realizable (non-negative) values for the compensation capacitors. Also shown in FIG. 10 are compensation capacitors ^^11, ^^12, ^^^^ , ^^^^, and ^^ℎ labeled 1086,1088, 1090, 1092 and 1094, respectively. Compensation capacitor ^^^^, 1090, may be added ^^ where ^^^^3is larger than^^22. Compensation capacitors ^^11, ^^12, ^^^^, and ^^ℎ may be addedwhere the parasiticare connected to first switching node 1002 rather than second switching node 1004.

[0114] With the compensation capacitors installed parallel to the switching elements, the voltage drops over the switching elements in the OFF state are equal, e.g., if the switching circuit 800 of FIG.8 is in the OFF state and a RF signal with amplitude 1500 V is applied at first switch node 802 with respect to second switch node 804, each switching element 820 in switching circuit 800 can have a RF voltage with amplitude 250 V across it (i.e., drain voltage with respect to source voltage).Attorney Docket No. AE2024-020PCT

[0115] If compensation capacitors are not used and a RF signal with amplitude 1500 V is applied at first switch node 802 with respect to second switch node 804, the switches closest to second switch node 804, will have a RF voltage with amplitude 188 V across it while the switches closest to first switch node 802, will have an RF voltage with amplitude 397 V across it, potentially enough to fail the switches closest to the first switch node 802. Analysis of PIN Diode Turn-off Losses

[0116] To illustrate the magnitude of a problem that this disclosure addresses, consider a typical high power PIN diode with a 3 kV breakdown voltage and ON-state resistance of 0.15 ohm when the forward bias current is 0.5 A. Such a PIN diode may have a carrier lifetime of 13 microseconds and an intrinsic region length of 325 micrometers. With ^^^^the forward bias current and ^^ the carrier lifetime (assumed constant although in reality ^^ depends on the ^^^^and other factors), the charge entering the PIN diode intrinsic region (either electrons entering from the cathode side or holes entering from the anode side) in an infinitesimal time ^^^^, ^^^^, is ^^^^^^^^ and the charge lost due to recombination in time ^^^^, is ^^^^^^ / ^^. The charge in the intrinsic region remains constant when the charge entering the PIN and the charge lost to recombination in the time ^^^^ are equal, i.e., when ^^^^^^^^ = ^^^^^^ / ^^ which meansthat the charge remains constant at ^^ = ^^^^^^. This charge is distributed in a volume ^^^^ with^^ being the cross-sectional area of the PIN diode and ^^ being the length of the intrinsic region leading to electron and hole densities in the intrinsic region of the PIN diode of ^^ = ^^ = ^^^^^^ / (^^^^^^) where ^^ is the electron charge. The electrical conductivity of theintrinsic region is given by ^^ = ^^(^^^^^^ + ^^^^^^) = ^^(^^^^ + ^^^^)^^^^^^ / (^^^^^^) and thus theresistance of the intrinsic region is given by ^^ =^^ ^= ^^2^^^ / (^^^^^^(^^^^ + ^^^^)). Thus, theAttorney Docket No. AE2024-020PCT theoretical resistance of this PIN diode at a forward current of 0.5 A is approximately 0.03252 / (0.5 × 13 × 10−6 × (1550 + 575) ≈ 0.076 ^. The rest of the 0.15 ^ comesfrom contact resistance and the resistance of the anode and cathode regions. The total charge stored in the intrinsic region at 0.5 A forward current is 6.5 microcoulomb. During one half cycle of the RF waveform with frequency ^^, an RMS current of ^^^^^^flowing through the PIN diode from the cathode to the anode removes charge equal to √2^^^^^^ / (^^^^). With a frequency of 13.56 MHz and an RMS RF current of 15 A, the chargein a half-cycle of the RF waveform is approximately 0.5 microcoulomb, or approximately 0.077 of the total charge stored in the intrinsic region of the PIN diode. If this fraction remains below approximately one third, the resistance modulation of the PIN diode due to this charge removal is small and the PIN diode behaves like a constant 0.15 ^ resistor.

[0117] To change the state of this PIN diode from ON to OFF, the 6.5 microcoulomb of charge stored in the intrinsic region of the PIN diode can be removed. If this charge is removed by closing switch 112 to connect the reverse bias supply 116 in FIG. 1 to the PIN diode 102 as soon as the forward bias supply 118 is disconnected by opening switch 114, the energy taken from the source 116 (which may be referred to as a reverse bias supply 116) is ^^^^^^^^^^ where ^^^^^^^^is the voltage of the reverse bias supply 116. For a 3 kV PIN diode the reverse bias supply 116 may be set to half the voltage rating of the PIN diode 102 or 1500 Vand thus the energy taken from the reverse bias supply 116 is 1500 × 6.5 × 10−6 =9.75 × 10−3 J. If the PIN diode 102 is continuously switched between the ON and OFFstates at a 10 kHz rate, the power taken from the reverse bias supply 116 is thus 97.5 W and most of this power may be dissipated in the PIN diode 102. This is more power than a typical PIN diode of this type may safely dissipate. A typical solid-state match (SSM) mayAttorney Docket No. AE2024-020PCT have 50 PIN diodes. If they all switch at a 10 kHz rate, the power taken from the reverse bias supply 116 is about 4.9 kW which may be more than the RF power supplied to the SSM leading to a very inefficient system.

[0118] Furthermore, at 13.56 MHz a typical value for the inductor 110 may be 40 microhenry. The voltage over the PIN diode 102 starts to rise sharply when about a third of the stored charge is removed from the PIN diode 102. If care is not taken, the stored energy in the inductor 110 when the PIN diode 102 voltage starts rising may cause the PIN diode 102 voltage to rise above the breakdown voltage of the PIN diode 102. To remedy this situation, a resistor (not shown) may be put in series with the reverse bias supply 116 limiting the current available from reverse bias supply 116, but this slows the ON to OFF transition of the PIN diode 102 leading to higher dissipation in the PIN diode 102 during the transitions. As noted above, there is therefore a need for an RF switching circuit using a PIN diode as the switching element that reduces losses associated with turning the PIN diode off.

[0119] FIG.2 shows the state 200 of the PIN diode when it is forward biased with 0.7 A forward current. In FIG.2 the cathode is on the left and anode on the right. The top graph 210 in FIG.2 shows the donor 212, acceptor 214, electron 216, and hole 218 concentrations as a function of distance 230 from the cathode end of the PIN diode. As shown in the top graph 210, the electron and hole concentrations in the intrinsic region of the PIN diode are, to a good approximation, equal and uniform across the length of the intrinsic region. The bottom graph 220 in FIG. 2 shows the total current 222, current due to electron flow (electron current) 224 and current due to hole flow (hole current) 226 as functions of distance 230 from the cathode end of the diode. Positive current is defined flowing from left to right. In the forward bias state current flows from the anode on the right to theAttorney Docket No. AE2024-020PCT cathode on the left and the total current is therefore negative. On the left (cathode) boundary, only electron flow is possible and on the right (anode) boundary only hole flow is possible. Electron current 224 thus has to start at -0.7 A on the left and end at 0 A on the right and hole current 226 has to start at 0 A on the left and end at -0.7 A on the right. Consider a small section of length ^^^^ at a distance ^^ from the cathode end of the diode. Let the hole current at ^^ be ^^ (^^). Then the number of holes entering this section from the^^left in a time ^^^^ is ^^^^(^^)^^^^ / ^^ and the holes entering this section from the right in time ^^^^ is −^^^^(^^ + ^^^^)^^^^ / ^^. In the time ^^^^ the hole concentration in this section, ^^(^^), thusby (^^^^(^^) − ^^ ^^^^(^^)^^^^^^1 ^^(^^ + ^^^^))^^^^ / (^^^^^^^^) or^^^^= −^^^^ ^^^^ due to the hole current^^^^. This rate of increase in holes may be balanced by thedue to recombination so that the hole concentration remains constant. Similarly, the rate of change of the electron ^^^^ ^^^^^^ 1( )^^concentration in this section, ^^(^^), is given by = . The change in sign in this ^^^^ ^^^^ ^^^^equation compared to the previous equation is current defined as positive when flowing from left to right, positive electron current means electrons are flowing from right to left.

[0120] FIG. 3 shows the state 300 of the PIN diode at the start of reverse biasing the PIN diode with 25 A. As shown in the top graph 310 of FIG.3, not enough time has elapsed since the start of reverse biasing the PIN diode to change the electron and hole concentrations compared to what is shown in the top graph 210 of FIG. 2. Since the electron and hole concentrations in the intrinsic region 312 are approximately equal and constant, current continuity along the length of the intrinsic region dictates that the electric field in the intrinsic region 322 is also constant. The approximate 3 to 1 ratio of electron mobility toAttorney Docket No. AE2024-020PCT hole mobility dictates that due to substantially equal concentrations 312 of hole and electrons, the electron current in the intrinsic region be approximately 3 times the hole current. Since hole current on the left must be zero, it follows that electron current on the left starts at the full 25 A reverse current and on left reduces by 1 / 4 of 25 A while hole current starts at 0 A and on the left increases to 1 / 4 of 25 A. On the right side the electron current must reduce from 3 / 4 of the reverse current to 0 and the hole current increase from 1 / 4 of the reverse current and increase to the full reverse current. Thus, as shown in the bottom graph 340 of FIG.3, both electron 344 and hole 346 current change approximately 3 times as much on the right (anode) side of the diode as on the left (cathode) side of the diode. Since, as shown above, the change in current relates to the change in electron and hole concentrations, approximately 3 times as many holes and electrons are removed on the anode side of the intrinsic region as on the cathode side of the intrinsic region. Note that the current changes at the edges of the intrinsic region while it is approximately constant in the middle of the intrinsic region. This means that, at least initially, charge is removed at the left and right edges of the intrinsic region, but not in the center of the intrinsic region. On the right, anode, side of the PIN diode, holes are moving to the right and removed from the diode while electrons are moving to the left. There is a large supply of holes that may be taken from the intrinsic region, but there is no supply of electrons on the right (anode) side of the diode. This means that eventually all electrons on the right (anode) side of the diode will be depleted while holes may still be removed from the intrinsic region to the left of where the holes are being removed. A similar thing is happening on the left (cathode) side of the diode with the roles of electrons and holesAttorney Docket No. AE2024-020PCT reversed, but it is happening approximately 3 times slower on the cathode side than on the anode side.

[0121] As shown in the graph 330 third from the top in FIG.3, the anode voltage 332 at this stage is still positive. It means that during this initial phase of reverse biasing the PIN diode the PIN diode is giving energy back to the external circuit connected to the diode, i.e., the PIN diode acts like a large capacitor charged to approximately 0.6 V.

[0122] FIG.4 shows the state of the PIN diode 140 nanoseconds after starting to reverse bias the PIN diode when about 8% of the total charge has been removed from the PIN diode. As shown in the top graph 410 of FIG.4, the electron and hole concentrations in the intrinsic region 412 have dropped, but the electron concentration has not dropped to a significantly reduced value compared to the hole concentration and the total voltage drop over the diode 432 is still positive, i.e., the PIN diode is still giving energy back to the external circuit.

[0123] FIG.5 shows the state of the PIN diode 16 microseconds after starting to reverse bias the PIN diode when about 94% of the charge has been removed from the PIN diode. As shown in the top graph 510 of FIG.5, the electron concentration 512 on the right (anode side) has dropped to almost zero as predicted from the fact that electrons are removed on the right side of the intrinsic region but there is no supply of electrons there. To the left of this region where the electron concentration has dropped to zero, there is a region, the plasma region, from the left (cathode) side of the diode to approximately 240 micrometers from the left side where the electron and hole concentrations are approximately equal. To the right of the plasma region there is an excess of positively charged holes 514 forming a space charge region. This creates a strong electric field 522 and resulting voltage 532. Even thoughAttorney Docket No. AE2024-020PCT approximately 50 V is applied from cathode to anode, the total current through the diode 542 has dropped to only 0.4 A. At this point in time 20 W is taken from the external circuit and dissipated in the diode to remove stored charge from the PIN diode.

[0124] The state of the PIN diode as shown in FIG. 5 may be analyzed with good accuracy by assuming that the electron and hole concentrations, ^^0, are equal and constant over the width of the plasma region, ^^. Measuring the distance, ^^, from the right of the plasma region to the right (i.e., towards the anode) and with ^^(^^) the ^^-directed electric field at ^^ and ^^(^^) the hole density at ^^, current continuity requires that (^^^^ + ^^^^)^^0^^0 =^^^^^^(^^)^^(^^), where ^^0is the ^^-directed electric field in the plasmabe constant for current continuity because the electron and hole densities are assumed constant). The electric field generated by the excess of holes in the space charge region is ^^ ^^given by ^^(^^) = ^^0 + ∫0 ^^ ^^(^^)^^^^ where ^^ is the dielectric constant of the semiconductor material (typically. the above equation gives ^^^^(^^) =^^ ^^^^(^^) =^^(^^^^+^^^^)^^0^^01^^^^^^^^ where ^^ indicates taking the derivative. This is a(^^) with boundary condition ^^(0) = ^^0 where ^̅^ =^^(^^^^+^^^^)^^0 ^^ . The solution to this boundary value problem is ^^(^^) = √2^^^^ ^^ + ^^2^^^^^^ 0 0 0where ^^ =^^(^^^^+^^^^)^^0. The electric potential at ^^, ^^(^^), is found by integrating the(2^^^^+^^0)√2^^0^^^^+^^2 2 e( ) 0lectric field, giving ^^ ^^ = −^^ ^^ −^^ +0. With ^^ the length of the03^^ 3^^ intrinsic region, ^^(^^ − ^^) is the voltage applied over the intrinsic region which may beapproximated by ^^ − ^^ where ^^ is the externally applied anode to cathode voltage^^^^^^ ^^ ^^^^^^Attorney Docket No. AE2024-020PCT and ^^^^is the voltage drop due to the semiconductor junctions (typically around 0.7 V). With ^^(^^ − ^^) estimated, the corresponding ^^0 may be found and thus the currentthrough the PIN diode.

[0125] FIG.6 shows the approximation to the state of the PIN diode 16 microseconds after starting to reverse bias the PIN diode based on the above approximations. The electron and hole concentration in the plasma region, ^^0, may be approximated using the value in the middle of the plasma region. The width of the plasma region estimated from FIG.5 is ^^ ≈ 0.0232and ^^0 ≈ 4.32 × 1015. As is evident from FIG. 5, W is relatively easy to estimate, but since the electron and hole concentrations vary over the plasma region, estimating ^^0is difficult. Fortunately, the estimate of ^^0has very little impact on the calculations. FIG.6 shows the resulting estimate of the state of the PIN diode for values of ^^0ten times lower and ten times higher than the estimate based on the value in the middle of the plasma region and the impact on the estimate of the total PIN diode current for the applied voltage is minimal.

[0126] The reason why the estimate of ^^0has such little impact on the estimation of the PIN diode current 16 microseconds after starting to reverse bias the PIN diode is that almost all the applied voltage drops over the space charge region. This is the case for most of the time after the space charge region has formed until all the charge is removed from the intrinsic region of the PIN diode (but e.g., it is not the case when the space charge region is small compared to the plasma region (immediately after the space charge region has formed) and just before the intrinsic region has been depleted when the charge density in the plasma region becomes comparable to that of the space charge region). Since the voltage drop overAttorney Docket No. AE2024-020PCT the space charge region dominates for extended periods of time during the discharging of the PIN diode, it is worth investigating further.

[0127] If most of the voltage drop is over the space charge region, the small electric field that exists at the start of the space charge region (i.e., at ^^ = 0) as well as the voltage drop over2 the plasma region may be ignored. This leads to ^^(^^) = √2^^^^ ^^ + ^^ ≈ 2^^^^ ^^ and0 0 √ 0^^(^^) = ^^(0) −^^^^(^^) ^^^^ ≈ −^^^^ ^^) ^^^^ ≈ −2 3 ∫ 0∫0(3 √2^^^^0^^2. Since ^^^^0 = ^̅^ =t ( )2hat ^^ ^^ ≈ −2^^^^ . √ √ ^^^^ ^^^^ 3 ^^^^^^ ^^ ^^32 2( ) Thus ^^ − ^^ ≈ ^^ ^^ − ^^ ≈ − ^^(^^ − ^^) and ^^ ≈ − √^^√^^^^^^3 ^^^^ 3 ^^^^^^ ^^3^^ − −3 ^^^^^^compared to the diode drop^^

[0128] For the extended period of time during the reverse biasing the PIN diode in which most of the applied voltage drop is over the space charge region, and with ^^ the cross-sectional area of the PIN diode, we thus have the relationship between the applied voltage and the 32 2 ^^2( ) diode current given by ^^ ≈ ^^ − ^^ where ^^ = −^^ and ^^ = ^^^^ is the diode√^^^^^^^^^^2( ) current. We thus have ^^ ∝ we assume that ^^ − ^^ ∝ ^^ in the sense thatover the time that charge is being removed from the diode (^^ − ^^) ranges from 0 to ^^ sothe range that (^^ − ^^) assumes over this time is proportional to ^^. To remove the chargein a fixed time, the current is proportional to the charge to be removed. To speed up removal of this charge by a factor ^^ , we thus have ^^ ∝ ^^ ^^ where ^^ is the charge that must be^^ ^^Attorney Docket No. AE2024-020PCT removed from the PIN diode. For a fixed PIN diode ON-resistance, the charge stored in 3 5 the PIN diode is proportional to ^^2. This leads to ^^ ∝ √^^^^^^ / √^^^^2 ∝ √^^^^ / √^^^^2. The 7 energy used to remove a charge ^^ with a voltage ^^ is ^^ = ^^^^ ∝ √^^^^ / √^^^^2. The voltage that a PIN diode may handle is proportional to ^^. To construct a switch using PIN diodes with smaller intrinsic region length ^^2but the same ON-resistance as the original diode with intrinsic region length ^^ involves putting ^^ / ^^2of the smaller PIN diodes in series to handle the voltage and putting ^^ / ^^2such strings in parallel to have the same ON-resistance as the original singl^^ 2 ePIN diode. This means ^^ = (^^2) smaller PIN diodes can be used and 7 the energy to extract the charge from theis ^^ = ^^^^^^ ∝ ^^√^^^^ / √^^^^2∝ 3 √^^^^ / √^^^^2.

[0129] The relationship above shows that if one were to replace a 3 kV capable PIN diode with 36 500 V capable PIN diodes, the energy to discharge the 36 diodes, assuming diodes of the 3000 1.5 same cross section and discharging in the same time, is ( )≈ 14.7 times smaller.charge 14.72 ≈ 116times faster and using the same energy or a combination such as switching 30 times faster and using 2.7 times less energy.

[0130] Limited combinations of PIN diode properties are available commercially. For example, PIN diodes with shorter intrinsic regions are typically only available in diodes with smaller cross-sectional areas. To consider available diodes it is useful to leave the charge ^^ as part 3 3 3 of the proportionality equation. This gives ^^ ∝ √^^^^√^^^^2 / √^^ and ^^ = ^^^^ ∝ √^^^^^^2^^2 / Attorney Docket No. AE2024-020PCT √^^. Consider changing a design using a single 3 kV diode with 0.15 ^ ON-resistance when the stored charge in the diode is 7.8 microcoulomb with a design using 72 500 V PIN diodes with an ON-resistance of 0.3 ^ with 0.173 microcoulomb stored in the diode. The 500 V PIN diode has a cross sectional area of 272mils2and the 3 kV PIN diode a cross sectional area of 1722mils2. The intrinsic region length of the 3 kV PIN diode is 325 micrometer and that of the 500 V PIN diode 50 micrometer. The energy required to 3 3 0.173 50 172 discharge the 72500 V PIN diodes is then 72√^^ ( )2 ( )2 ^^7.8 325 27≈ √^^^^ / 11 times theenergy to discharge the single 3 kV diode.

[0131] As shown above, significant design improvements in terms of switching speed and energy consumption to discharge, or combinations thereof, may be achieved by using multiple smaller PIN diodes rather than one larger PIN diode. METHODS OF OPERATION

[0132] FIG.12 is a flowchart of an example method for switching a bridge of switching elements between two switching nodes. The method 1200 includes sourcing a first current from a first driver (Block 1210), such as the driver 740 in FIG. 7A, and sinking the first current with a second driver (Block 1220), such as the complementary driver 750. The method 1200 further includes passing the first current through a coupled inductor and a bridge of switching elements (e.g., PIN diodes or FETs) and a first two nodes of the bridge to discharge (e.g., reverse bias) the switching elements (Block 1230) (e.g., to force holes and electrons out of the intrinsic region of a PIN diode). For instance, the coupled inductor can be implemented as the coupled inductors 730 in FIG. 7A, and the bridge can beAttorney Docket No. AE2024-020PCT implemented as the bridge configuration 710 of switching elements. The first two nodes can be implemented as first and third nodes 722 and 724—or control nodes of the bridge 710. As a result of the first current passing through the switching elements, the switching elements may be turned off, for instance, by depleting an intrinsic region of PIN diodes (or charging a FET), which can occur relatively quickly because the PIN diodes (or FETs) may be smaller than those that would be selected without the disclosed stacked bridge configuration. In turn, the method 1200 increases a magnitude of an impedance presented to an alternating current passing through the switching elements between a second two nodes in the bridge configuration (Block 1240). The second two nodes can be implemented as nodes 723 and 725—or RF power nodes of the bridge 710. In some embodiments, the method 1200 can be embodied as a non-transitory, tangible computer readable storage medium, encoded with processor readable instructions to perform the method 1200 for switching or for switching a bridge of switching elements between two switching nodes.

[0133] FIG.13 is a flowchart of an example method for switching a bridge of switching elements between two switching nodes. The method 1300 includes providing a cell between a first node and a second node, the first cell comprising a bridge of switching elements and four nodes, a first two for controlling a state of the switching elements, and a second two for passing alternating current between the first and second nodes as controlled by the state of the switching elements (Block 1302). One of the second two nodes connects to the first node and the other of the second two nodes connects to the second node. For instance, the first and second nodes may be implemented as switching nodes 702 and 704 while the first two nodes of the bridge may be implemented as 722 and 724, and the second two nodes of the bridge may be implemented as 723 and 725. The method 1300 includes forming aAttorney Docket No. AE2024-020PCT current loop including a first driver, a coupled inductor, the first two of the four nodes of the bridge, the bridge, and a second driver (Block 1304). When current is passed in a first direction in the current loop (e.g., driver 740 sourcing), charge stored in the switching elements decreases and a magnitude of the impedance presented to the alternating current between the first and second nodes increases (e.g., PIN diodes are reverse biased). Further, when current is passed in a second direction in the current loop (e.g., driver 750 sourcing), charge stored in the switching elements increases and the magnitude of the impedance presented to the alternating current between the first and second nodes decreases (e.g., PIN diodes are forward biased).

[0134] Those of skill in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0135] Those of skill will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionalityAttorney Docket No. AE2024-020PCT in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

[0136] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0137] The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor may read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC.Attorney Docket No. AE2024-020PCT

[0138] Many embodiments and methods described herein may be realized using a processor in connection with processor executable instructions and a field programmable gate array (programmed by hardware description language instructions). The nonvolatile memory may be encoded with instructions that are executable by a processor and / or are readable by a field programmable gate array, e.g., to program the field programmable gate array. In some embodiments, the FPGA is used for high-speed processing and control, including switching control, measurement, pulsing, and multi-level operation while a processor is utilized for other lower-speed processing. Referring to FIG. 11 for example, shown is a block diagram depicting physical components of a controller that may be utilized to realize control aspects disclosed herein.

[0139] As shown, in this embodiment a display 1112 and nonvolatile memory 1120 are coupled to a bus 1122 that is also coupled to random access memory (“RAM”) 1124, a processing portion (which includes N processing components) 1126, a field programmable gate array (FPGA) 1127, and a transceiver component 1128 that includes N transceivers. Although the components depicted in FIG.11 represent physical components, FIG.11 is not intended to be a detailed hardware diagram; thus, many of the components depicted in FIG.11 may be realized by common constructs or distributed among additional physical components. Moreover, it is contemplated that other existing and yet-to-be developed physical components and architectures may be utilized to implement the functional components described with reference to FIG.11.

[0140] This display 1112 generally operates to provide a user interface for a user, and in several implementations, the display is realized by a touchscreen display. In general, the nonvolatile memory 1120 is non-transitory memory that functions to store (e.g.,Attorney Docket No. AE2024-020PCT persistently store) data and processor-executable code (including executable code that is associated with effectuating the methods described herein). In some embodiments for example, the nonvolatile memory 1120 includes bootloader code, operating system code, file system code, and non-transitory processor-executable code to facilitate the execution of methods for RF switching as described herein. The nonvolatile memory 1120 may be encoded with instructions that are executable by a processor and / or are readable by a field programmable gate array, e.g., to program the field programmable gate array wherein the instructions (when executed by the processing portion 1126 or when effectuated by the FPGA 1127) cause the drivers 740, 750, 840, 850, and 870 to carry out the methods disclosed herein. The FPGA 1127 may also comprise a non-transitory tangible medium that is integrated with the FPGA.

[0141] In many implementations, the nonvolatile memory 1120 is realized by flash memory (e.g., NAND or ONENAND memory), but it is contemplated that other memory types may be utilized as well. Although it may be possible to execute the code from the nonvolatile memory 1120, the executable code in the nonvolatile memory is typically loaded into RAM 1124 and executed by one or more of the N processing components in the processing portion 1126.

[0142] The N processing components in connection with RAM 1124 generally operate to execute the instructions stored in nonvolatile memory 1120 to enable execution of the algorithms and functions disclosed herein. It should be recognized that several algorithms are disclosed herein, but some of these algorithms are not represented in flowcharts. Processor- executable code to effectuate methods described herein may be persistently stored in nonvolatile memory 1120 and executed by the N processing components in connectionAttorney Docket No. AE2024-020PCT with RAM 1124. As one of ordinarily skill in the art will appreciate, the processing portion 1126 may include a video processor, digital signal processor (DSP), micro-controller, graphics processing unit (GPU), or other hardware processing components or combinations of hardware and software processing components (e.g., an FPGA or an FPGA including digital logic processing portions).

[0143] In addition, or in the alternative, non-transitory FPGA-configuration- instructions may be persistently stored in nonvolatile memory 1120 and accessed (e.g., during boot up) to configure a field programmable gate array (FPGA) to implement the algorithms disclosed herein.

[0144] The input component 1130 may receive power-related observations indicative of, for example and without limitation, current, voltage, reflected power, and / or impedance (e.g., by current transducers, directional couplers, VI sensors, and / or voltage sensors). The output component 1131 may provide analog and / or digital signals to provide information or to provide control signals. As examples without limitation, the output component 1131 may provide control signals to the drivers 740, 750, 840, 850, 870 to operate as described herein.

[0145] Although not required, in some implementations the FPGA 1127 may sample the power- related signals and provide the digital representations of, for example and without limitation, output current, voltage, and / or reflected power. In some embodiments, the processing components 1126 (in connection with processor-executable instructions stored in the nonvolatile memory 1120) are used to implement control methodologies to control the switches disclosed herein.Attorney Docket No. AE2024-020PCT

[0146] The depicted transceiver component 1128 includes N transceiver chains, which may be used for communicating with external devices via wireless or wireline networks. Each of the N transceiver chains may represent a transceiver associated with a particular communication scheme (e.g., WiFi, Ethernet, Profibus, etc.).

[0147] As will be appreciated by one skilled in the art, aspects of the present disclosure may be embodied as a system, method or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

[0148] As used herein, the recitation of "at least one of A, B and C" is intended to mean "either A, B, C or any combination of A, B and C." The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0149] It will be understood that, although the terms first, second, third, etc., may be used herein to describe various elements, components, and / or sections, these elements, components,Attorney Docket No. AE2024-020PCT and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, or section from another element, component, or section. Thus, a first element, component, or section discussed below could be termed a second element, component, or section without departing from the teachings of the present disclosure.

[0150] Spatially relative terms, such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the circuits in use or operation in addition to the orientation depicted in the figures. For example, if the circuit in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” may encompass both an orientation of above and below. The circuits and power generation components may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0151] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements,Attorney Docket No. AE2024-020PCT components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “ / ”.

[0152] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element, it may be directly on, connected, coupled, or adjacent to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element, there are no intervening elements present.

[0153] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Claims

Attorney Docket No. AE2024-020PCT WHAT IS CLAIMED IS:

1. An apparatus comprising: a first driver; a second driver configured to provide an opposite polarity to the first driver; and a first cell comprising: a bridge configuration of first switching elements having a first node, a second node, a third node, and a fourth node, wherein the first and third nodes are coupled to the first and second driver through a first coupled inductor; wherein the second and fourth nodes are configured to pass alternating current between the second and fourth nodes when a first current is passed between the first and third nodes and wherein the second and fourth nodes are configured to block the alternating current when a second current is passed between the first and third nodes having an opposite polarity to the first current.

2. The apparatus of Claim 1, wherein the first switching elements are PIN diodes.

3. The apparatus of Claim 1, wherein after the second current has been applied for some time, the magnitude of the second current decreases towards zero and the drivers maintain a voltage between the first and third nodes.

4. The apparatus of Claim 1, wherein after the first current has been applied for some time, the magnitude of the first current decreases towards zero.

5. The apparatus of Claim 1, wherein the first switching elements are three-terminal devices.

6. The apparatus of Claim 1, further comprising an inductor coupled between the second and fourth nodes.Attorney Docket No. AE2024-020PCT 7. The apparatus of Claim 1, wherein the bridge configuration presents a variable impedance between the second and fourth nodes, and wherein the variable impedance is controlled by the polarity of the first and second currents or a polarity of a voltage applied between the first and third nodes.

8. The apparatus of Claim 1, wherein a first node of an impedance element is connected to the second node and an impedance between a second node of the impedance element and the fourth node is controlled by the polarity of the first and second currents or a polarity of a voltage applied between the first and third nodes.

9. The apparatus of Claim 8, wherein the impedance element is one of a resistor, a capacitor, or an inductor.

10. The apparatus of Claim 1, further comprising capacitors parallel to the switching elements to equalize voltages across the switching elements.

11. The apparatus of Claim 1, further comprising a second cell comprising a bridge configuration of second switching elements, and a first node, a second node, a third node, and a fourth node, wherein the second node of the second cell is coupled to the fourth node of the first cell, and wherein the second cell further comprises a second coupled inductor, wherein the first and third nodes of the second cell are coupled to the first and second drivers through the second coupled inductor.

12. The apparatus of Claim 11, wherein the first and second coupled inductors are cascaded.

13. The apparatus of Claim 11, wherein the first and second coupled inductors connect independently to the first and second drivers.Attorney Docket No. AE2024-020PCT 14. The apparatus of claim 11, further comprising inductors connecting the second nodes of each bridge to the fourth node of the second bridge 15. The apparatus of claim 14, wherein the inductors connect between the second node and the fourth node of each bridge.

16. The apparatus of claim 14, wherein the inductors connect the second node of each bridge to the fourth node of the second bridge.

17. The apparatus of Claim 11, wherein a first node of an impedance element is connected to the second node of the first bridge and an impedance between a second node of the impedance element and the fourth node of the second bridge is controlled by a polarity of the first and second currents or a polarity of a voltage applied between the first and third nodes of the bridges.

18. The apparatus of Claim 17, wherein the impedance element is one of a resistor, capacitor, or inductor.

19. The apparatus of Claim 11, further comprising capacitors parallel to the switching elements to equalize voltages across the switching elements.

20. The apparatus of Claim 1, further comprising N-1 additional cells, each cell comprising a bridge configuration of switching elements, and a first node, a second node, a third node, and a fourth node, wherein the second node of cell K is coupled to the fourth node of cell K-1 for K between 2 and N.

21. The apparatus of Claim 20, wherein cell K further comprises a K-th coupled inductor wherein the first and third nodes of cell K are coupled to the first and second drivers through the K-th coupled inductor.

22. The apparatus of Claim 20, wherein the coupled inductors are cascaded, and the K-thAttorney Docket No. AE2024-020PCT coupled inductor is connected to the drivers through coupled inductors K+1, K+2, …, N.

23. The apparatus of claim 20, further comprising inductors connecting the second nodes of each bridge to the fourth node of the N-th bridge.

24. The apparatus of claim 23, wherein the inductors connect between the second node and the fourth node of each bridge.

25. The apparatus of claim 23, wherein the inductors connect the second node of each bridge to the fourth node of the N-th bridge.

26. The apparatus of Claim 20, wherein a first node of an impedance element is connected to the second node of the first bridge and an impedance between a second node of the impedance element and the fourth node of the N-th bridge is controlled by a polarity of the first and second currents or a polarity of a voltage applied between the first and third nodes of the bridges.

27. The apparatus of Claim 26, wherein the impedance element is one of a resistor, capacitor, or inductor.

28. The apparatus of Claim 20, further comprising capacitors parallel to the switching elements to equalize voltages across the switching elements.Attorney Docket No. AE2024-020PCT 29. A method for operating a switch, the method comprising: providing a first cell between a first node and a second node, the first cell comprising a bridge of switching elements and four nodes, a first two of the four nodes for controlling a state of the switching elements, and a second two of the four nodes for passing alternating current between the first and second nodes as controlled by the state of the switching elements; and forming a current loop including a first driver, a coupled inductor, the first two of the four nodes of the bridge, and a second driver; wherein when a current in the current loop has a first polarity, a magnitude of an impedance presented to an AC current between the second two of the four nodes increases, and wherein when the current in the current loop has a second polarity, the magnitude of the impedance presented to the AC current between the second two of the four nodes decreases, wherein the second two of the four nodes comprise the switch nodes.

30. The method of Claim 29, wherein the switching elements are PIN diodes or three- terminal switches.

31. The method of Claim 30, wherein the three-terminal switches are field-effect transistors.

32. The method of Claim 29, further comprising providing capacitors parallel to the switching elements to equalize voltages across the switching elements in an OFF state.

33. The method of Claim 29, further comprising coupling a first node of an impedance element to the first node of the first cell and wherein a polarity of the current inAttorney Docket No. AE2024-020PCT the current loop or a voltage applied between the first two of the four nodes controls the magnitude of the impedance presented to the AC current between the second two of the four nodes.

34. The method of claim 33, wherein the impedance element is one of a resistor, a capacitor or an inductor.

35. A non-transitory, tangible computer readable storage medium, encoded with processor readable instructions to perform a method for switching, the method comprising: sourcing a first current from a first driver; sinking the first current with a second driver; passing the first current through a coupled inductor and a bridge of switching elements and a first two nodes of the bridge of switching elements to increase a magnitude of an impedance presented to an AC current passing through the switching elements and a second two nodes in the bridge of switching elements.

36. The non-transitory, tangible computer readable storage medium of Claim 35, the method further comprising: passing the first current through a bypass inductor and the second two nodes in the bridge of switching elements to complete the discharge of one of the switching elements when another one of the switching elements reaches an OFF state first.

37. The non-transitory, tangible computer readable storage medium of Claim 35, the method further comprising: wherein the switching elements are PIN diodes andAttorney Docket No. AE2024-020PCT the alternating current has a frequency high enough to prevent depletion of an intrinsic region of the PIN diodes during a cycle of the alternating current.

38. The non-transitory, tangible computer readable medium of Claim 35, the method further comprising: sourcing a second current from the second driver; sinking the second current with the first driver; passing the second current through the coupled inductor and the bridge of switching elements and the first two nodes of the bridge of switching elements to decrease a magnitude of an impedance presented to the AC current passing through the switching elements and the second two nodes in the bridge of switching elements.

39. The non-transitory, tangible computer readable medium of Claim 35, the method further comprising adjusting the sourcing and sinking such that the disabling removes a capacitive element from a reactance seen by a load.

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