Substrate stack structure and forming method therefor, and electronic device

Abstract

The present application relates to the technical field of electronic devices. Disclosed are a substrate stack structure and a forming method therefor, and an electronic device. The substrate stack structure comprises a plurality of laminated substrates and a first conduction structure. Among the plurality of substrates, a first substrate has a first device embedded therein, and a second substrate has a second device embedded therein. The first substrate is provided with a first trace electrically connected to the first device, and the second substrate is provided with a second trace electrically connected to the second device, the first conduction structure being used for electrically connecting the first trace and the second trace. In this way, the layout space can be maximized for arranging the first device and the second device, thereby optimizing the electrical performance of the substrate stack structure.

Description

Substrate stacking structure and forming method thereof, and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411332552.2, filed on September 20, 2024, and entitled "Substrate stacking structure and forming method thereof, and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of electronic devices, and in particular to a substrate stacking structure and forming method thereof, and an electronic device. BACKGROUND

[0003] Various electronic devices, such as chips, in current electronic devices rely on power modules for power supply. With the sharp increase in the amount of data processed by chips, the size of chips and the number of peripheral devices increase, and the layout space of the corresponding power modules is limited, and the power modules need to have better electrical performance. However, the layout scheme of the devices in the current power modules cannot meet the above-mentioned needs. SUMMARY

[0004] To solve the above-mentioned problems, the present application provides a substrate stacking structure and forming method thereof, and an electronic device, which can effectively improve the space utilization and electrical performance by reasonably designing the layout of the devices in the substrate stacking structure.

[0005] In a first aspect, the present application provides a substrate stacking structure. Specifically, the substrate stacking structure includes a plurality of stacked substrates and a first conduction structure. Wherein a first substrate in the plurality of substrates is embedded with a first device, and a second substrate in the plurality of substrates is embedded with a second device. The first substrate is provided with a first trace electrically connected to the first device, the second substrate is provided with a second trace electrically connected to the second device, and the first conduction structure is used to electrically connect the first trace and the second trace.

[0006] In the above-mentioned substrate stacking structure, the devices are embedded in the plurality of stacked substrates, so they do not occupy the layout space perpendicular to the thickness direction of the substrate stacking structure, thereby maximizing the use of the layout space to lay the first device and the second device, and further improving the electrical performance of the substrate stacking structure.

[0007] In a possible implementation of the first aspect, the first substrate and the second substrate are pressure-bonded and adhered.

[0008] In a possible implementation of the first aspect, the first conduction structure is arranged in the interior or the side wall of the substrate stacking structure.

[0009] In a possible implementation of the first aspect, the first conductive structure includes a first metalized via, the first metalized via penetrating through the first substrate and the second substrate to electrically connect the first trace and the second trace.

[0010] In a possible implementation of the first aspect, the first conductive structure includes a second metalized via, the second metalized via penetrating through the first substrate to electrically connect the first trace and the second trace.

[0011] In this way, a high-density conductive structure is implemented, thereby meeting the use requirement of large current flow, and the working performance of the substrate stack structure is good, and the process feasibility is high, and the forming difficulty is low. Meanwhile, the first conductive structure can be formed at any position on the second substrate, so as to be arranged arbitrarily according to actual needs, and the flexibility of layout design is stronger.

[0012] In a possible implementation of the first aspect, the first conductive structure includes a third metalized via and a conductive piece, the third metalized via being arranged on a surface of the second substrate away from the first substrate and electrically connected to the second trace, and the conductive piece being embedded in the second substrate and electrically connected to the third metalized via and the second trace.

[0013] In this way, a high-density conductive structure is implemented, thereby meeting the use requirement of large current flow, and the working performance of the substrate stack structure is good, and the process feasibility is high, and the forming difficulty is low. Meanwhile, the first conductive structure can be formed at any position on the second substrate, so as to be arranged arbitrarily according to actual needs, and the flexibility of layout design is stronger.

[0014] In a possible implementation of the first aspect, the first conductive structure includes a metal layer, the metal layer being arranged on a side wall of the substrate stack structure and covering the side wall of the first substrate and the side wall of the second substrate to electrically connect the first trace and the second trace.

[0015] In a possible implementation of the first aspect, a surface of the second device away from the first substrate is flush with a surface of the second substrate away from the first substrate, thereby helping to reduce the forming difficulty of the substrate stack structure.

[0016] In a possible implementation of the first aspect, the first device and the second device are inductors, capacitors, resistors or chips.

[0017] In a possible implementation of the first aspect, the capacitor is a silicon capacitor, a ceramic capacitor or an organic polymer capacitor. When the capacitor is a silicon capacitor, the thickness of the capacitor can be thinner, and therefore, the thickness of the substrate stack structure can be thinner, the forming is simpler, and the yield is high.

[0018] In a possible implementation of the first aspect, the substrate stack structure further includes a second conduction structure. A third substrate in the plurality of substrates is arranged on a side of the first substrate opposite to the second substrate, and the third substrate is embedded with a third device. The third substrate is provided with a third trace electrically connected to the third device. The second conduction structure is configured to electrically connect the first trace and the third trace. The first substrate and the second substrate are press-bonded, and the first substrate and the third substrate are press-bonded, sintered, or welded.

[0019] In a possible implementation of the first aspect, the substrate stack structure further includes a power chip. The first device is an inductor. The second device is an output capacitor. The third device is an input capacitor. The input capacitor, the power chip, the inductor, and the output capacitor are electrically connected in sequence.

[0020] Since the input capacitor, the inductor, and the output capacitor are sequentially stacked along the thickness direction of the substrate stack structure, other devices (for example, the input capacitor and the inductor) do not occupy the layout space of the output capacitor, and the layout space can be maximally utilized to lay out the output capacitor, thereby improving the capacitance of the output capacitor and optimizing the electrical performance of the substrate stack structure.

[0021] In a possible implementation of the first aspect, the power chip is located on a side of the third substrate opposite to the first substrate, and at least part of the power chip is exposed to the outside to enable heat dissipation of the power chip.

[0022] In a possible implementation of the first aspect, the substrate stack structure includes a fourth substrate. The fourth substrate is located on a side of the third substrate opposite to the first substrate and is electrically connected to the third substrate. The power chip is embedded in the fourth substrate.

[0023] In a possible implementation of the first aspect, the fourth substrate is further embedded with a heat conduction structure. One end of the heat conduction structure is attached to the power chip, and the other end is exposed to the outside.

[0024] In a possible implementation of the first aspect, the power chip is embedded in the third substrate. In this way, the forming process and structure of the substrate stack structure can be effectively simplified, and this is particularly suitable for scenarios where the layout space is sufficient.

[0025] In a possible implementation of the first aspect, the number of power chips is a plurality, and the plurality of power chips are stacked along the thickness direction of the substrate stack structure. In this way, more power chips can be arranged in the case of limited layout space, and the use of multiple power chips can be implemented, thereby achieving higher chip processing performance and improving power conversion efficiency and power density.

[0026] In a second aspect, the present application provides an electronic device including a carrier and a substrate stack structure according to the first aspect and any possible implementation of the first aspect. The substrate stack structure is arranged on the carrier.

[0027] It should be understood that the beneficial effects of the second aspect can be referred to the beneficial effects of the first aspect described above.

[0028] In a possible implementation of the second aspect, the substrate stack structure further includes a second through-structure, a third substrate of the plurality of substrates is arranged on a side of the first substrate away from the second substrate, and the third substrate is embedded with a third device. The third substrate is provided with a third trace electrically connected to the third device, and the second through-structure is configured to electrically connect the first trace and the third trace. The first device is an inductor, the second device is an output capacitor, and the third device is an input capacitor. The electronic device further includes a load arranged on the carrier, and the substrate stack structure is configured to supply power to the load.

[0029] In a possible implementation of the second aspect, the load is arranged on a side of the second substrate away from the first substrate. In this way, vertical power supply of the substrate stack structure to the load can be implemented, so as to effectively shorten the transmission path between the substrate stack structure and the load.

[0030] In a third aspect, the present application provides a forming method of a substrate stack structure. The method includes: embedding a first device in a first substrate, and forming a first trace electrically connected to the first device on the first substrate; forming a second substrate embedded with a second device on the first substrate; forming a second trace electrically connected to the second device on the second substrate, and forming a first through-structure configured to electrically connect the first trace and the second trace.

[0031] In the forming method described above, the substrate stack structure is obtained by performing layering on the first substrate. In this way, assembly solder joints do not need to be arranged between the substrates, so as to effectively reduce the link resistance and further improve the electrical performance of the substrate stack structure.

[0032] In a possible implementation of the third aspect, the forming of the second substrate embedded with the second device on the first substrate includes: forming a first layering structure on the first substrate; forming a slot on the first layering structure; laying the second device in the slot; and filling a second layering structure in the slot to cover the second device, so as to obtain the second substrate embedded with the second device.

[0033] In a possible implementation of the third aspect, the forming of the first through-structure includes: manufacturing a first metallized via, the first metallized via penetrating through the first substrate and the second substrate, and electrically connecting the first trace and the second trace, and the first metallized via constitutes the first through-structure. BRIEF DESCRIPTION OF DRAWINGS

[0034] FIG. 1 shows an exemplary structure of some devices in an electronic device according to some embodiments;

[0035] FIG. 2 shows an exemplary structure of some devices in an electronic device according to an embodiment of the present application;

[0036] FIG. 3 shows an exemplary structure of a power module in an electronic device according to an embodiment of the present application;

[0037] FIG. 4 shows an exemplary structure of a power module according to another embodiment of the present application;

[0038] FIG. 5 shows an exemplary structure of a part of an electronic device according to another embodiment of the present application;

[0039] FIG. 6 shows an exemplary structure of a power module in an electronic device according to another embodiment of the present application;

[0040] FIG. 7 shows an exemplary structure of a power module according to another embodiment of the present application;

[0041] FIG. 8 shows an exemplary structure of a power module according to another embodiment of the present application;

[0042] FIG. 9 shows an exemplary structure of a power module according to another embodiment of the present application;

[0043] FIG. 10 shows an exemplary structure of a power module according to another embodiment of the present application;

[0044] FIG. 11 shows an exemplary structure of a power module according to another embodiment of the present application;

[0045] FIG. 12 shows an exemplary structure of a power module according to another embodiment of the present application;

[0046] FIG. 13 shows an exemplary structure of a power module according to another embodiment of the present application;

[0047] FIG. 14 shows a flowchart of a forming method of a power module according to an embodiment of the present application;

[0048] FIG. 15A shows a forming schematic diagram one of a power module according to an embodiment of the present application;

[0049] FIG. 15B shows a forming schematic diagram two of a power module according to an embodiment of the present application;

[0050] FIG. 15C shows a forming schematic diagram three of a power module according to an embodiment of the present application;

[0051] FIG. 15D shows a forming schematic diagram four of a power module according to an embodiment of the present application;

[0052] FIG. 15E shows a forming schematic diagram five of a power module according to an embodiment of the present application;

[0053] FIG. 15F shows a forming schematic diagram six of a power module according to an embodiment of the present application;

[0054] FIG. 15G shows a seventh forming schematic diagram of the power module in the embodiment of the present application;

[0055] FIG. 15H shows an eighth forming schematic diagram of the power module in the embodiment of the present application. DETAILED DESCRIPTION

[0056] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0057] The specific embodiments of the present application are used to provide a substrate stack structure. The substrate stack structure can be applied in an electronic device. Wherein, the substrate stack structure can be, for example, a power module, a system on chip (SOC) module, or a radio frequency chip module, etc., which are not specifically limited in the present application. In addition, the electronic device can be, for example, a computing device, a wireless device, a network system device, and a vehicle-mounted device, etc., which are not specifically limited in the present application. For ease of description, the following will be introduced as an example that the substrate stack structure is a power module for supplying power to a load in an electronic device.

[0058] FIG. 1 shows an exemplary structure of some devices in an electronic device 1’ according to some technical solutions. Referring to FIG. 1, the electronic device 1’ includes a power module 10’, a chip 20 (as an example of a load), a circuit board 30 (as an example of a carrier), and a heat sink 40. In the Z direction, the power module 10’ and the chip 20 are respectively arranged on opposite sides of the circuit board 30 and are electrically connected through the circuit board 30, so that the power module 10’ can supply power to the chip 20 to enable the chip 20 to work normally. The heat sink 40 is arranged on the surface of the chip 20 away from the circuit board 30 to enable the heat generated by the chip 20 during operation to be dissipated. Wherein, the chip 20 can be, for example, a central processing unit (CPU) chip or a graphics processing unit (GPU), etc., which are not specifically limited in the present application.

[0059] Wherein, the power module 10’ includes a substrate 100’, an input capacitor 200, a power chip 300, an inductor 400, and an output capacitor 500. Wherein, the substrate 100’ is arranged on the surface of the circuit board 30 away from the chip 20. The input capacitor 200 and the power chip 300 are embedded in the substrate 100’. The inductor 400 is arranged on the surface of the substrate 100’ away from the circuit board 30. The output capacitor 500 is arranged on the surface of the circuit board 30 away from the chip 20. The input capacitor 200, the power chip 300, the inductor 400, and the output capacitor 500 are electrically connected in sequence. In this way, after the power module 10’ is turned on, the input voltage can pass through the input capacitor 200, the power chip 300, the inductor 400, and the output capacitor 500 in sequence, and finally output to the chip 20, thereby realizing the power supply to the chip 20.

[0060] It is worth noting that the layout space of the circuit board 30 perpendicular to the Z direction is limited, and the output capacitor 500 and the substrate 100' are laid on the circuit board 30 perpendicular to the Z direction, and the substrate 100' occupies the layout space of the output capacitor 500, so that the capacitance of the output capacitor 500 is limited, and the electrical performance of the power module 10' is poor.

[0061] Therefore, the present application provides a substrate stacking structure, by embedding a plurality of devices in a plurality of (for example, two, three, four or five, etc.) stacked substrates respectively, the space perpendicular to the Z direction (for the convenience of description, referred to as the horizontal layout space below) can be maximized to lay the devices, thereby optimizing the electrical performance of the substrate stacking structure. For the convenience of understanding, the following still continues to take the power module as an example to introduce in detail.

[0062] FIG. 2 shows an exemplary structure of some devices in the electronic device 1 in an embodiment of the present application. FIG. 3 shows an exemplary structure of the power module 10A in the electronic device 1 in an embodiment of the present application. Referring to FIG. 3 and combining FIG. 2, the power module 10A includes a plurality of stacked substrates. For example, in the embodiment shown in FIG. 2, the power module 10A can include a first substrate D1 and a second substrate D2 stacked. Among them, the stacking direction of the first substrate D1 and the second substrate D2 is the Z direction, and it can be understood that the Z direction is the thickness direction of the power module 10A. Among them, the first substrate D1 embeds an inductor 400 (as an example of the first device), and the second substrate D2 embeds an output capacitor 500 (as an example of the second device).

[0063] In order to realize the interconnection between the first substrate D1 and the second substrate D2, the first substrate D1 is further provided with a first trace L1 electrically connected with the inductor 400, and the second substrate D2 is provided with a second trace L2 electrically connected with the output capacitor 500. The power module 10A further includes a first conductive structure 101. The first conductive structure 101 is used to electrically connect the first trace L1 and the second trace L2, so as to realize the interconnection between the first substrate D1 and the second substrate D2, and further realize the electrical signal transmission between the inductor 400 and the output capacitor 500.

[0064] In the above-mentioned power module 10A, the inductor 400 and the output capacitor 500 are stacked along the Z direction, so that the layout space of the horizontal plane can be maximized to lay the output capacitor 500, thereby increasing the capacitance of the output capacitor 500 and optimizing the electrical performance of the power module 10.

[0065] In some embodiments of the present application, the power module 10A can further include a third substrate D3 disposed on the side of the first substrate D1 opposite to the second substrate D2. The third substrate D3 has an input capacitor 200 (as an example of the third device) embedded therein. To achieve the interconnection between the third substrate D3 and the first substrate D1, the third substrate D3 further has a third trace L3 electrically connected to the input capacitor 200. The power module 10A further includes a second conductive structure 102. The second conductive structure 102 is configured to electrically connect the first trace L1 and the third trace L3, thereby achieving the interconnection between the first substrate D1 and the third substrate D3.

[0066] In some embodiments of the present application, the power module 10A can further include a power chip 300. The input capacitor 200, the power chip 300, the inductor 400 and the output capacitor 500 are electrically connected in sequence, thereby achieving the power supply function of the power module 10A.

[0067] It can be understood that the number of the input capacitor 200, the power chip 300, the inductor 400 and the output capacitor 500 in the power module 10A described above can be one or more (for example, two, three, four or five, etc.), which is not specifically limited in the present application.

[0068] Continuing to refer to FIGS. 2 and 3, in some embodiments of the present application, the power chip 300 can be located on the side of the third substrate D3 opposite to the first substrate D1, and at least part of the power chip 300 is exposed to the outside to facilitate heat dissipation of the power chip 300. That is, at least part of the power chip 300 can be observed from the outside of the power module 10A after the power module 10A is assembled, or in other words, at least part of the surface of the power chip 300 constitutes the outer surface of the power module 10A.

[0069] In some implementations, the power chip 300 can be first molded to be wrapped by the molding compound 301. Then, the molding compound 301 on any surface is ground to expose one surface of the power chip 300 to the outside, thereby achieving heat dissipation. Meanwhile, the remaining part of the molding compound 301 can also protect the power chip 300 from physical damage, chemical corrosion and environmental factors (such as humidity, temperature change, etc.) to some extent, and provide good electrical insulation.

[0070] It can be understood that in the present embodiment, the lower surface of the power chip 300 (i.e., the surface opposite to the input capacitor 200) is exposed to the outside to maximize heat dissipation, but the present application is not limited thereto. In other embodiments, the four peripheral sides of the power chip 300 can also be exposed to the outside.

[0071] In some implementations, the heat sink 40 can be arranged on the part of the power supply chip 300 exposed to the outside (e.g., the surface of the power supply chip 300 facing away from the input capacitor 200), so as to further achieve rapid heat dissipation of the power supply chip 300. Compared with the layout scheme in which the power supply chip 300 is embedded in the substrate 100' in the example shown in FIG. 1, the heat generated by the power supply chip 300 during operation can be effectively and rapidly dissipated through the heat sink 40, and the working performance is better, so as to meet the working requirements of various application scenarios (e.g., large-current scenarios).

[0072] With reference to FIGS. 2 and 3, in some embodiments of the present application, the chip 20 can be arranged on the side of the second substrate D2 facing away from the first substrate D1. In this way, vertical power supply of the output capacitor 500 to the chip 20 can be achieved, so as to effectively shorten the transmission path between the output capacitor 500 and the chip 20.

[0073] Based on the stacked architecture of the power supply chip 300, the input capacitor 200, the inductor 400, the output capacitor 500, and the chip 20 in the order along the Z direction in the embodiments shown in FIGS. 2 and 3, a physical connection scheme and an electrical connection scheme between the input capacitor 200, the power supply chip 300, the inductor 400, the output capacitor 500, and the chip 20 in the power supply module 10A are introduced as follows.

[0074] With reference to FIGS. 2 and 3, in some embodiments of the present application, the first substrate D1 and the second substrate D2 are press-bonded, and the second substrate D2 and the third substrate D3 are press-bonded. That is, the third substrate D3 embedded with the input capacitor 200 and the second substrate D2 embedded with the output capacitor 500 can be obtained by increasing the layers on the upper and lower surfaces of the first substrate D1 embedded with the inductor 400. In this way, the assembly solder joints between the layers do not need to be arranged, and the link resistance can be effectively reduced.

[0075] Based on the above forming manner, in some embodiments of the present application, along the Z direction, the upper surface F1 of the second substrate D2 on which the output capacitor 500 is arranged is farther away from the output capacitor 500 than the lower surface F2. In other words, along the Z direction, the distance between the upper surface F1 and the output capacitor 500 is greater than the distance between the lower surface F2 and the output capacitor 500. The upper surface F1 of the second substrate D2 is the surface of the second substrate D2 facing away from the first substrate D1, and the lower surface F2 of the second substrate D2 is the surface of the second substrate D2 facing the first substrate D1.

[0076] In some implementations, a die attach film (DAF) 600 can be disposed on the lower surface F3 of the output capacitor 500. The die attach film 600 has excellent electrical insulation and adhesive strength, and can provide stable bonding force for the output capacitor 500 and ensure that the lower surface F3 of the output capacitor 500 is insulated from other structures. Exemplarily, the lower surface of the die attach film 600 (i.e., the surface of the die attach film 600 facing the inductor 400) can be flush with the lower surface F2 of the second substrate D2.

[0077] It can be understood that the output capacitor 500 is substantially the same as the input capacitor 200 in terms of the arrangement manner, and only needs to be changed in the arrangement direction. Therefore, the description of the arrangement manner of the input capacitor 200 can be referred to, and will not be repeated here.

[0078] The exemplary structures of the first trace L1, the second trace L2, the third trace L3, the first conductive structure 101, and the second conductive structure 102 will be described below.

[0079] In some embodiments of the present application, the second trace L2 is disposed on the upper surface F1 of the second substrate D2. The third trace L3 is disposed on the lower surface F4 of the third substrate D3 (i.e., the surface of the third substrate D3 facing away from the first substrate D1).

[0080] In some embodiments of the present application, the second trace L2 can include a metalized blind hole L21 and a circuit pattern L22. The metalized blind hole L21 is formed on the upper surface F1 of the second substrate D2 and is electrically connected to the output capacitor 500 embedded in the second substrate D2. The circuit pattern L22 is covered on the upper surface F1 of the second substrate D2 and is electrically connected to the metalized blind hole L21.

[0081] It can be understood that the first trace L1 and the third trace L3 have similar structures to the second trace L2. Therefore, the description of the second trace L2 can be referred to, and will not be repeated here.

[0082] The above FIG. 3 only schematically shows an exemplary structure of the first trace L1, the second trace L2, and the third trace L3, and does not constitute a limitation on the present application.

[0083] Continuing to refer to FIG. 3, in some embodiments of the present application, the first conductive structure 101 and the second conductive structure 102 can be arranged inside the power module 10A. For example, the first conductive structure 101 and the second conductive structure 102 can be formed by first plated through holes S1, or in other words, the first conductive structure 101 and the second conductive structure 102 are integrally formed structures. The first plated through holes S1 pass through the second substrate D2, the first substrate D1 and the third substrate D3 in the Z direction in sequence, thereby electrically connecting the first trace L1 and the second trace L2, and the first trace L1 and the third trace L3. The connection between the first substrate D1, the third substrate D3 and the second substrate D2 is achieved through the first plated through holes S1, which can effectively ensure the reliability of the electrical connection, and the structure is simple and easy to form.

[0084] In some embodiments of the present application, the third trace L3 is provided with a fourth trace L4 on the side away from the inductor 400. The fourth trace L4 is electrically connected to the third trace L3. The power chip 300 can be electrically connected to the fourth trace L4.

[0085] In some implementations, the power chip 300 can be fixed to the surface of the fourth trace L4 away from the inductor 400 by soldering, wherein the soldering forms a solder joint that can achieve electrical connection between the power chip 300 and the fourth trace L4.

[0086] In some embodiments of the present application, the second trace L2 is provided with a fifth trace L5 on the surface away from the inductor 400. The fifth trace L5 is electrically connected to the second trace L2. The fifth trace L5 is used to be electrically connected to the load side, for example, in the present embodiment, the fifth trace L5 can be electrically connected to the circuit board 30, thereby achieving electrical connection with the chip 20 through the circuit board 30.

[0087] In some implementations, the power module 10A can also be fixed to the surface of the circuit board 30 away from the chip 20 by soldering, wherein the soldering forms a solder joint that can achieve electrical connection between the fifth trace L5 and the circuit board 30.

[0088] It can be understood that the structure of the fourth trace L4 and the fifth trace L5 is similar to that of the second trace L2, and therefore reference can be made to the above description of the second trace L2, which will not be repeated here.

[0089] Based on this, the input capacitor 200 can be electrically connected with the power chip 300 via the third trace L3 and the fourth trace L4 in sequence. The power chip 300 can be electrically connected with the inductor 400 via the fourth trace L4, the third trace L3, the first metallized via S1 and the first trace L1 in sequence. The inductor 400 can be electrically connected with the output capacitor 500 via the first trace L1, the first metallized via S1 and the second trace L2 in sequence. The output capacitor 500 can be electrically connected with the chip 20 via the second trace L2, the fifth trace L5 and the circuit board 30 in sequence. Further, the power module 10A can supply power to the chip 20.

[0090] The above embodiments shown in FIGS. 2 and 3 only show the partial structure forms of the first conduction structure 101 and the second conduction structure 102, and in other embodiments, the first conduction structure 101 and the second conduction structure 102 can also have other structure forms, which are exemplarily introduced below.

[0091] FIG. 4 shows an exemplary structure of a power module 10B in another embodiment of the present application. The power module 10B shown in FIG. 4 is different from the power module 10A shown in FIGS. 2 and 3 in that the first conduction structure 101 and the second conduction structure 102 are different.

[0092] Specifically, referring to FIG. 4, the first conduction structure 101 includes a second metallized via S2. The second metallized via S2 penetrates the second substrate D2 where the output capacitor 500 is located, to electrically connect the first trace L1 and the second trace L2.

[0093] It can be understood that the structure form of the second conduction structure 102 is substantially the same as that of the first conduction structure 101, and only needs to be changed in the setting direction accordingly, so the description about the first conduction structure 101 above can be referred to, and will not be repeated here.

[0094] In this way, it is conducive to realizing a high-density conduction structure, thereby meeting the use requirement of large current flow, and the working performance of the power module 10B is good. Moreover, the first conduction structure 101 and the second conduction structure 102 can be formed at any position respectively, so that the first trace L1, the second trace L2 and the third trace L3 can be arbitrarily laid out according to actual needs, without being aligned in the Z direction, and the flexibility of layout design is stronger.

[0095] In addition, other structures of the power module 10B and its variants are substantially the same as those of the power module 10A in the embodiment shown in FIGS. 2 and 3, for example, the fixed connection manner between the first substrate D1, the third substrate D3 and the second substrate D2 in the power module 10B, the arrangement manner of the input capacitor 200, the power chip 300 and the output capacitor 500, which are substantially the same as those of the power module 10A, and thus the relevant descriptions about the power module 10A can be referred to and will not be repeated here.

[0096] FIG. 5 shows an exemplary structure of part of the electronic device 1 in another embodiment of the present application. FIG. 6 shows an exemplary structure of the power module 10C in the electronic device 1 in another embodiment of the present application. The power module 10C shown in FIGS. 5 and 6 is different from the power module 10A shown in FIGS. 2 and 3 in that the first conduction structure 101 and the second conduction structure 102 are different.

[0097] Specifically, referring to FIG. 5, the first conduction structure 101 includes a third metallized via S3 and a conductive piece S4. The third metallized via S3 is formed on the upper surface F1 of the second substrate D2 on which the output capacitor 500 is located, and one end of the third metallized via S3 is electrically connected to the second trace L2. The conductive piece S4 is embedded in the second substrate D2 and electrically connects the other end of the third metallized via S3 and the first trace L1 on the first substrate D1 on which the inductor 400 is located.

[0098] In some embodiments of the present application, the conductive piece S4 can be a conductive structure such as a copper pillar or a copper block, and the present application does not make specific limitations thereto.

[0099] It can be understood that the structure of the second conduction structure 102 is substantially the same as that of the first conduction structure 101, and only the arrangement direction needs to be changed accordingly, and thus the description about the first conduction structure 101 can be referred to and will not be repeated here.

[0100] In this way, it is beneficial to realize a high-density conduction structure, thereby meeting the use requirement of large current flow, and the working performance of the power module 10B is good, and the process feasibility is high and the forming difficulty is low. At the same time, the first conduction structure 101 and the second conduction structure 102 can be formed at any position on the second substrate D2 and the third substrate D3 respectively, so that the first trace L1, the second trace L2 and the third trace L3 can be arbitrarily arranged according to actual needs, without being aligned in the Z direction, and the flexibility of layout design is stronger.

[0101] In addition, other structures of the power module 10C and its variants are substantially the same as those of the power module 10A in the embodiments shown in FIGS. 2 and 3, for example, the fixed connection manner between the first substrate D1, the third substrate D3 and the second substrate D2 in the power module 10C, the arrangement manner of the input capacitor 200, the power chip 300 and the output capacitor 500, which are substantially the same as those of the power module 10A, and thus the relevant descriptions about the power module 10A can be referred to herein.

[0102] In some other embodiments of the present application, the first conductive structure 101 can also be arranged on the side wall of the power module 10A. For example, the first conductive structure 101 can further include a metal layer covering the side wall of the first substrate D1 where the inductor 400 is arranged and the side wall of the second substrate D2 where the output capacitor 500 is arranged, so as to electrically connect the first trace L1 and the second trace L2. That is, the first trace L1 and the second trace L2 are conductively connected to each other through the side wall of the power module 10A.

[0103] It can be understood that the structure of the second conductive structure 102 is substantially the same as that of the first conductive structure 101, and only the arrangement direction needs to be changed accordingly, and thus the description about the first conductive structure 101 can be referred to herein.

[0104] In the embodiments shown in FIGS. 2 to 6, the power chip 300 is arranged on the side of the input capacitor 200 away from the inductor 400, and at least part of the power chip 300 is exposed to the outside to facilitate heat dissipation of the power chip 300, but the present application is not limited thereto. In some other embodiments, the power chip 300 can also have other arrangement manners, which are exemplarily introduced as follows.

[0105] FIG. 7 shows an exemplary structure of a power module 10D in another embodiment of the present application. The power module 10D shown in FIG. 7 is different from the power module 10C shown in FIGS. 5 and 6 in that the arrangement manner of the power chip 300 is different.

[0106] Specifically, referring to FIG. 7, the plurality of substrates further include a fourth substrate D4, and the fourth substrate D4 is arranged on the side of the third substrate D3 away from the inductor 400, and the power chip 300 is embedded in the fourth substrate D4.

[0107] In some embodiments of the present application, the upper surface of the fourth substrate D4 (i.e., the surface of the fourth substrate D4 facing the first substrate D1) is provided with a sixth trace L6, which is used to electrically connect the power chip 300 and the fourth trace L4. In this way, the input capacitor 200 can be electrically connected to the power chip 300 in sequence via the third trace L3, the fourth trace L4, and the sixth trace L6. The power chip 300 can be electrically connected to the inductor 400 in sequence via the sixth trace L6, the fourth trace L4, the third trace L3, the second via structure 102, and the first trace L1.

[0108] In some implementations, the fourth substrate D4 in which the power chip 300 is embedded can be fixed to the surface of the third substrate D3 away from the first substrate D1 by welding. In this way, the welding point formed by welding can achieve electrical connection between the sixth trace L6 and the fourth trace L4.

[0109] In some other implementations, the fourth substrate D4 in which the power chip 300 is embedded can be fixed to the surface of the third substrate D3 away from the first substrate D1 by sintering. In this way, the sintering point formed by sintering can achieve electrical connection between the sixth trace L6 and the fourth trace L4.

[0110] Based on this, the fourth substrate D4 in which the power chip 300 is embedded can be formed first, then the sixth trace L6 can be formed on the upper surface of the fourth substrate D4 (i.e., the surface of the fourth substrate D4 facing the first substrate D1), and finally the fourth substrate D4 can be fixedly connected to the third substrate D3 by welding or sintering, which is low in forming difficulty.

[0111] In some other implementations, the fourth substrate D4 in which the power chip 300 is embedded can also be fixed to the surface of the third substrate D3 away from the first substrate D1 by pressure bonding. In this way, a metalized via hole can be formed on the bonding layer to achieve electrical connection between the sixth trace L6 and the fourth trace L4.

[0112] Based on this, the fourth substrate D4 in which the power chip 300 is embedded can be formed by layering and embedding on the surface of the third substrate D3 away from the first substrate D1.

[0113] To achieve heat dissipation of the power chip 300, in some embodiments of the present application, the power module 10D further comprises a heat conduction structure 700. One end of the heat conduction structure 700 is attached to the power chip 300, and the other end is exposed to the outside. That is, after the power module 10D is assembled, a part of the heat conduction structure 700 can be observed from the outside of the power module 10D. In this way, the heat conduction structure 700 can transfer the heat generated by the power chip 300 during operation to the external environment, thereby achieving heat dissipation of the power chip 300. Without the need for polishing after molding of the power chip 300, the risk of generating polishing cracks can be effectively reduced, and the molding yield is better.

[0114] In some implementations, the heat conduction structure 700 can be partially embedded in the fourth substrate D4 and attached to the power chip 300, and the other part is slightly protruding relative to the fourth substrate D4, but the present application is not limited to this. In other alternative implementations, the heat conduction structure 700 can also be flush with the fourth substrate D4, or the heat conduction structure 700 can also be recessed inwardly relative to the fourth substrate D4.

[0115] In some implementations, the heat conduction structure 700 can be a copper sheet, graphite, or a heat-conducting glue, etc. with heat conduction performance, and the present application does not make specific limitations as long as it can achieve the above heat dissipation function.

[0116] In addition, the other structures of the above-mentioned power module 10D and its variants are substantially the same as those of the power module 10C in the embodiments shown in Figures 5 and 6, for example, the fixed connection mode between the first substrate D1, the third substrate D3 and the second substrate D2 in the power module 10D, the setting mode of the input capacitor 200 and the output capacitor 500, the structure form of the first conduction structure 101 and the second conduction structure 102 and its variants, are substantially the same as those of the power module 10C described above, therefore, the relevant description about the power module 10C can be referred to, and will not be repeated here.

[0117] Figure 8 shows an exemplary structure of a power module 10E in another embodiment of the present application. The power module 10E shown in Figure 8 is different from the power module 10C shown in Figures 5 and 6 in that the setting mode of the power chip 300 is different.

[0118] Specifically, referring to Figure 8, the power chip 300 is embedded in the third substrate D3, that is, the power chip 300 and the input capacitor 200 are located in the same layer. In this way, the molding process and structure of the power module 10E can be effectively simplified, which is especially suitable for scenarios with sufficient layout space.

[0119] Based on this, the first substrate D1 embedded with the inductor 400 can be formed first. Then, the third substrate D3 embedded with the input capacitor 200 and the power chip 300 and the second substrate D2 embedded with the output capacitor 500 are formed by layering embedding on the two surfaces of the first substrate D1 opposite in the Z direction.

[0120] In some embodiments of the present application, the third wire L3 can also be electrically connected with the power chip 300. In this way, the input capacitor 200 can be electrically connected with the power chip 300 via the third wire L3. The power chip 300 can be finally electrically connected with the inductor 400 via the third wire L3, the second conduction structure 102 and the first wire L1 in sequence.

[0121] In addition, other structures of the power module 10E and its variants described above are substantially the same as those of the power module 10C in the embodiments shown in FIGS. 5 and 6, for example, the fixed connection mode between the first substrate D1, the third substrate D3 and the second substrate D2 in the power module 10E, the arrangement mode of the input capacitor 200 and the output capacitor 500, the structure of the first conduction structure 101 and the second conduction structure 102 and its variants, which are substantially the same as those of the power module 10C described above, and therefore, reference can be made to the related description of the power module 10C described above, and no further description is given here.

[0122] In the embodiments shown in FIGS. 2 to 7, the number of power chips 300 is multiple, and the multiple power chips 300 are laid along a plane perpendicular to the Z direction, but the present application is not limited thereto. In some other embodiments, the multiple power chips 300 can also be stacked along the Z direction, which will be described exemplarily below.

[0123] FIG. 9 shows an exemplary structure of a power module 10F in another embodiment of the present application. The power module 10F shown in FIG. 9 is different from the power module 10D shown in FIG. 7 in that the arrangement mode of the power chip 300 is different.

[0124] Referring to FIG. 9, the number of power chips 300 is multiple, and the multiple power chips 300 are stacked along the Z direction. For example, the multiple substrates can further include a fourth substrate D4 and a fifth substrate D5. The fourth substrate D4 is located between the third substrate D3 and the fifth substrate D5. One of the power chips 300 can be embedded in the fourth substrate D4, and another of the power chips 300 can be embedded in the fifth substrate D5.

[0125] In this way, more power chips 300 can be arranged in the case of limited layout space perpendicular to the Z direction, realizing the use of multiple power chips 300, so as to achieve higher chip processing performance, and improve the power conversion efficiency and power density of the power module 10F.

[0126] The third substrate D3, the fourth substrate D4 and the fifth substrate D5 can be fixedly connected by press bonding, welding or sintering, and the application does not limit this. The specific implementation manner is substantially the same as the connection scheme of the third substrate D3 and the fourth substrate D4 of the power module 10D shown in FIG. 7, and therefore, reference can be made to the related description in the embodiment shown in FIG. 7, and a detailed description is not repeated here.

[0127] In addition, other structures of the power module 10F and its variants are substantially the same as those of the power module 10D in the embodiment shown in FIG. 7, for example, the arrangement manner of the input capacitor 200 and the output capacitor 500 of the power module 10F, and the structure form of the first conduction structure 101 and the second conduction structure 102 and its variants, which are substantially the same as those of the power module 10D, and therefore, reference can be made to the related description of the power module 10D, and a detailed description is not repeated here.

[0128] FIG. 10 shows an exemplary structure of a power module 10G in another embodiment of the application. The power module 10G shown in FIG. 10 is different from the power module 10E shown in FIG. 8 in that the arrangement manner of the power chip 300 is different.

[0129] Specifically, referring to FIG. 10, the number of power chips 300 is multiple. The multiple power chips 300 are located in the third substrate D3 where the input capacitor 200 is located, and are stacked in the Z direction. In the embodiment shown in FIG. 10, the multi-layer structure formed by stacking the multiple power chips 300 is substantially the same as the multi-layer structure formed by stacking the multiple power chips 300 in the embodiment shown in FIG. 9, and therefore, reference can be made to the related description in the embodiment shown in FIG. 9, and a detailed description is not repeated here.

[0130] In this way, more power chips 300 can also be arranged in the case of limited layout space perpendicular to the Z direction, and the multiple power chips 300 can be used together to achieve higher chip processing performance, thereby improving the power conversion efficiency and power density of the power module 10F.

[0131] Based on the stacking architecture in the embodiment shown in FIG. 10, in some embodiments of the application, the multi-layer structure formed by stacking the multiple power chips 300 can be formed first, and then the multi-layer structure formed by stacking the multiple power chips 300 can be embedded into the third substrate D3.

[0132] In addition, other structures of the power module 10G and its variants are substantially the same as those of the power module 10E shown in FIG. 8, for example, the arrangement of the input capacitor 200 and the output capacitor 500 of the power module 10G, and the structures of the first conduction structure 101 and the second conduction structure 102 and its variants, are substantially the same as those of the power module 10E, and thus, the relevant descriptions of the power module 10E can be referred to herein.

[0133] It can be understood that FIGS. 9 and 10 only schematically show a part of the implementation mode of the plurality of power chips 300 arranged in the Z direction in a stacked manner, and do not constitute a limitation on the present application. For example, the plurality of power chips 300 in the embodiments shown in FIGS. 2 to 6 can also be arranged in the Z direction in a stacked manner and subjected to plastic encapsulation and polishing, so that at least part of the plurality of power chips 300 is exposed to the outside.

[0134] In the embodiments shown in FIGS. 2 to 10, the upper surface F1 of the second substrate D2 on which the output capacitor 500 is arranged is farther away from the output capacitor 500 than the lower surface F2 in the Z direction, but the present application is not limited thereto. In some other embodiments, the output capacitor 500 can also have other arrangement modes, which are exemplarily introduced as follows.

[0135] FIG. 11 shows an exemplary structure of a power module 10H in another embodiment of the present application. Referring to FIG. 11, the upper surface F5 of the output capacitor 500 is flush with the upper surface F1 of the second substrate D2 on which the output capacitor 500 is arranged, which helps to reduce the molding difficulty of the second wiring L2. For example, when the second wiring L2 is molded, only a layer of build-up structure needs to be formed on the upper surface F1 of the second substrate D2 on which the output capacitor 500 is arranged, then a circuit pattern L22 is made on the build-up structure, and a metallized blind hole L21 is made on the build-up structure to conduct the circuit pattern L22 and the output capacitor 500. The build-up structure has a thin thickness and good tolerance consistency, so that it is not necessary to separately open blind holes with different depths, and the conduction process of the metallized blind hole L21 is simpler.

[0136] It can be understood that the arrangement of the input capacitor 200 is substantially the same as that of the output capacitor 500, and only the arrangement direction needs to be changed accordingly, and thus, the description of the arrangement of the output capacitor 500 can be referred to herein.

[0137] Based on the stacked architecture in the embodiment shown in FIG. 11, the third substrate D3 embedded with the input capacitor 200, the second substrate D2 embedded with the output capacitor 500, and the first substrate D1 embedded with the inductor 400 can be formed respectively, and then the second substrate D2, the first substrate D1, and the third substrate D3 are stacked and bonded in the Z direction, thereby obtaining a multi-layer structure in which the input capacitor 200, the inductor 400, and the output capacitor 500 are stacked in the Z direction.

[0138] In addition, other structures of the power module 10H and its variants are substantially the same as those of the power module 10E in the embodiment shown in FIG. 8, for example, the arrangement of the power chip 300 of the power module 10H, and the structures of the first conduction structure 101 and the second conduction structure 102 and their variants are substantially the same as those of the power module 10E, and therefore, reference can be made to the related descriptions of the power module 10E above, which will not be repeated here.

[0139] In the embodiments shown in FIGS. 2-11, the first substrate D1 and the second substrate D2 are bonded and adhered, and the first substrate D1 and the third substrate D3 are bonded and adhered, but the present application is not limited thereto. In other embodiments, one group of two adjacent layers of the first substrate D1, the second substrate D2, and the third substrate D3 can be bonded and adhered, and the other group of two adjacent layers can be fixedly connected by other means (e.g., sintering connection or welding), which will be described below.

[0140] FIG. 12 shows an exemplary structure of a power module 10I in another embodiment of the present application. The power module 10I shown in FIG. 12 differs from the power module 10H shown in FIG. 11 in that the connection between the first substrate D1, the second substrate D2, and the third substrate D3 is different.

[0141] Specifically, referring to FIG. 12, the first substrate D1 and the second substrate D2 are fixedly connected by bonding and adhering, and a metallized via hole can be formed on the adhesive layer to achieve electrical connection between the first conduction structure 101 and the first trace L1. The first substrate D1 and the third substrate D3 are fixedly connected by welding, and the welding points 800 formed by welding can achieve electrical connection between the second conduction structure 102 and the first trace L1.

[0142] It can be understood that the above-mentioned FIG. 12 only schematically shows the fixed connection between the first substrate D1, the second substrate D2, and the third substrate D3, and does not constitute a limitation on the present application. For example, in other embodiments, the first substrate D1 and the third substrate D3 can be fixedly connected by bonding and adhering, and the first substrate D1 and the second substrate D2 can be fixedly connected by other means (e.g., sintering connection or welding).

[0143] Based on the power module 10I shown in FIG. 12, the first substrate D1 embedded with the inductor 400 can be first built-up, thereby forming the second substrate D2 embedded with the output capacitor 500, and then the third substrate D3 embedded with the input capacitor 200 which has been shaped is welded with the first substrate D1, thereby obtaining the multi-layer structure in which the input capacitor 200, the inductor 400 and the output capacitor 500 are sequentially stacked along the Z direction.

[0144] In the embodiments shown in FIGS. 2 to 12, the input capacitor 200 and the output capacitor 500 are both ceramic capacitors, but the present application is not limited thereto. In some other embodiments, the input capacitor 200 and the output capacitor 500 can also be other types of capacitors, such as silicon (Si) capacitors or organic polymer capacitors, which will be exemplarily introduced below.

[0145] FIG. 13 shows an exemplary structure of a power module 10J in another embodiment of the present application. The power module 10J shown in FIG. 13 is different from the power module 10C shown in FIGS. 5 and 6 in that the input capacitor 200 and the output capacitor 500 are different.

[0146] Referring to FIG. 13, in the power module 10J, the input capacitor 200 and the output capacitor 500 can both be silicon (Si) capacitors. In this way, the thickness of the input capacitor 200 and the output capacitor 500 can be thinner, and therefore the thickness of the third substrate D3 on which the input capacitor 200 is located and the thickness of the second substrate D2 on which the output capacitor 500 is located can be thinner, thereby making the thickness of the power module 10G thinner. It can be understood that the thickness of each device refers to the dimension of each device along the Z direction.

[0147] Based on the scheme that the input capacitor 200 and the output capacitor 500 are both silicon capacitors in the embodiment shown in FIG. 13, in some embodiments of the present application, the first conductive structure 101 can include a second metallized via S2 penetrating through the second substrate D2 on which the output capacitor 500 is located. Since the thickness of the input capacitor 200 and the output capacitor 500 can be thinner, the hole depth of the second metallized via S2 can be effectively reduced, thereby making the process feasibility of the second metallized via S2 higher, the shaping simpler and the yield higher.

[0148] It can be understood that the structure of the second conductive structure 102 is substantially the same as that of the first conductive structure 101, and only the arrangement direction needs to be changed accordingly, and therefore the description of the first conductive structure 101 can be referred to, which will not be repeated here.

[0149] In addition, other structures of the power module 10J and its variants are substantially the same as those of the power module 10C in the embodiment shown in FIGS. 5 and 6, for example, the arrangement of the input capacitor 200, the power chip 300, and the output capacitor 500 of the power module 10J, and the structures of the first conduction structure 101 and the second conduction structure 102 and their variants are substantially the same as those of the power module 10C, and thus, reference can be made to the relevant descriptions of the power module 10C above, and no further description is provided herein.

[0150] After introducing the structure of the power module, the forming method of the power module will be further introduced below in combination with the accompanying drawings. For ease of description, the power module 10A in the embodiment shown in FIG. 3 will be taken as an example for detailed description.

[0151] It should be noted that in the power module 10A, the second substrate D2 in which the output capacitor 500 is embedded is formed, and the first substrate D1 and the second substrate D2 are conducted in a manner substantially the same as that in which the third substrate D3 in which the input capacitor 200 is embedded is formed, and the first substrate D1 and the third substrate D3 are conducted. Therefore, for the sake of brevity of description, the first substrate D1 in which the inductor 400 is embedded and the second substrate D2 in which the output capacitor 500 is embedded will be mainly introduced below.

[0152] FIG. 14 shows a flowchart of the forming method of the power module 10A in the embodiment of the present application. FIGS. 15A to 15H show forming diagrams of the power module 10A in the embodiment of the present application. Referring to FIG. 13 and in combination with FIGS. 15A to 15H, the forming method specifically includes:

[0153] S110: embedding the inductor 400 in the first substrate D1, and forming the first trace L1 electrically connected to the inductor 400 on the first substrate D1.

[0154] Referring to FIG. 15A, in some embodiments of the present application, the inductor 400 can be embedded in the first substrate D1 by a buried electronic component packaging process.

[0155] In some embodiments of the present application, the first trace L1 can include a line pattern arranged on the surface of the first substrate D1 and a line pattern embedded in the first substrate D1, and the present application does not limit this.

[0156] S120: forming the second substrate D2 in which the output capacitor 500 is embedded on the first substrate D1.

[0157] Referring to FIG. 15B, and in combination with FIG. 15A, first, the first build-up structure 501 is formed on the first substrate D1, and then the slot 502 is formed on the first build-up structure 501. Next, referring to FIG. 15C, the output capacitor 500 is laid in the slot 502, for example, the output capacitor 500 can be bonded in the bottom wall of the slot 502 by wafer bonding film 600. Finally, referring to FIG. 15D, and in combination with FIG. 15C, the second build-up structure 503 is filled in the slot 502 to cover the output capacitor 500, and finally the second substrate D2 with the embedded output capacitor 500 is obtained.

[0158] S130: Forming the second trace L2 electrically connected to the output capacitor 500 on the second substrate D2, and forming the first conduction structure 101 for electrically connecting the first trace L1 and the second trace L2.

[0159] Referring to FIG. 15E, first, the through hole S11 is formed, which penetrates the first substrate D1 and the second substrate D2. For example, the through hole S11 can be formed by mechanical drilling. Then, referring to FIG. 15E, the blind hole S12 is formed so that at least part of the output capacitor 500 is exposed to the outside. For example, the blind hole S12 can be formed by laser drilling. Next, the impurities generated in the forming process of the through hole S11 and the blind hole S12 are removed to avoid interfering with the subsequent process. Then, referring to FIG. 15F, the through hole S11 and the blind hole S12 are metallized by copper plating, electroplating, etc. Finally, the first trace L1, the second trace L2, and the first conduction structure 101 electrically connecting the first trace L1 and the third trace L3 are formed, and the electrical connection between the first substrate D1 and the second substrate D2 is realized.

[0160] It should be noted that the forming process of the first trace L1, the second trace L2, and the first conduction structure 101 described above is only illustrative, and the application does not specifically limit the forming order of the first trace L1, the second trace L2, and the first conduction structure 101, as long as the electrical connection between the first substrate D1 and the second substrate D2 can be realized.

[0161] The above forming method can form the stacked structure of the first substrate D1 and the second substrate D2 by the build-up shown in S110-S130, and realize the interconnection between the first substrate D1 and the second substrate D2. In this way, there is no need to set an assembly solder joint between the layers, so that the link resistance can be effectively reduced, and the electrical performance of the power module 10A is improved.

[0162] In some embodiments of the application, after the stacked structure of the first substrate D1 and the second substrate D2 is formed, the traces for electrically connecting other devices can also be formed on the surface of the stacked structure.

[0163] Based on the above S110 to S130, the above forming method can further include:

[0164] S140: Form a fifth trace L5 electrically connected to the second trace L2 on the side of the second trace L2 facing away from the first substrate D1.

[0165] Referring to FIG. 15H, a circuit pattern can be made on the side of the second trace L2 facing away from the first substrate D1 to form the fifth trace L5. The fifth trace L5 is used to electrically connect to the load (for example, the chip 20).

[0166] For example, a build-up structure can be formed on the side of the second trace L2 facing away from the first substrate D1, and a dry film is laminated on the build-up structure. Then, the dry film is aligned with the negative film, and then placed in the exposure machine. Through ultraviolet light irradiation, the pattern on the negative film is transferred to the dry film, and the dry film in the exposed area is cured. Then, a developing solution is used to dissolve and remove the unexposed part of the dry film, and the exposed and cured dry film is retained on the board. In this way, the pattern on the negative film is transferred to the side of the second trace L2 facing away from the first substrate D1. Then, etching is performed, and after development, the copper surface not protected by the dry film is dissolved by the etching solution, thereby removing the excess copper and leaving the required circuit pattern. Finally, a specific chemical solution is used to strip the dry film, and the fifth trace L5 is obtained.

[0167] In addition, the fifth trace L5 can also be subjected to surface treatment. For example, the fifth trace L5 can be subjected to solder resist treatment to selectively expose the part of the fifth trace L5 required for soldering, so as to facilitate the subsequent soldering process.

[0168] It can be understood that the build-up method can be continued to form a third substrate D3 with the input capacitor 200 embedded therein on the surface of the first substrate D1 facing away from the second substrate D2, and then the power supply chip 300 is arranged on the side of the third substrate D3 facing away from the first substrate D1, and finally the power supply module 10A in the embodiment shown in FIG. 3 is obtained. The specific steps of forming the third substrate D3 with the input capacitor 200 embedded therein can refer to the above S110 to S130, which will not be described here.

[0169] It should be noted that the above FIGS. 14 to 15H only schematically show a forming process, and do not constitute a specific limitation on the present application. Depending on the specific structure of the power supply module, the forming method can also be different.

[0170] For example, based on the power supply module 10E shown in FIG. 8 and the power supply module 10G shown in FIG. 10, the formed power supply chip 300 can be embedded in the third substrate D3 in S120.

[0171] For example, based on the power module 10H shown in FIG. 11, the third substrate D3 in which the input capacitor 200 is embedded, the second substrate D2 in which the output capacitor 500 is embedded, and the first substrate D1 in which the inductor 400 is embedded can be formed separately, and then the second substrate D2, the first substrate D1, and the third substrate D3 can be laminated and bonded in the Z direction in this order, thereby obtaining a multilayer structure in which the input capacitor 200, the inductor 400, and the output capacitor 500 are laminated in the Z direction in this order.

[0172] For example, based on the power module 10H shown in FIG. 11, the third substrate D3 in which the input capacitor 200 is embedded, the second substrate D2 in which the output capacitor 500 is embedded, and the first substrate D1 in which the inductor 400 is embedded can be formed separately, and then the second substrate D2, the first substrate D1, and the third substrate D3 can be laminated and bonded in the Z direction in this order, thereby obtaining a multilayer structure in which the input capacitor 200, the inductor 400, and the output capacitor 500 are laminated in the Z direction in this order.

[0173] It should be noted that the embodiments are exemplary of the technical solutions of the present application, and those skilled in the art can make other modifications. For example, in the embodiments, the power module is taken as an example of the substrate lamination structure, and the substrate lamination structure includes the first substrate D1, the second substrate D2, and the third substrate D3 laminated in this order, wherein the first substrate D1 is embedded with the inductor 400, the second substrate D2 is embedded with the output capacitor 500, and the third substrate D3 is embedded with the input capacitor 200. However, the present application is not limited thereto, and in other embodiments, the substrate lamination structure can also have other purposes. The substrate lamination structure can include more or fewer substrates. Other types of devices can be embedded in different substrates. For example, the substrate lamination structure can include the first substrate D1 and the second substrate D2 laminated in this order, and the first substrate D1 and the second substrate D2 can be embedded with other types of devices. For example, the first substrate D1 can be embedded with a first capacitor (as another example of the first device), and the second substrate D2 can be embedded with a second capacitor (as another example of the second device). For example, the first substrate D1 can also be embedded with a chip (as another example of the first device), and the second substrate D2 can be embedded with an inductor (as another example of the second device). For example, the first substrate D1 can also be embedded with a resistor (as another example of the first device), and the second substrate D2 can be embedded with an inductor (as another example of the second device), and the present application does not make specific limitations thereto.

[0174] The above describes the embodiments of the present application by specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure. Although the description of the present application is introduced in combination with some embodiments, it does not mean that the features of the present application are limited to the embodiments. On the contrary, the purpose of introducing the present application in combination with the embodiments is to cover other options or modifications that can be extended based on the claims of the present application. The present application can also not use these details. In addition, in order to avoid confusion or obscure the focus of the present application, some specific details are omitted in the description. It should be noted that the embodiments and features in the embodiments in the present application can be combined with each other without conflict.

[0175] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "outer", "inner", "circumferential", "radial", "axial" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0176] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "set", "mount", "connect", "fit" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between the two elements inside. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0177] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and variations.

Claims

1. A substrate stack structure, characterized by, The plurality of substrates includes a first substrate embedded with a first device, and a second substrate embedded with a second device; The first substrate is further provided with a first trace electrically connected with the first device, and the second substrate is further provided with a second trace electrically connected with the second device, and the substrate stack structure further includes a first conductive structure for electrically connecting the first trace and the second trace.

2. The substrate stack structure of claim 1, wherein The first substrate and the second substrate are press-bonded.

3. The substrate stack structure of claim 1, wherein The first conductive structure is arranged inside or on a sidewall of the substrate stack structure.

4. The substrate stack structure of claim 3, wherein, The first conductive structure includes a first metallized via penetrating through the first substrate and the second substrate to electrically connect the first trace and the second trace.

5. The substrate stack structure of claim 3, wherein The first conductive structure includes a second metallized via penetrating through the second substrate to electrically connect the first trace and the second trace.

6. The substrate stack structure of claim 3, wherein The first conductive structure includes a third metallized via and a conductive member, the third metallized via is arranged on a surface of the second substrate facing away from the first substrate and electrically connected with the second trace, and the conductive member is embedded in the second substrate and electrically connected with the third metallized via and the first trace.

7. The substrate stack structure of claim 3, wherein The first conductive structure includes a metal layer arranged on a sidewall of the substrate stack structure and covering sidewalls of the first substrate and the second substrate to electrically connect the first trace and the second trace.

8. The substrate stack structure of claim 1, wherein, A surface of the second device facing away from the first substrate is flush with a surface of the second substrate facing away from the first substrate.

9. The substrate stack of claim 1, wherein, The first device and the second device are inductors, capacitors, resistors or chips.

10. The substrate stack of claim 9, wherein, The capacitor is a silicon capacitor, a ceramic capacitor or an organic polymer capacitor.

11. The substrate stack structure of claim 1, wherein A third substrate is arranged on a side of the first substrate facing away from the second substrate, and the third substrate is embedded with a third device, and the third substrate is provided with a third trace electrically connected with the third device, and the substrate stack structure further includes a second conductive structure for electrically connecting the first trace and the third trace. The first substrate and the second substrate are press-bonded, and the first substrate and the third substrate are press-bonded, sintered or welded.

12. The substrate stack of claim 11, wherein, The substrate stack structure further includes a power chip, the first device is an inductor, the second device is an output capacitor, the third device is an input capacitor, and the input capacitor, the power chip, the inductor and the output capacitor are electrically connected in sequence.

13. The substrate stack of claim 12, wherein, The power chip is located on a side of the third substrate facing away from the first substrate, and at least part of the power chip is exposed to the outside.

14. The substrate stack of claim 12, wherein, A fourth substrate is arranged on a side of the third substrate facing away from the first substrate and electrically connected with the third substrate, and the power chip is embedded in the fourth substrate.

15. The substrate stack of claim 14, wherein, The fourth substrate is further embedded with a heat-conducting structure, one end of the heat-conducting structure is attached to the power chip, and the other end is exposed to the outside.

16. The substrate stack structure of claim 12, wherein, The power chip is embedded in the third substrate.

17. The substrate stack of any of claims 12-16, wherein, The number of the power supply chips is multiple, and the multiple power supply chips are stacked along the thickness direction of the substrate stack structure.

18. An electronic device, comprising: The electronic device comprises a carrier and the substrate stack structure of any one of claims 1 to 17, and the substrate stack structure is arranged on the carrier.

19. The electronic device of claim 18, wherein, A third substrate in the multiple substrates is arranged on the side of the first substrate away from the second substrate, and the third substrate is embedded with a third device; The third substrate is provided with a third trace electrically connected to the third device, and the substrate stack structure further comprises a second through structure for electrically connecting the second trace and the third trace; The first device is an inductor, the second device is an output capacitor, and the third device is an input capacitor; The electronic device further comprises a load arranged on the carrier, and the substrate stack structure is used to supply power to the load.

20. The electronic device of claim 19, wherein, The load is arranged on the side of the second substrate away from the first substrate.

21. A method of forming a stack of substrates, the method comprising: The method comprises: embedding a first device in a first substrate, and forming a first trace electrically connected to the first device on the first substrate; forming a second substrate embedded with a second device on the first substrate; forming a second trace electrically connected to the second device on the second substrate, and forming a first through structure for electrically connecting the first trace and the second trace.

22. The molding method according to claim 21, wherein The forming of the second substrate embedded with the second device on the first substrate comprises: forming a first build-up structure on the first substrate; opening a groove on the first build-up structure; laying the second device in the groove; filling a second build-up structure in the groove to cover the second device, so as to obtain the second substrate embedded with the second device.

23. The molding method according to claim 21, wherein The forming of the first through structure comprises: making a first metallized via, the first metallized via penetrating through the first substrate and the second substrate and electrically connecting the first trace and the second trace, and the first metallized via constitutes the first through structure.

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