Clock signal generation circuit, chip, and electronic device

Abstract

Embodiments of the present application provide a clock signal generation circuit, a chip, and an electronic device. The clock signal generation circuit comprises: a reference voltage module, configured to output a reference voltage; a voltage-controlled oscillator module, configured to oscillate under the control of a control voltage and output a clock signal; a voltage feedback module, configured to output a feedback voltage on the basis of the clock signal, wherein the magnitude of the feedback voltage is negatively correlated with the frequency of the clock signal; and an error amplification module, configured to output a control voltage on the basis of the reference voltage and the feedback voltage, wherein the reference voltage periodically varies within at least a portion of an operating period of the clock signal generation circuit.

Description

Clock signal generation circuit, chip and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411327380.X, filed on September 23, 2024, and entitled "Clock signal generation circuit, chip and electronic device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of integrated circuits, in particular to a clock signal generation circuit, a chip and an electronic device. BACKGROUND

[0003] At present, an RC oscillator is an oscillation circuit that generates a clock signal by cyclically charging and discharging a capacitor and comparing the voltage in the charging and discharging process of the capacitor. In a system-on-chip circuit that does not have high requirements for clock source precision and frequency, the RC oscillator is widely used due to its low cost, fast circuit startup and easy on-chip integration.

[0004] When the RC oscillator generates a fixed frequency clock signal to control the corresponding circuit to work, for example, when the fixed frequency clock signal controls the switching action, the working circuit will usually generate a large electromagnetic interference (EMI) signal. In related technologies, clock spreading for the RC oscillator is an effective method to reduce chip electromagnetic interference. By adjusting the current for charging and discharging the capacitor or changing the capacitance value of the capacitor, the charging and discharging speed of the capacitor is changed to expand the frequency of the clock signal, thereby spreading the energy contained in the narrow band of the clock source in a wider frequency band, reducing the peak frequency energy of the fundamental frequency and harmonic frequency, and finally weakening the electromagnetic interference phenomenon when the circuit works.

[0005] However, the clock circuit based on the RC oscillator is affected by many non-ideal factors. For example, the RC oscillator needs to compare the reference voltage with the voltage in the charging and discharging process of the capacitor through a comparator during the working process. The delay of the comparator will seriously deteriorate the frequency drift of the RC oscillator, which leads to the problem of decreased output frequency precision of the RC oscillator. TECHNICAL PROBLEM

[0006] The embodiments of the present application provide a clock signal generation circuit, a chip and an electronic device to solve the electromagnetic interference phenomenon caused by the excessive energy of the clock signal fundamental frequency. TECHNICAL SOLUTION

[0007] The technical solution of the present application is as follows:

[0008] In a first aspect, the embodiments of the present application provide a clock signal generation circuit, comprising:

[0009] The reference voltage module is configured to output a reference voltage.

[0010] The voltage-controlled oscillation module is configured to oscillate under control of a control voltage and output a clock signal.

[0011] The voltage feedback module is configured to output a feedback voltage according to the clock signal, the magnitude of the feedback voltage being negatively related to the frequency of the clock signal.

[0012] The error amplification module is configured to output the control voltage according to the reference voltage and the feedback voltage.

[0013] The reference voltage periodically changes at least in part of a time period during operation of the clock signal generation circuit.

[0014] In a second aspect, the embodiments of the present application further provide a chip comprising the clock signal generation circuit.

[0015] In a third aspect, the embodiments of the present application further provide an electronic device comprising the chip or the clock signal generation circuit.

[0016] These and other aspects of the present application will become more apparent from the following description. Advantages

[0017] The error amplification module, the voltage feedback module and the voltage-controlled oscillation module form a loop, the voltage feedback module serving as a negative feedback module to output the feedback voltage, and through negative feedback control, the voltage-controlled oscillation module can output the clock signal with the target frequency, the process of generating the clock signal does not need to involve the comparator, and finally the influence of the delay of the comparator on the frequency accuracy of the clock signal can be avoided; meanwhile, since the reference voltage periodically changes in part of the time period during operation of the clock signal generation circuit, the clock signal output by the voltage-controlled oscillation module will also periodically change with the reference voltage, so that the frequency of the clock signal periodically changes around the target frequency, and finally the electromagnetic interference phenomenon caused by the clock signal can be weakened. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0019] FIG. 1 shows a circuit schematic diagram of an RC oscillator in the related art.

[0020] FIG. 2 shows a schematic diagram of a clock signal generation circuit in the embodiments of the present application.

[0021] Figure 3 shows a variation of the reference voltage and the control voltage in the embodiment of the application.

[0022] Figure 4 shows a frequency spectrum of the clock signal in the embodiment of the application.

[0023] Figure 5 shows another schematic diagram of the clock signal generation circuit in the embodiment of the application.

[0024] Figure 6 shows another schematic diagram of the clock signal generation circuit in the embodiment of the application.

[0025] Figure 7 shows another schematic diagram of the clock signal generation circuit in the embodiment of the application.

[0026] Figure 8 shows a schematic diagram of the reference voltage module in the embodiment of the application.

[0027] Figure 9 shows another schematic diagram of the reference voltage module in the embodiment of the application.

[0028] Figure 10 shows another schematic diagram of the reference voltage module in the embodiment of the application.

[0029] Figure 11 shows another schematic diagram of the reference voltage module in the embodiment of the application.

[0030] Figure 12 shows another schematic diagram of the clock signal generation circuit in the embodiment of the application.

[0031] Figure 13 shows another schematic diagram of the reference voltage module in the embodiment of the application.

[0032] Figure 14 shows another schematic diagram of the reference voltage module in the embodiment of the application.

[0033] Figure 15 shows a schematic diagram of the voltage feedback module in the embodiment of the application.

[0034] Figure 16 shows another schematic diagram of the clock signal generation circuit in the embodiment of the application.

[0035] wherein 10 is a reference voltage module, 11 is a first current mirror unit, 12 is a second current mirror unit, 13 is a resistance unit, 101 is a charge and discharge unit, 102 is a capacitor unit, 20 is a voltage controlled oscillation module, 30 is a voltage feedback module, 31 is a non-overlapping clock unit, 40 is an error amplification module,

[0036] The reference voltage Vref, the control voltage Vctrl, the clock signal CLK, the first clock signal CLK1, the second clock signal CLK2, the feedback voltage VFB, the first mirror current I1, the second mirror current I2, the third mirror current I3, the reference voltage VBG, the first preset voltage V1, the second preset voltage V2, the third preset voltage V3;

[0037] The first operational amplifier OP1, the first transistor M1, the first resistor R1, the first mirror transistor MP1, the second mirror transistor MP2, the third mirror transistor MP3, the first switch S1, the second operational amplifier OP2, the second transistor M2, the second resistor R2, the fourth mirror transistor MP4, the fifth mirror transistor MP5, the second switch S2;

[0038] The first current source IS1, the second current source IS2, the third switch S3, the fourth switch S4, the fifth switch S5, the first comparator COMP1, the second comparator COMP2, the third current source IS3, the first capacitor C1, the second capacitor C2, the sixth switch S6, the seventh switch S7.

[0039] Embodiments of the present application

[0040] The embodiments of the present application will be described in detail below, examples of the embodiments are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below are exemplary only, and are used only for explaining the present application, and cannot be understood as limiting the present application.

[0041] In order for those skilled in the technical field to better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0042] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any such actual relationship or order between or among the entities or actions.

[0043] Also, the use of "or" means "and / or" unless strictly stated otherwise. Moreover, the use of the term "including" as well as "comprising" is used in the sense of "including at least" and should not be interpreted as being restricted or limited to names of elements recited. Singular forms "a", "an" and "the" include plural references unless the context clearly dictates otherwise.

[0044] In the description of the embodiments of the present application, the words "example" or "for example" are used to mean serving as an example, instance, or illustration, and not to imply any preference or superiority. The use of words like "example" or "for example" is intended to present concepts in a clear and concise manner.

[0045] In addition, "multiple" in the embodiments of the present application refers to two or more, and therefore "multiple" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C means that A, B, C, A and B, A and C, B and C, or A and B and C can be included.

[0046] It should be noted that in the embodiments of the present application, the association relationship of the associated objects described by "and / or" means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / ", if not specially stated, generally represents a "or" relationship between the associated objects before and after it.

[0047] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.

[0048] The first pole / first end of each transistor in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and the drain of a transistor can be symmetrical in structure, the source and the drain of the transistor can be indistinguishable in structure, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be indistinguishable in structure. For example, when the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end of the transistor is the drain; for example, when the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end of the transistor is the source.

[0049] The nodes such as the first node and the second node in the circuit structure provided by the embodiments of the present application do not represent actual components, but represent the convergence points of relevant couplings in a circuit diagram, that is, these nodes are nodes equivalent to the convergence points of relevant couplings in the circuit diagram.

[0050] At present, an RC oscillator is an oscillation circuit that generates a clock signal by cyclically charging and discharging a capacitor and comparing the voltages in the charging and discharging processes of the capacitor. Referring to FIG. 1, FIG. 1 shows a circuit schematic of an RC oscillator in the related art, which includes a comparator COMP1, a comparator COMP2, an RS flip-flop composed of two NAND gates, a capacitor Cx, a capacitor Cy, a transistor MN1 for controlling charging and discharging of the capacitor Cx, and a transistor MN2 for controlling charging and discharging of the capacitor Cy.

[0051] In the working process of the RC oscillator, the two NAND gates respectively output control signals OUT1 and OUT2, thereby controlling the transistors MN1 and MN2 to alternately charge the capacitors Cx and Cy. When the voltages IN1 and IN2 output by the capacitors Cx and Cy exceed a reference voltage Vref, one of the capacitors Cx and Cy is charged and the other is discharged, thereby causing the output terminals of the comparators COMP1 and COMP2 to output clock signals with high and low levels alternately changing.

[0052] In an ideal case without considering loop delay (for example, comparator delay), the capacitors Cx and Cy are charged to the reference voltage Vref for half a period of the clock signal, and it can be known that the oscillation frequency f of the output clock signal is: f = N / (2RC)

[0053] wherein N is the ratio of the charging current NIref of the capacitors Cx and Cy to the reference current Iref, R is the resistance corresponding to the generation of the reference voltage Vref, and C is the capacitance value of the capacitors Cx and Cy.

[0054] In consideration of the actual situation of the comparator delay, the actual oscillation frequency f of the output clock signal is: f = N / 2(RC + t)

[0055] Wherein, t is the time corresponding to the comparator delay.

[0056] It can be seen that, since the RC oscillator needs to compare the reference voltage with the voltage in the process of capacitor charging and discharging in the working process, the delay of the comparator will seriously deteriorate the frequency drift of the RC oscillator. If the clock signal is spread by adjusting the current of capacitor charging and discharging or changing the capacitance value of the capacitor, the frequency accuracy of the clock signal will also be reduced.

[0057] Therefore, the present application provides a clock signal generation circuit, a chip and an electronic device, which are described in detail below.

[0058] First, referring to FIG. 2, FIG. 2 shows a schematic diagram of a clock signal CLK generation circuit in an embodiment of the present application, wherein the clock signal CLK generation circuit comprises a reference voltage module 10, a voltage controlled oscillation module 20, a voltage feedback module 30 and an error amplification module 40.

[0059] The reference voltage module 10 is used to output a reference voltage Vref, so as to control the size of the control voltage Vctrl output by the error amplification module 40. In some embodiments of the present application, the reference voltage module 10 can generate the reference voltage Vref through resistance, for example, the reference voltage module 10 generates the reference voltage Vref at one end of the resistance by controlling the current flowing through the resistance. In some embodiments of the present application, the reference voltage module 10 can generate the reference current through capacitance, for example, the reference voltage module 10 generates the reference voltage Vref at one end of the capacitor by controlling the way of charging and discharging the capacitor.

[0060] It can be understood that the reference voltage module 10 can also output the reference voltage Vref in other ways, such as band gap reference circuit, low dropout linear regulator, BOOST boost circuit, BUCK buck circuit, etc.

[0061] The control end of the voltage-controlled oscillation module 20 is connected with the output end of the error amplification module 40, so as to oscillate and output the clock signal CLK under the control of the control voltage Vctrl. The frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 is controlled by the size of the control voltage Vctrl. In some embodiments of the present application, the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 is positively correlated with the size of the control voltage Vctrl, for example, the greater the control voltage Vctrl, the greater the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20; on the contrary, the smaller the control voltage Vctrl, the smaller the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20. In some embodiments of the present application, the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 is negatively correlated with the size of the control voltage Vctrl, for example, the smaller the control voltage Vctrl, the greater the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20; on the contrary, the greater the control voltage Vctrl, the smaller the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20.

[0062] Exemplarily, the voltage-controlled oscillation module 20 can include but is not limited to a harmonic oscillator or a relaxation oscillator, wherein the harmonic oscillator is such as an LC crystal oscillator and a crystal oscillator, and the relaxation oscillator is such as a delay-based ring voltage-controlled oscillator, a ground-capacitance-based voltage-controlled oscillator, and an emitter-coupled voltage-controlled oscillator.

[0063] The voltage feedback module 30 is configured to output a feedback voltage VFB according to the clock signal CLK, wherein the size of the feedback voltage VFB is negatively correlated with the frequency of the clock signal CLK, for example, the higher the frequency of the clock signal CLK, the greater the voltage value of the feedback voltage VFB; on the contrary, the lower the frequency of the clock signal CLK, the smaller the voltage value of the feedback voltage VFB.

[0064] In some embodiments of the present application, the voltage feedback module 30 can include a switched-capacitor circuit. Since the capacitor has the characteristic of passing alternating current and blocking direct current, the higher the frequency of the switch opening / closing controlled by the clock signal CLK, the smaller the impedance of the capacitor, and the greater the feedback voltage VFB that the switched-capacitor circuit can generate; on the contrary, the lower the frequency of the switch opening / closing controlled by the clock signal CLK, the greater the impedance of the capacitor, and the smaller the feedback voltage VFB that the switched-capacitor circuit can generate.

[0065] In some embodiments of the present application, the voltage feedback module 30 can include a switched-inductor circuit. Since the inductor has the characteristic of passing direct current and blocking alternating current, the higher the frequency of the switch opening / closing controlled by the clock signal CLK, the greater the impedance of the inductor, and the greater the feedback voltage VFB that the switched-inductor circuit can generate; on the contrary, the lower the frequency of the switch opening / closing controlled by the clock signal CLK, the smaller the impedance of the inductor, and the smaller the feedback voltage VFB that the switched-inductor circuit can generate.

[0066] The error amplification module 40 is configured to output the control voltage Vctrl according to the reference voltage Vref and the feedback voltage VFB, so as to control the voltage-controlled oscillation module 20 to oscillate and output the clock signal CLK through the control voltage Vctrl. As an example, the error amplification module 40 can include an operational amplifier, the non-inverting input terminal of the operational amplifier is connected to the reference voltage Vref, and the inverting input terminal of the operational amplifier is connected to the feedback voltage VFB. Due to the virtual short and virtual open characteristics of the operational amplifier, the control voltage Vctrl output by the operational amplifier changes the frequency of the clock signal CLK, so that the feedback voltage VFB changes following the frequency of the clock signal CLK and approaches the reference voltage Vref. Finally, the frequency of the clock signal CLK is locked after the loop formed by the error amplification module 40, the voltage feedback module 30 and the voltage-controlled oscillation module 20 is stabilized, so as to ensure the stability of the clock signal CLK.

[0067] It can be seen that the present application forms a loop with the error amplification module 40, the voltage feedback module 30 and the voltage-controlled oscillation module 20. The voltage feedback module 30 is used as a negative feedback module to output the feedback voltage VFB to control the size of the control voltage Vctrl output by the error amplification module 40 in combination with the reference voltage Vref, so that the voltage-controlled oscillation module 20 can output the clock signal CLK with the target frequency f0 through negative feedback. The process of generating the clock signal CLK does not need to involve the comparator, so that the delay of the comparator can be avoided to affect the frequency accuracy of the oscillation circuit. Meanwhile, in the embodiment of the present application, the reference voltage Vref periodically changes in part of the time period during the working process of the clock signal CLK generating circuit, so that the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 also periodically changes following the reference voltage Vref, so that the frequency of the clock signal CLK periodically changes around the target frequency f0, and finally the electromagnetic interference phenomenon caused by the clock signal CLK is weakened.

[0068] In some embodiments of the present application, the size of the reference voltage Vref is equal to the first preset value before the frequency of the clock signal CLK is stabilized for the first time, and the reference voltage Vref periodically changes and the average size is equal to the first preset value after the frequency of the clock signal CLK is stabilized for the first time.

[0069] For example, referring to FIG. 3, which shows a variation diagram of the reference voltage Vref and the control voltage Vctrl in the embodiment of the present application, before the time t1, the reference voltage Vref keeps unchanged at a first preset value, the control voltage Vctrl first gradually increases to make the frequency of the clock signal CLK increase, and after the frequency of the clock signal CLK exceeds the target frequency f0, the control voltage Vctrl decreases, and at the time t1, the frequency of the clock signal CLK is first stabilized around the target frequency f0. After the time t2, the reference voltage Vref periodically varies with an average value equal to the first preset value, so that the control voltage Vctrl output by the error amplification module 40 periodically varies, and finally the spread spectrum of the clock signal CLK is realized under the control of the periodically varying control voltage Vctrl.

[0070] It should be noted that, according to the foregoing, the size of the reference voltage Vref can change the frequency of the clock signal CLK, and therefore the first preset value is a set parameter value corresponding to the frequency of the clock signal CLK. Those skilled in the art can set the size of the first preset value corresponding to the reference voltage Vref according to actual needs (for example, the frequency of the clock signal CLK), such as 1V, 2V, 2.2V, etc., which is not limited in the present application.

[0071] Continuing to refer to FIG. 4, which shows a frequency spectrum diagram of the clock signal CLK in the embodiment of the present application, it can be seen that, between the time t1 and the time t2, when the frequency of the clock signal CLK is stabilized at the target frequency f0, the energy of the clock signal CLK is concentrated at the target frequency f0, and therefore the electromagnetic interference phenomenon during the operation of the circuit is more serious. After the time t2, the frequency of the clock signal CLK periodically varies around the target frequency f0, and the energy contained in the narrow band of the clock signal CLK is spread in a wider frequency band. Compared with the clock signal CLK between the time t1 and the time t2, the peak frequency energy of the fundamental frequency and the harmonic frequency is reduced, and therefore the electromagnetic interference phenomenon during the operation of the circuit is weakened.

[0072] It can be understood that, in some possible embodiments, the reference voltage module 10 can also make the reference voltage Vref periodically vary with an average value equal to the first preset value before the frequency of the clock signal CLK is first stabilized, that is, the reference voltage module 10 can also start the spread spectrum process of the clock signal CLK before the clock signal CLK is stabilized.

[0073] In some embodiments of the present application, for example, for the embodiment in which the reference voltage module 10 can generate a reference current through a resistor, referring to FIG. 5, FIG. 5 shows another schematic diagram of the clock signal CLK generation circuit in an embodiment of the present application, wherein the reference voltage module 10 comprises a first current mirror unit 11, a second current mirror unit 12, and a resistor unit 13; the first current mirror unit 11 is configured to output a mirror current with a fixed size, and the second current mirror unit 12 is configured to output a mirror current with a periodically changing size; and the resistor unit 13 is configured to generate a reference voltage Vref according to the mirror current output by the first current mirror unit 11 and / or the second current mirror unit 12.

[0074] It should be noted that, since the first current mirror unit 11 can output a mirror current with a fixed size, and the second current mirror unit 12 can output a mirror current with a periodically changing size, before the frequency of the clock signal CLK is stabilized for the first time, the reference voltage module 10 can control the first current mirror unit 11 to output a mirror current, so as to generate a reference voltage Vref with a fixed size through the resistor unit 13; and after the frequency of the clock signal CLK is stabilized for the first time, the reference voltage module 10 can control the second current mirror unit 12 to output a mirror current, so as to generate a reference voltage Vref with a periodically changing size through the resistor unit 13.

[0075] For example, the first current mirror unit 11 and the second current mirror unit 12 can comprise one or more current sources, such as a voltage-controlled current source (VCCS) or a current-controlled current source (CCCS) for the first current mirror unit 11, and a triangular wave current source, a pulse current source, a sinusoidal wave current source, etc. for the second current mirror unit 12.

[0076] In some embodiments of the present application, the first current mirror unit 11 and the second current mirror unit 12 can output a single current signal, for example, referring to FIG. 6, FIG. 6 shows another schematic diagram of the clock signal CLK generation circuit in an embodiment of the present application, the first current mirror unit 11 is configured to output a second mirror current I2, a first switch S1 controls whether the second mirror current I2 flows into the resistor unit 13, the second current mirror unit 12 is configured to output a third mirror current I3, and a second switch S2 controls whether the third mirror current I3 flows into the resistor, wherein the third mirror current I3 periodically changes and has an average size equal to that of the second mirror current I2, so that the reference voltage Vref generated based on the third mirror current I3 will periodically change, and has an average size equal to that of the reference voltage Vref generated based on the second mirror current I2.

[0077] In some embodiments of the present application, the first current mirror unit 11 and / or the second current mirror unit 12 can output multiple current signals. For example, referring to FIG. 7, which shows another schematic diagram of the clock signal CLK generation circuit in an embodiment of the present application, the first current mirror unit 11 is configured to output a first mirror current I1 and a second mirror current I2, and the second current mirror unit 12 is configured to output a third mirror current I3. The first switch S1 controls whether the second mirror current I2 flows into the resistance unit 13, and the second switch S2 controls whether the third mirror current I3 flows into the resistance unit 13. The third mirror current I3 periodically varies and has an average size equal to that of the second mirror current I2.

[0078] It should be noted that in FIG. 7, the first mirror current I1 flows into the resistance unit 13 before and after the frequency of the clock signal CLK is stabilized for the first time. Therefore, before the frequency of the clock signal CLK is stabilized for the first time, the reference voltage Vref output by the reference voltage module 10 has a size of Vref = (I1 + I2) * R, and after the frequency of the clock signal CLK is stabilized for the first time, the reference voltage Vref output by the reference voltage module 10 has a size of Vref = (I1 + I3) * R. Since the third mirror current I3 periodically varies and has an average size equal to that of the second mirror current I2, the reference voltage Vref generated based on the first mirror current I1 and the third mirror current I3 not only periodically varies, but also has an average size equal to that of the reference voltage Vref generated based on the first mirror current I1 and the second mirror current I2.

[0079] It can be understood that the first current mirror unit 11 can also output more fixed mirror currents, or the second current mirror unit 12 can output multiple mirror currents that periodically vary in size, or one or more fixed mirror currents and one or more mirror currents that periodically vary in size, to adjust the size of the reference voltage Vref.

[0080] As an exemplary embodiment of the first current mirror unit 11, referring to FIG. 8, FIG. 8 shows a schematic diagram of the reference voltage module 10 in the embodiment of the present application, wherein the first current mirror unit 11 comprises a first operational amplifier OP1, a first transistor M1, a first resistor R1, a first mirror transistor MP1 and a second mirror transistor MP2; the first end of the first mirror transistor MP1 is connected with the power supply end VDD, and the control end of the first mirror transistor MP1 is connected with the second end of the first mirror transistor MP1; the first end of the second mirror transistor MP2 is connected with the power supply end VDD, the control end of the second mirror transistor MP2 is connected with the control end of the first mirror transistor MP1, and the second end of the second mirror transistor MP2 is connected with the resistor unit 13 to input the mirror current to the resistor unit 13; the first end of the first transistor M1 is connected with the second end of the first mirror transistor MP1, the second end of the first transistor M1 is connected with the first end of the first resistor R1, and the second end of the first resistor R1 is connected with the ground end; the first input end of the first operational amplifier OP1 is connected with the reference voltage VBG, the second input end of the first operational amplifier OP1 is connected with the first end of the first resistor R1, and the output end of the first operational amplifier OP1 is connected with the control end of the first transistor M1.

[0081] It should be noted that the reference voltage VBG can be provided by a bandgap reference source, and since the operational amplifier has the virtual short and virtual open characteristics, the voltage at the first end of the first resistor R1 is equal to the reference voltage VBG connected to the first input end of the first operational amplifier OP1, and thus the current flowing through the first mirror transistor MP1, the first transistor M1 and the first resistor R1 is: I = VBG / R1

[0082] At the same time, since the source voltage and the gate voltage of the first mirror transistor MP1 and the second mirror transistor MP2 are equal, the first mirror transistor MP1 and the second mirror transistor MP2 form a current mirror, and it can be known that the current flowing through the second mirror transistor MP2 (i.e. the first mirror current I1) is: I1 = I / n1 = VBG / (R1*n1)

[0083] Wherein, n1 is the mirror ratio between the first mirror transistor MP1 and the second mirror transistor MP2.

[0084] It can be seen that since the reference voltage VBG is fixed, the first mirror current I1 with a fixed size can be output through the above circuit structure, so as to output the reference voltage Vref with a fixed size to the error amplification module 40 through the resistor unit 13 before the frequency of the clock signal CLK is first stabilized.

[0085] In some embodiments of the present application, for example, for the embodiment in which the first current mirror unit 11 can output a plurality of current signals, referring to FIG. 9, FIG. 9 shows another schematic diagram of the reference voltage module 10 in the embodiments of the present application, wherein the first current mirror unit 11 further comprises a third mirror transistor MP3 and a first switch S1; the first end of the third mirror transistor MP3 is connected with the power supply end VDD, the control end of the third mirror transistor MP3 is connected with the control end of the second mirror transistor MP2; the first end of the first switch S1 is connected with the second end of the third mirror transistor MP3, and the second end of the first switch S1 is connected with the resistance unit 13.

[0086] Similarly, since the source voltage and the gate voltage of the first mirror transistor MP1 and the third mirror transistor MP3 are equal, the first mirror transistor MP1 and the third mirror transistor MP3 form a current mirror, and it can be known that the current (i.e. the second mirror current I2) flowing through the third mirror transistor MP3 when the first switch S1 is closed is: I2=I / n2=VBG / (R1*n2)

[0087] Wherein, n2 is the mirror ratio between the first mirror transistor MP1 and the third mirror transistor MP3.

[0088] Therefore, before the frequency of the clock signal CLK is stabilized for the first time, the first switch S1 is in the closed state, and at this time, the reference voltage Vref generated by the resistance unit 13 is: Vref=(I1+I2)*R0=(VBG / (R1*n1)+VBG / (R1*n2))*R0

[0089] It can be seen that since the reference voltage VBG is fixed, the reference voltage Vref with a fixed size can be output through the above current mirror structure, so as to facilitate the clock signal CLK generating circuit to quickly output the clock signal CLK with a stable frequency, and to spread the spectrum of the clock signal CLK after it is stabilized.

[0090] In some embodiments of the present application, referring to FIG. 10, FIG. 10 shows another schematic diagram of the reference voltage module 10 in the embodiments of the present application, wherein the second current mirror unit 12 comprises a second operational amplifier OP2, a second transistor M2, a second resistor R2, a fourth mirror transistor MP4, a fifth mirror transistor MP5, and a second switch S2; the first end of the fourth mirror transistor MP4 is connected with the power supply end VDD, the control end of the fourth mirror transistor MP4 is connected with the second end of the fourth mirror transistor MP4; the first end of the fifth mirror transistor MP5 is connected with the power supply end VDD, the control end of the fifth mirror transistor MP5 is connected with the control end of the fourth mirror transistor MP4; the first end of the second transistor M2 is connected with the second end of the fourth mirror transistor MP4, the second end of the second transistor M2 is connected with the first end of the second resistor R2, the second end of the second resistor R2 is connected with the ground end; the first input end of the second operational amplifier OP2 is connected with a periodically changing preset voltage signal, the second input end of the second operational amplifier OP2 is connected with the first end of the second resistor R2, the output end of the second operational amplifier OP2 is connected with the control end of the second transistor M2; the first end of the second switch S2 is connected with the second end of the fifth mirror transistor MP5, the first end of the second switch S2 is connected with the resistor unit 13.

[0091] It should be noted that the periodically changing preset voltage signal VTRI can be a triangular wave voltage signal, a sine / cosine alternating voltage signal, a pulse voltage signal, etc., which is not limited in the present application. Since the operational amplifier has the virtual short and virtual open characteristics, the voltage at the first end of the second resistor R2 is equal to the preset voltage signal connected to the first input end of the second operational amplifier OP2, and thus the current flowing through the first mirror transistor MP1, the first transistor M1 and the first resistor R1 is: I = VTRI / R2

[0092] At the same time, since the source voltage and the gate voltage of the fourth mirror transistor MP4 and the fifth mirror transistor MP5 are equal, the fourth mirror transistor MP4 and the fifth mirror transistor MP5 form a current mirror, and thus the current flowing through the fifth mirror transistor MP5 (i.e. the third mirror current I3) is: I3 = I / n3 = VTRI / (R1*n3)

[0093] Wherein, n3 is the mirror ratio between the fourth mirror transistor MP4 and the fifth mirror transistor MP5.

[0094] Therefore, after the frequency of the clock signal CLK is stabilized for the first time, the first switch S1 is in an open state, and the second switch S2 is in a closed state, at this time, the reference voltage Vref generated by the resistor unit 13 is: Vref = (I1+I3)*R0 = (VBG / (R1*n1)+VTRI / (R1*n3))*R0

[0095] It can be seen that, due to the periodic change of the preset voltage signal VTRI, the third mirror current I3 with periodically changing size can be output through the above-mentioned current mirror structure; meanwhile, when the mirror ratio between the first mirror transistor MP1 and the third mirror transistor MP3 is equal to the mirror ratio between the fourth mirror transistor MP4 and the fifth mirror transistor MP5 (i.e. n2=n3), if the average voltage of the preset voltage signal VTRI is equal to the reference voltage VBG, then the average current size of the third mirror current I3 is also equal to that of the second mirror current I2 at this time, and thus the average size of the reference voltage Vref generated by the resistance unit 13 is the same. Meanwhile, it can be known from the foregoing embodiments that, by closing the first switch S1 and opening the second switch S2 before the frequency of the clock signal CLK is stabilized for the first time, the stable reference voltage Vref can be output, and by opening the first switch S1 and closing the second switch S2 after the frequency of the clock signal CLK is stabilized for the first time, the periodically changing reference voltage Vref can be output.

[0096] It can be understood that, in FIG. 10, a single resistance R0 is used as the resistance unit 13, and in some possible embodiments, the resistance unit 13 includes a plurality of resistances connected in series and / or in parallel. Meanwhile, in some possible embodiments, the mirror ratio between the first mirror transistor MP1 and the second mirror transistor MP2 can also be equal to the mirror ratio between the fourth mirror transistor MP4 and the fifth mirror transistor MP5 (i.e. n1=n3), for example, refer to FIG. 11, which shows another schematic diagram of the reference voltage module 10 in the embodiments of the present application. The first current mirror unit 11 is controlled by the first switch S1 to output or not to output the first mirror current I1, and the second current mirror unit 12 is controlled by the second switch S2 to output or not to output the third mirror current I3. If the average voltage of the preset voltage signal VTRI is equal to the reference voltage VBG, then the average current size of the third mirror current I3 is also equal to that of the first mirror current I1 at this time, and thus the first current mirror unit 11 does not need to output the second mirror current I2, and the reference voltage module 10 can also output the reference voltage Vref with a fixed voltage and a periodically changing voltage and an average size equal to the first preset value.

[0097] In some embodiments of the present application, for example, for the embodiment in which the reference voltage module 10 can generate a reference current through a capacitor, referring to FIG. 12, FIG. 12 shows another schematic diagram of the clock signal CLK generation circuit in the embodiments of the present application, wherein the reference voltage module 10 comprises a charge-discharge unit 101 and a capacitor unit 102, the charge-discharge unit 101 can control the charging or discharging of the capacitor unit 102, thus before the frequency of the clock signal CLK is stabilized for the first time, the charge-discharge unit 101 controls the capacitor unit 102 to be connected to a fixed voltage, then the capacitor unit 102 can output a reference voltage Vref with a size equal to a first preset value; and after the frequency of the clock signal CLK is stabilized for the first time, the charge-discharge unit 101 alternately charges and discharges the capacitor unit 102, then the capacitor unit 102 can output a periodically changing reference voltage Vref.

[0098] As an exemplary embodiment of the reference voltage module 10, referring to FIG. 13, FIG. 13 shows another schematic diagram of the reference voltage module 10 in the embodiments of the present application, wherein the charge-discharge unit 101 comprises a first current source IS1, a second current source IS2, a third switch S3, a fourth switch S4 and a fifth switch S5; the input terminal of the first current source IS1 is connected to the power supply terminal VDD, the output terminal of the first current source IS1 is connected to the first terminal of the third switch S3, the second terminal of the third switch S3 is connected to the capacitor unit 102; the first terminal of the fourth switch S4 is connected to the capacitor unit 102, the second terminal of the fourth switch S4 is connected to the input terminal of the second current source IS2, the output terminal of the second current source IS2 is connected to the ground terminal; the first terminal of the fifth switch S5 is connected to a first preset voltage V1, the second terminal of the fifth switch S5 is connected to the capacitor unit 102.

[0099] It should be noted that before the frequency of the clock signal CLK is stabilized for the first time, the third switch S3 and the fourth switch S4 are in an open state, and the fifth switch S5 is in a closed state, thus the capacitor C0 is charged to the first preset voltage V1 to output a reference voltage Vref with a fixed size; and after the frequency of the clock signal CLK is stabilized for the first time, the fifth switch S5 is in an open state, and the third switch S3 and the fourth switch S4 are alternately switched between an open state and a closed state, for example, when the third switch S3 is closed, the fourth switch S4 is in an open state, the first current source IS1 charges the capacitor C0 to make the reference voltage Vref rise, when the reference voltage Vref rises to a certain size, the third switch S3 is opened, and the fourth switch S4 is closed, thus the second current source IS2 discharges the capacitor C0 to make the reference voltage Vref fall, when the reference voltage Vref falls to a certain size, the third switch S3 is closed again, and the fourth switch S4 is opened again, and the above process is repeated, finally a periodically changing reference voltage Vref is generated.

[0100] It can be appreciated that the above embodiment employs a single capacitor C0 as the capacitor unit 102, and in some possible embodiments, the capacitor unit 102 comprises a plurality of capacitors connected in series and / or in parallel.

[0101] In some embodiments of the present application, referring to FIG. 14, FIG. 14 shows another schematic diagram of the reference voltage module 10 in the embodiments of the present application, wherein the reference voltage module 10 further comprises a first comparator COMP1, a second comparator COMP2 and an RS flip-flop; a first input terminal of the first comparator COMP1 is connected with the capacitor unit 102, a second input terminal of the first comparator COMP1 is connected with a second preset voltage V2, and an output terminal of the first comparator COMP1 is connected with a first input terminal of the RS flip-flop; a second input terminal of the second comparator COMP2 is connected with the capacitor unit 102, a first input terminal of the second comparator COMP2 is connected with a third preset voltage V3, and an output terminal of the second comparator COMP2 is connected with a second input terminal of the RS flip-flop; an output terminal of the RS flip-flop is connected with a control terminal of a third switch S3 and a control terminal of a fourth switch S4, and an average value of the second preset voltage V2 and the third preset voltage V3 is equal to the first preset voltage V1.

[0102] It should be noted that since the first input terminal of the first comparator COMP1 is connected with the capacitor unit 102 and the second input terminal of the first comparator COMP1 is connected with the second preset voltage V2, when the reference voltage Vref output by the capacitor unit 102 is greater than the second preset voltage V2, the first comparator COMP1 outputs one of a high level signal and a low level signal, and vice versa; at the same time, since the second input terminal of the first comparator COMP1 is connected with the capacitor unit 102 and the first input terminal of the first comparator COMP1 is connected with the third preset voltage V3, when the reference voltage Vref output by the capacitor unit 102 is greater than the third preset voltage V3, the second comparator COMP2 outputs one of a high level signal and a low level signal, and vice versa.

[0103] Therefore, the RS flip-flop can control the third switch S3 and the fourth switch S4 according to the signals CLKc of the first comparator COMP1 and the second comparator COMP2, so as to alternately charge and discharge the capacitor unit 102 and generate the periodically changing reference voltage Vref. For example, when the reference voltage Vref is greater than the second preset voltage V2, the first comparator COMP1 outputs a high-level signal, and the second comparator COMP2 outputs a low-level signal, so that the RS flip-flop can control the third switch S3 to be open and the fourth switch S4 to be closed, so as to stop charging the capacitor unit 102 and discharge the capacitor unit 102 through the second current source IS2, so that the reference voltage Vref decreases until it is less than the third preset voltage V3; and when the reference voltage Vref is less than the third preset voltage V3, the first comparator COMP1 outputs a low-level signal, and the second comparator COMP2 outputs a high-level signal, so that the RS flip-flop can control the third switch S3 to be closed and the fourth switch S4 to be open, so as to stop discharging the capacitor unit 102 and charge the capacitor unit 102 through the first current source IS1, so that the reference voltage Vref rises until it is greater than the second preset voltage V2. Since the above process is repeatedly executed, the purpose of alternately charging and discharging the capacitor unit 102 and generating the periodically changing reference voltage Vref can be finally achieved.

[0104] In some embodiments of the present application, referring to FIG. 15, FIG. 15 shows a schematic diagram of the voltage feedback module 30 in the embodiments of the present application, wherein the voltage feedback module 30 comprises a third current source IS3, a first capacitor C1, a second capacitor C2, a sixth switch S6, a seventh switch S7, and a non-overlapping clock unit 31; the input end of the third current source IS3 is connected with the power supply end VDD, the output end of the third current source IS3 is connected with the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected with the ground end; the first end of the sixth switch S6 is connected with the first end of the first capacitor C1, the second end of the sixth switch S6 is connected with the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected with the ground end; the first end of the seventh switch S7 is connected with the first end of the second capacitor C2, and the second end of the seventh switch S7 is connected with the second end of the second capacitor C2; the non-overlapping clock unit 31 is configured to output a first clock signal CLK1 and a second clock signal CLK2 according to a clock signal CLK, the first clock signal CLK1 and the second clock signal CLK2 do not overlap each other, the control end of the sixth switch S6 is connected with the first clock signal CLK1, and the control end of the seventh switch S7 is connected with the second clock signal CLK2.

[0105] It should be noted that the non-overlapping first clock signal CLK1 and the second clock signal CLK2 can make the sixth switch S6 and the seventh switch S7 not closed or disconnected at the same time, for example, when the sixth switch S6 is closed and the seventh switch S7 is disconnected, the third current source IS3 charges the second capacitor C2; when the sixth switch S6 is disconnected and the seventh switch S7 is closed, the second capacitor C2 discharges to the ground terminal, according to the switch capacitor equivalent impedance calculation formula, it can be known that the equivalent impedance R of the second capacitor C2 at this time is: R = 1 / fC

[0106] Wherein, f is the frequency of the first clock signal CLK1 and the second clock signal CLK2, C is the capacitance value of the second capacitor C2.

[0107] Therefore, the feedback voltage VFB generated by the voltage feedback module 30 is: VFB = I0*R = I0 / fC

[0108] Wherein, I0 is the current size output by the third current source IS3.

[0109] Taking the error amplifier module 40 as an example, due to the virtual short and virtual open characteristics of the operational amplifier, VFB = VREF during the working process of the clock signal CLK generation circuit, and the frequency of the clock signal CLK can be calculated according to the following formula: f = I0 / (VREF*C)

[0110] According to the above formula, it can be seen that the voltage feedback module 30 of the present application can output the feedback voltage VFB according to the clock signal CLK, and make the size of the feedback voltage VFB and the frequency of the clock signal CLK negatively related, and finally the reference voltage Vref can be used to control the frequency of the clock signal CLK.

[0111] It should be noted that the above content about the clock signal CLK generation circuit is intended to clearly illustrate the implementation process of the present application, and those skilled in the art can make equivalent modifications or further designs under the guidance of the present application, for example, referring to FIG. 16, FIG. 16 shows another schematic diagram of the clock signal CLK generation circuit in the embodiment of the present application, wherein the clock signal CLK generation circuit can also include a frequency divider 50, and the clock signal CLK output by the frequency divider 50 makes the voltage feedback module 30 output the feedback voltage VFB.

[0112] The embodiment of the present application further provides a chip, which comprises the clock signal CLK generation circuit described above. The chip (IC) is also called a chip, which can be but is not limited to a SOC (System on Chip) chip, a SIP (system in package) chip. Since the chip of the present application is provided with the clock signal CLK generation circuit described in the above embodiment, it has all the beneficial effects of the clock signal CLK generation circuit in the above embodiment, which will not be repeated here.

[0113] The embodiment of the present application further provides an electronic device, which comprises a device main body and a chip as described above arranged in the device main body. The electronic device can be but is not limited to a body weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a touch pen, a true wireless earphone, a car central control screen, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes but is not limited to a smart watch, a smart bracelet, a cervical vertebra massage instrument. The mobile terminal includes but is not limited to a smart phone, a notebook computer, a tablet computer, a POS (point of sales terminal) machine. The smart home device includes but is not limited to a smart socket, a smart rice cooker, a smart sweeper, a smart lamp.

[0114] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as the above preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of the present application. Any modification, change and modification of the above embodiment according to the technical essence of the present application, which does not depart from the technical solution of the present application, is still within the scope of the technical solution of the present application.

Claims

1. A clock signal generating circuit, characterized by comprising: include: Reference voltage module, the reference voltage module being used to output a reference voltage; A voltage-controlled oscillator module, wherein the voltage-controlled oscillator module is used to oscillate under the control of a control voltage and output a clock signal; A voltage feedback module is provided, wherein the voltage feedback module is used to output a feedback voltage according to the clock signal, and the magnitude of the feedback voltage is negatively correlated with the frequency of the clock signal; An error amplification module is used to output the control voltage based on the reference voltage and the feedback voltage; The reference voltage changes periodically for at least a portion of the time during the operation of the clock signal generation circuit.

2. The clock signal generation circuit of claim 1, wherein, The reference voltage module includes a first current mirror unit, a second current mirror unit, and a resistor unit; The first current mirror unit is used to output a mirror current of fixed magnitude, and the second current mirror unit is used to output a mirror current of periodically varying magnitude. The resistor unit is used to generate the reference voltage based on the mirrored current output by the first current mirror unit and / or the second current mirror unit.

3. The clock signal generation circuit of claim 2, wherein, The first current mirror unit is used to output a second mirror current, and the second current mirror unit is used to output a third mirror current. The third mirror current changes periodically and its average magnitude is equal to that of the second mirror current. or The first current mirror unit is used to output a first mirror current and a second mirror current, and the second current mirror unit is used to output a third mirror current, wherein the third mirror current changes periodically and its average magnitude is equal to that of the second mirror current.

4. The clock signal generation circuit of claim 2, wherein, The first current mirror unit includes a first operational amplifier, a first transistor, a first resistor, a first mirror transistor, and a second mirror transistor; The first terminal of the first mirror transistor is connected to the power supply terminal, and the control terminal of the first mirror transistor is connected to the second terminal of the first mirror transistor. The first terminal of the second mirror transistor is connected to the power supply terminal, the control terminal of the second mirror transistor is connected to the control terminal of the first mirror transistor, and the second terminal of the second mirror transistor is connected to the resistor unit to input mirror current to the resistor unit. The first terminal of the first transistor is connected to the second terminal of the first mirror transistor, the second terminal of the first transistor is connected to the first terminal of the first resistor, and the second terminal of the first resistor is connected to the ground terminal. The first input terminal of the first operational amplifier is connected to a reference voltage, the second input terminal of the first operational amplifier is connected to the first terminal of the first resistor, and the output terminal of the first operational amplifier is connected to the control terminal of the first transistor.

5. The clock signal generation circuit of claim 4, wherein, The first current mirror unit also includes a third mirror transistor and a first switch; The first terminal of the third mirror transistor is connected to the power supply terminal, and the control terminal of the third mirror transistor is connected to the control terminal of the second mirror transistor. The first terminal of the first switch is connected to the second terminal of the third mirror transistor, and the second terminal of the first switch is connected to the resistor unit.

6. The clock signal generation circuit of claim 2, wherein, The second current mirror unit includes a second operational amplifier, a second transistor, a second resistor, a fourth mirror transistor, a fifth mirror transistor, and a second switch; The first end of the fourth mirror transistor is connected with a power supply end, and the control end of the fourth mirror transistor is connected with the second end of the fourth mirror transistor; The first end of the fifth mirror transistor is connected with the power supply end, and the control end of the fifth mirror transistor is connected with the control end of the fourth mirror transistor; The first end of the second transistor is connected with the second end of the fourth mirror transistor, the second end of the second transistor is connected with the first end of the second resistor, and the second end of the second resistor is connected with a ground end; The first input end of the second operational amplifier is connected with a preset voltage signal which periodically changes, the second input end of the second operational amplifier is connected with the first end of the second resistor, and the output end of the second operational amplifier is connected with the control end of the second transistor; The first end of the second switch is connected with the second end of the fifth mirror transistor, and the first end of the second switch is connected with the resistance unit.

7. The clock signal generation circuit of claim 1, wherein, The reference voltage module comprises a charge-discharge unit and a capacitor unit; Before the frequency of the clock signal is stabilized for the first time, the charge-discharge unit controls the capacitor unit to be connected with a fixed voltage, so that the capacitor unit outputs the reference voltage with a first preset value; After the frequency of the clock signal is stabilized for the first time, the charge-discharge unit alternately charges and discharges the capacitor unit, so that the capacitor unit outputs the reference voltage which periodically changes.

8. The clock signal generation circuit of claim 7, wherein, The charge-discharge unit comprises a first current source, a second current source, a third switch, a fourth switch and a fifth switch; The input end of the first current source is connected with a power supply end, the output end of the first current source is connected with the first end of the third switch, and the second end of the third switch is connected with the capacitor unit; The first end of the fourth switch is connected with the capacitor unit, the second end of the fourth switch is connected with the input end of the second current source, and the output end of the second current source is connected with a ground end; The first end of the fifth switch is connected with a first preset voltage, and the second end of the fifth switch is connected with the capacitor unit.

9. The clock signal generation circuit of claim 8, wherein, The reference voltage module further comprises a first comparator, a second comparator and an RS flip-flop; The first input end of the first comparator is connected with the capacitor unit, the second input end of the first comparator is connected with a second preset voltage, and the output end of the first comparator is connected with the first input end of the RS flip-flop; The second input end of the second comparator is connected with the capacitor unit, the first input end of the second comparator is connected with a third preset voltage, and the output end of the second comparator is connected with the second input end of the RS flip-flop; The output end of the RS flip-flop is connected with the control end of the third switch and the control end of the fourth switch, and the average value of the second preset voltage and the third preset voltage is equal to the first preset voltage.

10. The clock signal generation circuit of any one of claims 1 to 9, wherein, Before the frequency of the clock signal is stabilized for the first time, the reference voltage has a first preset value; After the frequency of the clock signal is stabilized for the first time, the reference voltage periodically changes and has an average value equal to the first preset value.

11. The clock signal generation circuit of claim 1, wherein, The voltage feedback module comprises a third current source, a first capacitor, a second capacitor, a sixth switch, a seventh switch and a non-overlapping clock unit; an input end of the third current source is connected with a power supply end, an output end of the third current source is connected with a first end of the first capacitor, a second end of the first capacitor is connected with a ground end; a first end of the sixth switch is connected with the first end of the first capacitor, a second end of the sixth switch is connected with a first end of the second capacitor, a second end of the second capacitor is connected with the ground end; a first end of the seventh switch is connected with the first end of the second capacitor, a second end of the seventh switch is connected with the second end of the second capacitor; the non-overlapping clock unit is used for outputting a first clock signal and a second clock signal according to the clock signal, the first clock signal and the second clock signal do not overlap each other, a control end of the sixth switch is connected with the first clock signal, and a control end of the seventh switch is connected with the second clock signal.

12. A chip, characterized by The clock signal generation circuit comprises the chip.

13. An electronic device, comprising: The chip comprises the clock signal generation circuit.

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