Method for manufacturing a silicon-carbide-based semiconductor structure and intermediate composite structure

Abstract

The invention relates to a method for manufacturing a semiconductor structure, which method comprises: a) providing an initial graphite substrate; b) depositing a polycrystalline silicon carbide carrier layer on an initial substrate; c) cutting the initial substrate along a plane parallel to its front face and / or to its rear face, resulting in two stacks, each composed of a temporary graphite wafer derived from the initial substrate, and a carrier layer; d) shaping at least one of the stacks, comprising mechanically thinning the temporary wafer, the stack having a front face on the carrier layer side and a rear face on the temporary wafer side; e) then forming an encapsulation layer on the stack, so as to cover the rear face, the edges and at least partially the front face thereof; f) removing the encapsulation layer from the front face of the stack in order to gain access to a free surface of the carrier layer of the stack; g) transferring a useful layer made of a single-crystal semiconductor material onto the free surface of the carrier layer, either directly or via an intermediate layer, to form a composite structure; h) producing a layer of components on the useful layer; i) removing the temporary wafer to form the semiconductor structure, said semiconductor structure including the layer of components, the useful layer and the carrier layer.

Description

Method for manufacturing a silicon carbide-based semiconductor structure and intermediate composite structure FIELD OF INVENTION

[0001] The present invention relates to the field of semiconductor materials for microelectronic components. It relates in particular to a method for manufacturing a semiconductor structure comprising a layer of a high-quality single-crystal semiconductor material (e.g., SiC or GaN) containing electronic components, said layer being deposited on a polycrystalline silicon carbide support layer. The invention also relates to an intermediate composite structure obtained during said method. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Interest in silicon carbide (SiC) has increased considerably in recent years because this semiconductor material can enhance power processing capabilities. SiC is increasingly being used to manufacture innovative power devices to meet the needs of emerging areas of electronics, such as electric vehicles.

[0003] Power devices and integrated power systems based on single-crystal silicon carbide can handle significantly higher power densities compared to their traditional silicon counterparts, and with smaller active area dimensions. To further reduce the size of SiC power devices, vertical rather than horizontal component layouts are advantageous. This requires allowing vertical electrical conduction between an electrode on the front face of the component assembly and an electrode on the rear face.

[0004] Bulk substrates of single-crystal SiC for the microelectronics industry remain expensive and difficult to source in large sizes. Furthermore, when fabricated on a bulk substrate, the electronic component assembly often requires the substrate to be thinned on its back side, typically by around 100 micrometers, to reduce vertical electrical resistivity and / or to meet size and miniaturization specifications.

[0005] It is therefore advantageous to use thin-film transfer solutions to fabricate composite structures typically comprising a single-crystal SiC thin film on a lower-cost substrate, with the thin film then used to form the electronic components. A well-known thin-film transfer solution is the Smart Cut process. TMThis process, based on light ion implantation and direct bonding, allows, for example, the fabrication of a composite structure comprising a thin layer of monocrystalline SiC (m-SiC), taken from an m-SiC donor substrate, in direct contact with a polycrystalline SiC support substrate, thus permitting vertical electrical conduction. The support substrate, which must be thick enough to support the component formation, is then thinned to obtain the complete set of electronic components ready for integration. Even if the support substrate is of lower quality, the thinning steps and material loss remain cost contributors that should be eliminated.

[0006] Document W2022 / 189732 proposes a method for manufacturing a semiconductor structure, involving a temporary graphite substrate onto which a polycrystalline silicon carbide support layer is deposited; a useful layer of monocrystalline silicon carbide is transferred onto the support layer, and then an active layer is formed on said useful layer; finally, the temporary substrate is removed, resulting in the semiconductor structure. This method avoids the need for thinning steps on the silicon carbide support and the associated significant material loss. SUBJECT OF THE INVENTION

[0007] The present invention relates to an alternative solution to that mentioned above and aims to further optimize the manufacturing process. It relates in particular to a method for manufacturing a semiconductor structure for microelectronic components, advantageously vertical, fabricated on and / or in a layer of a high-quality single-crystal semiconductor material (for example SiC or GaN), which is deposited on a polycrystalline silicon carbide support layer.

[0008] The invention also relates to a composite structure obtained at an intermediate stage of said manufacturing process. BRIEF DESCRIPTION OF THE INVENTION

[0009] The invention relates to a method for manufacturing a semiconductor structure, comprising the following steps:

[0010] a) the supply of an initial graphite substrate;

[0011] b) the deposition of a polycrystalline silicon carbide support layer on a front face and on a back face of the initial substrate;

[0012] c) cutting the initial substrate along a plane parallel to the front face and / or the back face, leading to the obtaining of two stacks, each composed of a temporary graphite slice from the initial substrate and a support layer;

[0013] d) the shaping of at least one of the stacks, including mechanical thinning of the temporary slice, the stack having a front face on the side of the support layer and a back face on the side of the temporary slice;

[0014] e) then, the formation of an encapsulation layer on the stack, so as to cover its back face, its edges and at least partially its front face;

[0015] f) the removal of the encapsulation layer from the front face of the stack, to provide access to a free surface of the support layer of the stack;

[0016] (g) the transfer of a useful layer of a single-crystal semiconductor material onto the free surface of the support layer, directly or via an intermediate layer, to form a composite structure, said transfer employing molecular adhesion bonding,

[0017] h) the development of a component layer on top of the useful layer,

[0018] (i) the removal of the temporary wafer to form the semiconductor structure, said semiconductor structure including the component layer, the useful layer and the support layer.

[0019] According to other advantageous and non-limiting features of the invention, taken alone or in any technically feasible combination: the single-crystal semiconductor material forming the useful layer is silicon carbide or gallium nitride; the thickness of the initial substrate is greater than or equal to 2.1 mm, advantageously between 5 mm and 50 mm; step b) and / or step d) comprises a mechanical, mechano-chemical, and / or chemical treatment of one or more free faces of the support layer; the support layer has a thickness between 50 micrometers and 250 micrometers, after step b) and / or in the composite structure resulting from step g); the temporary wafer has a thickness between 250 micrometers and 700 micrometers, after step d); the encapsulation layer is composed of a material selected from silicon, aluminum nitride, tantalum, the tungsten, and carbides other than silicon carbide;the encapsulation layer is composed of polycrystalline silicon carbide; the deposition of step b) is carried out at a temperature greater than or equal to 1100°C; the formation of the encapsulation layer of step e) is carried out at a temperature less than 1000°C, or even less than or equal to 800°C; the transfer step g) comprises: > the introduction of light species into a donor substrate of monocrystalline silicon carbide, to form a buried brittle plane defining, together with a front face of the donor substrate, the useful layer, > the assembly of the front face of the donor substrate onto the support layer, directly or via an intermediate layer, by molecular adhesion bonding, > the separation along the buried brittle plane to transfer the useful layer onto the support layer; the intermediate layer is formed of tungsten, silicon, silicon carbide or other conductive or semiconducting materials;step i) includes mechanical dismantling by propagation of a crack in the temporary slice following the application of a mechanical stress, the crack extending substantially parallel to the plane of the interface between the temporary slice and the support layer, and / or step i) includes mechanical removal or chemical etching of all or part of the temporary slice, and / or step i) includes dismantling by thermal damage of the graphite of the temporary slice.

[0020] The invention also relates to a composite structure comprising:

[0021] - a temporary graphite slice with a thickness between 250 micrometers and 700 micrometers,

[0022] - a polycrystalline silicon carbide support layer with a thickness between 50 micrometers and 250 micrometers, disposed on and in contact with one face of the temporary wafer,

[0023] - a useful layer made of a single-crystal semiconductor material, in particular silicon carbide or gallium nitride, deposited on the support layer,

[0024] - an encapsulation layer disposed on and in contact with the temporary wafer, at least everywhere where said temporary wafer is not in contact with the support layer, the encapsulation layer being composed of a material selected from silicon, aluminum nitride, tantalum, tungsten, and carbides other than silicon carbide.

[0025] Advantageously, the encapsulation layer has a thickness between 100 nm and 10 micrometers. BRIEF DESCRIPTION OF THE FIGURES

[0026] Other features and advantages of the invention will become apparent from the detailed description of the invention which follows with reference to the accompanying figures in which:

[0027] Presents a semiconductor structure developed according to a manufacturing process conforming to the invention;

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[0039] Figures 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2g', 2h, 2h', 2i and 2i' show steps of a manufacturing process according to the invention;

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[0044] Figures 3a and 3b show steps of a particular embodiment of the manufacturing process according to the invention.

[0045] The same references on the figures can be used for elements of the same type.

[0046] The figures are schematic representations which, for the sake of readability, are not to scale. In particular, the layer thicknesses along the z-axis are not to scale with respect to the lateral dimensions along the x and y axes; and the relative thicknesses of the layers are not necessarily to scale in the figures. DETAILED DESCRIPTION OF THE INVENTION

[0047] The present invention relates to a method for manufacturing a semiconductor structure 300. By semiconductor structure 300, we mean a structure comprising a component layer 50, a useful layer 40, and a support layer 20. The semiconductor structure 300 is advantageously in the form of a circular wafer and is intended to undergo the individualization steps prior to packaging one or more microelectronic devices fabricated in the component layer 50. The wafer diameter is typically 150 mm, 200 mm, or even 300 mm.

[0048] The manufacturing process is advantageously applicable to the manufacture of vertical microelectronic devices, which require vertical electrical conduction through the support layer 20, which forms the mechanical support of the devices.

[0049] The manufacturing process includes first a step a) supplying an initial graphite substrate 1 having a front face 1a, a rear face 1b and a peripheral edge 1c (). The initial substrate 1 can be produced, for example, by plasma deposition, ion sputtering, cathode arc deposition, laser evaporation of graphite, resin carbonization, etc.

[0050] The graphite in the initial substrate 1 is intended to form a seed for the deposition of a polycrystalline silicon carbide layer, hereafter referred to as support layer 20, which will be described with reference to step b) of the process. Reference may be made to document W2022 / 189732, cited in the introduction, to select graphite characteristics favorable to the deposition of support layer 20.

[0051] The initial substrate 1 has a thickness greater than 0.5 mm, preferably greater than or equal to 2 mm, greater than or equal to 2.1 mm, greater than or equal to 2.5 mm, more advantageously between 5 mm and 50 mm, typically between 5 mm and 10 mm, between 10 mm and 20 mm, or between 20 mm and 50 mm.

[0052] The initial substrate 1 is compatible with temperatures up to 1800°C when the atmosphere is controlled, i.e. without oxygen; because if exposed to air, graphite begins to burn in a low temperature range, typically 400°C – 600°C.

[0053] The manufacturing process then includes a step b) of deposition, directly onto the front faces 1a and rear faces 1b of the initial substrate 1, of the support layer 20 mentioned previously, made of polycrystalline silicon carbide (). Advantageously, the edges 1c of the initial substrate 1 are also covered with polycrystalline silicon carbide.

[0054] The deposition can be carried out using any known technique, notably chemical vapor deposition (CVD), at a temperature typically between 1100°C and 1800°C. Examples include thermal CVD techniques such as atmospheric pressure CVD (APCVD) or low pressure CVD (LPCVD), with precursors such as methylsilane, dimethyldichlorosilane, or dichlorosilane + i-butane. Plasma-enhanced CVD (PECVD) can also be used, with precursors such as silicon tetrachloride and methane; preferably, the frequency of the source used to generate the electrical discharge creating the plasma is around 3.3 MHz, and more commonly between 10 kHz and 100 GHz.

[0055] Prior to deposition, conventional cleaning sequences can be applied to the initial substrate 1 to remove all or part of particulate, metallic or organic contaminants potentially present on its free faces and edges 1a,1b,1c.

[0056] After the deposition of polycrystalline silicon carbide, one or more mechanical, mechano-chemical, and / or chemical treatments may be applied to one or more free faces 20a of the support layer 20 to uniformize the thickness of the support layer 20 on one or both sides of the initial substrate 1, or even at the edge 1c of said initial substrate. This treatment may also improve the roughness of the free faces 20a.

[0057] The significant thickness of the initial substrate 1 allows it to be less sensitive to the stress introduced by the deposition of p-SiC: the initial substrate 1 and support layer 20 together thus retain a low curvature, favorable to the continuation of the steps of the process.

[0058] At the end of step b), the polycrystalline silicon carbide support layer 20 typically has a thickness between 50 micrometers and 250 micrometers, between 50 micrometers and 200 micrometers, or preferably between 80 micrometers and 180 micrometers. This thickness is defined to meet the thickness specifications expected for the semiconductor structure 300.

[0059] In the final semiconductor structure 300, support layer 20 will act as a mechanical substrate and must potentially provide vertical electrical conduction. To guarantee this latter property of electrical conduction (low resistivity), support layer 2 is advantageously doped with n-type or p-type doping, depending on the requirement.

[0060] The polycrystalline silicon carbide layer, if present on the edges 1c of the initial substrate 1, may have a different thickness than the thickness on the front faces 1a and rear faces 1b.

[0061] The next step c) of the manufacturing process according to the invention corresponds to cutting the initial substrate 1 along a plane parallel to its front face 1a and / or its rear face 1b, in other words along the (x,y) plane on the.

[0062] This cutting can be carried out by any known technique, including mechanical sawing with diamond wire, laser cutting, etc.

[0063] The process then includes a step d) of shaping at least one of the stacks 120 (preferably of the two stacks 120 from step c)). The stack 120 has a front face 120a on the side of the support layer 20, a back face 120b on the side of the temporary slice 10 and a peripheral edge 120c.

[0064] Step d) involves mechanically thinning the temporary wafer 10 to a thickness typically between 250 micrometers and 700 micrometers. The objective is for the stack 120 to have a total thickness consistent with the thicknesses of substrates commonly processed in microelectronic lines.

[0065] Mechanical thinning can include mechanical grinding, using a diamond wheel, or other mechanical thinning techniques using a matrix with SiC grains. For example, when the initial substrate 1 is 10 mm thick, the temporary wafer 10 can be approximately 5 mm thick at the start of step d). A mechanical grinding technique with a coarse-grained wheel allows for rapid material removal to achieve the target thickness of the graphite temporary wafer 10. The ease of thinning this material is an advantage for this step of the process.

[0066] Step d) may also include other mechanical, mechano-chemical and / or chemical treatments of the rear face 120b of the stack 120, to participate in the thinning of the temporary slice 10, prior to or preferably after the aforementioned mechanical thinning.

[0067] Such treatments can also be implemented to standardize the thickness of the temporary slice 10 or that of the support layer 20, to improve the roughness of the faces 120a,120b, to adapt the shape of the edge 120c of the stack 120 ("edge shaping" according to Anglo-Saxon terminology), or to define a flat or a notch at the level of said edge 120c.

[0068] Advantageously, the 120 stack has a total thickness between 350 microns and 750 microns. We can cite the particular example of a 120 stack having a diameter (in the (x,y) plane) of 150mm and comprising a temporary slice 10 of 250 micrometers thick and a support layer 20 of 100 micrometers thick, or of a 120 stack having a diameter (in the (x,y) plane) of 200mm and comprising a temporary slice 10 of 625 micrometers thick and a support layer 20 of 100 micrometers thick.

[0069] The process then includes a step e) corresponding to the formation of an encapsulation layer 3 on the stack 120 so as to completely cover all the free graphite surfaces of the stack 120 (). The encapsulation layer 3 is advantageously formed on the back face 120b of the stack 120, on the edges 120c and at least partially on the front face 120a.

[0070] According to the invention, the encapsulation layer material 3 is preferably chosen from silicon, aluminum nitride, tantalum, tungsten, silicon carbide, and other carbides. The encapsulation layer material 3 is, of course, chosen to be compatible with subsequent processing, namely the fabrication of the component layer (which will be described later). For example, a silicon encapsulation layer 3 will be compatible with the fabrication of a gallium nitride (GaN)-based component layer, but not with the fabrication of a silicon carbide (SiC)-based component layer.

[0071] The encapsulation layer 3 can have a thickness of between 100 nm and 10 micrometers, advantageously between 500 nm and 2 micrometers.

[0072] The encapsulation layer 3 can be deposited at low or medium temperatures (for example, by CVD at temperatures below 1000°C, or even below or equal to 800°C, or below or equal to 600°C, or even around 500°C, depending on the deposition recipe and / or the type of material). In a deposition chamber, the front face 120a of the stack 120 is preferably placed on retaining pins or on a support, with the rear face 120b of the stack oriented upwards to promote an intact deposition on said face 120b and perfect coverage of the graphite.

[0073] In the case where it is made of polycrystalline silicon carbide, it can exhibit properties in terms of grain sizes and crystal orientations, doping, stresses, etc., that are more relaxed than those of the polycrystalline silicon carbide constituting the support layer 20, which is deposited at high temperatures to guarantee its quality.

[0074] Note that, for some materials of the encapsulation layer 3, the formation temperature may be higher, typically up to 1700°C.

[0075] One role of encapsulation layer 3 is to isolate the temporary graphite wafer 10 so that it does not introduce contamination into the microelectronic manufacturing lines. Additionally, this layer 3 protects the graphite and makes it compatible with very high-temperature heat treatments, regardless of the atmosphere.

[0076] The next step f) of the process includes removing the encapsulation layer 3 from the front face 120a of the stack 120, to give access to a free surface of the support layer 20.

[0077] Removal is preferably carried out by mechanical etching (grinding), mechanical polishing, or chemical etching. Alternatively, it can be performed by chemical etching in a single-plate machine, allowing etching on only one face of the stack 120.

[0078] The process then includes a step g) of transferring a useful layer 40 of a single-crystal semiconductor material, in particular single-crystal silicon carbide (m-SiC) or single-crystal gallium nitride (m-GaN), onto the free surface of the support layer 20, directly ( ) or via an intermediate layer 6 ('), to form a composite structure 200. The transfer implements a bonding by molecular adhesion, and consequently a bonding interface 5. The intermediate layer 6 can be formed on the side of the useful layer 40 and / or on the side of the support layer 20 (as illustrated in the '), to promote said bonding.

[0079] Advantageously, and as is known in reference to the Smart Cut process TM Step g) of the transfer process comprises successively:

[0080] - the introduction of light species into a donor substrate 4 made of single-crystal semiconductor material (in particular silicon carbide, gallium nitride), to form a buried brittle plane 41, defining with the front face 4a of the donor substrate 4, the useful layer 40 (),

[0081] - the assembly of the front face 4a of the donor substrate 4 onto the support layer 20, directly or via an intermediate layer 6, by molecular adhesion bonding, along a bonding interface 5 (,'),

[0082] - the separation along the fragile buried plane 41 to transfer the useful layer 40 onto the support layer 20 (,').

[0083] The light species are preferentially hydrogen, helium, or a co-implantation of these two species, and are implanted at a specific depth in the donor substrate 4, consistent with the thickness of the intended useful layer 40. These light species will form microcavities around the specified depth, distributed in a thin layer parallel to the free surface 4a of the donor substrate 4, i.e., parallel to the (x,y) plane in the figures. For the sake of simplicity, this thin layer is called the buried fragile layer 41.

[0084] The implantation energy of the light species is chosen to reach the determined depth. For example, hydrogen ions will be implanted at an energy between 10 keV and 250 keV, and at a dose between 5 E 16 / cm 2 and 1 E 17 / cm 2To define a useful layer 40 with a thickness of approximately 100 to 1500 nm, for a donor substrate 4 made of m-SiC. Note that an additional layer may be deposited on the front face 4a of the donor substrate 4 prior to the ion implantation step. This additional layer may be composed of a material such as silicon oxide or silicon nitride, for example. It may be retained for the next step (and form all or part of the aforementioned intermediate layer), or it may be removed.

[0085] The assembly occurs between the front face 4a of the donor substrate 4 and the free surface of the support layer 20 (on the side of the front face 120a of the stack 120), forming a bonded assembly along the bonding interface 5 (,'). As is well known, molecular adhesion bonding does not require an adhesive material; bonds are established at the atomic scale between the bonded surfaces. Several types of molecular adhesion bonding exist, differing in particular by the conditions of temperature, pressure, atmosphere, or pretreatments prior to contacting the surfaces. Examples include room-temperature bonding with or without prior plasma activation of the surfaces to be bonded, atomic diffusion bonding (ADB), surface-activated bonding (SAB), etc.

[0086] The assembly step may include, prior to bringing the surfaces to be joined into contact, conventional cleaning, surface activation, or other surface preparation sequences that can promote the quality of the bonding interface 5 (low defects, high adhesion energy). The free surface of the support layer 20 can also be prepared by mechanical or chemical polishing to achieve a roughness of less than 1 nm RMS (measured by atomic force microscopy on 5 x 5 μm scans). 2 or more). These preparation steps for the front face 120a of the polycrystalline silicon carbide stack 120 can be carried out simultaneously or sequentially with step f) of removing the encapsulation layer 3.

[0087] As previously mentioned, the front face 4a of the donor substrate 4 and / or the free surface of the support layer 20 may optionally include an intermediate layer 6, for example metallic (tungsten, etc.) or doped semiconductor (silicon, silicon carbide, etc.) to promote vertical electrical conduction, or alternatively insulating (silicon oxide, silicon nitride, etc.) for applications not requiring vertical electrical conduction. The intermediate layer 6 is likely to promote bonding by molecular adhesion, notably by smoothing out residual roughness or surface defects present on the faces to be joined. It may undergo planarization or smoothing treatments to achieve a roughness of less than 1 nm RMS, or even less than 0.5 nm RMS, which is favorable for bonding.

[0088] Separation along the buried fragile plane 41 is usually achieved by applying a heat treatment at a temperature between 800°C and 1200°C in the case of an m-SiC donor substrate (,'). Such a heat treatment induces the development of cavities and microcracks in the buried fragile plane 41, and their pressurization by the light species present in gaseous form, until a fracture propagates along said fragile plane 41. Alternatively or concurrently, mechanical stress can be applied to the bonded assembly, and in particular to the buried fragile plane 41, so as to propagate or mechanically assist the propagation of the fracture leading to separation.At the end of this separation, we obtain on the one hand the composite structure 200 comprising the temporary slice 10 in graphite, the support layer 20 in p-SiC, the encapsulation layer 3, the useful layer 40 transferred in single-crystal semiconductor material (in particular c-SiC or m-GaN) and optionally the intermediate layer 6, and on the other hand, the remainder 4' of the donor substrate.

[0089] The useful layer 40 typically has a thickness between 100nm and 1500nm. Its level and type of doping are defined by the choice of the properties of the donor substrate 4 or can be adjusted subsequently via known semiconductor layer doping techniques.

[0090] The free surface of the useful layer 40 (front face 200a of the composite structure 200) is usually rough after separation: for example, it has a roughness between 5nm and 100nm RMS (AFM, 20x20μm scan) 2Cleaning and / or smoothing steps can be applied to restore a good surface condition (typically, a roughness of less than a few angstroms RMS on a 20x20μm scan). 2 (by AFM).

[0091] Alternatively, the free surface of the useful layer 4 can remain rough, as separated, when the next step of the process tolerates this roughness.

[0092] Since temporary unit 10 is completely isolated from the external environment, very high temperature heat treatments, possibly in an oxidizing atmosphere, can be applied without risk of contamination of the equipment by graphite and without risk of degradation of said graphite.

[0093] The manufacturing process according to the invention then includes a step h) of developing a layer of components 50 on the useful layer 40 (,').

[0094] Usually, step h) includes the formation of an active layer developed by epitaxial growth of at least one additional layer (in doped single-crystal silicon carbide or alternatively in gallium nitride), on the useful layer 40. This epitaxial growth is carried out in the classic temperature range, namely between 1500°C and 1900°C for SiC, and forms a layer with a thickness of on the order of 1 micrometer to a few tens of micrometers, depending on the electronic components targeted.

[0095] Here again, the total encapsulation of the temporary wafer 10 ensures that the aforementioned very high temperature treatments do not induce cross-contamination and do not damage the graphite.

[0096] All or part of the electronic devices are then fabricated on and / or within the active layer. For example, microelectronic devices in component layer 50 may consist of transistors or other high-voltage and / or high-frequency components. Their fabrication on and / or within the active layer involves conventional steps such as cleaning, deposition, lithography, implantation, etching, planarization, and heat treatment. In particular, some of the heat treatments mentioned are designed to activate dopants introduced locally into the active layer (or the useful layer 40) and are typically carried out at a temperature of 1600°C or higher in the case of SiC.

[0097] Finally, the manufacturing process according to the invention includes a step i) of removing the temporary wafer 10 to form the semiconductor structure 300, said structure including the component layer 50, the useful layer 40, the support layer 20 () and optionally the intermediate layer 6 (').

[0098] Several variants can be implemented for this step: one variant (first variant described below) is based on the dismantling of the temporary tranche 10 and can therefore potentially include the recycling of the latter for a new use; other variants (second and third variants) involve the partial or total elimination of the temporary tranche 10.

[0099] According to the first variant, step i) includes mechanical dismantling by propagation of a crack in the temporary wafer 10 following the application of a mechanical stress, the crack extending substantially parallel to the plane of the interface between the temporary wafer 10 and the support layer 20. For example, the insertion of a beveled tool opposite or near said interface allows an opening to be initiated and propagated at this interface or in the graphite of the temporary wafer 10, until complete separation between the semiconducting structure 300 and said wafer 10.

[0100] Advantageously, the encapsulation layer 3 present on the edges 200c of the composite structure 200 is removed, and optionally, the polycrystalline silicon carbide layer, if present on the edges 200c, is removed in whole or in part, this to promote the initiation of the crack at the graphite – polycrystalline SiC interface in the (x,y) plane.

[0101] According to the second variant, step i) includes mechanical removal and / or chemical etching of all or part of the temporary wafer 10. Mechanical removal can, for example, be carried out by grinding the edges 200c and the back face 200b of the composite structure 200. Chemical etching can, in particular, employ a solution based on nitric acid and / or sulfuric acid, for example, a solution of concentrated sulfuric acid and potassium dichromate or a solution of sulfuric acid, nitric acid, and potassium chlorate. Chemical etching using an alkaline solution (such as potassium hydroxide (KOH) or sodium hydroxide (NaOH)) can also be applied.Of course, care will be taken to protect the free face and edges of the component layer 50, and / or to limit the contact time with the etching solution, to avoid damaging them during this chemical disassembly. In the case of purely chemical etching, it is necessary to preserve access to the graphite by removing at least the encapsulation layer 3 from the rear face 200b of the composite structure 200.

[0102] According to the third variant, step i) includes dismantling by thermal damage of the graphite composing the temporary wafer 10. In this case, it is required to remove the encapsulation layer 3 present on the back face 200b of the composite structure 200. Dismantling by thermal damage can be carried out at a temperature between 600°C and 1000°C, in the presence of oxygen: the graphite of the temporary wafer 10 is then burned and crumbles to leave only the semiconductor structure 300 intact.

[0103] Of course, this disassembly variant can only be applied if the component layer 50 is compatible with the applied temperature.

[0104] Note that the aforementioned variants may possibly be combined with each other, according to any technically feasible combination.

[0105] Regardless of the variant implemented, the removal of the temporary wafer 10 may leave residues on the back face 300b of the semiconductor structure 300 (the newly free face of the support layer 20). These residues are then removed by mechanical grinding or grinding, chemical polishing, chemical etching, and / or thermal damage. Chemical polishing or chemical etching techniques may also be used to reduce the roughness of the back face 300b, if necessary.

[0106] The semiconductor structure 300 obtained by the fabrication process according to the invention comprises a component layer 50, deposited on a useful layer 40 of m-SiC (alternatively, of m-GaN), itself deposited on a polycrystalline SiC support layer 20 having the thickness required for the application. No mechanical thinning of the SiC support, resulting in a significant loss of SiC material, is required. The support layer 20 is made of high-quality poly-SiC (because it is deposited at relatively high temperatures) but at low cost, compared to a bulk substrate of monocrystalline or polycrystalline SiC which would have had to be significantly thinned before the devices were formed.

[0107] The temporary graphite wafer 10 is advantageously recovered for recycling. If it is not reused, since graphite is a low-cost material, the manufacturing process according to the invention remains economically advantageous compared to a solution with a bulk SiC substrate.

[0108] In addition, two temporary wafers 10 are derived from the initial graphite substrate 1 on which the support layer 20 is deposited: a single deposit of polycrystalline SiC is made to obtain two stacks 120, which also optimizes manufacturing costs and time.

[0109] The composite structure 200 is robust and compatible with conventional microelectronic device fabrication lines, particularly due to the presence of the encapsulation layer 3, which acts as a barrier against any contamination that might originate from the temporary graphite wafer 10. This composite structure 200 enables the fabrication of a reliable and high-performance semiconductor structure 300. The performance of the component layer 50 devices also stems from the fact that the composite structure 200 allows for very high-temperature processing during the formation of the component layer 50.

[0110] The present invention also relates to the composite structure 200, described previously with reference to the manufacturing process, and corresponding to an intermediate structure obtained during said process (,').

[0111] The composite structure 200 comprises: - a temporary wafer 10 of graphite having a thickness of between 250 micrometers and 700 micrometers, - a support layer 20 of polycrystalline silicon carbide having a thickness of between 50 micrometers and 250 micrometers, disposed on and in contact with a face of the temporary wafer 10, - a useful layer 40 of a single-crystal semiconductor material, in particular silicon carbide or gallium nitride, disposed on the support layer 20, - an encapsulation layer 3 disposed on and in contact with the temporary wafer 10, at least everywhere said temporary wafer 10 is not in contact with the support layer 20.

[0112] In particular, the encapsulation layer 3 is in direct contact with the temporary wafer 10 on the rear face 200b of the composite structure 200. In some embodiments, it is possible for the encapsulation layer 3 to be in direct contact with the edges of the temporary wafer 10, at the edges 200c of the composite structure 200 (not shown). In the embodiments illustrated in the figures, the support layer 20 covers the edges of the temporary wafer 10, so the encapsulation layer 3 is in contact with the polycrystalline silicon carbide at the edges 200c of the composite structure 200.

[0113] Advantageously, the encapsulation layer 3 is composed of a material selected from silicon, aluminum nitride, tantalum, tungsten, silicon carbide and other carbides. It preferably has a thickness between 100 nm and 10 micrometers, or even between 500 nm and 2 micrometers.

[0114] In certain embodiments of the invention, the encapsulation layer 3 is composed of a material other than silicon carbide. The preparation of the front face 120a (p-SiC) of the stack 120, after local removal of the encapsulation layer 3 from the front face, and prior to the transfer of the useful layer 40, can therefore be carried out without risk of attack on the encapsulation layer 3 at the edges 120c or the rear face 120b of the stack 120, the temporary wafer 10 thus remaining completely protected.

[0115] In the case where the encapsulation layer 3 is made of polycrystalline silicon carbide, the removal of said layer 3 at the front face 120a of the stack 120 can be integrated into the surface treatments of the front face 120a in view of the assembly with the useful layer 40. As the surface to be assembled of the support layer 20 is made of polycrystalline silicon carbide, the surface treatments (mechanical, mechano-chemical and / or chemical) are applicable to the encapsulation layer 3, which has an advantage in terms of simplifying the process.

[0116] Of course, the invention is not limited to the embodiments and examples described, and alternative embodiments may be introduced without departing from the scope of the invention as defined by the claims.

Claims

A method for manufacturing a semiconductor structure (300), comprising the following steps: a) supplying an initial substrate (1) of graphite; b) depositing a support layer (20) of polycrystalline silicon carbide, on a front face (1a) and on a back face (1b) of the initial substrate (1); c) cutting the initial substrate (1) along a plane parallel to the front face (1a) and / or the back face (1b), leading to the obtaining of two stacks (120), each composed of a temporary graphite wafer (10) from the initial substrate (1) and a support layer (20); d) shaping at least one of the stacks (120), comprising a mechanical thinning of the temporary wafer (10), the stack (120) having a front face (120a) on the side of the support layer (20) and a back face (120b) on the side of the temporary wafer (10);e) then, the formation of an encapsulation layer (3) on the stack (120), so as to cover its rear face (120b), its edges (120c) and at least partially its front face (120a); f) the removal of the encapsulation layer (3) from the front face (120a) of the stack (120), to provide access to a free surface of the support layer (20) of the stack (120); g) the transfer of a useful layer (40) of a single-crystal semiconductor material onto the free surface of the support layer (20), directly or via an intermediate layer (6), to form a composite structure (200), said transfer employing molecular adhesion; h) the fabrication of a component layer (50) on the useful layer (40); i) the removal of the temporary wafer (10) to form the semiconductor structure (300), said semiconductor structure (300) including the component layer (50), the useful layer (40) and the support layer (20).; A manufacturing process according to the preceding claim, wherein the single-crystal semiconductor material forming the useful layer (40) is silicon carbide or gallium nitride. A manufacturing process according to any one of the preceding claims, wherein the thickness of the initial substrate (1) is greater than or equal to 2.1 mm, advantageously between 5 mm and 50 mm. Manufacturing process according to any one of the preceding claims, wherein step b) and / or step d) comprises a mechanical, mechano-chemical and / or chemical treatment of one (or more) free face(s) (20a) of the support layer (20). A manufacturing method according to any one of the preceding claims, wherein the support layer (20) has a thickness of between 50 micrometers and 250 micrometers, at the end of step b) and / or in the composite structure (200) resulting from step g). A manufacturing method according to any one of the preceding claims, wherein the temporary slice (10) has a thickness of between 250 micrometers and 700 micrometers, at the end of step d). A manufacturing process according to any one of the preceding claims, wherein the encapsulation layer (3) is composed of a material selected from silicon, aluminum nitride, tantalum, tungsten, and non-silicon carbide carbides. A manufacturing method according to any one of claims 1 to 6, wherein the encapsulation layer (3) is composed of polycrystalline silicon carbide. A manufacturing process according to any one of the preceding claims, wherein: - the deposition in step b) is carried out at a temperature greater than or equal to 1100°C, and - the formation of the encapsulation layer (3) in step e) is carried out at a temperature less than 1000°C, or even less than or equal to 800°C. A manufacturing process according to any one of the preceding claims, wherein the transfer step g) comprises: - the introduction of light species into a donor substrate (4) of single-crystal silicon carbide, to form a buried brittle plane (41) defining, together with a front face (4a) of the donor substrate (4), the useful layer (40), - the assembly of the front face (4a) of the donor substrate (4) onto the support layer (20), directly or via an intermediate layer (6), by molecular adhesion bonding, - the separation along the buried brittle plane (41) to transfer the useful layer (40) onto the support layer (20). A manufacturing method according to the preceding claim, wherein the intermediate layer (6) is formed of tungsten, silicon, silicon carbide or other conductive or semiconducting materials. A manufacturing method according to any one of the preceding claims, wherein: - step i) comprises mechanical dismantling by propagation of a crack in the temporary wafer (10) following the application of a mechanical stress, the crack extending substantially parallel to the plane of the interface between the temporary wafer (10) and the support layer (20), and / or - step i) comprises mechanical removal or chemical etching of all or part of the temporary wafer (10), and / or - step i) comprises dismantling by thermal damage of the graphite of the temporary wafer (10). Composite structure (200) comprising: - a temporary wafer (10) of graphite having a thickness of between 250 micrometers and 700 micrometers, - a support layer (20) of polycrystalline silicon carbide having a thickness of between 50 micrometers and 250 micrometers, disposed on and in contact with a face of the temporary wafer (10), - a useful layer (40) of a single-crystal semiconductor material, in particular of silicon carbide or gallium nitride, disposed on the support layer (20), - an encapsulation layer (3) disposed on and in contact with the temporary wafer (10), at least everywhere said temporary wafer (10) is not in contact with the support layer (20), the encapsulation layer (3) being composed of a material selected from silicon, aluminum nitride, tantalum, tungsten, and carbides other than silicon carbide. Composite structure (200) according to the preceding claim, wherein the encapsulation layer (3) has a thickness between 100 nm and 10 micrometers.

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