An electronic device

Abstract

An electronic device is proposed. It comprises an insulating substrate; a multi-terraced nanosheet arranged on the insulating substrate; and an electrode contacting each terrace of the multi-terraced nanosheet. The multi-terraced nanosheet is formed of a single semiconducting material and comprises at least three consecutives and non-overlapping terraces, such that a first electrode is connected to the first terrace, a second electrode is connected to the second terrace, and a third electrode is connected to the third terrace, the first terrace acting as collector and the third terrace acting as emitter, or vice versa, and the second terrace acting as base. The second terrace, which has a length of 10-200 nanometers, is disposed between the first terrace and the third terrace, and the first and third terraces each have a thickness that is either greater than or less than a thickness of the second terrace.

Description

[0001] AN ELECTRONIC DEVICE

[0002] TECHNICAL FIELD

[0003] The present invention generally relates to semiconductor nanoelectronic devices. More specifically, it relates to an electronic device than can operate as a junction or nano-transistor device.

[0004] BACKGROUND OF THE INVENTION

[0005] To face challenging requirements raised by current data processing and management, such as the Internet of Things, the continuous miniaturization of Si-based microelectronics has driven the exponential growth of integrated circuits. In consequence, the total number of transistors per chip has been significantly increased. Nevertheless, the miniaturization of Si metal-oxide-semiconductor field-effect-transistors (MOSFETs) has reached the 10 nm length-size technology barrier, following the Moore’s Law, where further size-reduction to achieve higher transistor density and performance (i.e., higher speed and lower power consumption) becomes increasingly challenging. The reason of this limitation can be found in the physical limits of bulk materials [1], Specifically, when the width of the depletion region on the drain terminal in a FET is comparable to the length of the conducting channel, the dynamics of charge carriers are not merely modulated by the gate electric field but also by the drain bias, which contributes to the charge injection by lowering the potential barrier and consequently reducing the threshold voltage as well as increasing the off-state current [2], Such situation, named short channel effect, causes drastic degradation in the carrier mobility and subthreshold characteristics of the Si-based transistors, together with larger leakage floor and higher static power dissipation that hinder their potential in realizing next-generation electronics.

[0006] Two dimensional (2D) semiconductors have been proposed as alternative candidates to push the performance abilities of the current transistor technology below the spatial limit established by channel effect existing in Si MOSFETs, due to their unique atomically thin structure and dangling-bond-free surface. The last decade has witnessed significant progress in the size scaling of 2D transistors by various approaches, in which the physical gate length of the transistors has shrank from micrometer to sub-one nanometer with superior performance. For instance, few layers of transition-metal dichalcogenide (TMD) semiconductors, as M0S2 and WSe2, have been used to obtain switching current ratios of up to 108and excellent subthreshold slope (60 mV / decade) [3, 4, 5, 6, 7], The standard approach of an ideal transistor made by 2D materials (see Fig. 1) would be composed of a TMD material as the channel, with a layered insulator as the gate dielectric, and layered metallic source / drain and gate contacts. By using the same stacking-like approach, atomically thin p-n diodes have been reported, using M0S2 and WSe2 monolayers as the electron and hole conducting layers, respectively [8], These stacked heterostructure diodes have exhibited excellent rectification behavior owing to the abruptness of the 2D-2D interface, with ideality factor of 1.2. M0S2 transistors with graphene (Gr) source / drain contacts have been used to fabricate flexible, transparent transistors [9], Also, flexible and transparent M0S2 transistors with graphene source / drain contacts were fabricated with h-BN as back gate dielectric, demonstrating negligible hysteresis in transport characteristics

[0010] , Heterostructures with 2D materials have been used for memory applications and tunnel transistors. Gr / MoS2 heterostructures have been used for nonvolatile memory cells

[0011] , Tunnel transistors fabricated with Gr / hexagonal- BN (h-BN) / Gr and Gr / MoS2 / Gr open the prospect of obtaining steep transistors with such an architecture

[0012] , Vertical Gr / h-BN / Gr devices have also exhibited negative differential resistance, allowing the prospect of van der Waals (vdW) heterostructures in analog electronics

[0013] , Gr / WS2 / Gr heterostructures have demonstrated strong light-matter interactions, leading to enhanced photon absorption and electron-hole creation

[0014] , This has opened the possibility of flexible photovoltaic devices with layered 2D materials. Heterobilayers of WSe2 and M0S2 have shown strong interlayer coupling with spatially direct absorption and spatially indirect emission, exhibiting yet another unique property of TMD heterostructures. TMDC heterojunctions with 111— V, Si, and carbon nanotubes have also been explored previously, demonstrating electrically active interfaces built from highly dissimilar semiconductors [15,16,17,18], Even transistors made completely from two dimensional materials to leverage the absence of interface states with digitally controlled and atomically uniform thickness has been reported

[0019] , with high on-off current ratios.

[0007] Two-dimensional devices based on TMDs have demonstrated outstanding properties for electronics and optoelectronics as has been evidenced above. However, in the fields of nanoelectronics, 2D semiconductors seem to offer new and promising perspectives as Bipolar Junction Transistors (BJT) [20,21], These devices, formed by facing each other two P-N junctions in close contact to give rise to PNP or NPN transistors, are indispensable circuit elements in modern electronics due to their capability of high-power signal amplification and used in various fields such as communication or high-speed computation. Two-dimensional materials are expected to provide for high-performance 2D-BJTs due to their nanometric thickness. However, the use of appropriate 2D materials is challenging to obtain devices with high p factor. Only recently

[0022] , a vertically stacked sequence of 2D semiconductors: CU9S5, PtS2, and WSe2, has demonstrated to act as a PNP attributed to the large bandgap difference between CugSs and PtS2 (that is, a built-in potential of 1.6 eV) and the high mobility of PtS2.

[0008] From the above, it is clear that the selection of 2D materials with appropriate built-in potential values and the development of devices with configurations radically different from the usual vertical stacking-one are key for development of new 2D-based BJTs which can enter into the market. As it has been widely reported, the bandgap of TMDs increases as their thickness is reduced due to quantum confinement effects [23, 24, 25], Among the most studied compounds of the TMD family (WSe2, MoSe2, M0S2, and WS2), the highest bandgap increase achieved by sample thinning has been found in WS2 (from 1.3 eV in the bulk to 1.7 eV in the bilayer and 2.0 eV in the monolayer [26, 27]). Such a bandgap window offers interesting possibilities for optoelectronics, but competitive built-in barrier values for modern electronic technologies can be only obtained between the bulk and the monolayer (as a reference, the built-in potential barrier of silicon is about 0.7 eV). Moreover, quantum-size confinement effects achieve the tuning of the bandgap of few-layer TMD nanosheets, but only atomically thin TMDs exhibit photoluminescence due to an indirect to-direct character transition occurring at the monolayer [23, 24, 25], This fact makes that all optoelectronic devices based on 2D TMDs require the use (or combination) of monolayer samples. Another important fact that hampers the incorporation of 2D TMDs into competitive electronic devices is the low carrier mobilities of TMDs (of about -100 cm2A / s)

[0028] , is a consequence of the intrinsically localized nature and orbital character of the d-states that dominate their valence and conduction bands [24, 29],

[0009] With a view to the potential applications of 2D semiconductors in nanoelectronics, other candidates, with stronger quantum-confinement effects and higher effective masses, may become competitive. However, few layered semiconductors have valence and conduction bands coming from more delocalized s- and p-orbitals. Indium selenide (InSe), a layered semiconductor of the I II— VI family with a direct band gap of -1.25 eV at room temperature

[0030] , is one of these exceptions, since its lowermost conduction band basically stems from antibonding In s states whereas its uppermost valence band has a nonbonding Se-pzorbital character

[0031] , On top of these electronic properties, InSe is exfoliable and chemically stable

[0032] , and presents the highest electron mobility among layered semiconductors (~103cm2 / Vs at room temperature)

[0033] , high values of diffusion length of carriers (around 100-200 nm for minority carriers)

[0034] , and has an anomalous electron effective-mass anisotropy (m*e,nc / m*e,±c= 0.081 / 0.138, where the c-axis is perpendicular to the layer plane)

[0035] , The confluence in a single material of such characteristics and applicability allows to envisage 2D InSe to become a very versatile material for electronics with tunable and optimized functionalities. In fact, it has been demonstrated that 2D InSe nanosheets exhibit carrier mobilities as high as these of their bulk counterpart

[0036] , strong quantum-confinement effects are able to tune the InSe band gap from 1.25 eV in bulk, to 1.6 in the four-layer and 2.1 eV in the monolayer [37, 38], In this way, quantum confinement effects, which produce remarkable effects in the bandgap of InSe nanosheets thinner than 10 nm, can tune the bandgap of InSe by 0.9 eV insofar the thickness of the InSe nanosheet runs from 10 nm to 1 nm (i.e., from the bulk to the single layer) [37,38],

[0010] With these perspectives, 2D InSe seems to be called to break established paradigms in nanoelectronics, not only as BJT but also as FET. In fact, it has been recently reported in Nature the realization of a Field Effect Transistor (FET) with 2D InSe with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS prn"1and a room temperature ballistic ratio in the saturation region of 83%

[0039] , surpassing those of any reported silicon FETs. An yttrium doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. The realized InSe FET has appeared to effectively suppress shortchannel effects with a low subthreshold swing of 75 mV per decade and drain-induced barrier lowering of 22 mV / V. Furthermore, low contact resistance of 62 Q pm is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit.

[0011] In spite of the known solution, new and improved electronic devices capable of operating as nano- or junction transistor devices are therefore needed.

[0012] References:

[0013] [1] K.J. Kuhn, et al., (invited) ECS Trans. 33, 3-17 (2010).

[0014] [2] G. Hiblot IEEE Trans. Electron Devices 65, 4015-4018 (2018).

[0015] [3] H. Fang, et al., Nano Lett. 13, 1991-1995(2013).

[0016] [4] H. Fang, et al., Nano Lett. 12, 3788-3792 (2012).

[0017] [5] B. Radisavljevic, et al., ACS Nano 5, 9934-9938 (2011).

[0018] [6] S. Chuang, et al., Nano Lett. 14, 1337-1342 (2014).

[0019] [7] S. Das, et al., Nano Lett. 13, 100-105 (2013). [8] B. W. H. Baugher, et al., Nat. Nanotechnol. 9, 262-267 (2014).

[0020] [9] J. Yoon, et al., Small 9, 3295-3300 (2013).

[0021]

[0010] G.-H. Lee, et al., ACS Nano 7, 7931- 7936 (2013).

[0022]

[0011] S. Bertolazzi, et al., ACS Nano 7, 3246-3252 (2013).

[0023]

[0012] L. Britnell, et al., Science 335, 947-950 (2012).

[0024]

[0013] L. Britnell, et al., Nat. Commun. 41794 (2013).

[0025]

[0014] T. Georgiou, et al., Nat. Nanotechnol 8, 100-103 (2013).

[0026]

[0015] S. Chuang, et al., Appl. Phys. Lett. 102, 242101 (2013).

[0027]

[0016] G. A. Rance, et al., ACS Nano 4, 4920-4928 (2010).

[0028]

[0017] L. A. Ponomarenko, et al., Nat. Phys. 7, 958-961 (2011).

[0029]

[0018] C. R. Dean, et al., Nat. Nanotechnol. 5, 722-726 (2010).

[0030]

[0019] T. Roy, et al., ACS Nano 8, 6, 6259-6264 (2014).

[0031]

[0020] C.-Y. Lin, et al., ACS Nano 11 , 11015 (2017).

[0032]

[0021] B.-W. Su, et al., Nanoscale Adv. 2, 1733 (2020).

[0033]

[0022] S. Yang, et al., Adv. Mater 33, 2106537 (2021).

[0034]

[0023] K. F. Mak, et al., Phys. Rev. Lett. 105, 136805 (2010).

[0035]

[0024] A. Splendiani, et al., Nano Lett. 10, 1271-1275 (2010).

[0036]

[0025] S. Tongay, et al., Nano Lett. 12, 5576-5580 (2012).

[0037]

[0026] J. Gusakova, et al., Phys. Status Sol. a 214, 1700218 (2017).

[0038]

[0027] A. Chaves, et al., npj 2D Mater Appl 4, 29 (2020).

[0039]

[0028] S. H. Mir, et al., ACS Omega 5, 14203-14211 (2020).

[0040]

[0029] E. Cappelluti, et al., Phys. 88, 075409 (2013).

[0041]

[0030] J. Camassel, et al., Phys. Rev. B 17, 4718-4725 (1978).

[0042]

[0031] P. Gomes da Costa, et al., Phys. Rev. B 48, 14135-14141 (1993).

[0043]

[0032] M. Brotons-Gisbert, et al., Appl. Surf. Sci. 2015, 354, 453-458 (2015).

[0044]

[0033] A. Segura, et al., Phys. Rev. B 29, 5708-5717 (1984).

[0045]

[0034] J. F. Sanchez-Royo, et al., J. Appl. Phys. 90, 2818-2823 (2001).

[0046]

[0035] E. Kress-Rogers, et al., solid State Commun. 44, 379-383 (1982).

[0047]

[0036] D. A. Bandurin, et al., Nature Nanotech. 12, 223-227 (2017).

[0048]

[0037] J. F. Sanchez-Royo, et al., Nano Res. 7, 1556-156 (2014).

[0049]

[0038] M. Brotons-Gisbert, et al., Nano Lett., 16, 3221-3229 (2016).

[0050]

[0039] J. Jiang, et al., Nature 616, 470-475 (2023).

[0051] DESCRIPTION OF THE INVENTION To that end, present invention proposes an electronic device that can be operated as a junction or nano-transistor device and that comprises: an insulating substrate, a multiterraced nanosheet disposed (or lying) on the insulating substrate, and an electrode contacting each terrace of the multi-terraced nanosheet.

[0052] Characteristically, in the present invention, the multi-terraced nanosheet is made of a single 2D semiconducting material and comprises three or more consecutive and non-overlapping terraces (named here as first, second and third terraces), such that a first electrical contact is made (e.g. using lithography or the like) in the first terrace, a second electrical contact is made in the second terrace, and a third electrical contact is made in the third terrace. That is, the electrical contacts (electrodes) are independent to each other and can be used to apply voltage to the second terrace and control the current between the first and third terraces.

[0053] Likewise, the first terrace is configured to act as collector and the third terrace is configured to act as emitter, or vice versa, while the second terrace is configured to act as base.

[0054] Moreover, the first terrace and the third terrace have similar thickness, which is either greater than (or thicker) or less than (or thinner) than the thickness of the second terrace. In this way, the bandgap of the thinnest terrace(s) widens due to quantum-size confinement effects. Equally, the second terrace has an average length of 10-200 nanometers (i.e. close to that of the diffusion length of charge carriers at room temperature).

[0055] In some embodiments, the thickness of the second terrace is less than 10 nanometers, and the thickness of the first and third terraces is greater than the second terrace, such that the electronic device is configured to operate as a NPN bipolar junction transistor. Alternatively, in other embodiments, the thickness of the first and third terraces is less than 10 nanometers, and the thickness of the second terrace is greater than both the first and third terraces, such that the electronic device is configured to operate as a PNP bipolar junction transistor.

[0056] In some embodiments, the semiconducting material is InSe. Alternatively, other HI-VI compounds can be employed instead of InSe (such as GaSe, ln2Se3, GaTe, and GaS). In some embodiments it comprises black phosphorus or other layered materials.

[0057] The insulating substrate can be made of any insulating material. In a particular embodiment it is made of silicon. In other embodiments it is made of silicon dioxide or any dielectric substrate. In some embodiments, the device also includes an encapsulating layer / element for eventual protection from environment or for the application of gate voltages. This gate voltage can be used to add novel functionalities to multiterraced InSe-based transistors, to develop ferroelectric bipolar junction transistors or insulated gate bipolar transistors.

[0058] Accordingly, present invention provides for a new electronic device in the semiconductor nanoelectronics field than can operate as a bipolar junction nano-transistor device. Such a new technology of electronic device can be considered, at the same time, as a homojunction -since only one material constitutes the device- and a heterojunction -since each side of the interface has a different bandgap (see Fig. 2). In addition, the invention has the advantages of avoiding not only lattice mismatch problems at the interface, but also the occurrence of interface defects. Also, such a technology generates base / collector and base / emitter built-in potentials by means of band gap tuning driven by quantum-size confinement effects, skipping standard methods such as doping techniques or the use of different semiconductors as base, emitter and collector.

[0059] The proposed device can operate as a photoconductor or photodiode, or form the basis of logic gates based on 2D materials, using a single semiconducting material.

[0060] BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The previous and other advantages and features will be more fully understood from the following detailed description of embodiments, with reference to the attached figures, which must be considered in an illustrative and non-limiting manner, in which:

[0062] Fig. 1 . Illustration of a standard transistor configuration made by the (vertical) stacking of 2D materials.

[0063] Fig. 2. Illustration of the technology of an embodiment of present invention. Top plot represents a multi-terraced nanosheet composed by two uniform terraces. Bottom plot illustrates band-gap alignment at the interface.

[0064] Fig. 3. (A)-(B) Scheme of a PNP and NPN transistor, respectively, which could be built up by means of multi-terraced nanosheets, according to different embodiments of the present invention. (C) Multi-terraced nanosheet nanolithography contacted. Terraces acting as emitter, base and collector have been identified. Fig. 4. (A) Optical image of a single-terrace InSe nanosheet. (B) l(V) characteristic of the nanosheet shown in (a), for different illumination conditions. These curves represent a sample that behaves as a resistance. (C) Optical image of a multi-terraced nanosheet. (D) l(V) characteristic of the nanosheet shown in (C), measured under different illumination conditions. These curves represent a diode p-n (like) behavior.

[0065] DETAILED DESCRIPTION OF THE INVENTION AND OF PREFERRED EMBODIMENTS

[0066] The present invention provides for an electronic device having an insulating substrate, which can be formed from any suitable insulating material, a multi-terraced nanometric-thick nanosheet, made of a single semiconducting material with consecutive terraces of different thicknesses. An electrode is electrically coupled to each terrace.

[0067] In one embodiment, the multi-terraced nanosheet is made of InSe (not limitative as in other embodiments it can be made of alternative materials such as dichalcogenide materials, black phosphorus or other HI-VI compounds). The nanosheet comprises three or more terraces of different thicknesses.

[0068] In the case of InSe, quantum confinement effects induce bandgap widening in nanosheets thinner than 10 nm. As the nanosheet thickness decreases, the bandgap increases. Consequently, a nanosheet comprising two terraces of different thicknesses — one thinner than 10 nm and the other thicker than 10 nm, as exemplified in Fig. 2 — exhibits heterojunction behavior. In this configuration, the thinner terrace corresponds to a p-type region due to its larger bandgap. Extending this principle, a multi-terraced nanosheet as disclosed herein can operate as a bipolar junction transistor (BJT), wherein the first terrace functions as the collector and the third terrace as the emitter, or vice versa, with the intermediate terrace serving as the base.

[0069] Fig. 3 illustrates two different embodiments of the proposed electronic device. In Fig. 3(A), the electronic device is configured to operate as a PNP bipolar junction transistor, whereas in Fig. 3(B), the electronic device is configured to operate as an NPN bipolar junction transistor. In both figures, “CB” stands for conduction band, while “VB” stands for valence band.

[0070] In Fig. 3(A), i.e. in the PNP configuration, the thickness of the first terrace (d1) and the thickness of the third terrace (d3) are both lower than 10 nanometers, although values of d1 and d3 are not required to be identical. In this configuration, the second terrace, of thickness d2, must be thicker than both the first and third terraces (d2>d1 and d2>d3), in order to promote the appearance of an emitter-base built-in potential and a base-collector built-in potential. As an example, to have the largest possible built-in potential in such an InSe-based device, the first and terraces should be one single-layer thick whereas the second terrace should be thicker than 10 nm.

[0071] In Fig. 3(B), i.e. in the NPN configuration, the first terrace (of thickness d1) and the third terrace (of thickness d3) must be thicker than the second terrace (of thickness d2). Again, the values of d1 and d3 are not required to be identical. In this configuration, the second terrace must be thinner than 10 nanometers in order to promote the appearance of an emitter-base built-in potential and a base-collector built-in potential. As an example, to have the largest possible built-in potential in such an InSe-based device, the first and third terraces should be thicker than 10 nm whereas the second terrace should be one single-layer thick.

[0072] In the two embodiments described above, the length of the second terrace (or base terminal), that is, the distance between the emitter and collector, should be lower or similar than the diffusion length of charge carriers, which is about 10-200 nanometers at room temperature.

[0073] Moreover, the first and third terraces should not have any common edge. The second terrace by being disposed in between the first and third terraces is the only physical bridge connecting the collector and the emitter.

[0074] Fig. 4 shows some results obtained from a specific embodiment of the proposed electronic device featuring a multi-terraced InSe nanosheet.

[0075] The scope of the present invention is defined in the following set of claims.

Claims

CLAIMS1. An electronic device, comprising: an insulating substrate; a multi-terraced nanosheet disposed on the insulating substrate; and an electrode contacting each terrace of the multi-terraced nanosheet; characterized in that: the multi-terraced nanosheet is formed of a single semiconducting material and comprises at least three consecutive and non-overlapping terraces including a first terrace, a second terrace, and a third terrace, such that a first electrode is connected to the first terrace, a second electrode is connected to the second terrace, and a third electrode is connected to the third terrace, wherein the first terrace is configured to act as collector and the third terrace is configured to act as emitter, or vice versa, and the second terrace is configured to act as base; the second terrace is disposed between the first terrace and the third terrace; the second terrace has a length of 10-200 nanometers; and the first and third terraces each have a thickness that is either greater than or less than a thickness of the second terrace.

2. The electronic device of claim 1 , wherein the thickness of the second terrace is less than 10 nanometers, and the thickness of the first and third terraces is greater than the second terrace, such that the electronic device is configured to operate as a NPN bipolar junction transistor.

3. The electronic device of claim 1 , wherein the thickness of the first and third terraces is less than 10 nanometers, and the thickness of the second terrace is greater than both the first and third terraces, such that the electronic device is configured to operate as a PNP bipolar junction transistor.

4. The electronic device of any one of the previous claims, wherein the semiconducting material is Indium Selenide, InSe.

5. The electronic device of any one of the previous claims 1-3, wherein the semiconducting material comprises HI-VI compounds including GaSe, ln2Se3, GaTe, and GaS; black phosphorus; or other layered materials.

6. The electronic device of any one of the previous claims, wherein the insulating substrate is made of an insulating material.

7. The electronic device of claim 6, wherein the insulating material comprises silicon, silicon dioxide or a dielectric material.

8. The electronic device of any one of the previous claims, further comprising an encapsulating layer to protect the insulating substrate, multi-terraced nanosheet, and electrodes.

Images