Semiconductor device

Abstract

Provided is a semiconductor device which is capable of suppressing the occurrence of current collapse. A semiconductor device according to an embodiment of the present invention comprises first to third semiconductor regions, first and second electrodes, a gate electrode, and a first field plate electrode. The first semiconductor region contains Alx1Ga1-x1N (0 ≤ x1 < 1). The second semiconductor region contains Alx2Ga1-x2N (0 < x2 < 1, x1 < x2). The first field plate electrode is provided on the gate electrode and is electrically connected to the gate electrode. A first end part of the first field plate electrode in a second direction is located on the second electrode side with respect to the gate electrode. The third semiconductor region is provided between the second semiconductor region and the first end part in a first direction. The third semiconductor region is separated from the gate electrode and the second electrode in the second direction. The third semiconductor region contains Alx3Ga1-x3N (0 ≤ x3 < 1, x3 < x2).

Description

Semiconductor equipment

[0001] Embodiments of the present invention relate to semiconductor devices.

[0002] There are semiconductor devices that contain gallium nitride. A technology is needed to suppress the occurrence of current collapse in these semiconductor devices.

[0003] Japanese Patent Publication No. 2021-118198

[0004] The problem that the embodiments of the present invention aim to solve is to provide a semiconductor device that can suppress the occurrence of current collapse.

[0005] The semiconductor device according to this embodiment comprises a first semiconductor region, a second semiconductor region, a first electrode, a second electrode, a gate electrode, a first field plate electrode, and a third semiconductor region. The first semiconductor region is made of Al ｘ１ Ga １－ｘ１ It contains N (0 ≤ x1 < 1). The second semiconductor region is provided on the first semiconductor region, and Al ｘ２ Ga １－ｘ２ It contains N (0 < x2 < 1, x1 < x2). The first electrode is provided on a portion of the second semiconductor region. The second electrode is provided on another portion of the second semiconductor region. The second electrode is separated from the first electrode in a second direction perpendicular to a first direction toward the second semiconductor region. The gate electrode is provided between the first electrode and the second electrode. The gate electrode faces the second semiconductor region via a gate insulator. The first field plate electrode is provided on the gate electrode and is electrically connected to the gate electrode. The first end of the first field plate electrode in the second direction is located toward the second electrode relative to the gate electrode. The third semiconductor region is provided between the second semiconductor region and the first end in the first direction. The third semiconductor region is separated from the gate electrode and the second electrode in the second direction. The third semiconductor region is Al ｘ３ Ga １－ｘ３ It contains N (0 ≤ x³ < 1, x³ < x²).

[0006] Figure 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. Figure 2 is a plan view showing a semiconductor device according to the first embodiment. Figures 3(a) and 3(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. Figures 4(a) and 4(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. Figure 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. Figure 6 is a cross-sectional view showing a semiconductor device according to a first modification of the first embodiment. Figure 7 is a plan view showing a semiconductor device according to a first modification of the first embodiment. Figure 8 is a cross-sectional view showing a semiconductor device according to a second modification of the first embodiment. Figure 9 is a cross-sectional view showing a semiconductor device according to a third modification of the first embodiment. Figure 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. Figure 11 is a cross-sectional view showing a semiconductor device according to a third embodiment.

[0007] The embodiments of the present invention will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes of the parts, etc., are not necessarily the same as those of reality. Furthermore, even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In this specification and each drawing, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) Figure 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. As shown in Figure 1, the semiconductor device 100 according to the first embodiment includes a semiconductor substrate 10, a first semiconductor region 11, a second semiconductor region 12, a third semiconductor region 13, a source electrode 21 (first electrode), a drain electrode 22 (second electrode), a gate electrode 23, a first field plate electrode (first FP electrode) 31, and an insulating layer 40.

[0009] In the description of the embodiments, an XYZ orthogonal coordinate system is used. The direction from the first semiconductor region 11 to the second semiconductor region 12 is defined as the Z direction (the first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (the second direction) and the Y direction. Also, for the sake of explanation, the direction from the first semiconductor region 11 to the second semiconductor region 12 is referred to as "up", and the opposite direction is referred to as "down". These directions are independent of the direction of gravity based on the relative positional relationship between the first semiconductor region 11 and the second semiconductor region 12.

[0010] The first semiconductor region 11 is provided on the semiconductor substrate 10 and contains Al ｘ１ Ga １－ｘ１ N (0 ≤ x1 < 1). The semiconductor substrate 10 is, for example, a Si substrate. A buffer layer (not shown) may be provided between the semiconductor substrate 10 and the first semiconductor region 11. The second semiconductor region 12 is provided on the first semiconductor region 11 and contains Al ｘ２ Ga １－ｘ２ N (0 < x2 < 1, x1 < x2). As an example, the first semiconductor region 11 is a GaN layer substantially free of Al, and the second semiconductor region 12 is an AlGaN layer. Here, "substantially free of Al" means that the concentration of Al is less than 0.1 at%.

[0011] The source electrode 21 is provided on a part of the second semiconductor region 12 and is electrically connected to the second semiconductor region 12. The drain electrode 22 is provided on another part of the second semiconductor region 12 and is electrically connected to the second semiconductor region 12. The source electrode 21 and the drain electrode 22 are separated from each other in the X direction.

[0012] The gate electrode 23 is provided between the source electrode 21 and the drain electrode 22 in the X direction. The gate electrode 23 is separated from the source electrode 21 and the drain electrode 22. For example, the distance in the X direction between the source electrode 21 and the gate electrode 23 is shorter than the distance in the X direction between the drain electrode 22 and the gate electrode 23.

[0013] The insulating layer 40 is provided between the source electrode 21 and the gate electrode 23, between the drain electrode 22 and the gate electrode 23, and between the second semiconductor region 12 and the gate electrode 23. The gate electrode 23 faces the second semiconductor region 12 in the Z direction via the gate insulating portion 45 of the insulating layer 40.

[0014] The first FP electrode 31 is provided on the gate electrode 23 and is electrically connected to the gate electrode 23 by a contact C1. The first end e1 of the first FP electrode 31 in the X direction is located on the drain electrode 22 side relative to the gate electrode 23. In other words, the position p1 of the first end e1 in the X direction is between the position p2 of the gate electrode 23 in the X direction and the position p3 of the drain electrode 22 in the X direction. By providing the first FP electrode 31, the electric field strength near the gate electrode 23 can be reduced.

[0015] The third semiconductor region 13 is provided between the second semiconductor region 12 and the first end e1 in the Z direction. An insulating layer 40 is located between the third semiconductor region 13 and the first end e1. The third semiconductor region 13 is made of Al ｘ３ Ga １－ｘ３ It contains N (0 ≤ x³ < 1, x³ < x²). For example, the third semiconductor region 13 is a GaN layer that is substantially free of Al. The composition of the third semiconductor region 13 may be the same as the composition of the first semiconductor region 11.

[0016] The third semiconductor region 13 is located away from the drain electrode 22 and the gate electrode 23 in the X direction. For example, the length of the third semiconductor region 13 in the X direction is longer than the distance between the third semiconductor region 13 and the gate electrode 23 in the X direction, and shorter than the distance between the third semiconductor region 13 and the drain electrode 22 in the X direction.

[0017] The insulating layer 40 includes a first insulating portion 41 and a second insulating portion 42. The first insulating portion 41 is located in the X direction between the third semiconductor region 13 and the gate electrode 23. The second insulating portion 42 is located in the X direction between the third semiconductor region 13 and the drain electrode 22.

[0018] The source electrode 21, drain electrode 22, gate electrode 23, and first FP electrode 31 include a metallic material such as titanium, copper, or aluminum. The insulating layer 40 includes an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating layer 40 may be composed of a plurality of insulating films. For example, the insulating layer 40 may include a first insulating film 40a and a second insulating film 40b. The first insulating film 40a is formed along the surface of the second semiconductor region 12 and the surface of the third semiconductor region 13. The second insulating film 40b is formed on top of the first insulating film 40a. The first insulating film 40a includes silicon nitride, and the second insulating film 40b includes silicon oxide. The thickness of the second insulating film 40b is greater than the thickness of the first insulating film 40a.

[0019] Figure 2 is a plan view showing a semiconductor device according to the first embodiment. Figure 1 corresponds to the I-I cross-sectional view in Figure 2. In Figure 2, the source electrode 21, the drain electrode 22, and the first FP electrode 31 are shown with dashed lines and are depicted as transparent. The insulating layer 40 is omitted. As shown in Figure 2, the semiconductor device 100 includes a device effective region R. The third semiconductor region 13, the source electrode 21, the drain electrode 22, the gate electrode 23, and the first FP electrode 31 are provided in the device effective region R. In the device effective region R, 2DEG occurs between the first semiconductor region 11 and the second semiconductor region 12. For example, in regions other than the device effective region R, the crystal structure of the second semiconductor region 12 is destroyed by ion implantation so that 2DEG does not occur. Alternatively, the second semiconductor region 12 may be provided only in the device effective region R.

[0020] A portion of the source electrode 21 is provided on a region other than the device effective region R and extends in the X direction around the first FP electrode 31. This portion of the source electrode 21 is electrically connected to the third semiconductor region 13 by a contact C2 on the region other than the device effective region R.

[0021] The operation of the semiconductor device 100 will now be described. The semiconductor device 100 is a normally-on type power device. A two-dimensional electron gas (2DEG) is generated at the interface between the first semiconductor region 11 and the second semiconductor region 12. When a positive voltage is applied to the drain electrode 22 relative to the source electrode 21, electrons contained in the 2DEG move from the source electrode 21 to the drain electrode 22. As a result, a current flows between the source electrode 21 and the drain electrode 22. When a negative voltage is applied to the gate electrode 23, electrons in the region directly below the gate electrode 23 are repelled, and that region becomes depleted. As a result, the semiconductor device 100 turns off.

[0022] Figures 3(a), 3(b), 4(a), 4(b), and 5 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. First, a semiconductor substrate 10 is prepared. As shown in Figure 3(a), a first semiconductor region 11, a second semiconductor region 12, and a semiconductor region 13a are sequentially formed on the semiconductor substrate 10 by metal-organic vapor deposition (MOCVD). For example, the first semiconductor region 11 is a GaN layer, the second semiconductor region 12 is an AlGaN layer, and the semiconductor region 13a is a GaN layer.

[0023] A portion of the semiconductor region 13a is etched by photolithography and reactive ion etching (RIE). As a result, a third semiconductor region 13 is formed on top of a portion of the second semiconductor region 12, as shown in Figure 3(b).

[0024] A first insulating film 40a is formed along the surface of the second semiconductor region 12 and the surface of the third semiconductor region 13 by chemical vapor deposition (CVD). For example, the first insulating film 40a is a silicon nitride film. A metal layer is formed on top of the first insulating film 40a. This metal layer is patterned by photolithography and RIE. As a result, the gate electrode 23 is formed as shown in Figure 4(a).

[0025] On the first insulating film 40a and the gate electrode 23, a second insulating film 40b is formed by CVD. For example, the second insulating film 40b is a silicon oxide film. By photolithography and RIE, a part of the first insulating film 40a and a part of the second insulating film 40b are removed. As a result, as shown in FIG. 4(b), a part of the upper surface of the second semiconductor region 12 and a part of the upper surface of the gate electrode 23 are exposed.

[0026] A metal layer is formed on the second insulating film 40b. By patterning this metal layer, as shown in FIG. 5, a source electrode 21, a drain electrode 22, and a first FP electrode 31 are formed. Through the above steps, the semiconductor device 100 according to the first embodiment is manufactured.

[0027] In the above manufacturing method, instead of forming the third semiconductor region 13 by etching, the third semiconductor region 13 may be formed by selectively epitaxially growing a semiconductor material on the second semiconductor region 12.

[0028] The advantages of the first embodiment will be described. Current collapse in a semiconductor device is caused by electron trapping. Electron trapping occurs at crystal defects in the semiconductor region, the interface of the semiconductor region, etc. In the semiconductor device 100, a third semiconductor region 13 is provided to suppress the occurrence of current collapse. The concentration of aluminum in the third semiconductor region 13 is smaller than the concentration of aluminum in the second semiconductor region 12. For example, the third semiconductor region 13 is a GaN layer that does not substantially contain Al. When the third semiconductor region 13 is provided, a two-dimensional hole gas (2DHG) is generated at the interface between the second semiconductor region 12 and the third semiconductor region 13. The generation of 2DHG supplies holes to the trapped electrons and neutralizes them. Thereby, the occurrence of current collapse is suppressed.

[0029] In particular, electron trapping is likely to occur in a region where the electric field strength is high. In the semiconductor device 100, the electric field strength in the region directly under the first end e1 is higher than the electric field strength in other regions. The third semiconductor region 13 is located directly under the first end e1. Thereby, holes can be efficiently supplied to the region where electron trapping is likely to occur.

[0030] On the other hand, directly below the region where 2DHG occurs, the electron concentration in 2DEG decreases. When the electron concentration in 2DEG decreases, the on-resistance of the semiconductor device 100 increases. In the semiconductor device 100, in order to suppress the decrease in electron concentration in 2DEG, a third semiconductor region 13 is partially provided on the second semiconductor region 12 and is separated from the drain electrode 22 and the gate electrode 23. In other words, the third semiconductor region 13 is selectively provided only in regions where electron trapping is likely to occur, and is not provided in other regions. This makes it possible to suppress the decrease in electron concentration in 2DEG while suppressing current collapse.

[0031] The third semiconductor region 13 is preferably electrically connected to the source electrode 21. By electrically connecting the third semiconductor region 13 to the source electrode 21, holes are supplied from the source electrode 21 to the third semiconductor region 13. This allows for a higher hole concentration in 2DHG and further suppresses the occurrence of current collapse.

[0032] To generate 2DHG and increase the hole concentration in 2DHG, it is effective to increase the thickness of the third semiconductor region 13 in the Z direction. For example, by designing the thickness of the third semiconductor region 13 to be 15 nm or more, 2DHG is more likely to be generated at the interface between the second semiconductor region 12 and the third semiconductor region 13.

[0033] The hole concentration in 2DHG also depends on the composition ratio of Al in the second semiconductor region 12. Specifically, the smaller the proportion of Al in the second semiconductor region 12, the lower the hole concentration in 2DHG. In order to generate 2DHG regardless of the proportion of Al in the second semiconductor region 12 and to increase the hole concentration in 2DHG, the thickness of the third semiconductor region 13 is preferably 20 nm or more, and more preferably 25 nm or more.

[0034] The thickness of the third semiconductor region 13 is most preferably 30 nm or more. For example, in order to generate the minimum 2DEG required for the practical operation of the device, the proportion of Al in the second semiconductor region 12 is designed to be as small as 15%. If the thickness of the third semiconductor region 13 is 30 nm or more, even if the proportion of Al in the second semiconductor region 12 is as small as 15%, it is possible to generate 2DHG with a hole concentration sufficient to suppress current collapse.

[0035] Furthermore, the hole concentration in 2DHG also depends on the composition ratio of Al in the third semiconductor region 13. The smaller the proportion of Al in the third semiconductor region 13, the higher the hole concentration in 2DHG. For this reason, it is preferable that the third semiconductor region 13 is substantially free of Al.

[0036] (First Modification) Figure 6 is a cross-sectional view showing a semiconductor device according to the first modification of the first embodiment. Compared to the semiconductor device 100, the semiconductor device 110 in Figure 6 further comprises a fourth semiconductor region 14 and a second field plate electrode (second FP electrode) 32.

[0037] The fourth semiconductor region 14 is provided on the second semiconductor region 12 and is located between the third semiconductor region 13 and the drain electrode 22 in the X direction. The fourth semiconductor region 14 is Al ｘ４ Ga １－ｘ４ It contains N (0 ≤ x4 < 1, x4 < x2). The composition of the fourth semiconductor region 14 may be the same as the composition of the third semiconductor region 13. As an example, the fourth semiconductor region 14 is a GaN layer that is substantially free of Al.

[0038] The fourth semiconductor region 14 is separated from the third semiconductor region 13 and the drain electrode 22. For example, the length of the fourth semiconductor region 14 in the X direction is shorter than the distance between the third semiconductor region 13 and the fourth semiconductor region 14 in the X direction.

[0039] The insulating layer 40 includes a first insulating portion 41, a second insulating portion 42, and a third insulating portion 43. The first insulating portion 41 is located in the X direction between the gate electrode 23 and the third semiconductor region 13. The second insulating portion 42 is located in the X direction between the third semiconductor region 13 and the fourth semiconductor region 14. The third insulating portion 43 is located in the X direction between the fourth semiconductor region 14 and the drain electrode 22.

[0040] The second FP electrode 32 is provided on the insulating layer 40. The second FP electrode 32 is separated from the first FP electrode 31 and the drain electrode 22 in the X direction. The second end e2 of the second FP electrode 32 in the X direction is located directly above the fourth semiconductor region 14.

[0041] Figure 7 is a plan view showing a semiconductor device according to a first modification of the first embodiment. Figure 6 corresponds to the VI-VI cross-sectional view in Figure 7. As shown in Figure 7, the second FP electrode 32 is electrically connected to the source electrode 21. The third semiconductor region 13 and the fourth semiconductor region 14 are electrically connected to the source electrode 21 by contact C2.

[0042] As shown in the diagram, the source electrode 21 and the second FP electrode 32 may be formed integrally. The third semiconductor region 13 and the fourth semiconductor region 14 may be formed integrally or separately from each other.

[0043] By providing the second FP electrode 32, the electric field strength near the first FP electrode 31 can be reduced, and the breakdown voltage of the semiconductor device 110 can be improved. On the other hand, when the second FP electrode 32 is provided, electron trapping is more likely to occur in the region directly below the second FP electrode 32. By providing a fourth semiconductor region 14 in the region directly below the second FP electrode 32 and generating 2DHG, the trapped electrons can be neutralized. According to the first modified example, the breakdown voltage of the semiconductor device 110 can be improved while suppressing current collapse.

[0044] For example, the thickness of the fourth semiconductor region 14 in the Z direction is 15 nm or more. In order to increase the hole concentration in 2DHG, the thickness of the fourth semiconductor region 14 is preferably 20 nm or more, more preferably 25 nm or more, and most preferably 30 nm or more.

[0045] (Second Modification) Figure 8 is a cross-sectional view showing a semiconductor device according to a second modification of the first embodiment. The semiconductor device 120 shown in Figure 8 further comprises a fifth semiconductor region 15 compared to the semiconductor device 110. The fifth semiconductor region 15 is provided on the second semiconductor region 12 and is in contact with the drain electrode 22. The fifth semiconductor region 15 is Al ｘ５ Ga １－ｘ５ It contains N (0 ≤ x5 < 1, x5 < x2). The composition of the fifth semiconductor region 15 may be the same as the composition of the third semiconductor region 13 or the fourth semiconductor region 14. As an example, the fifth semiconductor region 15 is a GaN layer that is substantially free of Al.

[0046] The fifth semiconductor region 15 is separated from the fourth semiconductor region 14 in the X direction. The third insulating portion 43 of the insulating layer 40 is located between the fourth semiconductor region 14 and the fifth semiconductor region 15.

[0047] The drain electrode 22 includes a third end e3 that protrudes in the direction opposite to the X direction. The third end e3 is located directly above the fifth semiconductor region 15. A portion of the insulating layer 40 is located between the third end e3 and the fifth semiconductor region 15.

[0048] By providing a third end e3 on the drain electrode 22, the electric field strength near the drain electrode 22 can be reduced, and the breakdown voltage of the semiconductor device 120 can be improved. On the other hand, when a third end e3 is provided, electron trapping is more likely to occur in the region directly below the third end e3. By providing a fifth semiconductor region 15 in the region directly below the third end e3 and generating 2DHG, the trapped electrons can be neutralized. According to the second modified example, the breakdown voltage of the semiconductor device 120 can be improved while suppressing current collapse.

[0049] For example, the thickness of the fifth semiconductor region 15 in the Z direction is 15 nm or more. In order to increase the hole concentration in 2DHG, the thickness of the fifth semiconductor region 15 is preferably 20 nm or more, more preferably 25 nm or more, and most preferably 30 nm or more.

[0050] (Third Modification) Figure 9 is a cross-sectional view showing a semiconductor device according to a third modification of the first embodiment. The semiconductor device 130 shown in Figure 9 differs from the semiconductor device 120 in the structure of the second semiconductor region 12 and the gate electrode 23. A part of the second semiconductor region 12 and another part of the second semiconductor region 12 are separated from each other in the X direction. The gate electrode 23 is provided between these parts via a gate insulating portion 45. The gate electrode 23 also faces the first semiconductor region 11 in the Z direction via the gate insulating portion 45. The semiconductor device 130 has a recessed gate structure.

[0051] In the semiconductor device 130, the 2DEG generated directly below the source electrode 21 and the 2DEG generated directly below the drain electrode 22 are separated by the gate insulating portion 45. For this reason, the semiconductor device 130 is a normally-off type power device. When a voltage above a threshold is applied to the gate electrode 23, a channel is formed in the first semiconductor region 11 near the gate insulating portion 45. As a result, current flows between the source electrode 21 and the drain electrode 22, and the semiconductor device 130 turns on.

[0052] (Second Embodiment) Figure 10 is a cross-sectional view showing a semiconductor device according to the second embodiment. Compared to the semiconductor device 100, the semiconductor device 200 shown in Figure 10 includes a fourth semiconductor region 14 and a second FP electrode 32 instead of a third semiconductor region 13 and a first FP electrode 31.

[0053] The fourth semiconductor region 14 is separated from the drain electrode 22 and the gate electrode 23 in the X direction. A portion of the insulating layer 40 is located between the fourth semiconductor region 14 and the drain electrode 22, and between the fourth semiconductor region 14 and the gate electrode 23. The fourth semiconductor region 14 is electrically connected to the source electrode 21.

[0054] The insulating layer 40 is provided on the fourth semiconductor region 14 and the gate electrode 23. The second FP electrode 32 is provided on the insulating layer 40. The position p4 of the second FP electrode 32 in the X direction is between the position p2 of the gate electrode 23 in the X direction and the position p3 of the drain electrode 22 in the X direction. The second end e2 of the second FP electrode 32 in the X direction is located directly above the fourth semiconductor region 14.

[0055] In the semiconductor device 200, the electric field strength near the gate electrode 23 is mitigated by the second FP electrode 32. By providing the second FP electrode 32, the breakdown voltage of the semiconductor device 200 can be improved compared to when the second FP electrode 32 is not provided.

[0056] Electron trapping is likely to occur in the region directly below the second end e2. In the semiconductor device 200, a fourth semiconductor region 14 is provided in the region directly below the second end e2. By providing the fourth semiconductor region 14 and generating 2DHG, the trapped electrons can be neutralized. According to the second embodiment, the breakdown voltage of the semiconductor device 200 can be improved while suppressing current collapse.

[0057] (Third Embodiment) Figure 11 is a cross-sectional view showing a semiconductor device according to the third embodiment. Compared to the semiconductor device 100, the semiconductor device 300 shown in Figure 11 includes a fifth semiconductor region 15 instead of the third semiconductor region 13 and the first FP electrode 31, and the drain electrode 22 is provided with a third end e3.

[0058] The fifth semiconductor region 15 is separated from the gate electrode 23 in the X direction and is in contact with the drain electrode 22. A portion of the insulating layer 40 is located between the fifth semiconductor region 15 and the gate electrode 23. The third end e3 is located directly above the fifth semiconductor region 15 via the insulating layer 40.

[0059] In the semiconductor device 300, the electric field strength near the drain electrode 22 is mitigated by the third end e3. By providing the third end e3, the breakdown voltage of the semiconductor device 300 can be improved compared to when the third end e3 is not provided.

[0060] Electron trapping is likely to occur in the region directly below the third end e3. In the semiconductor device 300, a fifth semiconductor region 15 is provided in the region directly below the third end e3. By providing the fifth semiconductor region 15 and generating 2DHG, the trapped electrons can be neutralized. According to the third embodiment, the breakdown voltage of the semiconductor device 300 can be improved while suppressing current collapse.

[0061] The embodiments described above can be combined as appropriate. For example, semiconductor devices 100, 110, 200, or 300 may have a recessed gate structure, similar to the third modification of the first embodiment. The third embodiment may be combined with the second embodiment, and the semiconductor device 200 may be provided with a fifth semiconductor region 15 and a third end e3.

[0062] Embodiments of the present invention include the following features: (Feature 1) Al ｘ１ Ga １－ｘ１ A first semiconductor region containing N (0 ≤ x1 < 1), and provided on the first semiconductor region, Al ｘ２ Ga １－ｘ２ A second semiconductor region containing N (0 < x2 < 1, x1 < x2), a first electrode provided on a part of the second semiconductor region, a second electrode provided on another part of the second semiconductor region and away from the first electrode in a second direction perpendicular to a first direction toward the second semiconductor region, a gate electrode provided between the first electrode and the second electrode and facing the second semiconductor region via a gate insulating portion, a first field plate electrode provided on the gate electrode and electrically connected to the gate electrode, with its first end in the second direction positioned toward the second electrode relative to the gate electrode, and provided between the second semiconductor region and the first end in the first direction and away from the gate electrode and the second electrode in the second direction, Al ｘ３ Ga １－ｘ３A semiconductor device comprising a third semiconductor region containing N (0 ≤ x3 < 1, x3 < x2), and (Feature 2) The semiconductor device according to Feature 1, wherein the third semiconductor region is electrically connected to the first electrode. (Feature 3) The semiconductor device according to Feature 1 or 2, wherein the thickness of the third semiconductor region in the first direction is 15 nm or more. (Feature 4) Provided on the second semiconductor region, located between the third semiconductor region and the second electrode, and separated from the third semiconductor region and the second electrode, Al ｘ４ Ga １－ｘ４ A semiconductor device according to any one of features 1 to 3, further comprising: a fourth semiconductor region containing N (0 ≤ x4 < 1, x4 < x2); and a second field plate electrode whose position in the second direction is between the position of the gate electrode in the second direction and the position of the second electrode in the second direction, and whose second end in the second direction is located directly above the fourth semiconductor region. (Feature 5) A semiconductor device according to feature 4, wherein the fourth semiconductor region and the second field plate electrode are electrically connected to the first electrode. (Feature 6) A semiconductor device according to feature 4 or 5, wherein the thickness of the fourth semiconductor region in the first direction is 15 nm or more. (Feature 7) Provided on the second semiconductor region and in contact with the second electrode, Al ｘ５ Ga １－ｘ５ A semiconductor device according to any one of features 4 to 6, further comprising a fifth semiconductor region containing N (0 ≤ x5 < 1, x5 < x2), wherein the second electrode includes a third end protruding in the direction opposite to the first direction, and the third end is located directly above the fifth semiconductor region. (Feature 8) Al ｘ１ Ga １－ｘ１ A first semiconductor region containing N (0 ≤ x1 < 1), and provided on the first semiconductor region, Al ｘ２ Ga １－ｘ２A second semiconductor region containing N (0 < x2 < 1, x1 < x2), a first electrode provided on a part of the second semiconductor region, a second electrode provided on another part of the second semiconductor region and away from the first electrode in a second direction perpendicular to a first direction toward the second semiconductor region, a gate electrode provided between the first electrode and the second electrode and facing the second semiconductor region via a gate insulating portion, and provided on the second semiconductor region and away from the gate electrode and the second electrode in the second direction, Al ｘ４ Ga １－ｘ４ A semiconductor device comprising: a fourth semiconductor region containing N (0 ≤ x4 < 1, x4 < x2); and a second field plate electrode whose position in the second direction is between the position of the gate electrode in the second direction and the position of the second electrode in the second direction, and whose second end in the second direction is located directly above the fourth semiconductor region. (Feature 9) The semiconductor device according to Feature 8, wherein the thickness of the fourth semiconductor region in the first direction is 15 nm or more. (Feature 10) Al ｘ１ Ga １－ｘ１ A first semiconductor region containing N (0 ≤ x1 < 1), and provided on the first semiconductor region, Al ｘ２ Ga １－ｘ２ A second semiconductor region containing N (0 < x2 < 1, x1 < x2), a first electrode provided on a part of the second semiconductor region, a second electrode provided on another part of the second semiconductor region, having a third end that is separated from the first electrode in a second direction perpendicular to a first direction toward the second semiconductor region and protruding in the direction opposite to the first direction, a gate electrode provided between the first electrode and the second electrode and facing the second semiconductor region via a gate insulating portion, and provided on the second semiconductor region and in contact with the second electrode, Al ｘ５ Ga １－ｘ５ A semiconductor device comprising a fifth semiconductor region located directly below the third end, which contains N (0 ≤ x5 < 1, x5 < x2).

[0063] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other.

Claims

1. Al ｘ１ Ga １－ｘ１ A first semiconductor region containing N (0 ≤ x1 < 1), and provided on the first semiconductor region, Al ｘ２ Ga １－ｘ２ A second semiconductor region containing N (0 < x2 < 1, x1 < x2), a first electrode provided on a part of the second semiconductor region, a second electrode provided on another part of the second semiconductor region and away from the first electrode in a second direction perpendicular to a first direction toward the second semiconductor region, a gate electrode provided between the first electrode and the second electrode and facing the second semiconductor region via a gate insulating portion, a first field plate electrode provided on the gate electrode and electrically connected to the gate electrode, with its first end in the second direction positioned toward the second electrode relative to the gate electrode, and provided between the second semiconductor region and the first end in the first direction and away from the gate electrode and the second electrode in the second direction, Al ｘ３ Ga １－ｘ３ A semiconductor device comprising a third semiconductor region containing N (0 ≤ x³ < 1, x³ < x²), and 2. The semiconductor device according to claim 1, wherein the third semiconductor region is electrically connected to the first electrode.

3. The semiconductor device according to claim 1, wherein the thickness of the third semiconductor region in the first direction is 15 nm or more.

4. Provided on the second semiconductor region, located between the third semiconductor region and the second electrode, and separated from the third semiconductor region and the second electrode, Al ｘ４ Ga １－ｘ４ A semiconductor device according to any one of claims 1 to 3, further comprising: a fourth semiconductor region containing N (0 ≤ x4 < 1, x4 < x2); and a second field plate electrode whose position in the second direction is between the position of the gate electrode in the second direction and the position of the second electrode in the second direction, and whose second end in the second direction is located directly above the fourth semiconductor region.

5. The semiconductor device according to claim 4, wherein the fourth semiconductor region and the second field plate electrode are electrically connected to the first electrode.

6. The semiconductor device according to claim 4, wherein the thickness of the fourth semiconductor region in the first direction is 15 nm or more.

7. Provided on the second semiconductor region, in contact with the second electrode, Al ｘ５ Ga １－ｘ５ The semiconductor device according to claim 4, further comprising a fifth semiconductor region containing N (0 ≦ x5 < 1, x5 < x2), wherein the second electrode includes a third end portion protruding in a direction opposite to the first direction, and the third end portion is located directly above the fifth semiconductor region.

8. Al ｘ１ Ga １－ｘ１ A first semiconductor region containing N (0 ≤ x1 < 1), and provided on the first semiconductor region, Al ｘ２ Ga １－ｘ２ A second semiconductor region containing N (0 < x2 < 1, x1 < x2), a first electrode provided on a part of the second semiconductor region, a second electrode provided on another part of the second semiconductor region and away from the first electrode in a second direction perpendicular to a first direction toward the second semiconductor region, a gate electrode provided between the first electrode and the second electrode and facing the second semiconductor region via a gate insulating portion, and provided on the second semiconductor region and away from the gate electrode and the second electrode in the second direction, Al ｘ４ Ga １－ｘ４ A semiconductor device comprising: a fourth semiconductor region containing N (0 ≤ x4 < 1, x4 < x2); and a second field plate electrode whose position in the second direction is between the position of the gate electrode in the second direction and the position of the second electrode in the second direction, and whose second end in the second direction is located directly above the fourth semiconductor region.

9. The semiconductor device according to claim 8, wherein the thickness of the fourth semiconductor region in the first direction is 15 nm or more.

10. Al ｘ１ Ga １－ｘ１ A first semiconductor region containing N (0 ≤ x1 < 1), and provided on the first semiconductor region, Al ｘ２ Ga １－ｘ２ A second semiconductor region containing N (0 < x2 < 1, x1 < x2), a first electrode provided on a part of the second semiconductor region, a second electrode provided on another part of the second semiconductor region, having a third end that is separated from the first electrode in a second direction perpendicular to a first direction toward the second semiconductor region and protruding in the direction opposite to the first direction, a gate electrode provided between the first electrode and the second electrode and facing the second semiconductor region via a gate insulating portion, and provided on the second semiconductor region and in contact with the second electrode, Al ｘ５ Ga １－ｘ５ A semiconductor device comprising a fifth semiconductor region located directly below the third end, which contains N (0 ≤ x5 < 1, x5 < x2).

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