Semiconductor device

Abstract

The present invention addresses the problem of configuring a semiconductor device such that a connection terminal of an external device can be joined to the semiconductor device by either welding or screwing.　This semiconductor device comprises: a case (10) formed from an insulating material; and a main terminal (43) (first external connection terminal) having a flat connection surface (43a1) that is exposed from the upper side of the case (10) and has a rectangular shape in plan view, with at least a portion of the main terminal (43) being embedded inside the case (10). In this semiconductor device, the connection surface (43a1) includes: a hole part (43c2); and a welding region (43d) (first weldable region) that is disposed on the longitudinal direction side of the connection surface (43a1) with respect to the hole part (43c2) and to which the lower surface of a flat plate-shaped first connection terminal can be welded.

Description

Semiconductor device

[0001] The present invention relates to a semiconductor device.

[0002] A semiconductor device has an external connection terminal that can be connected to a connection terminal of an external device. As an example of such a semiconductor device, a semiconductor module provided with an external connection terminal joined by laser welding to the positive terminal of a capacitor via a connecting member has been proposed (see, for example, Patent Document 1). Also, as another example, a semiconductor package having a case in which nuts are embedded and an external connection terminal to which an external wiring (bus bar) is joined by screws attached to the nuts has been proposed (for example, Patent Document 2).

[0003] Japanese Patent Application Laid-Open No. 2022-103052 Japanese Patent Application Laid-Open No. 2023-31941

[0004] An object of the present invention is to provide a semiconductor device capable of joining a connection terminal of an external device by either welding or screwing.

[0005] According to one aspect of the invention, there is provided a semiconductor device having a case formed of an insulating material and a first external connection terminal having a flat and rectangular first connection surface exposed upward from the case and at least a part of which is embedded inside the case. In this semiconductor device, the first connection surface includes a first hole portion and a first weldable region where the lower surface of a flat plate-shaped first connection terminal disposed on the longitudinal direction side of the first connection surface with respect to the first hole portion can be welded.

[0006] Also, according to one aspect of the invention, there is provided a semiconductor device having a case formed of an insulating material and an external connection portion protruding from a side surface on the first direction side of the case and having a flat and rectangular upper surface and lower surface exposed from the case, including an end portion on the first direction side, and an external connection terminal at least a part of which is embedded inside the case. In this semiconductor device, the external connection portion includes a cylindrical hole portion that opens on one surface side of the upper surface or the lower surface and is non-penetrating on the other surface side.

[0007] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention.

[0008] According to the disclosed technology, connection terminals for external devices can be joined to a semiconductor device by either welding or screwing. The above and other objects, features and advantages of the present invention will become apparent from the following description in conjunction with the accompanying drawings illustrating preferred embodiments as examples of the present invention.

[0009] This is a plan view showing the external appearance of a semiconductor device according to the first embodiment. This is a side view showing the external appearance of a semiconductor device according to the first embodiment. This is a plan view of the insulating substrate, main terminal and output terminal. This is a diagram showing an example of a circuit configuration of a 3-level inverter. This is an enlarged plan view of a part of the semiconductor device according to the first embodiment. This is a side view of the semiconductor device according to the first embodiment. This is an enlarged cross-sectional view of a part of the semiconductor device according to the first embodiment. This is a plan view showing an example of a semiconductor device with an external device connected. This is a cross-sectional view showing an example of a semiconductor device with an external device connected. This is a plan view showing a semiconductor device according to the first embodiment with a capacitor connected. This is a cross-sectional view showing a semiconductor device according to the first embodiment with a capacitor connected. This is a cross-sectional view showing an evaluation device connected to the semiconductor device according to the first embodiment. This is a plan view showing a first arrangement example of holes and welding areas in the main terminal. This is a plan view showing a second arrangement example of holes and welding areas in the main terminal. This is an enlarged plan view and cross-sectional view of a part of the semiconductor device according to the second embodiment. This is an enlarged plan view of a part of the semiconductor device according to the third embodiment. This is a side view of the semiconductor device according to the third embodiment. This is an enlarged cross-sectional view of a part of the semiconductor device according to the third embodiment. This is a cross-sectional view showing an external device connected to the semiconductor device according to the third embodiment. This is a plan view of a modified example of the semiconductor device according to the third embodiment. This is an enlarged plan view of a part of the semiconductor device according to the fourth embodiment. This is an enlarged cross-sectional view of a part of the semiconductor device according to the fourth embodiment. This is an enlarged plan view and cross-sectional view of a part of the semiconductor device according to the fifth embodiment. This is a cross-sectional view showing a capacitor connected to the semiconductor device according to the fifth embodiment.

[0010] The embodiments will be described below with reference to the drawings. In the following description, "front surface" and "top surface" refer to the X-Y plane facing upwards (+Z direction) in the semiconductor device shown in the drawings. Similarly, "up" refers to the direction upwards (+Z direction) in the semiconductor device shown in the drawings. "Back surface" and "bottom surface" refer to the X-Y plane facing downwards (-Z direction) in the semiconductor device shown in the drawings. Similarly, "down" refers to the direction downwards (-Z direction) in the semiconductor device shown in the drawings. The same directionality will be used in other drawings as needed. "Front surface," "top surface," "up," "back surface," "bottom surface," "down," and "side" are merely convenient expressions to specify relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions "up" and "down" are not limited to the direction of gravity.

[0011] [First Embodiment] First, the appearance of the semiconductor device according to the embodiment will be described using Figures 1 and 2. Figure 1 is a plan view showing the appearance of the semiconductor device according to the first embodiment. Figure 2 is a side view showing the appearance of the semiconductor device according to the first embodiment. Note that Figure 2 is a side view of the semiconductor device 1 of Figure 1 when viewed in the +Y direction.

[0012] The semiconductor device 1 is a modularized device consisting of a circuit board on which semiconductor chips are mounted, external connection terminals, and other components. The semiconductor device 1 is mounted on the upper surface (the surface in the +Z direction) of a cooling module (not shown). The cooling module may be, for example, a heat dissipation base equipped with heat dissipation fins, or a cooling device in which a coolant circulates inside.

[0013] The semiconductor device 1 has a case 10 that houses a wiring board 20 and an insulating board 30. The case 10 includes a storage section 11 and terminal holding sections 12 and 13. The terminal holding section 12 is integrally connected to the -X side of the storage section 11, and the terminal holding section 13 is integrally connected to the +X side of the storage section 11. Furthermore, both the storage section 11 and the terminal holding sections 12 and 13 have upper surfaces that are parallel to the horizontal plane (X-Y plane) and have the same height, and these upper surfaces constitute the upper surface 10a of the case 10.

[0014] The storage section 11 is box-shaped and includes an upper surface portion that forms part of the upper surface 10a of the case 10 and is rectangular in plan view, and side wall portions 11a to 11d provided on the lower side (-Z direction side) of each of the four edges of the upper surface portion. The storage section 11 includes a storage area 11e surrounded by the upper surface portion and the side wall portions 11a to 11d, with the bottom side (-Z direction side) open. Inside the storage area 11e, an insulating substrate 30 is placed on the bottom side, and a wiring board 20 is placed opposite the upper side (+Z direction side) of the insulating substrate 30.

[0015] The interior of the storage area 11e is sealed by the sealing member 10b. In this embodiment, the lower surface of the insulating substrate 30 is exposed from the storage area 11e and is on the same plane as the lower surfaces of the storage section 11 and terminal holding sections 12 and 13 of the case 10. Also, the side surface of the insulating substrate 30 and the side walls 11a to 11d of the storage section 11 are not in contact, and there is a gap between them. For this reason, the sealing member 10b is filled inside the storage area 11e so as to cover the lower end of the side surface of the insulating substrate 30, and the sealing member 10b covering the side surface of the insulating substrate 30 along with the lower surface of the insulating substrate 30 is exposed from the bottom of the storage area 11e. A metal plate (not shown) is formed on the lower surface of the insulating substrate 30, and this metal plate is in contact with the upper surface of the cooling module.

[0016] Furthermore, the side wall portion 11c of the storage portion 11 is provided with an opening 11f for injecting the sealing member 10b. A similar opening may also be provided in the side wall portion 11a facing the side wall portion 11c.

[0017] The upper surface of the storage section 11 includes edges 11g1 and 11g2 extending in the X-axis direction on the +Y-direction side and the -Y-direction side, respectively. External connection terminals 14a to 14d, 14i, and 14j are provided on edge 11g1, and external connection terminals 14e to 14h are provided on edge 11g2. The external connection terminals 14a to 14j are columnar in shape and extend generally in the vertical direction (Z-axis direction). The columnar shape may be a rectangular prism or a cylindrical shape.

[0018] External connection terminals 14a to 14d, 14i, and 14j are held on edge 11g1 with the terminals penetrating vertically through edge 11g1. External connection terminals 14e to 14h are held on edge 11g2 with the terminals penetrating vertically through edge 11g2. The upper ends of external connection terminals 14a to 14d, 14i, and 14j that protrude above edge 11g1 and the upper ends of external connection terminals 14e to 14h that protrude above edge 11g2 form connection terminals for connecting to an external circuit. In this embodiment, these connection terminals are press-fit pins. On the other hand, the lower ends of the external connection terminals 14a to 14d, 14i, and 14j that protrude from the edge 11g1 to the lower storage area 11e, and the lower ends of the external connection terminals 14e to 14h that protrude from the edge 11g2 to the lower storage area 11e, are inserted into wiring holes (not shown) provided in the wiring board 20 and are electrically connected to a predetermined wiring layer (not shown) formed on the wiring board 20.

[0019] The terminal holding section 12 is provided with main terminals 41 to 43 as external connection terminals. Rectangular external connection sections 41a, 42a, and 43a are formed at the -X-direction ends (outer ends) of the main terminals 41 to 43, respectively, in a plan view. The main terminals 41 to 43 are held by the terminal holding section 12 with the upper surfaces of the external connection sections 41a, 42a, and 43a exposed above the terminal holding section 12. The upper surfaces of the external connection sections 41a, 42a, and 43a exposed from the terminal holding section 12 can be connected to the connection terminals of an external device. On the other hand, the +X-direction ends (inner ends) of the main terminals 41 to 43 are electrically connected to the circuit pattern on the upper surface of the insulating substrate 30 in the storage area 11e of the storage section 11.

[0020] The terminal holding portion 13 is provided with an output terminal 44 as an external connection terminal. A rectangular external connection portion 44a is formed at the +X direction end (outer end) of the output terminal 44 in a plan view. The output terminal 44 is held by the terminal holding portion 13 with the upper surface of the external connection portion 44a exposed above the terminal holding portion 13. The upper surface of the external connection portion 44a exposed from the terminal holding portion 13 can be connected to an external circuit. On the other hand, the -X direction end (inner end) of the output terminal 44 is connected to the circuit pattern on the upper surface of the insulating substrate 30 in the storage area 11e of the storage portion 11.

[0021] In this embodiment, a three-level inverter circuit is formed by a wiring board 20, an insulating board 30, and a semiconductor chip (described later) housed inside the case 10. The main terminals 41 to 43 correspond to the P terminal, N terminal, and neutral terminal of the three-level inverter circuit, respectively, and the output terminal 43 corresponds to the output terminal of the three-level inverter circuit. The external connection terminals 14a to 14h correspond to control terminals for controlling the switching operation of the transistors included in the three-level inverter circuit. The external connection terminals 14h and 14i correspond to output terminals for temperature sensing.

[0022] The case 10, which includes the storage section 11 and the terminal holding sections 12 and 13, is integrally molded by injection molding using a thermoplastic resin, with parts of the external connection terminals 14a to 14i, the main terminals 41 to 43, and the output terminal 44 embedded within it. The thermoplastic resin is, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, acrylonitrile butadiene styrene resin, or liquid crystal polymer. The external connection terminals 14a to 14e and 41 to 44 are formed from a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy mainly composed of at least one of these.

[0023] Furthermore, a thermosetting resin is used as the sealing material for the sealing member 10b. The thermosetting resin is, for example, epoxy resin. By sealing the housing area 11e of the case 10, which houses the wiring board 20, the insulating board 30, and the semiconductor chip, using such a resin, a highly rigid semiconductor device 1 is manufactured.

[0024] Figure 3 is a plan view of the insulating substrate, main terminals, and output terminals. As mentioned above, the main terminals 41-43 and output terminal 44 are integrally molded with the case 10. In Figure 3, the main terminals 41-43 and output terminal 44 are shown together with the insulating substrate 30 with the case 10 removed.

[0025] The insulating substrate 30 includes an insulating plate 32, circuit patterns 33a to 33g formed on the upper surface (the surface in the +Z direction) of the insulating plate 32, and a metal plate (not shown) formed on the lower surface (the surface in the -Z direction) of the insulating plate 32. Semiconductor chips 31a to 31e are mounted on the insulating substrate 30.

[0026] The insulating plate 32 is made of, for example, a resin. The resin may be a material with low thermal resistance and high insulating properties. Examples of such resins include thermosetting resins and thermoplastic resins. Examples of thermosetting resins include at least one of epoxy resins, cyanate resins, polyimide resins, benzoxazine resins, unsaturated polyester resins, phenolic resins, melamine resins, silicone resins, and maleimide resins. Examples of thermoplastic resins include at least one of acrylic resins and polyamide resins. Furthermore, these resins may contain fillers. The fillers are made of at least one of oxides and nitrides. Examples of oxides include silicon oxide and aluminum oxide. Examples of nitrides include silicon nitride, aluminum nitride, and boron nitride. Furthermore, hexagonal boron nitride may also be used as the filler.

[0027] The insulating plate 32 may be made of a ceramic substrate instead of resin. The ceramic substrate is made of a ceramic material with good thermal conductivity. The ceramic material is made of a material mainly composed of aluminum oxide, aluminum nitride, or silicon nitride, for example. The insulating substrate 30, which includes an insulating plate 32 having such a configuration, can use, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate.

[0028] The circuit patterns 33a to 33f and the metal plates are formed from metals with excellent conductivity. Such metals are, for example, copper, aluminum, or alloys mainly composed of at least one of these.

[0029] The semiconductor chips 31a to 31d may be power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) mainly composed of silicon carbide. The power MOSFET may have a body diode that functions as a FWD (Free Wheeling Diode). Such semiconductor chips 31a to 31d, for example, have an input electrode (drain electrode) which is the main electrode on the back surface, and an output electrode (source electrode) and a control electrode (gate electrode), which are the main electrodes, on the front surface.

[0030] The semiconductor chips 31a to 31d may include switching elements composed mainly of silicon. The switching elements may be, for example, RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). An RC-IGBT is a semiconductor element in which an IGBT and an FWD are configured in antiparallel within a single chip. Such semiconductor chips 31a to 31d have, for example, an input electrode (collector electrode), which is the main electrode, on the back surface, and an output electrode (emitter electrode) and a control electrode (gate electrode), which are the main electrodes, on the front surface.

[0031] Furthermore, semiconductor chips 31a to 31d may each include a pair of switching elements and diode elements, respectively, which are mainly composed of silicon. The switching elements are, for example, power MOSFETs and IGBTs. A semiconductor chip including a switching element has, for example, an input electrode (drain electrode in the case of a power MOSFET, collector electrode in the case of an IGBT) as the main electrode on its back surface, and a gate electrode as the control electrode and an output electrode as the main electrode (source electrode in the case of a power MOSFET, emitter electrode in the case of an IGBT) on its front surface. The diode elements include, for example, SBDs (Schottky Barrier Diodes) and PiN (P-intrinsic-N) diodes used as FWDs. A semiconductor chip including a diode element has, for example, an output electrode (cathode electrode) as the main electrode on its back surface and an input electrode (anode electrode) as the main electrode on its front surface.

[0032] In this embodiment, the semiconductor chips 31a to 31d are power MOSFETs mainly composed of silicon carbide.

[0033] As an example, four semiconductor chips 31c are mounted on the upper surface of circuit pattern 33c. Although not shown in the diagram, the input electrodes on the lower surface of semiconductor chips 31c are electrically connected to the upper surface of circuit pattern 33c via solder. As an example, four semiconductor chips 31d are mounted on the upper surface of circuit pattern 33d. Although not shown in the diagram, the input electrodes on the lower surface of semiconductor chips 31d are electrically connected to the upper surface of circuit pattern 33d via solder. As an example, four semiconductor chips 31a and as an example, four semiconductor chips 31b are mounted on the upper surface of circuit pattern 33e. Although not shown in the diagram, the input electrodes on the lower surfaces of semiconductor chips 31a and 31b are electrically connected to the upper surface of circuit pattern 33e via solder.

[0034] A semiconductor chip 31e is mounted on the upper surface of the circuit pattern 33g. The semiconductor chip 31e includes semiconductor elements that perform various sensing operations. For example, the semiconductor chip 31e includes a diode element that detects temperature. Although not shown in the figure, electrodes provided on the lower surface of the semiconductor chip 31e are electrically connected to the upper surface of the circuit pattern 33g via solder.

[0035] The circuit pattern 33a is electrically connected to the main terminal 42. Specifically, an external connection portion 42a is formed at the -X side end of the main terminal 42. At the +X side end of the external connection portion 42a of the main terminal 42, a horizontally flat internal connection portion 42b is formed via an intermediate portion (not shown) that extends downward (-Z direction). The lower surface of the internal connection portion 42b is electrically connected to the upper surface of the circuit pattern 33a.

[0036] The circuit pattern 33b is electrically connected to the main terminal 43. Specifically, an external connection portion 43a is formed at the -X side end of the main terminal 43. Furthermore, a horizontally flat internal connection portion 43b is formed at the +X side end of the external connection portion 43a of the main terminal 43, via an intermediate portion (not shown) that extends downward (-Z direction). The lower surface of the internal connection portion 43b is electrically connected to the upper surface of the circuit pattern 33b.

[0037] The circuit pattern 33d is electrically connected to the main terminal 41. Specifically, an external connection portion 41a is formed at the -X side end of the main terminal 41. Furthermore, a horizontally flat internal connection portion 41b is formed at the +X side end of the external connection portion 41a of the main terminal 41, via an intermediate portion (not shown) that extends downward (-Z direction). The lower surface of the internal connection portion 41b is electrically connected to the upper surface of the circuit pattern 33d.

[0038] The circuit pattern 33f is electrically connected to the output terminal 44. Specifically, an external connection portion 44a is formed at the +X side end of the output terminal 44. Furthermore, a horizontally flat internal connection portion 44b is formed at the -X side end of the external connection portion 44a of the output terminal 44, via an intermediate portion (not shown) that extends downward (-Z direction). The lower surface of the internal connection portion 44b is electrically connected to the upper surface of the circuit pattern 33f.

[0039] The wiring board 20 is, for example, a multilayer printed circuit board (PCB). In the wiring board 20, for example, a wiring layer may be formed on at least one of the upper and lower surfaces of an insulating layer. Furthermore, multiple insulating layers may be laminated on the wiring board 20, and a wiring layer may also be formed on one of the adjacent insulating layers.

[0040] The insulating layer is formed of, for example, an insulating resin. Examples of insulating resins include paper phenolic substrates, paper epoxy substrates, glass composite substrates, glass epoxy substrates, Teflon® substrates, and polyimide substrates. The wiring layer is formed of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or alloys mainly composed of at least one of these.

[0041] The wiring board 20 is provided with a plurality of wiring holes (through-holes, not shown) that penetrate the wiring board 20, and wiring pins (not shown) are inserted into each wiring hole. The wiring pins are made of a metal with excellent conductivity. Each wiring hole is connected to a circuit pattern of one of the wiring layers formed on the wiring board 20, and the wiring pin is electrically connected to the circuit pattern connected to the wiring hole into which it is inserted. The lower end of the wiring pin is electrically connected via solder to one of the electrodes on the upper surface of the semiconductor chips 31a to 31e mounted on the insulating substrate 30, or to one of the circuit patterns 33a to 33g formed on the upper surface of the insulating substrate 30. The wiring layers, wiring holes, and wiring pins provided on the wiring board 20 as described above make it possible to wire between one of the electrodes on the upper surface of the semiconductor chips 31a to 31e and one of the circuit patterns 33a to 33g, or between one of the circuit patterns 33a to 33g and another.

[0042] Figure 4 shows an example of a circuit configuration for a three-level inverter. The semiconductor device 1 is equipped with a three-level inverter as shown in Figure 4. This three-level inverter is a T-type NPC (Neutral Point Clamped) inverter circuit and includes four transistors Q1 to Q4. Transistor Q1 corresponds to semiconductor chip 31d, transistor Q2 corresponds to semiconductor chip 31c, transistor Q3 corresponds to semiconductor chip 31b, and transistor Q4 corresponds to semiconductor chip 31a.

[0043] The drain electrode of transistor Q1 is connected to the positive input terminal P via the insulating substrate 30. The P terminal corresponds to the main terminal 41. The source electrode of transistor Q2 is connected to the negative input terminal N via the wiring substrate 20 and the insulating substrate 30. The N terminal corresponds to the main terminal 42.

[0044] The drain electrode of transistor Q3 and the drain electrode of transistor Q4 are connected via the insulating substrate 30, and the source electrode of transistor Q3 is connected to the M terminal (neutral terminal), which is an input terminal at an intermediate potential, via the wiring board 20 and the insulating substrate 30. The M terminal corresponds to the main terminal 43.

[0045] The source electrode of transistor Q1, the drain electrode of transistor Q2, and the source electrode of transistor Q4 are connected via the insulating substrate 30 and the wiring substrate 20, and these connection points are connected to the U terminal, which is an output terminal, via the wiring substrate 20 and the insulating substrate 30. The U terminal corresponds to the output terminal 44.

[0046] The gate electrodes of transistors Q1 to Q4 are connected via the wiring substrate 20 to gate terminals (control terminals) G1 to G4, which are input terminals for control signals for the switching operation. The gate terminals G1 to G4 correspond to, for example, external connection terminals 14c, 14g, 14b, and 14f, respectively. The source electrodes of transistors Q1 to Q4 are connected via the wiring substrate 20 to auxiliary source terminals S1 to S4, which are output terminals. The auxiliary source terminals S1 to S4 correspond to external connection terminals 14d, 14h, 14a, and 14e, respectively.

[0047] In this three-level inverter, when the control signals to gate terminals G1 and G3 are on and the control signals to gate terminals G2 and G4 are off, the output voltage from the U terminal is E / 2. When the control signals to gate terminals G3 and G4 are on and the control signals to gate terminals G1 and G2 are off, the output voltage from the U terminal is 0. When the control signals to gate terminals G2 and G4 are on and the control signals to gate terminals G1 and G3 are off, the output voltage from the U terminal is -E / 2.

[0048] As described above, transistors Q1 to Q4 included in the three-level inverter correspond to semiconductor chips 31a to 31d, respectively. Also, as shown in FIG. 3, the semiconductor device 1 of the present embodiment includes four semiconductor chips 31a to 31d each. Therefore, the semiconductor device 1 includes four sets of arms each including one semiconductor chip 31a to 31d, and these three-level inverters are connected in parallel.

[0049] Although not shown in the diagram, three semiconductor devices 1 equipped with parallel 3-level inverters as described above are used in combination. One semiconductor device 1 generates a U-phase output voltage, another semiconductor device 1 generates a V-phase output voltage, and another semiconductor device 1 generates a W-phase output voltage.

[0050] Next, the configuration of the main terminals 41 to 43 and their surroundings will be described in detail. As mentioned above, the ends (outer ends) of the main terminals 41 to 43 on the -X direction each have rectangular external connection parts 41a, 42a, and 43a formed in plan view. Connection terminals of external devices are connected to the upper surfaces of the external connection parts 41a, 42a, and 43a. Since the upper surfaces of the external connection parts 41a, 42a, and 43a are flat, flat terminals are mainly used as connection terminals for external devices. In that case, the lower surface of the flat terminal is joined to the flat upper surface of the external connection parts 41a, 42a, and 43a. Examples of external devices include capacitors.

[0051] When the semiconductor device 1 is shipped and put into use by the user (hereinafter referred to as the "use stage"), the connection terminals of external devices are basically joined to the upper surfaces of the external connection parts 41a, 42a, and 43a by laser welding. As a result, the connection terminals of external devices and the main terminals 41 to 43 are firmly joined in a manner that makes them difficult to remove.

[0052] On the other hand, during the development phase of the semiconductor device 1, the pre-shipment inspection phase, and the post-shipment user inspection phase, an external device for performance evaluation (hereinafter referred to as "evaluation device") may be connected to the main terminals 41 to 43. In these phases (hereinafter referred to as "evaluation phase"), for example, the performance evaluation of multiple semiconductor devices 1 may be performed sequentially using one evaluation device. For this reason, in the evaluation phase, it is required that the connection terminals of the external device and the main terminals 41 to 43 be easily detachable.

[0053] Here, one possible method for joining the connection terminals of an external device to the main terminals 41-43 in a removable manner is to use solder. With this method, the terminals can be joined relatively firmly during use, while during evaluation, the connection terminals of the external device can be relatively easily removed from the main terminals 41-43 by heating. However, the joint is heated for solder melting each time the terminals are joined and removed during evaluation, and again when joining the terminals during use. In this case, it is difficult to heat only the joint locally, and the case 10 of the semiconductor device 1 also gets heated. As a result, excessive heat history occurs throughout the semiconductor device 1, which may cause deformation and deterioration of the wiring board 20, insulating board 30, semiconductor chips 31a-31e, and case 10, potentially damaging the semiconductor device 1 and making normal operation impossible.

[0054] Another possible method for connecting the external device's connection terminals to the main terminals 41-43 in a detachable manner is to fasten them with screws. This method allows for easy attachment and detachment of the terminals during the evaluation phase.

[0055] In this embodiment, screw holes are formed on the upper surfaces of the external connection portions 41a, 42a, and 43a of the main terminals 41 to 43. At the same time, a flat area (weldable area) of sufficient size (width) for laser welding is formed on the upper surfaces of the external connection portions 41a, 42a, and 43a, excluding the holes. As a result, the main terminals 41 to 43 can be joined to the connection terminals of external devices by both laser welding and screw fastening.

[0056] Figure 5 is an enlarged plan view of a part of the semiconductor device according to the first embodiment. Figure 6 is a side view of the semiconductor device according to the first embodiment. Figure 7 is an enlarged cross-sectional view of a part of the semiconductor device according to the first embodiment.

[0057] Figure 5 shows an enlarged plan view of the area around the terminal holding portion 12 that holds the main terminals 41 to 43 of the semiconductor device 1. Figure 6 shows a side view of the semiconductor device 1 as seen in the +X direction. Figure 7 shows an enlarged cross-sectional view of the area around the terminal holding portion 12, obtained by cutting the semiconductor device 1 along the lines I1-I1 and I2-I2 in Figure 5, respectively.

[0058] An external connection portion 41a is formed at the -X direction end of the main terminal 41, and an internal connection portion 41b is formed at the +X direction end. A flat connection surface 41a1 is formed on the upper surface of the external connection portion 41a. In plan view, the connection surface 41a1 is a rectangle with a long side along the Y-axis direction. The connection surface 41a1 is exposed above the case 10, and the connection terminals of an external device can be connected to the connection surface 41a1. On the other hand, the internal connection portion 41b is connected to the circuit pattern on the upper surface of the insulating substrate 30 in the storage area 11e of the storage portion 11. Furthermore, the area between the external connection portion 41a and the internal connection portion 41b of the main terminal 41 is embedded inside the case 10.

[0059] An external connection portion 42a is formed at the -X direction end of the main terminal 42, and an internal connection portion 42b is formed at the +X direction end. A flat connection surface 42a1 is formed on the upper surface of the external connection portion 42a. In plan view, the connection surface 42a1 is a rectangle with a long side along the Y axis. The connection surface 42a1 is exposed above the case 10, and the connection terminals of an external device can be connected to the connection surface 42a1. On the other hand, the internal connection portion 42b is connected to the circuit pattern on the upper surface of the insulating substrate 30 in the storage area 11e of the storage portion 11. Furthermore, the area between the external connection portion 42a and the internal connection portion 42b of the main terminal 42 is embedded inside the case 10.

[0060] An external connection portion 43a is formed at the -X direction end of the main terminal 43 (first external connection terminal), and an internal connection portion 43b (first connection surface) is formed at the +X direction end. A flat connection surface 43a1 is formed on the upper surface of the external connection portion 43a. In plan view, the connection surface 43a1 is a rectangle with a long side along the Y axis. The connection surface 43a1 is exposed above the case 10, and the connection terminals of an external device can be connected to the connection surface 43a1. On the other hand, the internal connection portion 43b is connected to the circuit pattern on the upper surface of the insulating substrate 30 in the storage area 11e of the storage portion 11. Furthermore, the area between the external connection portion 43a and the internal connection portion 43b of the main terminal 43 is embedded inside the case 10.

[0061] The area of ​​the main terminal 43 excluding the external connection portion 43a is a flat plate with approximately the same thickness. On the other hand, the external connection portion 43a is formed to be thicker than the area other than the external connection portion 43a, and in a side view, it is offset upward (towards the +Z direction) relative to the area other than the external connection portion 43a. The upper side of the external connection portion 43a protrudes upward from the upper surface 10a of the case 10, and the height of the connection surface 43a1 is higher than the upper surface 10a of the case 10. The connection surface 43a1 of the external connection portion 43a may be approximately parallel to the upper surface 10a of the case 10.

[0062] The main terminals 41 and 42 are arranged in parallel in the Y-axis direction (in a straight line). The external connection portions 41a and 42a of the main terminals 41 and 42 are positioned offset to the -X direction from the external connection portion 43a of the main terminal 43. The area between the external connection portion 41a and the internal connection portion 41b of the main terminal 41, and the area between the external connection portion 42a and the internal connection portion 42b of the main terminal 42, are located below the external connection portion 43a of the main terminal 43. As a result, a laminated connector structure is formed in which the main terminals 41, 42 and the main terminal 43 are stacked.

[0063] The area of ​​the main terminal 41 excluding the external connection portion 41a is a flat plate shape with approximately the same thickness. On the other hand, the external connection portion 41a is formed to be thicker than the area other than the external connection portion 41a and has a cross-sectional shape that protrudes upward overall from the area other than the external connection portion 41a. Similarly, the area of ​​the main terminal 42 excluding the external connection portion 42a is a flat plate shape with approximately the same thickness. On the other hand, the external connection portion 42a is formed to be thicker than the area other than the external connection portion 42a and has a cross-sectional shape that protrudes upward overall from the area other than the external connection portion 42a.

[0064] Furthermore, on the upper side (+Z direction side) of the terminal holding portion 12's end region on the -X direction side, a side wall portion 12a is formed on the +Y direction side, a side wall portion 12b is formed on the -Y direction side, and partition portions 12c and 12d are formed in the central part. The side walls 12a, 12b and partition portions 12c and 12d are flat plates parallel to the X-Z plane, and the height of the upper ends of the side walls 12a, 12b and partition portions 12c and 12d coincides with the height of the upper surface 10a of the case 10. In addition, a gap is provided between the partition portions 12c and 12d.

[0065] Furthermore, upper surfaces 12e1 and 12e2 are formed on the upper side (+Z direction side) of the terminal holding portion 12's -X direction end region, perpendicular to the side walls 12a and 12b and the partition walls 12c and 12d, and facing the -X direction. Upper surface 12e1 is connected to the +X direction ends of the side walls 12a and the partition walls 12c. Upper surface 12e2 is connected to the +X direction ends of the side walls 12b and the partition walls 12d.

[0066] The external connection portion 41a of the main terminal 41 is positioned in a space enclosed by the inner wall 12a1 (side on the -Y direction) of the side wall 12a, the inner wall 12c1 (side on the +Y direction) of the partition wall 12c, and the upper side 12e1, with openings in the upward direction (+Z direction) and the -X direction. The connection surface 41a1 of the external connection portion 41a is exposed to the outside of the case 10 through the upper opening of this space. On the other hand, the lower surface of the external connection portion 41a is in contact with the lower member 12g of the terminal holding portion 12.

[0067] Furthermore, the external connection portion 42a of the main terminal 42 is positioned in a space enclosed by the inner wall 12b1 (the side facing the +Y direction) of the side wall 12b, the inner wall 12d1 (the side facing the -Y direction) of the partition wall 12d, and the upper side surface 12e2, with openings in the upward direction (+Z direction) and the -X direction. The connection surface 42a1 of the external connection portion 42a is exposed to the outside of the case 10 through the upper opening of this space. On the other hand, the lower surface of the external connection portion 42a is in contact with the lower member 12h of the terminal holding portion 12.

[0068] The height of the connection surfaces 41a1 and 42a1 of the main terminals 41 and 42 is lower than the height of the case 10. On the other hand, the height of the upper end of the partition wall portions 12c and 12d provided between the main terminals 41 and 42 is the same as the height of the case 10 and is higher than the height of the connection surfaces 41a1 and 42a1. By providing such partition wall portions 12c and 12d between the main terminals 41 and 42, creepage distances can be secured between the connection surfaces 41a1 and 42a1 of the main terminals 41 and 42, and insulation between the main terminals 41 and 42 can be maintained.

[0069] Furthermore, the ends of the external connection portions 41a and 42a of the main terminals 41 and 42 on the -X direction may protrude in the -X direction from the end of the terminal holding portion 12 of the case 10 in the same direction, or they may be on the same plane. Here, the case where they protrude is given as an example.

[0070] Next, we will describe the configuration of the connection between the main terminals 41 to 43 and the connection terminals of external devices.

[0071] A hole 41c is formed in the connection surface 41a1 of the main terminal 41. The hole 41c is a screw hole for screwing in the connection terminal of an external device, and a screw groove is cut into the inner wall of the hole 41c. The lower end of this hole 41c does not penetrate the external connection part 41a. The connection surface 41a1 also includes a welding area 41d on the longitudinal side (Y-axis side) relative to the hole 41c. The welding area 41d is flat and is an area in which the lower surface of the connection terminal of an external device can be joined by laser welding.

[0072] A hole 42c is formed in the connection surface 42a1 of the main terminal 42. The hole 42c is a screw hole for screwing in the connection terminal of an external device, and a screw groove is cut into the inner wall of the hole 42c. The lower end of this hole 42c does not penetrate the external connection part 42a. In addition, the connection surface 42a1 includes a welding area 42d on the longitudinal side (Y-axis side) relative to the hole 42c. The welding area 42d is flat and is an area in which the lower surface of the connection terminal of an external device can be joined by laser welding.

[0073] A hole is formed in the connection surface 43a1 of the main terminal 43. In this embodiment, as an example, two holes 43c1 and 43c2 are formed in the connection surface 43a1 along the longitudinal direction (Y-axis direction) of the connection surface 43a1. The holes 43c1 and 43c2 are screw holes for screwing in the connection terminals of an external device, and screw grooves are cut into the inner walls of the holes 43c1 and 43c2. The lower ends of these holes 43c1 and 43c2 do not penetrate the external connection part 43a. In addition, the connection surface 43a1 includes a welding area 43d on the longitudinal side (Y-axis direction) relative to the holes 43c1 and 43c2. In this embodiment, as an example, the welding area 43d is located between the two holes 43c1 and 43c2. The welding area 43d is flat and is an area on which the lower surface of the connection terminal of an external device can be joined by laser welding.

[0074] Here, a comparative example of semiconductor device 1 will be described using Figures 8 and 9. Figure 8 is a plan view showing the comparative example of semiconductor device with an external device connected. Figure 9 is a cross-sectional view showing the comparative example of semiconductor device with an external device connected.

[0075] Figure 8 shows an enlarged plan view of the area around the terminal holding portion 12 that holds the main terminals 41 to 43 in the comparative example of semiconductor device 1. Figure 9 shows an enlarged cross-sectional view of the area around the terminal holding portion 12 in the comparative example of semiconductor device 1 when it is cut along the lines I3-I3 and I4-I4 in Figure 8, respectively. Figures 8 and 9 also show the state in which the external device 50 is connected to the comparative example of semiconductor device 1. In Figure 8, the outlines of the external device 50 and the connection terminals 51 to 53 are shown by thick dashed lines.

[0076] The external device 50 is an external device connected during the usage phase (e.g., a capacitor 50a) or an evaluation device 50b connected during the evaluation phase. Connection terminals 51 to 53 are provided on the side of the external device 50 in the +X direction. Connection terminals 51 to 53 are terminals that are connected to the main terminals 41 to 43, and all of them are flat.

[0077] The capacitor 50a is equipped with connection terminals 51a, 52a, and 53a, which correspond to the connection terminals 51, 52, and 53 described above. The evaluation device 50b is also equipped with connection terminals 51b, 52b, and 53b, which correspond to the connection terminals 51, 52, and 53 described above. In the following description, it will be assumed that the external shapes of the connection terminals 51, 51a, and 51b are the same, the external shapes of the connection terminals 52, 52a, and 52b are the same, and the external shapes of the connection terminals 53, 53a, and 53b are the same.

[0078] In the comparative example of the semiconductor device 1 shown in Figures 8 and 9, the main terminals 41 to 43 are all flat plates of approximately the same thickness. The connection surfaces 41a1, 42a1, and 43a1 of the main terminals 41, 42, and 43 are connected to the lower surfaces of the +X direction ends of the connection terminals 51, 52, and 53, respectively. In this configuration, the connection surfaces 41a1, 42a1, and 43a1 and the lower surfaces of the connection terminals 51, 52, and 53 can be joined by laser welding or soldering. However, as mentioned above, it is difficult to remove the connection terminals 51 to 53 from the main terminals 41 to 43 when joining by laser welding. Also, as mentioned above, when joining by soldering, the semiconductor device 1 is heated when attaching and detaching the main terminals 41 to 43 and the connection terminals 51 to 53, so there is a possibility that the semiconductor device 1 may be damaged by heat.

[0079] In Figure 9, as an example, a portion of the lower side of the external connection portion 43a of the main terminal 43 is embedded in the terminal holding portion 12 of the case 10.

[0080] Figure 10 is a plan view showing a semiconductor device according to the first embodiment with a capacitor connected. Figure 11 is a cross-sectional view showing a semiconductor device according to the first embodiment with a capacitor connected.

[0081] Figures 10 and 11 show a state in which a capacitor 50a, which is an example of an external device 50 connected during use, is connected to the semiconductor device 1 according to the first embodiment. The capacitor 50a is provided with connection terminals 51a, 52a, and 53a, which correspond to the aforementioned connection terminals 51, 52, and 53, respectively. The external shapes of the capacitor 50a and the connection terminals 51a, 52a, and 53a are the same as those of the external device 50 and connection terminals 51, 52, and 53 shown in Figures 8 and 9, respectively.

[0082] Figure 10 also shows a plan view of the semiconductor device 1 in the same region as in Figure 5. Figure 11 shows an enlarged view of the area around the terminal holding portion 12 in a cross-sectional view obtained by cutting the semiconductor device 1 along the line I5-I5 in Figure 10. In Figure 10, the outlines of the capacitor 50a and the connection terminals 51a, 52a, and 53a are shown by thick dashed lines.

[0083] The connection surfaces 41a1, 42a1, and 43a1 of the main terminals 41, 42, and 43 are connected to the lower surfaces of the +X-direction ends of the connection terminals 51a, 52a, and 53a, respectively. At this time, a laser is irradiated from above the area of ​​the upper surface of connection terminal 51a that faces the welding area 41d of connection surface 41a1. As a result, the contact surface with the welding area 41d on the lower surface of connection terminal 51a and the welding area 41d are joined by welding. In addition, a laser is irradiated from above the area of ​​the upper surface of connection terminal 52a that faces the welding area 42d of connection surface 42a1 in the direction of arrow A1. As a result, the contact surface with the welding area 42d on the lower surface of connection terminal 52a and the welding area 42d are joined by welding. Furthermore, a laser is irradiated from above the area of ​​the upper surface of connection terminal 53a that faces the welding area 43d of connection surface 43a1 in the direction of arrow A2. As a result, the contact surface between the lower surface of the connection terminal 53a and the welding area 43d is joined by welding.

[0084] Figure 12 is a cross-sectional view showing the semiconductor device according to the first embodiment with an evaluation device connected to it.

[0085] Figure 12 shows a state in which an evaluation device 50b, which is connected during the evaluation stage, is connected to the semiconductor device 1 according to the first embodiment. Figure 12 shows a cross-sectional view of the semiconductor device 1 and evaluation device 50b when they are cut along the line I6-I6 in Figure 10, assuming that in Figure 11, the evaluation device 50b is connected to the semiconductor device 1 instead of the capacitor 50a.

[0086] The evaluation device 50b is provided with connection terminals 51b, 52b, and 53b that correspond to the aforementioned connection terminals 51, 52, and 53, respectively. Here, the external shape of the connection terminals 51b, 52b, and 53b of the evaluation device 50b is assumed to be the same as the connection terminals 51, 52, and 53 of the external device 50 shown in Figures 8 and 9. However, as will be described later, the shape of the connection terminals 51b, 52b, and 53b of the evaluation device 50b may differ from the connection terminals 51, 52, and 53 of the external device 50 shown in Figures 8 and 9, as long as they can be screwed in while maintaining connection to the connection surfaces 41a1, 42a1, and 43a1 of the main terminals 41, 42, and 43.

[0087] The connection surfaces 41a1, 42a1, and 43a1 of the main terminals 41, 42, and 43 are connected to the lower surfaces of the +X-direction ends of the connection terminals 51b, 52b, and 53b, respectively. In this process, the connection surfaces 41a1, 42a1, and 43a1 and the connection terminals 51b, 52b, and 53b are fastened together with screws. For this reason, each of the connection terminals 51b, 52b, and 53b has a through hole into which a screw is inserted during connection.

[0088] As shown in Figure 12, with the hole 42c of the main terminal 42 and the through hole 52b1 of the connecting terminal 52b aligned, a screw 62 is inserted into the through hole 52b1 and the hole 42c and tightened. This joins the main terminal 42 and the connecting terminal 52b by the screw 62. Although not shown in the figure, with the hole 41c of the main terminal 41 and the through hole of the connecting terminal 51b aligned, a screw is inserted into the through hole and the hole 41c and tightened. This joins the main terminal 41 and the connecting terminal 51b by the screw.

[0089] Furthermore, as shown in Figure 12, with the hole 43c2 of the main terminal 43 and the through hole 53b1 of the connecting terminal 53b aligned, a screw 63 is inserted into the through hole 53b1 and the hole 43c2 and tightened. Also, although not shown in the figure, with the other hole 43c1 of the main terminal 43 and the through hole of the connecting terminal 53b aligned, a screw is inserted into this through hole and the hole 43c2 and tightened. In this way, the main terminal 43 and the connecting terminal 53b are joined by two screws.

[0090] Thus, in the first embodiment, the connection terminals of external devices can be joined to the main terminals 41 to 43 by either laser welding or screw fastening. For example, during the evaluation stage, the connection terminals of the evaluation device 50b can be attached to the main terminals 41 to 43 by screws, making it possible to easily remove the connection terminals of the evaluation device 50b. Furthermore, during the usage stage, the connection terminals of external devices such as capacitors 50a can be firmly joined to the main terminals 41 to 43 by laser welding.

[0091] Furthermore, in the main terminals 41, 42, and 43 described above, the thickness of the external connection portions 41a, 42a, and 43a, where the screw holes 41c, 42c, and 43c (43c1, 43c2) are formed, is greater than that of the other portions. This makes it possible to ensure sufficient depth for the holes 41c, 42c, and 43c (43c1, 43c2) to firmly connect the terminals of external devices.

[0092] One method for manufacturing a flat main terminal that includes a thicker external connection section at one end is to use a mold that matches the shape of the main terminal and perform press working. Another method involves folding back one end of a flat conductive plate. In this method, one end of the conductive plate is folded back by the length of the external connection section (corresponding to the length in the X-axis direction). The folded end becomes a layered conductive plate, making it thicker than the rest of the plate, and this end becomes the external connection section. Alternatively, the end of the conductive plate may be folded back multiple times depending on the required thickness of the external connection section, resulting in a layered structure of three or more layers at the end.

[0093] Next, using Figures 13 and 14, we will describe examples of the arrangement of holes and welding areas in the main terminals 41 to 43.

[0094] Figure 13 is a plan view showing a first example of the arrangement of holes and welding areas in a main terminal. In the example in Figure 13, one hole 41c (first hole) and one welding area 41d (first flat surface) are arranged along the longitudinal direction (Y-axis direction) on the connection surface 41a1 of the main terminal 41. In Figure 13, the length in the longitudinal direction of the connection surface 41a1 is denoted as D1, and the length in the short direction is denoted as D2. For example, D1 = 20 mm and D2 = 10 mm.

[0095] The opening diameter D3 of the hole 41c is set so that sufficient bonding strength can be obtained when the connection terminal of an external device is joined to the connection surface 41a1 by screw fastening. The size of the welding area 41d is also set so that sufficient bonding strength can be obtained when the connection terminal of an external device is joined to the connection surface 41a1 by laser welding. Furthermore, for example, in order to enable a stable joint with sufficiently low contact resistance both when screw fastening and when welding, the contact area between the connection surface 41a1 and the connection terminal of the external device when screwed fastened may be equal to the area of ​​the welding area 41d.

[0096] Figure 14 is a plan view showing a second example of the arrangement of holes and welding areas in the main terminal. In the example in Figure 14, welding areas 41d1 and 41d2 (second and third flat surfaces) are arranged on the connection surface 41a1 of the main terminal 41, flanking the hole 41c (first hole) along the longitudinal direction (Y-axis direction).

[0097] Similar to the case in Figure 13, the opening diameter D3 of the hole 41c is set so that sufficient bonding strength is obtained when the connection terminal of the external device is joined to the connection surface 41a1 by screw fastening. The sizes of the welding areas 41d1 and 41d2 are also set so that sufficient bonding strength is obtained when the connection terminal of the external device is joined to the connection surface 41a1 by laser welding. Furthermore, for example, in order to enable a stable joint with sufficiently low contact resistance both when screw fastening and when welding, the contact area between the connection surface 41a1 and the connection terminal of the external device when screwed fastened may be equal to the total area of ​​the welding areas 41d1 and 41d2.

[0098] Let D4 be the longitudinal width of the welding region 41d in Figure 13. Also, let D4a and D4b be the longitudinal widths of the welding regions 41d1 and 41d2 in Figure 14, respectively. If the longitudinal width of the welding region 41d in the short direction (X-axis direction) is the same as the longitudinal widths of the welding regions 41d1 and 41d2, then for example, D4 ​​= D4a + D4b. In this case, the opening diameter D3 of the hole 41c in Figure 13 may be the same as the opening diameter D3 of the hole 41c in Figure 14.

[0099] Furthermore, the same conditions regarding the diameter of the opening of the hole, the size of the connection surface, the relationship between the contact area and the welding area when screwed in, and the width of the welding area also apply to the main terminals 42 and 43.

[0100] [Second Embodiment] Next, as a second embodiment, a semiconductor device 1 in which a part of the configuration of the first embodiment is modified will be described.

[0101] Figure 15 is an enlarged plan view and a cross-sectional view of a part of the semiconductor device according to the second embodiment. The plan view in Figure 15 shows an enlarged plan view of the vicinity of the terminal holding portion 12 of the semiconductor device 1 according to the second embodiment. The cross-sectional view in Figure 15 shows an enlarged view of the vicinity of the terminal holding portion 12 in the cross-sectional view obtained when the semiconductor device 1 is cut along the line I7-I7 in the plan view.

[0102] In this embodiment, the entire main terminals 41 and 42 have substantially the same thickness. That is, the thickness of the external connection portions 41a and 42a of the main terminals 41 and 42 is the same as the thickness of the portion adjacent to the +X direction side of the external connection portion 41a and 42a.

[0103] Furthermore, on the connection surface 41a1 of the main terminal 41, a hole 41c and a welding area 41d are arranged in the same positions as in the first embodiment when viewed from above. However, the hole 41c penetrates the external connection part 41a. Moreover, no screw threads are cut into the inner wall of the hole 41c. A nut 10c is embedded in the lower member 12g (see Figure 6) of the terminal holding part 12, which contacts the lower surface (first back surface) of the external connection part 41a. The nut 10c is positioned so that its center coincides with the center of the hole 41c, and the upper side of the screw hole in the nut 10c is open to the hole 41c. This allows a screw to be inserted into the screw hole of the nut 10c from above through the hole 41c.

[0104] The lower surface of the connection terminal 51 of the external device 50 (for example, the connection terminal 51b of the evaluation device 50b) is joined to the connection surface 41a1 of the main terminal 41 by a screw. At this time, a screw is inserted from above the connection terminal 51 through the hole in the connection terminal 51 and the hole 41c in the connection surface 41a1 into the screw hole of the nut 10c and tightened. This screw connection makes it possible to easily remove the connection terminal 51 from the main terminal 41.

[0105] Furthermore, the connection surface 42a1 of the main terminal 42 has a hole 42c and a welding area 42d positioned in the same location as in the first embodiment when viewed from above. However, the hole 42c penetrates the external connection part 42a. Moreover, no screw threads are cut into the inner wall of the hole 42c. A nut 10d is embedded in the lower member 12h of the terminal holding part 12, which contacts the lower surface (back surface) of the external connection part 42a. The nut 10d is positioned so that its center coincides with the center of the hole 42c, and the upper side of the screw hole 10d1 of the nut 10d is open to the hole 42c. This allows a screw to be inserted into the screw hole 10d1 of the nut 10d from above through the hole 42c.

[0106] The lower surface of the connection terminal 52 of the external device 50 (for example, the connection terminal 52b of the evaluation device 50b) is joined to the connection surface 42a1 of the main terminal 42 by a screw. At this time, a screw is inserted from above the connection terminal 52 through the hole in the connection terminal 52 and the hole 42c in the connection surface 42a1 into the screw hole 10d1 of the nut 10d and tightened. This screw connection makes it possible to easily remove the connection terminal 52 from the main terminal 42.

[0107] [Third Embodiment] Next, as a third embodiment, a semiconductor device 1 in which a part of the configuration of the first embodiment is modified will be described.

[0108] Figure 16 is an enlarged plan view of a part of the semiconductor device according to the third embodiment. Figure 17 is a side view of the semiconductor device according to the third embodiment. Figure 18 is an enlarged cross-sectional view of a part of the semiconductor device according to the third embodiment.

[0109] Figure 16 shows an enlarged plan view of the semiconductor device 1 according to the third embodiment, showing the area around the terminal holding portion 12. Figure 17 shows a side view of the semiconductor device 1 as seen in the +X direction. Figure 18 shows an enlarged cross-sectional view of the area around the terminal holding portion 12, obtained when the semiconductor device 1 is cut along the lines I8-I8 and I9-I9 in Figure 16, respectively.

[0110] In this embodiment, a hole 41c (second hole) is formed in the connection surface 41a1 of the main terminal 41, but a welding area 41d is not provided. Similar to the first embodiment, the upper side of the hole 41c is open, while the lower side does not penetrate the external connection portion 41a. Furthermore, the hole 41c is formed near the center of the connection surface 41a1 in the longitudinal direction.

[0111] Similarly, in this embodiment, a hole 42c (second hole) is formed in the connection surface 42a1 of the main terminal 42, but a welding area 42d is not provided. Similar to the first embodiment, the upper side of the hole 42c is open, while the lower side does not penetrate the external connection portion 42a. Furthermore, the hole 42c is formed near the center of the connection surface 42a1 in the longitudinal direction.

[0112] Furthermore, in the terminal holding portion 12, the side wall portions 12a, 12b and partition wall portions 12c, 12d formed at the end on the -X direction side extend to the lower end of the terminal holding portion 12.

[0113] Furthermore, the +X-direction ends of the inner wall 12a1 (the side facing the -Y direction) of the side wall portion 12a and the inner wall 12c1 (the side facing the +Y direction) of the partition wall portion 12c are connected to the aforementioned upper side surface 12e1 at the top and to the lower side surface 12f1 at the bottom. The lower side surface 12f1 is a vertical surface facing the -X direction, and its position in the X-axis direction coincides with the upper side surface 12e1. In addition, the lower end of the lower side surface 12f1 reaches the lower end of the terminal holding portion 12.

[0114] With this configuration, a space is formed that is enclosed by the inner wall 12a1 of the side wall portion 12a, the upper side surface 12e1 and the lower side surface 12f1, and the inner wall 12c1 of the partition wall portion 12c, with openings in the vertical and -X directions. Furthermore, the external connection portion 41a of the main terminal 41 protrudes in the -X direction from between the upper side surface 12e1 and the lower side surface 12f1 and is positioned in this space. Therefore, not only the upper surface (connection surface 41a1) but also the lower surface (second back surface) of the external connection portion 41a is exposed from the terminal holding portion 12.

[0115] When the connection terminal 51 of the external device 50 is screwed to the main terminal 41, the upper surface (connection surface 41a1) of the external connection portion 41a and the lower surface of the connection terminal 51 are joined, similar to the first embodiment. On the other hand, when laser welding is performed, the lower surface of the external connection portion 41a and the upper surface of the connection terminal 51 are joined. That is, the lower surface of the external connection portion 41a also functions as a connection surface. In this case, a laser is irradiated from above onto the bottom of the hole portion 41c. Therefore, the area of ​​the lower surface of the external connection portion 41a that faces the bottom of the hole portion 41c becomes the welding area that is welded to the connection terminal 51.

[0116] Furthermore, the +X-direction ends of the inner wall 12b1 (the side facing the +Y direction) of the side wall 12b and the inner wall 12c1 (the side facing the -Y direction) of the partition wall 12d are connected to the upper side 12e2 and to the lower side 12f2. The lower side 12f2 is a vertical surface facing the -X direction, and its position in the X-axis direction coincides with the upper side 12e2. The lower end of the lower side 12f2 also reaches the lower end of the terminal holding portion 12.

[0117] With this configuration, a space is formed that is enclosed by the inner wall 12b1 of the side wall portion 12b, the upper side surface 12e2 and the lower side surface 12f2, and the inner wall 12d1 of the partition wall portion 12d, with openings in the vertical and -X directions. In addition, the external connection portion 42a of the main terminal 42 protrudes in the -X direction from between the upper side surface 12e2 and the lower side surface 12f2 and is positioned in this space. Therefore, not only the upper surface (connection surface 42a1) but also the lower surface of the external connection portion 42a is exposed from the terminal holding portion 12.

[0118] When the connection terminal 52 of the external device 50 is screwed to the main terminal 42, the upper surface (connection surface 42a1) of the external connection portion 42a and the lower surface of the connection terminal 52 are joined, similar to the first embodiment. On the other hand, when laser welding is performed, the lower surface of the external connection portion 42a and the upper surface of the connection terminal 52 are joined. That is, the lower surface of the external connection portion 42a also functions as a connection surface. In this case, a laser is irradiated from above onto the bottom of the hole portion 42c. Therefore, the area of ​​the lower surface of the external connection portion 42a that faces the bottom of the hole portion 42c becomes the welding area 42d that is welded to the connection terminal 52.

[0119] Figure 19 is a cross-sectional view showing an external device connected to a semiconductor device according to the third embodiment.

[0120] The upper and middle sections of Figure 19 show the state in which the evaluation device 50b is attached to the semiconductor device 1 according to the third embodiment by screw fastening. The upper section of Figure 19 shows a cross-sectional view when the semiconductor device 1 in this state is cut along the line I8-I8 in Figure 16, and the middle section shows a cross-sectional view when the semiconductor device 1 in this state is cut along the line I9-I9 in Figure 16.

[0121] As shown in the upper diagram of Figure 19, when joining the connection surface 43a1 of the main terminal 43 to the lower surface of the +X direction end of the connection terminal 53b of the evaluation device 50b, the hole 43c2 of the connection surface 43a1 and the through hole 53b1 of the connection terminal 53b are aligned, and a screw 63 is inserted into the through hole 53b1 and the hole 43c2 and tightened. Although not shown in the diagram, the hole 43c1 of the connection surface 43a1 and the through hole of the connection terminal 53b are aligned, and a screw is inserted into the through hole and the hole 43c1 and tightened.

[0122] Furthermore, as shown in the middle diagram of Figure 19, when joining the connection surface 42a1 of the main terminal 42 to the lower surface of the +X-direction end of the connection terminal 52b of the evaluation device 50b, the hole 42c of the connection surface 42a1 and the through hole 52b1 of the connection terminal 52b are aligned, and a screw 62 is inserted into the through hole 52b1 and the hole 42c and tightened. Also, although not shown in the diagram, when joining the connection surface 41a1 of the main terminal 41 to the lower surface of the +X-direction end of the connection terminal 51b of the evaluation device 50b, the hole 41c of the connection surface 41a1 and the through hole of the connection terminal 51b are aligned, and a screw is inserted into the through hole and the hole 41c and tightened.

[0123] On the other hand, the lower part of Figure 19 shows the state in which the capacitor 50a is joined to the semiconductor device 1 according to the third embodiment by laser welding. The lower part of Figure 19 shows a cross-sectional view when the semiconductor device 1 in this state is cut along the line I9-I9 in Figure 16.

[0124] As shown in this figure, when the main terminal 42 and the connection terminal 52a of the capacitor 50a are joined by laser welding, the lower surface of the external connection portion 42a of the main terminal 42 and the upper surface of the +X direction end of the connection terminal 52a come into contact. In this state, a laser is irradiated from above the hole 42c of the external connection portion 42a to its bottom in the direction of arrow A3. As a result, the welding region 42d on the lower surface of the external connection portion 42a that faces the bottom of the hole 42c and the contact surface on the upper surface of the connection terminal 52a that comes into contact with the welding region 42d are joined by welding.

[0125] Furthermore, although not shown in the diagram, when the main terminal 41 and the connection terminal 51a of the capacitor 50a are joined by laser welding, the lower surface of the external connection portion 41a of the main terminal 41 and the upper surface of the +X direction end of the connection terminal 51a come into contact. In this state, a laser is irradiated from above the hole 41c of the external connection portion 41a to its bottom. As a result, the welding region on the lower surface of the external connection portion 41a facing the bottom of the hole 41c and the contact surface on the upper surface of the connection terminal 51a that comes into contact with the welding region are joined by welding.

[0126] Regarding the connection terminal 53a of the main terminal 43 and the capacitor 50a, similar to the first embodiment, the connection surface 43a1 of the main terminal 43 and the lower surface of the +X direction end of the connection terminal 53a are in contact. In this state, a laser is irradiated from above the portion of the upper surface of the connection terminal 53a that faces the welding region 43d of the connection surface 43a1 of the main terminal 43. As a result, the contact surface with the welding region 43d on the lower surface of the connection terminal 53a and the welding region 43d are joined by welding.

[0127] Thus, in the third embodiment, the connection terminals of an external device can be joined to the main terminals 41 to 43 by either laser welding or screw fastening.

[0128] In this embodiment, as described above, the area of ​​the lower surface of the external connection parts 41a and 42a that faces the bottom of the holes 41c and 42c becomes the welding area that is welded to the connection terminals of the external device. For this reason, the opening diameter of the holes 41c and 42c is set so that the bottom surface area of ​​the holes 41c and 42c is large enough to obtain sufficient bonding strength during laser welding.

[0129] For example, in the third embodiment, the opening diameters of the holes 41c and 42c are set to a larger value than the opening diameters of the holes 41c and 42c in the first embodiment (see Figure 5), which are used only for screw fastening and not for laser welding. Also, in the third embodiment, as shown in Figure 16, the opening diameters of the holes 41c and 42c are set to a larger value than the opening diameters of the holes 43c1 and 43c2 formed in the main terminal 43.

[0130] However, by increasing the number of holes formed in each of the main terminals 41 and 42, the opening diameter of those holes can be made smaller than the holes 41c and 42c in Figure 16.

[0131] Figure 20 is a plan view of a modified example of the semiconductor device according to the third embodiment. The modified example shown in Figure 20 is a modification of part of the configuration of the main terminals 41 and 42 in the third embodiment. Figure 20 shows an enlarged plan view of the vicinity of the terminal holding portion 12 of the semiconductor device 1 according to this modified example.

[0132] In the example shown in Figure 20, two holes 41c1 and 41c2 are formed in the connection surface 41a1 of the main terminal 41. Similar to the hole 41c in Figure 16, the upper side of the holes 41c1 and 41c2 is open, while the lower side does not penetrate the external connection part 41a. Furthermore, by irradiating the bottom of the holes 41c1 and 41c2 from the upper side (+Z direction side), the lower surface of the external connection part 41a and the upper surface of the +X direction end of the connection terminal of the external device are welded together.

[0133] In this configuration, by setting the combined opening area of ​​holes 41c1 and 41c2 to a value greater than or equal to the opening area of ​​hole 41c in Figure 16, the welding area (welding volume) using holes 41c1 and 41c2 can be made equal to or greater than the welding area (welding volume) using hole 41c in Figure 16. Therefore, even if the opening diameters of holes 41c1 and 41c2 are smaller than the opening diameter of hole 41c in Figure 16, it is possible to secure sufficient joining strength by welding between the main terminal 41 and the connection terminal of the external device. Furthermore, by making the combined opening area of ​​holes 41c1 and 41c2 larger than the opening area of ​​hole 41c in Figure 16, or by increasing the number of holes formed on the connection surface 41a1 of the main terminal 41, it is also possible to increase the joining strength by welding between the main terminal 41 and the connection terminal of the external device.

[0134] Furthermore, two holes 42c1 and 42c2 are formed in the connection surface 42a1 of the main terminal 42. Similar to the hole 42c in Figure 16, the upper side of the holes 42c1 and 42c2 is open, while the lower side does not penetrate the external connection part 42a. Also, by irradiating the bottom of the holes 42c1 and 42c2 from the upper side (+Z direction side), the lower surface of the external connection part 42a and the upper surface of the +X direction end of the connection terminal of the external device are welded together.

[0135] In this configuration, by setting the combined opening area of ​​holes 42c1 and 42c2 to a value greater than or equal to the opening area of ​​hole 42c in Figure 16, the welding area (welding volume) using holes 42c1 and 42c2 can be made equal to or greater than the welding area (welding volume) using hole 42c in Figure 16. Therefore, even if the opening diameters of holes 42c1 and 42c2 are smaller than the opening diameter of hole 42c in Figure 16, it is possible to secure sufficient joining strength by welding between the main terminal 42 and the connection terminal of the external device. Furthermore, by making the combined opening area of ​​holes 42c1 and 42c2 larger than the opening area of ​​hole 42c in Figure 16, or by increasing the number of holes formed on the connection surface 42a1 of the main terminal 42, it is also possible to increase the joining strength by welding between the main terminal 42 and the connection terminal of the external device.

[0136] [Fourth Embodiment] Next, as a third embodiment, a semiconductor device 1 in which a part of the configuration of the second embodiment is modified will be described.

[0137] Figure 21 is an enlarged plan view of a part of the semiconductor device according to the fourth embodiment. Figure 22 is an enlarged cross-sectional view of a part of the semiconductor device according to the fourth embodiment. Figure 21 shows an enlarged plan view of the vicinity of the terminal holding portion 12 of the semiconductor device 1 according to the fourth embodiment. Figure 22 shows a cross-sectional view when the semiconductor device 1 is cut along the line I10-I10 in Figure 21.

[0138] In this embodiment, as shown in the comparative example in Figure 9, the entire main terminal 43 (first external connection terminal) is a flat plate of substantially uniform thickness. Furthermore, a hole 43c (first hole) is formed in the center of the connection surface 43a1 (first connection surface) of the main terminal 43 in the longitudinal direction (Y-axis direction), and welding areas 43d1 and 43d2 are arranged on both sides of the hole 43c in the longitudinal direction. The hole 43c penetrates the external connection portion 43a, and screw threads are cut into the inner wall of the hole 43c.

[0139] Furthermore, in this embodiment, as an example, a portion of the lower side of the external connection portion 43a of the main terminal 43 is embedded in the terminal holding portion 12 of the case 10. A hole 10e is formed in the contact surface of the terminal holding portion 12 with the lower surface of the external connection portion 43a, at a position where the central axis coincides with the hole 43c of the main terminal 43. The hole 10e is open at the top and does not penetrate the terminal holding portion 12 at the bottom. The opening diameter of the hole 10e is the same as the opening diameter of the hole 43c, and screw threads are cut into the inner wall of the hole 10e. As a result, the hole 10e and the hole 43c function as a single screw hole.

[0140] The lower surface of the external connection portion 43a may not be embedded in the terminal holding portion 12 of the case 10, but may be in contact with the upper surface 10a of the case 10. In this case, it is sufficient that the above-mentioned hole 10e is formed in the upper surface 10a of the case 10. However, regardless of whether the lower surface of the external connection portion 43a is embedded in the terminal holding portion 12 or not, the height of the bottom of the hole 10e (position in the Z-axis direction) is higher than the height of the main terminals 41 and 42 directly below the hole 10e (position in the Z-axis direction).

[0141] Here, the configuration of the main terminals 41 and 42 and their vicinity will be described. The configuration of the notches of the main terminals 41 and 42 and the connection between them described here is common to the first to fourth embodiments. Therefore, the notches and connection will be explained using Figure 16 in addition to Figures 21 and 22.

[0142] The main terminals 41 and 42 are arranged in parallel in the Y-axis direction. In the cross-sectional area shown in Figure 22, the height of the upper surfaces of the main terminals 41 and 42 is the same, and the height of the lower surfaces of the main terminals 41 and 42 is also the same. Here, in the area of ​​the terminal holding portion 12 of the case 10 shown in Figure 22, the area below the lower surfaces of the main terminals 41 and 42 is represented as the bottom plate portion 12i, and the area between the upper surfaces of the main terminals 41 and 42 and the lower surface of the main terminal 43 is represented as the intermediate portion 12j. The main terminals 41 and 42 and the main terminal 43 are insulated from each other by the intermediate portion 12j.

[0143] Furthermore, as shown in Figure 16, a substantially semicircular first notch 41e is formed at the -Y direction end of the main terminal 41 (second external connection terminal). In addition, a substantially semicircular second notch 42e is formed at the +Y direction end of the main terminal 42 (third external connection terminal) at a position opposite to the first notch 41e.

[0144] A circular gap is formed between the first notch 41e and the second notch 42e in a plan view. This circular gap is provided to align the main terminals 41 and 42 with respect to the mold when manufacturing at least a part of the case 10 (for example, the lower region of the case 10, including the bottom plate portion 12i of the terminal holding portion 12) by injection molding. Furthermore, in the manufactured state of the case 10, a cylindrical connecting portion 12k is formed in the above-mentioned circular gap, connecting the upper surface of the bottom plate portion 12i and the lower surface of the intermediate portion 12j.

[0145] In the fourth embodiment, the hole 43c of the main terminal 43 and the hole 10e of the case 10 are arranged so that their central axes coincide with the central axis of the connecting portion 12k. Furthermore, the opening diameters of the holes 10e and 43c are set to a value less than or equal to the diameter of the connecting portion 12k (less than or equal to the diameter of the circular gap between the first notch 41e and the second notch 42e). Moreover, as described above, the height of the bottom of the hole 10e (position in the Z-axis direction) is higher than the height of the main terminals 41 and 42 directly below the hole 10e (position in the Z-axis direction).

[0146] In this fourth embodiment, when the connection terminal 53 of the external device 50 is joined to the main terminal 43 by screw fastening, the through hole formed in the connection terminal 53 is aligned with the holes 10e and 43c, and a screw is inserted from above into the screw hole formed by the holes 10e and 43c and tightened. At this time, in addition to the hole 43c which has the same depth as the thickness of the external connection portion 43a, a screw is also inserted into the hole 10e formed on the case 10 side (terminal holding portion 12 side). Therefore, even if the thickness of the external connection portion 43a is thinner than in the first to third embodiments, sufficient bonding strength can be obtained between the connection terminal 53 of the external device 50 and the main terminal 43.

[0147] Furthermore, when screwed in, the conductive main terminals 41 and 42 are not located directly below the tip (lower end) of the screw. For this reason, even if the height from the upper surface of the main terminals 41 and 42 to the lower surface of the main terminal 43 in the cross-sectional area shown in Figure 22 is the same as in the first to third embodiments, a sufficient creepage distance can be secured between the tip of the screw and the main terminals 41 and 42, and the insulation between the main terminal 43 and the main terminals 41 and 42 can be maintained.

[0148] In other words, it is possible to make the thickness from the lower surface of the terminal holding portion 12 of the case 10 to the upper surface of the external connection portion 43a of the main terminal 43 thinner than in the first to third embodiments, while maintaining the insulation between the main terminal 43 and the main terminals 41 and 42 when the connection terminal 53 of the external device 50 is joined to the main terminal 43 by screw fastening.

[0149] In this description, we have explained the case in which the semiconductor device 1 according to the third embodiment is provided with a through-hole 43c and a hole 10e on the case 10 side. However, it is also possible to provide the semiconductor device 1 according to the first and second embodiments with a through-hole 43c and a hole 10e on the case 10 side.

[0150] [Fifth Embodiment] Next, as a fifth embodiment, a semiconductor device 1 in which a part of the configuration of the fourth embodiment is modified will be described.

[0151] Figure 23 is an enlarged plan view and cross-sectional view of a part of the semiconductor device according to the fifth embodiment. The plan view in Figure 23 shows an enlarged plan view of the vicinity of the terminal holding portion 12 of the semiconductor device 1 according to the fifth embodiment. The cross-sectional view in Figure 23 shows an enlarged view of the vicinity of the terminal holding portion 12 in the cross-sectional view obtained when the semiconductor device 1 is cut along the line I11-I11 in the plan view.

[0152] As in the third and fourth embodiments described above, if both the upper surface (the surface on the +Z direction) and the lower surface (the surface on the -Z direction) of the external connection portions 41a and 42a of the main terminals 41 and 42 are exposed, the screw holes 41c and 42c may be formed on the lower surface of the external connection portions 41a and 42a. Furthermore, the cross-sectional shape of the external connection portions 41a and 42a may be such that they protrude downward (on the -Z direction) rather than upward (on the +Z direction) from the area of ​​the main terminals 41 and 42 other than the external connection portions 41a and 42a. The fifth embodiment illustrates a case in which the main terminals 41 and 42 of the semiconductor device 1 according to the fourth embodiment are changed to main terminals 41 and 42 of such shape.

[0153] In this embodiment, the upper surfaces of the external connection parts 41a and 42a are flat, and laser welding forms connection surfaces 41a1 and 42a1 to which the lower surfaces of the +X-direction ends of the connection terminals 51 and 52 of the external device 50 are connected. The lower surfaces of the external connection parts 41a and 42a form lower connection surfaces to which the lower surfaces of the +X-direction ends of the connection terminals 51 and 52 of the external device 50 are connected by screws. The cross-sectional view in Figure 23 shows the lower connection surface 42a3 of the external connection part 42a. The lower connection surface 42a3 of the external connection part 42a has a hole 42c formed therein that is open at the bottom and not penetrated at the top. The lower connection surface of the external connection part 41a has a hole 41c formed therein that is open at the bottom and not penetrated at the top. Screw threads are cut into the inner walls of these holes 41c and 42c.

[0154] When the connection terminal 52 of the external device 50 is screwed to the main terminal 42, the lower connection surface 42a3 of the external connection portion 42a and the upper surface of the connection terminal 52 are joined by the screw inserted into the hole 42c. Similarly, when the connection terminal 51 of the external device 50 is screwed to the main terminal 41, the lower connection surface of the external connection portion 41a and the upper surface of the connection terminal 51 are joined by the screw inserted into the hole 41c.

[0155] On the other hand, when laser welding is performed, the upper connection surface 42a1 of the external connection portion 42a and the lower surface of the connection terminal 52 are joined. At this time, the laser is irradiated from below onto the bottom (upper end) of the hole 42c, so the area of ​​the connection surface 42a1 of the external connection portion 42a that faces the bottom of the hole 42c becomes the welding area 42d that is welded with the connection terminal 52. Similarly, the upper connection surface 41a1 of the external connection portion 41a and the lower surface of the connection terminal 51 are joined by laser welding. At this time, the laser is irradiated from below onto the bottom (upper end) of the hole 41c, so the area of ​​the connection surface 41a1 of the external connection portion 41a that faces the bottom of the hole 41c becomes the welding area that is welded with the connection terminal 51.

[0156] Figure 24 is a cross-sectional view showing a semiconductor device according to the fifth embodiment with a capacitor connected. This Figure 24 shows a state in which a capacitor 50a is joined to the semiconductor device 1 according to the fifth embodiment by laser welding. Figure 24 shows a cross-sectional view when the semiconductor device 1 in this state is cut along the line I11-I11 in the plan view of Figure 23.

[0157] As shown in Figure 24, when the main terminal 42 and the connection terminal 52a of the capacitor 50a are joined by laser welding, the upper surface (connection surface 42a1) of the external connection portion 42a of the main terminal 42 and the lower surface of the +X direction end of the connection terminal 52 come into contact. In this state, a laser is irradiated from below the hole 42c of the external connection portion 42a to its bottom (upper end) in the direction of arrow A4. As a result, the welding region 42d of the connection surface 42a1 of the external connection portion 42a that faces the bottom of the hole 42c and the contact surface of the lower surface of the connection terminal 52a that comes into contact with the welding region 42d are joined by welding.

[0158] Furthermore, although not shown in the figures, when the main terminal 41 and the connection terminal 51a of the capacitor 50a are joined by laser welding, the upper surface (connection surface 41a1) of the external connection portion 41a of the main terminal 41 and the lower surface of the +X direction end of the connection terminal 51 come into contact. In this state, a laser is irradiated from below the hole 41c of the external connection portion 41a to its bottom (upper end). As a result, the welding region of the connection surface 41a1 of the external connection portion 41a facing the bottom of the hole 41c and the contact surface of the lower surface of the connection terminal 51a that comes into contact with the welding region are joined by welding.

[0159] In the fifth embodiment described above, the connection terminals of an external device can be joined to the main terminals 41 to 43 by either laser welding or screw fastening.

[0160] Furthermore, with the semiconductor device 1 configured as shown in Figures 23 and 24, the height of the connection surfaces 41a1 and 42a1 of the main terminals 41 and 42 from the bottom surface of the case 10 can be made the same as the height of the connection surfaces 41a1 and 42a1 in the comparative example shown in Figure 9. Also, the height of the connection surface 43a1 of the main terminal 43 from the bottom surface of the case 10 can be made the same as the height of the connection surface 43a1 in the comparative example shown in Figure 9. For this reason, the existing external device 50 used in the comparative example can be used as the external device 50 (e.g., capacitor 50a) to be connected during use.

[0161] The above merely illustrates the principle of the present invention. Furthermore, numerous modifications and changes are possible for those skilled in the art, and the present invention is not limited to the exact configurations and applications shown and described above, and all corresponding modifications and equivalents are considered to be within the scope of the present invention as defined by the appended claims and equivalents.

[0162] 1 Semiconductor device 10 Case 10a Top surface 10b Sealing member 10c, 10d Nut 10d1 Screw hole 10e Hole 11 Storage section 11a-11d Side wall section 11e Storage area 11f Opening 11g1, 11g2 Edge section 12, 13 Terminal holding section 12a, 12b Side wall section 12a1, 12b1, 12c1, 12d1 Inner wall 12c, 12d Partition section 12e1, 12e2 Upper side section 12f1, 12f2 Lower side section 12g, 12h Lower member 12i Bottom plate section 12j Middle section 12k Connection section 14a-14j External connection terminal 20 Wiring board 30 Insulating board 31a-31e Semiconductor chip 32 Insulating plates 33a-33g Circuit patterns 41-43 Main terminals 41a, 42a, 43a, 44a External connection parts 41a1, 42a1, 43a1 Connection surfaces 41b, 42b, 43b, 44b Internal connection parts 41c, 41c1, 41c2, 42c, 42c1, 42c2, 43c, 43c1, 43c2 Holes 41d, 41d1, 41d2, 42d, 43d, 43d1, 43d2 Welding area 41e First notch 42a3 Lower connection surface 42e Second notch 44 Output terminal 50 External device 50a Capacitor 50b Evaluation device 51-53, 51a, 51b, 52a, 52b, 53a, 53b Connection terminals 52b1, 53b1; Through holes 62, 63; Screws A1-A4; Arrows D1, D2; Length D3; Opening diameter D4, D4a, D4b; Width G1-G4; Gate terminals Q1-Q4; Transistors S1-S4; Auxiliary source terminals

Claims

1. A semiconductor device comprising: a case formed of an insulating material; and a first external connection terminal having a flat, rectangular first connection surface exposed above the case, with at least a portion of it embedded inside the case, wherein the first connection surface includes a first hole and a first weldable region positioned longitudinally on the first connection surface relative to the first hole, on which the lower surface of the flat first connection terminal can be welded.

2. The semiconductor device according to claim 1, wherein a screw thread is cut into the inner wall of the first hole.

3. The semiconductor device according to claim 1, wherein the lower end of the first hole is not a through-hole.

4. The semiconductor device according to claim 1, wherein the first hole penetrates the first external connection terminal, the case includes a member that contacts the first back surface opposite to the first connection surface of the first external connection terminal, and a nut is embedded in the first back surface side of the member, the center of which coincides with the center of the first hole.

5. The semiconductor device according to claim 1, wherein the first connection surface further includes a second weldable region along the longitudinal direction of the first connection surface, at a position on either side of the first hole, to which the lower surface of the first connection terminal can be welded.

6. The semiconductor device according to claim 1, further comprising a second external connection terminal positioned below the first external connection terminal, insulated from the first external connection terminal by a part of the case, wherein the second external connection terminal is offset from the first connection surface along the short-side direction of the first connection surface and has a rectangular second connection surface in plan view that is exposed upward from the case, and at least a part of it is embedded inside the case.

7. The semiconductor device according to claim 6, wherein, in a plan view, the second connection surface and the second back surface opposite the second connection surface of the second external connection terminal protrude from the side of the case, the second connection surface and the second back surface are exposed from the case, and the second external connection terminal includes a cylindrical second hole portion, one of which is open and the other is not through.

8. The semiconductor device according to claim 7, wherein the opening diameter of the second hole is larger than the opening diameter of the first hole.

9. The semiconductor device according to claim 7, wherein the second external connection terminal includes an opening for the second hole on one of the second connection surface or the second back surface, and includes a third weldable region on the other surface at a position opposite to the opening, on which a flat plate-shaped second connection terminal can be welded.

10. The semiconductor device according to claim 8, wherein the second external connection terminal includes a plurality of second holes having the same opening diameter as the first hole.

11. The semiconductor device according to claim 10, wherein the second holes are arranged in parallel along the longitudinal direction of the second connecting surface.

12. The case further comprises a third external connection terminal located on the first back surface, which is the opposite side of the first connection surface of the first external connection terminal, and adjacent to the second connection surface of the second external connection terminal along the longitudinal direction, the third external connection terminal being insulated from the first and second external connection terminals by a part of the case, the third external connection terminal being offset from the first connection surface along the short direction of the first connection surface, having a rectangular third connection surface in plan view that is exposed upward from the case, and at least a part of it being embedded inside the case, a first notch formed at the end of the second external connection terminal facing the third external connection terminal, a second notch formed at a position opposite to the first notch at the end of the third external connection terminal facing the second external connection terminal, the first hole passing through the first external connection terminal, and the case having a bottom plate portion that contacts the second back surface opposite to the second connection surface of the second external connection terminal and the third back surface opposite to the third connection surface of the third external connection terminal, A semiconductor device according to claim 7, comprising: an intermediate portion whose upper surface contacts the first back surface of the first external connection terminal and whose lower surface contacts the second external connection terminal and the third external connection terminal; a connecting portion that connects the upper surface of the bottom plate portion and the lower surface of the intermediate portion in a region corresponding to the first notch portion and the second notch portion in a plan view; and a screw hole that opens on the upper side of the intermediate portion, is not penetrating on the lower side, and whose center coincides with the center of the first hole portion.

13. A semiconductor device comprising: a case formed of an insulating material; and an external connection terminal having an external connection portion projecting from the side surface of the case in a first direction, with a flat, rectangular upper and lower surface exposed from the case, at the end in the first direction, and at least a portion of which is embedded inside the case, wherein the external connection portion includes a cylindrical hole that is open on one side of the upper or lower surface and is not through on the other side.

14. The semiconductor device according to claim 13, wherein the holes are arranged in parallel in a plurality along the longitudinal direction of the external connection portion.

Images