Semiconductor device and method of manufacturing semiconductor device

Abstract

This semiconductor device comprises: a semiconductor chip; a wiring board on which a semiconductor chip is mounted and on the rear surface side of which an external connection terminal for performing electrical connection with the outside is formed, the rear surface being opposite to the front surface on which the semiconductor chip is mounted; and a lid part which is bonded to the semiconductor chip by an adhesive member formed on an outer edge part of the semiconductor chip and covers the semiconductor chip. A part of the adhesive member protrudes outward beyond the outer edge end of the semiconductor chip.

Description

Semiconductor device and method for manufacturing the same

[0001] The present technology relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a semiconductor chip, a wiring board on which an external connection terminal for making an electrical connection with the outside is formed on a back surface side which is a surface opposite to a surface on which the semiconductor chip is mounted, and a lid portion covering the semiconductor chip, and a method for manufacturing the same.

[0002] For example, in a semiconductor device such as an image sensor, there is a type in which a semiconductor chip is mounted on a wiring board, and a lid portion is adhered to the semiconductor chip by an adhesive material applied to an outer edge portion of the semiconductor chip, and the lid portion covers the semiconductor chip. The wiring board is a portion where wirings for enabling signal exchange between the semiconductor chip and an external device are formed. For example, the semiconductor chip is wire-bonded to terminals formed on the surface of the wiring board, that is, the surface on which the semiconductor chip is mounted, and is electrically connected to the wiring board. In a semiconductor device such as an image sensor, electrical elements such as light-receiving elements are formed on the surface of the semiconductor chip, and the formation region of the electrical elements in the semiconductor chip is sealed by adhering the lid portion by the adhesive material applied to the outer edge portion of the semiconductor chip as described above.

[0003] Further, in the semiconductor device of the above type, a portion outside the structure formed by the semiconductor chip, an adhesive member (a member formed of the above adhesive material), and the lid portion on the wiring board is sealed with a sealing material.

[0004] Note that the following Patent Document 1 can be cited as a related prior art. Patent Document 1 discloses a technique for applying a sealing material in two steps with respect to a technique for sealing a portion outside the structure formed by the semiconductor chip, the adhesive member, and the lid portion as described above.

[0005] Japanese Unexamined Patent Application Publication No. 2015-19031

[0006] In semiconductor devices of the type described above, where a semiconductor chip mounted on a wiring board is covered by a lid, miniaturization of the semiconductor chip is desirable. By miniaturizing the semiconductor chip, it is possible to increase the number of semiconductor chips that can be extracted from the wafer, that is, to improve the theoretical yield.

[0007] This technology was developed in view of the above circumstances, and aims to miniaturize semiconductor chips in semiconductor devices in which semiconductor chips mounted on a wiring board are covered by a lid.

[0008] The semiconductor device according to this technology comprises a semiconductor chip, a wiring board on which the semiconductor chip is mounted and on which external connection terminals for electrical connection to the outside are formed on the back side, which is the side opposite to the front side on which the semiconductor chip is mounted, and a cover portion that is bonded to the semiconductor chip by an adhesive member formed on the outer edge of the semiconductor chip and covers the semiconductor chip, wherein a part of the adhesive member protrudes outward from the outer edge of the semiconductor chip. As described above, by having a part of the adhesive member protrude outward from the outer edge of the semiconductor chip, the area of ​​the adhesive member that needs to be applied to the outer edge of the semiconductor chip can be reduced.

[0009] A method for manufacturing a semiconductor device according to this technology comprises a semiconductor chip, a wiring substrate on which the semiconductor chip is mounted and on which external connection terminals for electrical connection to the outside are formed on the back side, which is the side opposite to the front side on which the semiconductor chip is mounted, and a cover portion that is bonded to the semiconductor chip by an adhesive member formed on the outer edge of the semiconductor chip and covers the semiconductor chip, wherein the method for manufacturing a semiconductor device comprises at least a step of applying an adhesive material for forming the adhesive member so as to extend beyond the outer edge of the semiconductor chip. By such a manufacturing method, it is possible to manufacture the semiconductor device according to this technology described above.

[0010] This is a schematic longitudinal cross-sectional view of a semiconductor device as a prior example. This is an explanatory diagram of an example of a semiconductor device manufacturing method as a prior example. This is also an explanatory diagram of an example of a semiconductor device manufacturing method as a prior example. This is an enlarged view of region P1 in Figure 1. This is a schematic longitudinal cross-sectional view of a semiconductor device as an embodiment of the present technology. This is a schematic plan view of a semiconductor device as an embodiment. This is an enlarged view of region P2 in Figure 5. This is an explanatory diagram of an example of a semiconductor device manufacturing method as an embodiment. This is also an explanatory diagram of an example of a semiconductor device manufacturing method as an embodiment. This is a diagram showing the results of calculations on how much the semiconductor chip can be miniaturized compared to the prior example. This is an explanatory diagram of an example of material load improvement. This is an explanatory diagram of the filler sedimentation phenomenon in the sealing portion. This is an explanatory diagram of an example of the thickness of the filler sparse portion in the prior example. This is an explanatory diagram of an example of the thickness of the filler sparse portion in the embodiment. This is an explanatory diagram of the problems associated with substrate warping.

[0011] The embodiments will be described below in the following order: <1. Semiconductor device as a prior example> (1-1. Example of semiconductor device configuration) (1-2. Example of semiconductor device manufacturing method) (1-3. Problems with the prior example) <2. Semiconductor device as an embodiment> (2-1. Example of semiconductor device configuration) (2-2. Example of semiconductor device manufacturing method) (2-3. Effects) <3. Modified examples> <4. Summary of embodiments> <5. This technology>

[0012] <1. Semiconductor Devices as Prior Examples> (1-1. Example of Semiconductor Device Configuration) The semiconductor device 1 as an embodiment is configured as a semiconductor device of the type in which a semiconductor chip mounted on a wiring board is covered by a lid, as described above. First, we will explain a prior example of this type of semiconductor device.

[0013] Figure 1 is a schematic longitudinal cross-sectional view of a semiconductor device 100 as a prior example. Here, the longitudinal direction is the direction parallel to the thickness direction of the semiconductor chip 2 provided on the semiconductor device 100. In this example, the semiconductor device 100 is shown as an image sensor (solid-state image sensor) such as a CMOS (Complementary Metal Oxide Semiconductor) type or a CCD (Charge Coupled Device) type.

[0014] As shown in the figure, the semiconductor device 100 as a prior example comprises a semiconductor chip 2, a wiring substrate 3, a lid portion 4, a bonding layer 5, an adhesive member 6, a sealing portion 7, and a solder ball B. The semiconductor device 100 has a hollow package structure in which the semiconductor chip 2 is mounted on the wiring substrate 3, and the lid portion 4 is mounted on the semiconductor chip 2 via the adhesive member 6, forming a cavity C between the semiconductor chip 2 and the lid portion 4. On the wiring substrate 3, the sides of the hollow structure having such a cavity C, that is, the structure formed by the semiconductor chip 2, the adhesive member 6, and the lid portion 4, are sealed by the sealing portion 7.

[0015] The semiconductor chip 2 is constructed including a semiconductor substrate made of a semiconductor such as silicon (Si), and various electrical elements such as photodetectors such as photodiodes and transistors are formed on this semiconductor substrate. Specifically, on the surface 2a side of the semiconductor chip 2, multiple pixels 21 having photodetectors, optical filters such as color filters, and microlenses are arranged in two dimensions. Here, the surface 2a of the semiconductor chip 2 is the surface facing the lid 4. On the semiconductor chip 2, the surface opposite to the surface 2a is the back surface 2b. The semiconductor chip 2 in this example has a rectangular shape when viewed from above.

[0016] On the surface 2a side of the semiconductor chip 2, the region in which multiple pixels 21 are arranged in two dimensions is defined as the pixel formation region 22. The pixel formation region 22 is defined as a rectangular region in plan view, and in this example, the center of the pixel formation region 22 coincides with the center of the semiconductor chip 2.

[0017] The semiconductor chip 2 has a readout circuit (not shown) that reads out the light-receiving signals obtained from each pixel 21, and is configured to obtain a signal indicating the amount of light received by each pixel 21, i.e., an image capture signal. Furthermore, the semiconductor chip 2 in this example has an ADC (Analog to Digital Converter) that digitally samples the image capture signal as an analog signal, thereby enabling the acquisition of the image capture as digital data.

[0018] Multiple terminals for electrical connection with the wiring board 3 are formed on the surface 2a side of the semiconductor chip 2. Specifically, these are the chip-side pads pc shown in the figure. These chip-side pads pc are formed on the outer edge of the semiconductor chip 2. Specifically, in the semiconductor chip 2 of this example, the chip-side pads pc are formed on each of the four sides so as to follow the rectangular outer shape of the semiconductor chip 2.

[0019] The semiconductor chip 2 is mounted on the front surface 3a of the wiring board 3. Here, the side of the wiring board 3 opposite to the front surface 3a is the back surface 3b. In this example, the wiring board 3, like the semiconductor chip 2, has a rectangular shape when viewed from above.

[0020] The wiring board 3 is a circuit board constructed as an organic substrate using an organic material such as plastic as the base material, and having a predetermined circuit pattern formed by a metal material. The wiring board 3 may also be other types of substrates, such as a ceramic substrate formed from a ceramic material.

[0021] Multiple terminals, specifically substrate-side pads pw, are formed on the surface 3a of the wiring board 3 for electrical connection with the semiconductor chip 2. Similar to the chip-side pads pc described above, these substrate-side pads pw are also formed on each of the four sides of the wiring board 3.

[0022] The semiconductor chip 2 has its back surface 2b bonded (adhered) to the front surface 3a of the wiring substrate 3 by a chip adhesive material such as die bond, and a bonding layer 5 made of the chip adhesive material is formed between the semiconductor chip 2 and the wiring substrate 3.

[0023] The semiconductor chip 2 is wire-bonded to the wiring board 3 by bonding wires W. Specifically, each chip-side pad pc on the semiconductor chip 2 and the corresponding board-side pad pw on the wiring board 3 are electrically connected via bonding wires W.

[0024] Multiple external connection terminals are formed on the back surface 3b of the wiring board 3 for electrical connection between the semiconductor device 100 and external devices. In this example, these external connection terminals are formed by pads pb formed on the back surface 3b of the wiring board 3 and solder balls B formed on pads pd. The solder balls B are arranged in a two-dimensional grid pattern along the rectangular outline of the wiring board 3, for example, to form a BGA (Ball Grid Array).

[0025] The adhesive member 6 is interposed between the semiconductor chip 2 and the lid 4, and by bonding them together while keeping them separated from each other, it forms a sealed space, the cavity C, between the semiconductor chip 2 and the lid 4. The adhesive member 6 is provided on the outer edge of the semiconductor chip 2 so as to surround the pixel formation region 22 on the surface 2a of the semiconductor chip 2. Specifically, the adhesive member 6 is provided around the entire circumference along the planar outline of the semiconductor chip 2 and the lid 4, and is formed in an endless manner so as to form a rectangular frame in plan view. Together with the lid 4, such an adhesive member 6 functions as a sealing part that hermetically seals the pixel formation region 22. Specifically, it blocks the intrusion of moisture (water vapor) and dust from the outside into the pixel formation region 22.

[0026] The adhesive member 6 is formed of an insulating material. Specifically, the material used to form the adhesive member 6 (adhesive material) could be, for example, a photosensitive adhesive such as a UV (ultraviolet) curable resin, such as an acrylic resin, a thermosetting resin such as an epoxy resin, or a mixture thereof.

[0027] Furthermore, the adhesive member 6 is formed from a light-shielding material. Specifically, in this example, the adhesive member 6 is made of black resin. In this case, the material for the adhesive member 6 could be a resin material containing a black pigment such as carbon black or titanium black. The light-shielding properties of the adhesive member 6 prevent light incident through the light-transmitting lid 4 from being diffusely reflected within the cavity C. In particular, in a semiconductor device 100 configured as an image sensor as in this example, flare can be suppressed.

[0028] The adhesive member 6 is formed on the semiconductor chip 2 in a position that covers the chip-side pad pc. Thus, the adhesive member 6 also functions as a protective member between the chip-side pad pc and the end of the bonding wire W on the semiconductor chip 2 side.

[0029] The lid portion 4 is a roughly rectangular plate shape and, together with the adhesive member 6, covers the surface 2a of the semiconductor chip 2 via the cavity C, sealing the pixel formation region 22. Here, the cavity C may be sealed in an atmospheric environment, but it is preferable that it be filled with dry air or nitrogen and then sealed by the lid portion 4, or that it be sealed by the lid portion 4 under vacuum (i.e., vacuum sealed).

[0030] In the semiconductor device 100 of this example, which is an image sensor, the cover portion 4 is made of a transparent material, thereby enabling light to be guided from outside the semiconductor device 100 to the pixel formation area 22. Specifically, the cover portion 4 in this example is made of a glass plate.

[0031] The sealing portion 7 is formed, for example, from a resin material and seals the portion on the wiring board 3 that is outside the structure formed by the semiconductor chip 2, the adhesive member 6, and the lid portion 4. In this example, the sealing portion 7 functions as a resin portion that covers the bonding wire W and the substrate-side pad pw on the wiring board 3 to which the bonding wire W is connected. The sealing portion 7 covers and seals the entire perimeter of the above-mentioned structure (semiconductor chip 2, adhesive member 6, and lid portion 4). In this example, the sealing portion 7 is formed by applying a resin material around the above-mentioned structure on the wiring board 3 and then curing it.

[0032] For the material of the sealing portion 7, for example, a thermosetting resin mainly composed of silicon oxide or containing fillers such as alumina may be used. As the resin material for forming the sealing portion 7, for example, thermosetting resins such as phenolic resins, silicone resins, acrylic resins, epoxy resins, urethane resins, silicon resins, and polyetheramide resins, thermoplastic resins such as polyamide-imide, polypropylene, and liquid crystal polymers, photosensitive resins such as UV-curable acrylic resins, rubber, and other known resin materials may be used alone or in combination of several.

[0033] The sealing portion 7 is insulating. In this example, the sealing portion 7 is made of a light-shielding material, specifically a black resin. In this case, the material for the sealing portion 7 could be a resin material containing a black pigment such as carbon black or titanium black.

[0034] In the semiconductor device 100 configured as described above, light transmitted through the lid 4 passes through the cavity C and is received by each pixel 21 arranged in the pixel formation region 22 of the semiconductor chip 2. As a result, image data is obtained in the semiconductor device 100.

[0035] (1-2. Example of a semiconductor device manufacturing method) Figures 2 and 3 are explanatory diagrams of an example of a semiconductor device manufacturing method 100. In the manufacturing method of the semiconductor device 100, first, a step is taken to prepare a substrate member 3' which will become the wiring board 3 (see Figure 2A). The substrate member 3' is formed as a substrate member in which multiple portions that will become the wiring board 3, on which substrate-side pads pw and pads pb are formed, are connected in two dimensions.

[0036] In this substrate member 3', a process is carried out to bond semiconductor chips 2 to each section corresponding to one wiring board 3 by die bonding (see Figure 2B). In this process, the semiconductor chips 2 are bonded to predetermined mounting positions on the surface 3a of the substrate member 3' by a die bonding material such as an insulating or conductive resin paste that forms a bonding layer 5.

[0037] Next, a wire bonding process is performed to electrically (and physically) connect the semiconductor chip 2 and the substrate member 3' (see Figure 2C). In this process, wire bonding is performed to electrically connect the substrate-side pad pw on the substrate member 3' and the chip-side pad pc on the semiconductor chip 2 using bonding wires W.

[0038] Next, a step is taken to attach the lid portion 4 to the semiconductor chip 2 via an adhesive member 6 (see Figure 2D). Specifically, first, an adhesive material 6', which is a resin material that will become the adhesive member 6, is applied to the outer edge of the surface 2a of the semiconductor chip 2 using a dispenser or the like. This application of the adhesive material 6' is done in a rectangular frame shape along the planar outline of the semiconductor chip 2. Then, the lid portion 4 is placed on the adhesive material 6' and the adhesive material 6' is cured. For example, if the adhesive material 6' is thermosetting, a heating step (curing) is performed to cure the adhesive material 6' with the lid portion 4 mounted on the semiconductor chip 2 via the adhesive material 6'. As the adhesive material 6' hardens, the lid portion 4 is fixed to the semiconductor chip 2 via the adhesive member 6 formed by the adhesive material 6', and a sealed space, the cavity C, is formed.

[0039] Next, a dam D is formed on the surface 3a of the substrate member 3' (see Figure 2E), and then a sealing portion 7 is formed (see Figure 2F). In this example, the sealing portion 7 is formed in units of a predetermined number of wiring boards 3, such as one line of the substrate member 3'. Therefore, the dam D is formed to surround the area of ​​the wiring board 3 for that predetermined number of units.

[0040] In the process shown in Figure 2F, the sealing material 7' that will form the sealing portion 7 is applied to the area enclosed by the dam D. As can be understood from the above explanation, the sealing material 7' is a thermosetting resin containing a filler or a UV-curing resin. The application process of the sealing material 7' is carried out so that the sealing material 7' is filled in the area around the structure formed by the semiconductor chip 2, adhesive member 6 and lid portion 4 on the substrate member 3'. In this example, the filling of the sealing material 7' is performed by potting using a dispenser.

[0041] Also, in the process of FIG. 2F, after the sealing material 7' is filled, a predetermined treatment such as heating or UV irradiation is performed on the sealing material 7', and the sealing material 7' is cured. Thereby, a resin portion as the sealing portion 7 is formed.

[0042] After the process of FIG. 2F, a process of forming solder balls B shown in FIG. 3A is performed. Specifically, it is a process of providing solder balls B on each pad pb formed on the back surface 3b side of the substrate member 3'. Here, a ball mounting and reflow process of arranging and fixing solder on each of a plurality of pads pb arranged and formed in a grid pattern on the back surface 3b side of the substrate member 3' is performed. By performing this process of forming the solder balls B, an aggregate of a plurality of semiconductor devices 100 is obtained.

[0043] Next, by a dicing process (see FIG. 3B), each semiconductor device 100 is separated from the above aggregate (see FIG. 3C). In the dicing process, a portion of each semiconductor device 100 is cut out from the above aggregate using a blade.

[0044] Through the manufacturing process as described above, a semiconductor device 100 having the structure shown in FIG. 1 is manufactured.

[0045] (1-3. Problems of the prior example) Here, in the semiconductor device 100 as the prior example described above, as described in the process from FIG. 2D to FIG. 2F, first, the lid portion 4 is adhered onto the semiconductor chip 2 via the adhesive member 6, and then a manufacturing method of forming the sealing portion 7 around the structure formed by the semiconductor chip 2, the adhesive member 6, and the lid portion 4 on the substrate member 3' (wiring board 3) is adopted.

[0046] FIG. 4 is an enlarged view of the region P1 shown in FIG. 1. By adopting the manufacturing method as described above, in the semiconductor device 100 as the prior example, it is necessary to form an adhesive member 6 having a width necessary for adhering the semiconductor chip 2 and the lid portion 4 on the semiconductor chip 2. Therefore, it is necessary to secure a space for arranging the adhesive member 6 having the necessary width, as shown by "Me" in the figure, between the outer end of the pixel formation region 22 and the outer edge end of the semiconductor chip 2. As a result, it has been difficult to miniaturize the semiconductor chip 2.

[0047] <2. Semiconductor Device as an Embodiment> (2-1. Configuration Example of Semiconductor Device) In this embodiment, in order to solve the problems in the above prior examples, a semiconductor device 1 having a structure as shown in FIG. 5 is proposed. In the following description, the same parts as those already described will be denoted by the same reference numerals and the description thereof will be omitted.

[0048] In the semiconductor device 1, the difference from the semiconductor device 100 is that a part of the adhesive member 6 protrudes outside the outer edge of the semiconductor chip 2.

[0049] In the semiconductor device 1, instead of the sealing portion 7, a sealing portion 8 is formed. The sealing portion 8, similar to the sealing portion 7, is a member that seals the portion outside the structure formed by the semiconductor chip 2, the adhesive member 6, and the lid portion 4 on the wiring substrate 3 (that is, covers the substrate-side pad pw and the bonding wire W), but the difference from the sealing portion 7 is that it has a first sealing portion 8a that surrounds the side portion of the semiconductor chip 2 on the wiring substrate 3, and a second sealing portion 8b that covers the side portions of the adhesive member 6 and the lid portion 4 on the first sealing portion 8a.

[0050] As will be described later, the first sealing portion 8a is a portion formed to surround the side portion of the semiconductor chip 2 before forming the adhesive member 6 on the semiconductor chip 2. For this reason, it is possible to form the adhesive member 6 so as to protrude outside the outer edge of the semiconductor chip 2 as described above.

[0051] The second sealing portion 8b is formed on the first sealing portion 8a after the lid portion 4 is adhered via the adhesive member 6 that protrudes from the outer edge of the semiconductor chip 2 onto the first sealing portion 8a as described above.

[0052] Here, as with the sealing portion 7, it is conceivable to use a thermosetting resin or a UV-curable resin for the sealing portion 8 (the first sealing portion 8a and the second sealing portion 8b). Also, it is conceivable to configure the sealing portion 8 with a material having insulating and light-shielding properties.

[0053] For reference, Figure 6 shows a schematic plan view of the semiconductor device 1. Similar to the semiconductor device 100, the wiring board 3, semiconductor chip 2, and cover 4 of the semiconductor device 1 are each rectangular in plan view. Accordingly, the sealing portion 8 and adhesive member 6 are also formed in a rectangular frame shape in plan view, as shown in the figure. The external dimensions of the semiconductor device 1 in plan view are, for example, 6 mm to 10 mm on each side.

[0054] Figure 7 is an enlarged view of region P2 in Figure 5. As described above, by forming a part of the adhesive member 6 that extends beyond the outer edge of the semiconductor chip 2, the size of the semiconductor chip 2 can be reduced by the length Os of the protruding portion of the adhesive member 6. In other words, in the prior example, the length of the space that needed to be secured from the outer edge of the pixel formation region 22 to the outer edge of the semiconductor chip 2 was "Me", whereas in the semiconductor device 1 of this embodiment, this length can be reduced to "Me-Os", thereby miniaturizing the semiconductor chip 2.

[0055] In the semiconductor device 1, the adhesive member 6 also serves as a spacer to prevent the lid portion 4 from coming into contact with the pixel formation area 22 or the bonding wire W. In this example, the top height of the bonding wire W is approximately 100 μm, and considering variations, it is desirable that the thickness of the adhesive member 6 be approximately 150 μm. Furthermore, it is desirable to use an adhesive material 6', which is the material of the adhesive member 6, that has a high thixotropy ratio.

[0056] (2-2. Example of a Method for Manufacturing a Semiconductor Device) Figures 8 and 9 are explanatory diagrams of an example of a method for manufacturing a semiconductor device 1. First, the steps in Figures 8A to 8C are the same as the steps in Figures 2A to 2C in the method for manufacturing a semiconductor device 100, so redundant explanation will be avoided.

[0057] In the manufacturing method of the semiconductor device 1, the dam formation process shown in Figure 8D is performed upon completion of the wire bonding process shown in Figure 8C. In this case as well, the method for forming the dam D is the same as in the prior example, so redundant explanation will be avoided.

[0058] As the next step after Figure 8D, the first sealing portion 8a is formed, as shown in Figure 8E. Specifically, the first sealing material 8a', which is the material for forming the first sealing portion 8a, such as a thermosetting resin or a UV-curable resin, is applied to the area around the semiconductor chip 2 on the substrate member 3', and the first sealing material 8a' is cured by heat treatment or UV irradiation treatment. At this time, the first sealing material 8a' is applied so that its position (height) in the thickness direction of the semiconductor device 1 coincides with the surface 2a of the semiconductor chip 2. The application of the first sealing material 8a' can be carried out by potting using a dispenser.

[0059] As described above, the first sealing material 8a' is cured to form the first sealing portion 8a, and then the bonding process for the lid portion 4 shown in Figure 8F is performed. In this process shown in Figure 8F, first, the adhesive material 6', which will become the adhesive member 6, is applied to the outer edge of the semiconductor chip 2. At this time, the adhesive material 6' is applied so that a portion of it extends beyond the outer edge of the semiconductor chip 2. In other words, it is applied so that a portion of it overlaps onto the first sealing portion 8a. The application of the adhesive material 6' can also be done, for example, by potting using a dispenser.

[0060] In the process shown in Figure 8F, after the adhesive material 6' is applied, the lid portion 4 is placed on the adhesive material 6' and the adhesive material 6' is cured. As a result, the lid portion 4 is fixed onto the semiconductor chip 2 via the adhesive member 6, and a sealed space C is formed inside.

[0061] Following the process shown in Figure 8F, the process of forming the second sealing portion 8b, as shown in Figure 8G, is carried out. Specifically, the second sealing material 8b', which will become the second sealing portion 8b, is applied to the area enclosed by the dam D. As for this second sealing material 8b', a thermosetting resin containing a filler or a UV-curing resin is used, similar to the sealing material 7' in the prior example. The application of the second sealing material 8b' is carried out so that the second sealing material 8b' fills the area around the structure formed by the adhesive member 6 and the lid 4 on the first sealing portion 8a. This filling of the second sealing material 8b' can also be carried out by potting using a dispenser.

[0062] In the process shown in Figure 8G, after filling with the second sealing material 8b' as described above, the second sealing material 8b' is subjected to a predetermined curing treatment such as heating or UV irradiation. As a result, the second sealing portion 8b is formed on the first sealing portion 8a, and a sealing portion 8 is formed that seals the portion of the substrate member 3' that is outside the structure formed by the semiconductor chip 2, adhesive member 6, and lid portion 4. In this example, since the substrate-side pads pw and bonding wires W are present in the portion of the substrate member 3' (wiring board 3) that is outside the above-mentioned structure, the sealing portion 8 also has the function of sealing and protecting these substrate-side pads pw and bonding wires W.

[0063] After the process shown in Figure 8G, the solder ball B formation process shown in Figure 9A is performed, and then, as the next step, the dicing process shown in Figure 9B is performed to divide the semiconductor device 1 into individual pieces (see Figure 9C). Note that the solder ball B formation process in Figure 9A and the dicing process in Figure 9B are the same as those explained in Figures 3A and 3B, respectively, so redundant explanations will be avoided.

[0064] In this example, the second sealing portion 8b is formed from a filler-filled resin as described above, and the amount of filler in the second sealing portion 8b is set to be in the range of 83 wt% to 90 wt%.

[0065] Furthermore, in the semiconductor device 1 of this example, the first sealing portion 8a and the second sealing portion 8b have different coefficients of thermal expansion. Here, the coefficients of thermal expansion of the first sealing portion 8a and the second sealing portion 8b are determined according to the coefficients of thermal expansion of the wiring board 3 and the lid portion 4 in order to solve the problems described later. Specifically, in this example, the wiring board 3 is made of an organic substrate with an organic material such as plastic as the base material, and the lid portion 4 is made of glass, and the coefficient of thermal expansion of the wiring board 3 is greater than the coefficient of thermal expansion of the lid portion 4. In this example, under these conditions, the coefficient of thermal expansion of the first sealing portion 8a is made greater than the coefficient of thermal expansion of the second sealing portion 8b.

[0066] The significance of these configurations will be explained in more detail later.

[0067] (2-3. Effects) In the semiconductor device 1 as an embodiment described above, the semiconductor chip 2 can be miniaturized, thereby improving the theoretical yield of the semiconductor chip 2. The effect of improving the theoretical yield of the semiconductor chip 2 will be explained with reference to Figures 10 and 11. Figure 10 is a diagram showing the results of an estimate of how much the semiconductor chip 2 can be miniaturized compared to the prior example. Figure 10A is an explanatory diagram of the space that should be secured from the outer edge of the pixel formation region 22 to the outer edge of the semiconductor chip 2 in the prior example, and Figure 10B is an explanatory diagram of the same space in this embodiment. Hereinafter, in the following explanation, the space that should be secured from the outer edge of the pixel formation region 22 to the outer edge of the semiconductor chip 2 will be referred to as "margin space".

[0068] In Figures 10A and 10B, "pixel edge" refers to the outer edge of the pixel formation region 22, and "chip edge" refers to the outer edge of the semiconductor chip 2. Also, in Figure 10B, "rib width" refers to the width of the adhesive member 6, "rib edge" refers to the end of the adhesive member 6 in the width direction (direction perpendicular to the thickness direction), and "pad edge" refers to the inner edge of the chip-side pad pc. Here, an example is given of a case where a dummy OCL region (OCL: On Tip Lens) is formed adjacent to the outer periphery of the pixel formation region 22. The dummy OCL region is a region where no light-receiving element is formed, and an optical filter such as a color filter and a microlens are formed. In this example, the condition for deriving the margin space is given as being that the adhesive member 6 does not extend into this dummy OCL region.

[0069] As illustrated in Figure 10A, in the prior example, the distance between the pixel edge and the chip edge, which serves as the margin space, is 634.5 μm. This is set on the condition that the outer edge of the adhesive member 6 does not extend beyond the outer edge of the semiconductor chip 2, and that the adhesive member 6 completely covers the chip-side pad. Specifically, the maximum assumed width of the adhesive member 6 is 550 μm, and the dummy OCL area is 84.5 μm, so the margin space is the above-mentioned 634.5 μm.

[0070] In contrast, the margin space in this embodiment is 440.5 μm, as shown in Figure 10B. When the adhesive material 6' is applied to lock the adhesive member 6, variations in the width of the adhesive member 6 occur, as illustrated in Figure 10B. The margin space is derived on the premise that such variations occur, and that when the width of the adhesive member 6 reaches its maximum width, the adhesive member 6 does not extend beyond the dummy OCL area. Here, the minimum and maximum widths of the adhesive member 6 are calculated based on the actual width values ​​of the adhesive member 6 in its current state, with the minimum width being "average value - 5σ" and the maximum width being "average value + 5σ". Here, the actual width values ​​of the adhesive member 6 in its current state are: average value = 352 μm, σ (standard deviation) = 38.5 μm.

[0071] In this example, we assume a position where the inner edge of the adhesive member 6 coincides with the pad edge when the width of the adhesive member 6 is at its minimum width, and the position of the outer edge of the semiconductor chip 2 is set based on the position of the outer edge of the adhesive member 6 at this time. Specifically, in this case, based on the minimum width of the adhesive member 6 = 159.5 μm, the position of the outer edge of the semiconductor chip 2 is set to 163.5 μm from the pad edge. For the distance inward from the pad edge, we use 192.5 μm (5σ), which is the fluctuation range on one side of the width of the adhesive member 6. Specifically, in order to prevent the adhesive member 6 from overflowing into the dummy OCL area even when the adhesive member 6 is at its maximum width, we apply this 192.5 μm as the distance from the pad edge to the outer edge of the dummy OCL area. As a result, adding the width of the dummy OCL area = 84.5 μm, the margin space as the distance between the pixel edge and the chip edge is set to the above 440.5 μm by "84.5 + 192.5 + 163.5". This represents a reduction of 194 μm compared to previous examples.

[0072] In this case, the maximum amount of outward overhang of the adhesive member 6 is 188.5 μm when the adhesive member 6 is at its maximum width (544.5 μm). This means that 34.6% of the width of the adhesive member 6 extends beyond the outer edge of the semiconductor chip 2.

[0073] Figure 11 is an explanatory diagram illustrating an example of improved payload. As shown in the figure, in the prior example, when the margin space (distance between pixel edge and chip edge) is 635 μm, the number of semiconductor chips 2 is 1051. In contrast, in this embodiment, when the margin space is 440.5 μm, the number of semiconductor chips 2 is 1258. As a result, according to this embodiment, a 19.7% improvement in payload can be achieved.

[0074] Furthermore, in semiconductor device 1, if a material with small variation in spread width during application is selected as the adhesive material 6', the margin space can be reduced, and the size of the semiconductor chip 2 can be further reduced.

[0075] In this embodiment, the semiconductor device 1 has a sealing portion 8 that covers the side of the structure formed by the semiconductor chip 2, adhesive member 6, and lid portion 4. This sealing portion 8 has a first sealing portion 8a that surrounds the side of the semiconductor chip 2 on the wiring board 3, and a second sealing portion 8b that covers the side of the adhesive member 6 and the side of the lid portion 4 on the first sealing portion 8a. This configuration solves the problem of filler sedimentation that occurred in the sealing portion 7 in the prior art.

[0076] Figure 12 is an explanatory diagram of the filler sedimentation phenomenon. Filler sedimentation is a phenomenon in which the filler settles in a filler-filled resin, creating a filler-sparse area at the top where the filler density is low.

[0077] In the sealing portion 7 of the prior example, cracks are more likely to occur in the lid portion 4 due to the formation of filler-sparse areas caused by filler sedimentation. Experiments have shown that these cracks tend to occur more easily the greater the thickness of the filler-sparse area.

[0078] By adopting a structure in which a second sealing portion 8b is formed on the first sealing portion 8a, as in the semiconductor device 1 of this embodiment, the resin thickness of the second sealing portion 8b that is in contact with the lid portion 4 can be reduced. The thickness of the filler sparse portion caused by filler sedimentation tends to decrease as the resin thickness of the filler-filled resin decreases. Therefore, according to this embodiment, compared with the prior example in which a sealing portion 7 is formed, the thickness of the filler sparse portion can be reduced, the possibility of cracks occurring in the lid portion 4 due to the filler sparse portion can be reduced, and the reliability of the product can be improved.

[0079] Figure 13 is an explanatory diagram illustrating an example of the thickness of the filler-sparse portion in a prior example, and Figure 14 is an explanatory diagram illustrating an example of the thickness of the filler-sparse portion in an embodiment. Here, the thickness of the filler-sparse portion was estimated by assuming that the filler settling rate, i.e., the ratio of the thickness of the filler-sparse portion to the total resin thickness, is 5%. In the prior example using the sealing portion 7 as shown in Figure 13, the total thickness of the sealing portion 7 in contact with the lid portion 4 (the same as the thickness from the back surface 2b of the semiconductor chip 2 to the surface of the lid portion 4) is 1.165 mm, and the thickness of the filler-sparse portion is 0.058 mm. The thickness of the semiconductor chip 2 is 0.615 mm.

[0080] In contrast, in the embodiment shown in Figure 14, the total thickness of the second sealing portion 8a in contact with the lid portion 4 (the same as the thickness from the surface 2a of the semiconductor chip 2 to the surface of the lid portion 4) is 0.550 mm, and the thickness of the filler-sparse portion is 0.028 mm. Therefore, in this example, the thickness of the filler-sparse portion can be reduced by 30 μm.

[0081] Here, in order to reduce the rate of crack occurrence due to filler sedimentation, it is also important to appropriately set the amount of filler in the second sealing section 8b so that the filler sedimentation phenomenon is less likely to occur. Specifically, as mentioned earlier, it is desirable that the amount of filler in the second sealing section 8b be in the range of 83 wt% to 90 wt%.

[0082] Furthermore, in the semiconductor device 1 of this embodiment, in order to solve the problems caused by the deformation of the wiring board 3 in response to temperature changes as shown in Figure 15, the coefficients of linear expansion of the first sealing portion 8a and the second sealing portion 8b are set to the aforementioned relationship. Here, one of the problems caused by the deformation of the wiring board 3 is the delamination of the substrate-side pad pw. In this example, the wiring board 3 is made of an organic substrate and the lid portion 4 is made of glass, and the coefficient of linear expansion of the wiring board 3 is set to be greater than that of the lid portion 4. Due to this difference in coefficients of linear expansion, the stress when the wiring board 3 deforms in response to temperature changes becomes large, causing the substrate-side pad pw to delaminate. It should be noted that if this stress becomes large, delamination may occur not only at the joint between the wiring board 3 and the sealing portion 8, but also at the joint between the lid portion 4 and the sealing portion 8.

[0083] Therefore, in the semiconductor device 1 of this embodiment, the coefficient of thermal expansion of the first sealing portion 8a is made larger than that of the second sealing portion 8b. This makes it possible to gradually decrease the coefficient of thermal expansion from the wiring board 3 to the lid portion 4 when the coefficient of thermal expansion of the wiring board 3 is larger than that of the lid portion 4. Consequently, stress caused by the difference in the coefficients of thermal expansion of the wiring board 3 and the lid portion 4 can be alleviated, and the possibility of delamination occurring at the joint between the wiring board 3 and the sealing portion 8, or at the joint between the lid portion 4 and the sealing portion 8, due to this stress can be reduced. In particular, the possibility of delamination of the substrate-side pad pw can be reduced. Note that it is not essential to have different coefficients of thermal expansion for the first sealing portion 8a and the second sealing portion 8b; a configuration in which the coefficients of thermal expansion of the first sealing portion 8a and the second sealing portion 8b are the same can also be considered.

[0084] Here, regarding stress relief against deformation of the wiring board 3, it is also possible to appropriately set the elastic modulus of the adhesive member 6. If the elasticity of the adhesive member 6 is insufficient, delamination will occur between the semiconductor chip 2 and the lid 4 when the wiring board 3 deforms. The elastic modulus of the adhesive member 6 should be appropriately set so that such delamination does not occur.

[0085] <3. Modifications> Here, the embodiments are not limited to the specific examples described above, but a variety of modified configurations can be adopted. For example, the materials and shapes exemplified for each part constituting the semiconductor device are merely examples, and it goes without saying that materials and shapes other than those exemplified can be used.

[0086] Furthermore, although the above example shows the adhesive member 6 being formed by a single application of adhesive material 6', it is also conceivable that the adhesive member 6 be formed by applying the adhesive material 6' multiple times. By applying the adhesive material 6' multiple times, the height of each application can be reduced. If the height of each application is reduced, the width of the adhesive material 6' can also be reduced, and as a result, the width of the adhesive member 6 can be narrowed, the margin space can be reduced, and the semiconductor chip 2 can be miniaturized.

[0087] Furthermore, while the above example cited the application of this technology to a semiconductor device as an image sensor, this technology can be broadly and suitably applied to semiconductor devices other than image sensors, such as semiconductor devices as light-emitting devices in which light-emitting elements such as VCSELs (Vertical Cavity Surface Emitting Lasers) are arranged in an array, or semiconductor devices as distance measuring sensors formed by a two-dimensional arrangement of pixels that receive light for distance measurement. In particular, it is suitable when the cover portion 4 is light-transmitting and the light incident through the cover portion 4 is received by a photodetector formed on the semiconductor chip 2, or when the light emitted by a light-emitting element formed on the semiconductor chip 2 is emitted to the outside through the cover portion 4. This technology can be broadly and suitably applied to semiconductor devices of the type in which a semiconductor chip mounted on a wiring board is covered by a cover portion.

[0088] <4. Summary of Embodiments> As described above, the semiconductor device (1) of the embodiment comprises a semiconductor chip (2), a wiring board (3) on which the semiconductor chip is mounted and on which external connection terminals for electrical connection to the outside are formed on the back side, which is the side opposite to the front side on which the semiconductor chip is mounted, and a cover portion (4) which is bonded to the semiconductor chip by an adhesive member (6) formed on the outer edge of the semiconductor chip and covers the semiconductor chip, wherein a part of the adhesive member protrudes outward from the outer edge of the semiconductor chip. As described above, by a part of the adhesive member protruding outward from the outer edge of the semiconductor chip, the area of ​​the adhesive member that needs to be applied to the outer edge of the semiconductor chip can be reduced.Therefore, in a semiconductor device of the type in which a semiconductor chip mounted on a wiring board is covered by a cover portion, the semiconductor chip can be miniaturized.

[0089] Furthermore, in the semiconductor device of this embodiment, the semiconductor chip is die-bonded to the surface of the wiring substrate, and the chip-side terminal (chip-side pad pc) formed on the outer edge on the surface side and the substrate-side terminal (substrate-side pad pw) formed on the surface side of the wiring substrate are connected by bonding wire (same W) and wire-bonded to the wiring substrate. This improves the bonding strength between the semiconductor chip and the wiring substrate.

[0090] Furthermore, in the semiconductor device of this embodiment, the adhesive member is formed in a position that covers the chip-side terminal. As a result, the adhesive member covers the semiconductor chip-side end of the bonding wire. Therefore, by bonding the cover portion with the adhesive member, the semiconductor chip-side end of the bonding wire can be protected at the same time.

[0091] Furthermore, the semiconductor device of this embodiment includes a sealing portion (8) that seals the portion of the wiring board that is outside the structure formed by the semiconductor chip, adhesive member, and lid. As a result, the bonding wire and the sides of the structure formed by the semiconductor chip, adhesive member, and lid are covered with sealing material. Therefore, the bonding wire and the structure formed by the semiconductor chip, adhesive member, and lid are protected.

[0092] Furthermore, in the semiconductor device of this embodiment, the sealing portion includes a first sealing portion (8a) that surrounds the side of the semiconductor chip on the wiring substrate, and a second sealing portion (8b) that covers the side of the adhesive member and the side of the lid on the first sealing portion. The first sealing portion described above can be formed on the wiring substrate before applying the adhesive material for forming the adhesive member on the semiconductor chip. Therefore, after the formation of the first sealing portion, a manufacturing method can be adopted in which the adhesive material is applied so as to span the inner edge of the first sealing portion and the outer edge of the semiconductor chip. With such a manufacturing method, an overhang configuration of the adhesive member can be easily realized. In addition, by adopting a structure in which the second sealing portion is separately formed on the first sealing portion as described above, the thickness of the filler sparse portion caused by filler sedimentation can be reduced, the possibility of cracks occurring in the lid due to the filler sparse portion can be reduced, and the reliability of the product can be improved.

[0093] Furthermore, in the semiconductor device of this embodiment, the second sealing portion is formed of a filler-filled resin, and the amount of filler in the second sealing portion is in the range of 83 wt% to 90 wt%. By appropriately determining the amount of filler in the second sealing portion, filler sedimentation can be made less likely to occur. By making it less likely for filler sedimentation to occur in the second sealing portion, the possibility of cracks occurring in the lid portion due to sparse filler areas can be reduced, thereby improving the reliability of the product.

[0094] Furthermore, in the semiconductor device of this embodiment, the coefficient of linear expansion of the first sealing portion and the coefficient of linear expansion of the second sealing portion are different. By providing a difference in the coefficient of linear expansion between the first and second sealing portions, it becomes possible to adjust the transmission characteristics of the force transmitted between the wiring board and the lid via the first and second sealing portions when deformation of the wiring board or the lid occurs due to temperature changes. Therefore, when the coefficients of linear expansion of the wiring board and the lid are different, it is possible to alleviate the stress caused by the difference in the coefficients of linear expansion, and the possibility of delamination occurring at the joint between the wiring board and the sealing portion or the joint between the lid and the sealing portion due to this stress can be reduced. In other words, the reliability of the product can be improved.

[0095] Furthermore, in the semiconductor device of this embodiment, the coefficient of thermal expansion of the wiring board is greater than that of the lid, and the coefficient of thermal expansion of the first sealing portion is greater than that of the second sealing portion. This makes it possible to gradually decrease the coefficient of thermal expansion from the wiring board to the lid when the coefficient of thermal expansion of the wiring board is greater than that of the lid, for example, when the lid is made of glass. Consequently, stress caused by the difference in the coefficients of thermal expansion between the wiring board and the lid can be alleviated, and the possibility of delamination occurring at the joint between the wiring board and the sealing portion, or between the lid and the sealing portion, due to this stress can be reduced. In particular, the possibility of delamination occurring at the terminals on the board side can be reduced.

[0096] Furthermore, in the semiconductor device of this embodiment, a photodetector or light-emitting element is formed in a region on the surface side of the semiconductor chip that is inside the adhesive member, and the cover portion is light-transmitting. When a photodetector is formed on the semiconductor chip, it can receive light incident through the light-transmitting cover portion, and when a light-emitting element is formed on the semiconductor chip, the light emitted by the light-emitting element can be emitted to the outside through the light-transmitting cover portion. Therefore, the semiconductor device with the above configuration is suitable as a photodetector and a light-emitting device.

[0097] Furthermore, in the semiconductor device of this embodiment, the adhesive member has light-shielding properties. This prevents light incident through the light-transmitting lid or light emitted by the light-emitting element from being diffusely reflected within the cavity. In particular, when multiple light-receiving elements are formed on the semiconductor chip and the semiconductor device is configured as an image sensor, flare can be suppressed.

[0098] Furthermore, in the semiconductor device of this embodiment, the adhesive member is formed of a black material. This makes it possible to realize a light-shielding adhesive member.

[0099] Furthermore, in the semiconductor device of this embodiment, multiple light-receiving elements are arranged in two dimensions in a region inside the adhesive member of the semiconductor chip, and the device is configured as an image sensor to obtain an captured image. This makes it possible to miniaturize the semiconductor chip for the semiconductor device used as an image sensor.

[0100] A semiconductor device manufacturing method as an embodiment comprises a semiconductor chip, a wiring substrate on which the semiconductor chip is mounted and on which external connection terminals for electrical connection to the outside are formed on the back side, which is the side opposite to the front side on which the semiconductor chip is mounted, and a cover portion that is bonded to the semiconductor chip by an adhesive member formed on the outer edge of the semiconductor chip and covers the semiconductor chip, wherein the manufacturing method includes at least a step of applying an adhesive material for forming the adhesive member so as to extend beyond the outer edge of the semiconductor chip. By such a manufacturing method, the semiconductor device as an embodiment described above can be manufactured.

[0101] Furthermore, the effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0102] <5. This Technology> This technology can also be configured as follows: (1) A semiconductor device comprising: a semiconductor chip; a wiring board on which the semiconductor chip is mounted, and on the back side opposite to the surface on which the semiconductor chip is mounted, an external connection terminal for making an electrical connection to the outside is formed thereon; and a cover portion that is bonded to the semiconductor chip by an adhesive member formed on the outer edge of the semiconductor chip and covers the semiconductor chip, wherein a part of the adhesive member protrudes outward from the outer edge of the semiconductor chip. (2) The semiconductor device according to (1), wherein the semiconductor chip is die-bonded to the surface of the wiring board, and a chip-side terminal formed on the outer edge on the surface side and a substrate-side terminal formed on the surface side of the wiring board are connected by a bonding wire and wire-bonded to the wiring board. (3) The semiconductor device according to (2), wherein the adhesive member is formed in a position to cover the chip-side terminal. (4) The semiconductor device according to (2) or (3), further comprising a sealing portion that seals the portion on the wiring board that is outside the structure formed by the semiconductor chip, the adhesive member and the cover portion. (5) The semiconductor device according to (4), wherein the sealing portion comprises a first sealing portion that surrounds the side of the semiconductor chip on the wiring board, and a second sealing portion that covers the side of the adhesive member and the side of the lid on the first sealing portion. (6) The semiconductor device according to (5), wherein the second sealing portion is formed of a filler-filled resin, and the amount of filler in the second sealing portion is in the range of 83 wt% to 90 wt%. (7) The semiconductor device according to (5), wherein the coefficient of thermal expansion of the first sealing portion and the coefficient of thermal expansion of the second sealing portion are different. (8) The semiconductor device according to (7), wherein the coefficient of thermal expansion of the wiring board is greater than the coefficient of thermal expansion of the lid, and the coefficient of thermal expansion of the first sealing portion is greater than the coefficient of thermal expansion of the second sealing portion. (9) The semiconductor device according to any one of (1) to (8), wherein a light-receiving element or a light-emitting element is formed in a region on the surface side of the semiconductor chip that is inside the adhesive member, and the lid is light-transmitting. (10) The semiconductor device described in (9) above, wherein the adhesive member has light-shielding properties.(11) The semiconductor device according to (10), wherein the adhesive member is made of a black material. (12) The semiconductor device according to (9), wherein a plurality of light-receiving elements are arranged in two dimensions in a region inside the adhesive member on the semiconductor chip, and configured as an image sensor for obtaining an image. (13) A method for manufacturing a semiconductor device comprising: a semiconductor chip; a wiring substrate on which the semiconductor chip is mounted, and on the back side opposite to the surface on which the semiconductor chip is mounted, external connection terminals for making an electrical connection to the outside are formed; and a cover portion that is bonded to the semiconductor chip by an adhesive member formed on the outer edge of the semiconductor chip and covers the semiconductor chip, the method for manufacturing a semiconductor device comprising at least the step of applying an adhesive material for forming the adhesive member so as to extend beyond the outer edge of the semiconductor chip.

[0103] 1,100 Semiconductor device 2 Semiconductor chip 2a Front surface 2b Back surface 21 Pixel 22 Pixel formation area 3 Wiring substrate 3a Front surface 3b Back surface 4 Cover 5 Bonding layer 6 Adhesive member 7 Sealing part 8 Sealing part 8a First sealing part 8b Second sealing part C Cavity pc Chip-side pad pw Substrate-side pad W Bonding wire pb Pad B Solder ball 3' Substrate member 6' Adhesive material D Dam 7' Sealing material 8a' First sealing material 8b' Second sealing material

Claims

1. A semiconductor device comprising: a semiconductor chip; a wiring board on which the semiconductor chip is mounted, and on the back side opposite to the front side on which the semiconductor chip is mounted, external connection terminals for electrical connection to the outside are formed; and a cover portion that is bonded to the semiconductor chip by an adhesive member formed on the outer edge of the semiconductor chip and covers the semiconductor chip, wherein a part of the adhesive member protrudes outward beyond the outer edge of the semiconductor chip.

2. The semiconductor device according to claim 1, wherein the semiconductor chip is die-bonded to the surface of the wiring substrate, and the chip-side terminal formed on the outer edge on the surface side and the substrate-side terminal formed on the surface side of the wiring substrate are connected by bonding wires and wire-bonded to the wiring substrate.

3. The semiconductor device according to claim 2, wherein the adhesive member is formed in a position that covers the chip-side terminal.

4. The semiconductor device according to claim 2, further comprising a sealing portion that seals the portion on the wiring board that is outside the structure formed by the semiconductor chip, the adhesive member, and the lid portion.

5. The semiconductor device according to claim 4, wherein the sealing portion comprises a first sealing portion that surrounds the side of the semiconductor chip on the wiring board, and a second sealing portion that covers the side of the adhesive member and the side of the lid on the first sealing portion.

6. The semiconductor device according to claim 5, wherein the second sealing portion is formed of a filler-filled resin, and the amount of filler in the second sealing portion is in the range of 83 wt% to 90 wt%.

7. The semiconductor device according to claim 5, wherein the coefficient of linear expansion of the first sealing portion and the coefficient of linear expansion of the second sealing portion are different.

8. The semiconductor device according to claim 7, wherein the coefficient of thermal expansion of the wiring board is greater than the coefficient of thermal expansion of the lid, and the coefficient of thermal expansion of the first sealing portion is greater than the coefficient of thermal expansion of the second sealing portion.

9. The semiconductor device according to claim 1, wherein a light-receiving element or a light-emitting element is formed in a region on the surface side of the semiconductor chip that is inside the adhesive member, and the lid portion is light-transmitting.

10. The semiconductor device according to claim 9, wherein the adhesive member has light-shielding properties.

11. The semiconductor device according to claim 10, wherein the adhesive member is formed of a black material.

12. The semiconductor device according to claim 9, configured as an image sensor in which a plurality of light-receiving elements are arranged in two dimensions in a region inside the adhesive member of the semiconductor chip to obtain an image.

13. A method for manufacturing a semiconductor device, comprising: a semiconductor chip; a wiring substrate on which the semiconductor chip is mounted, and on the back side opposite to the front side on which the semiconductor chip is mounted, external connection terminals for making an electrical connection to the outside are formed; and a cover portion that is bonded to the semiconductor chip by an adhesive member formed on the outer edge of the semiconductor chip and covers the semiconductor chip, the method for manufacturing a semiconductor device comprising at least a step of applying an adhesive material for forming the adhesive member so that it extends beyond the outer edge of the semiconductor chip.

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