Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component that can suppress cracks and noise caused by vibration.　A multilayer ceramic electronic component 100 according to the present invention is a multilayer ceramic capacitor comprising: a laminate including a plurality of laminated ceramic layers, and including a first main surface and second main surface opposing each other in a height direction, a first side surface and second side surface opposing each other in a width direction orthogonal to the height direction, a first end surface and second end surface opposing each other in a longitudinal direction orthogonal to the height direction and the width direction, first internal electrodes that are alternately laminated with the plurality of ceramic layers and exposed on the first end surface, and second internal electrodes that are alternately laminated with the plurality of ceramic layers and exposed on the second end surface; a first external electrode disposed so as to extend across the first main surface and the second main surface from the first end surface; and a second external electrode disposed so as to extend across the first main surface and the second main surface from the second end surface. The multilayer ceramic capacitor also comprises a first spacer that is joined to the first external electrode, a second spacer that is joined to the second external electrode, and a third spacer that joins the first spacer and the first main surface and joins the second spacer and the first main surface. The third spacer is included inside of the first spacer and the second spacer; and the first spacer and the second spacer include a first side surface-side region disposed on the first side surface side, a second side surface-side region disposed on the second side surface side, and a central region disposed between the first side surface-side region and the second side surface-side region. The percentage of the central region occupied by the third spacer is large

Description

Multilayer ceramic electronic component

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] In recent years, a large number of multilayer ceramic capacitors, which are chip-type electronic components, are used in electronic devices. The electronic devices in which such multilayer ceramic capacitors are used are becoming more and more high-performance, and accordingly, the multilayer ceramic capacitors are also rapidly becoming more high-performance, such as miniaturization and large capacitance.

[0003] A multilayer ceramic capacitor has an inner layer portion in which ceramic layers and internal electrodes are alternately stacked. Then, a rectangular parallelepiped laminate is formed in which ceramic layers as outer layer portions are disposed above and below the inner layer portion, and external electrodes are provided on both end faces in the longitudinal direction of the laminate to form a multilayer ceramic capacitor. In the multilayer ceramic capacitor, capacitance is generated when the internal electrodes face each other through the ceramic layer. At this time, it is known that the multilayer ceramic capacitor generates vibration due to the piezoelectric phenomenon, and this vibration is transmitted to the substrate, thereby causing so-called "whining".

[0004] In order to reduce the phenomenon of "whining", a multilayer ceramic capacitor with a spacer (bump) (referred to as a "connection terminal" in Patent Document 1) added to the external electrode has been developed so far (see Patent Document 1).

[0005] Japanese Patent Application Laid-Open No. 2018-190952

[0006] However, when using a conventional spacer, it has been difficult to suppress cracks due to vibration caused by the electrostriction phenomenon of the multilayer ceramic capacitor while reducing the whining phenomenon.

[0007] Therefore, an object of the present invention is to provide a multilayer ceramic electronic component capable of suppressing cracks and whining caused by vibration.

[0008] The multilayer ceramic electronic component according to the present invention comprises a laminate including a plurality of stacked ceramic layers, a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, a first end surface and a second end surface facing each other in the longitudinal direction perpendicular to the height direction and the width direction, a first internal electrode alternately stacked with the plurality of ceramic layers and exposed on the first end surface, a second internal electrode alternately stacked with the plurality of ceramic layers and exposed on the second end surface, and a first external electrode arranged from the first end surface across the first and second main surfaces, and a second external electrode arranged from the second end surface across the first and second main surfaces, wherein the multilayer ceramic capacitor comprises The device comprises a first spacer joined to the first external electrode, a second spacer joined to the second external electrode, and a third spacer that joins the first spacer to the first main surface and the second spacer to the first main surface, wherein the third spacer is contained within the first spacer and the second spacer, and the first spacer and the second spacer have a first side region located on the first side, a second side region located on the second side, and a central region located between the first side region and the second side region, wherein the content of the third spacer in the central region is greater than the content of the third spacer in the first side region and the second side region.

[0009] According to the multilayer ceramic electronic component of the present invention, by setting the "content ratio of the third spacer: central region > first and second side regions," the third spacer contained in the central region acts as a cushion, and the amplitude of vibration can be mitigated in the central region, where the amplitude of vibration tends to be large during mounting. Therefore, a suppression effect against cracks and noises caused by vibration can be obtained.

[0010] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can suppress cracks and noises caused by vibration.

[0011] The above-mentioned objectives, other objectives, features, and advantages of the present invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings.

[0012] This is an external perspective view showing a multilayer ceramic electronic component according to an embodiment of the present invention. This is a front view showing a multilayer ceramic electronic component according to an embodiment of the present invention. This is a bottom view of a multilayer ceramic electronic component according to an embodiment of the present invention. This is a cross-sectional view taken along line IV-IV in Figure 2. This is a cross-sectional view taken along line V-V in Figure 3. This is a partially enlarged view of the cross-sectional view of the multilayer ceramic electronic component shown in Figure 5, enlarged around the second spacer. This is an enlarged view of part A in Figure 5. This is a diagram showing the mounting state of a multilayer ceramic electronic component according to an embodiment of the present invention. This is a diagram showing a modified example of the first spacer and the second spacer in the multilayer ceramic electronic component, and is a cross-sectional view corresponding to Figure 4.

[0013] 1. Multilayer Ceramic Electronic Components The multilayer ceramic electronic component 100 according to the present invention will be described based on Figures 1 to 9. Figure 1 is an external perspective view showing a multilayer ceramic electronic component according to an embodiment of the present invention. Figure 2 is a front view showing a multilayer ceramic electronic component according to an embodiment of the present invention. Figure 3 is a bottom view of a multilayer ceramic electronic component according to an embodiment of the present invention. Figure 4 is a cross-sectional view taken along line IV-IV in Figure 2. Figure 5 is a cross-sectional view taken along line V-V in Figure 3. Figure 6 is a partially enlarged view of the cross-sectional view of the multilayer ceramic electronic component shown in Figure 5, enlarged around the second spacer. Figure 7 is an enlarged view of part A in Figure 5. Figure 8 is a diagram showing the mounting state of a multilayer ceramic electronic component according to an embodiment of the present invention. Figure 9 is a diagram showing a modified example of the first spacer and the second spacer in the multilayer ceramic electronic component, and is a cross-sectional view corresponding to Figure 4.

[0014] The multilayer ceramic electronic component 100 according to the present invention comprises a multilayer ceramic capacitor 10 having a laminate 12 and two external electrodes 30a and 30b, a first spacer 52 connected to one external electrode 30a, a second spacer 54 connected to the other external electrode 30b, and a third spacer 56 disposed between the first spacer 52 and the second spacer 54.

[0015] (Laminate) The laminate 12 has a plurality of stacked ceramic layers 14 and a plurality of internal electrodes 16 stacked on the ceramic layers 14. The laminate 12 has a first main surface 12a and a second main surface 12b opposite to the height direction x, a first end surface 12c and a second end surface 12d perpendicular to the height direction x and opposite to the first direction y, and a first side surface 12e and a second side surface 12f perpendicular to the height direction x and the first direction y and opposite to the second direction z. In this embodiment, the side of the first main surface 12a of the laminate 12 is the mounting surface side, and the side of the second main surface 12b of the laminate 12 is the non-mounting surface side. The height direction x is the direction perpendicular to the mounting surface S (shown in Figure 8).

[0016] The laminate 12 has a hexahedral shape. Preferably, the corners and edges of the laminate 12 are rounded. The corners are the parts where three adjacent faces of the laminate 12 intersect, and the edges are the parts where two adjacent faces of the laminate 12 intersect. Furthermore, some or all of the first main surface 12a and the second main surface 12b, the first end surface 12c and the second end surface 12d, and the first side surface 12e and the second side surface 12f may have irregularities or other features formed on them.

[0017] The laminate 12 has an inner layer 18 on which a plurality of internal electrodes 16 face each other. In other words, in the inner layer 18, the first internal electrode 16a and the second internal electrode 16b face each other.

[0018] The laminate 12 is located on the side of the first main surface 12a and has a first outer layer 20a formed from a plurality of ceramic layers 14 located between the first main surface 12a and the outermost surface of the inner layer 18 on the side of the first main surface 12a and the extension of that outermost surface.

[0019] Similarly, the laminate 12 has a second outer layer 20b located on the second main surface 12b side, which is formed from a plurality of ceramic layers 14 located between the second main surface 12b and the outermost surface of the inner layer 18 on the second main surface 12b side and the extension of that outermost surface.

[0020] (Ceramic layer) As the ceramic material constituting the ceramic layer 14, for example, dielectric ceramics consisting of main components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3 can be used. Alternatively, materials to which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds have been added to these main components may be used.

[0021] Furthermore, the thickness of the ceramic layer 14 is preferably 0.5 μm or more and 10 μm or less. In addition, the number of ceramic layers 14, including the first outer layer portion 20a and the second outer layer portion 20b, is preferably 10 to 700.

[0022] (Internal electrodes) The internal electrode 16 has a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b.

[0023] The first internal electrode 16a is arranged on a plurality of ceramic layers 14 and is exposed on the first end face 12c.

[0024] The second internal electrode 16b is arranged on a plurality of ceramic layers 14 and is exposed on the second end face 12d.

[0025] The first internal electrode 16a comprises a first opposing electrode portion 26a that faces the second internal electrode 16b, and a first drawn-out electrode portion 28a that is drawn out from the first opposing electrode portion 26a to the first end face 12c of the laminate 12. The end of the first drawn-out electrode portion 28a of the first internal electrode 16a is drawn out to the surface of the first end face 12c of the laminate 12, forming an exposed portion.

[0026] The second internal electrode 16b comprises a second opposing electrode portion 26b that faces the first internal electrode 16a, and a second leading electrode portion 28b that is drawn out from the second opposing electrode portion 26b to the second end face 12d of the laminate 12. The end of the second leading electrode portion 28b of the second internal electrode 16b is drawn out to the surface of the second end face 12d of the laminate 12, forming an exposed portion.

[0027] The shape of the first opposing electrode portion 26a of the first internal electrode 16a and the second opposing electrode portion 26b of the second internal electrode 16b is not particularly limited, but it is preferably rectangular. However, the corners may be rounded or formed at an angle (tapered shape).

[0028] The widths of the first opposing electrode portion 26a of the first internal electrode 16a and the second opposing electrode portion 26b of the second internal electrode 16b, and the widths of the first leading electrode portion 28a of the first internal electrode 16a and the second leading electrode portion 28b of the second internal electrode 16b may be the same width, or one of them may be formed to be narrower.

[0029] In this embodiment, capacitance is formed when the opposing electrode portions 26 of the internal electrode 16 face each other via the ceramic layer 14, and the characteristics of a capacitor are exhibited.

[0030] The first internal electrode 16a and the second internal electrode 16b can be made of a suitable conductive material, such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0031] Furthermore, the presence of a Sn layer containing Sn between the first internal electrode 16a and the ceramic layer 14, and between the second internal electrode 16b and the ceramic layer 14, can mitigate electric field concentration at the interface between the internal electrode 16 and the ceramic layer 14, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is included in only one of the internal electrodes 16, either the first internal electrode 16a or the second internal electrode 16b.

[0032] The thickness of the first internal electrode 16a and the second internal electrode 16b is preferably, for example, 0.2 μm or more and 2.0 μm or less. The number of internal electrodes 16 is preferably 10 or more and 700 or less.

[0033] (External electrodes) The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0034] The first external electrode 30a is connected to the first internal electrode 16a and is positioned on the first end face 12c. It may also be positioned on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12e, and a portion of the second side surface 12f. In this embodiment, it is formed extending from the first end face 12c to a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12e, and a portion of the second side surface 12f.

[0035] The second external electrode 30b is connected to the second internal electrode 16b and is positioned on the second end face 12d. It may also be positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, a portion of the first side surface 12e, and a portion of the second side surface 12f. In this embodiment, it is formed extending from the second end face 12d to a portion of the first main surface 12a and a portion of the second main surface 12b, a portion of the first side surface 12e, and a portion of the second side surface 12f.

[0036] The first external electrode 30a and the second external electrode 30b each have a base electrode layer 32 placed on the surface of the laminate 12 and a plating layer 34 placed so as to cover the base electrode layer 32.

[0037] (Underlayment electrode layer) The underlayment electrode layer 32 is arranged on the first end face 12c and the second end face 12d. It may also be arranged on a part of the first main surface 12a and a part of the second main surface 12b, a part of the first side surface 12e and a part of the second side surface 12f, on the first external electrode 30a side and the second external electrode 30b side, respectively. In this embodiment, on the first external electrode 30a side and the second external electrode 30b side, it is formed extending from the first end face 12c and the second end face 12d to a part of the first main surface 12a and a part of the second main surface 12b, a part of the first side surface 12e and a part of the second side surface 12f, respectively.

[0038] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0039] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc.

[0040] (In the case of the baking layer) The baking layer contains a glass component and a metal. The glass component of the baking layer contains, for example, at least one selected from B, Si, Ba, Mg, Al, and Li. The metal of the baking layer contains, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.

[0041] The baking layer may be a plurality of layers. Also, the baking layer is formed by applying and baking a conductive paste containing glass and metal to the laminate 12. The baking layer may be formed by co-firing a laminated chip having an internal electrode 16 and a ceramic layer 14 and a conductive paste applied to the laminated chip, or after firing a laminated chip having an internal electrode 16 and a ceramic layer 14 to obtain the laminate 12, applying and baking a conductive paste to the laminate 12. When co-firing a laminated chip having an internal electrode 16 and a ceramic layer 14 and a conductive paste applied to the laminated chip, it is preferable to form the baking layer by baking a material in which a dielectric material is added instead of the glass component.

[0042] The thickness in the first direction y connecting the first end face 12c and the second end face 12d at the center in the height direction x connecting the first main face 12a and the second main face 12b of the first baking layer located on the first end face 12c (that is, the thickness of the base electrode layer at the center of the first end face 12c) is preferably, for example, 3 μm or more and 160 μm or less.

[0043] The thickness in the first direction y connecting the first end face 12c and the second end face 12d at the center in the height direction x connecting the first main face 12a and the second main face 12b of the second baking layer located on the second end face 12d (that is, the thickness of the base electrode layer at the center of the second end face 12d) is preferably, for example, 3 μm or more and 160 μm or less.

[0044] Also, the thickness in the height direction x connecting the first main face 12a and the second main face 12b at the center in the first direction y connecting the first end face 12c and the second end face 12d of the first baking layer located on a part of the first main face 12a and a part of the second main face 12b is preferably, for example, 3 μm or more and 40 μm or less.

[0045] Further, the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center in the first direction y connecting the first end surface 12c and the second end surface 12d of the second baking layer located on a part of the first main surface 12a and a part of the second main surface 12b is preferably, for example, 3 μm or more and 40 μm or less.

[0046] (In the case of the conductive resin layer) When a conductive resin layer is provided as the base electrode layer 32, the conductive resin layer may be arranged to cover the baking layer. Further, it may be directly arranged on the laminate 12 without providing the baking layer. The conductive resin layer may completely cover the base electrode layer 32 or may cover a part of the base electrode layer 32. Further, the conductive resin layer may be formed of a plurality of layers.

[0047] The conductive resin layer contains, for example, a thermosetting resin and a metal component.

[0048] As specific examples of the thermosetting resin, various known thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin can be used. Among them, the epoxy resin, which is excellent in heat resistance, moisture resistance, adhesion, etc., is one of the most suitable resins.

[0049] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenolic, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide imide-based compounds can be used as the curing agent.

[0050] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powders coated with Ag can be used. When using metal powders coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or their alloy powders as the metal powder. The reason for using Ag conductive metal powder as the metal in the conductive resin layer is that Ag has the lowest resistivity among metals, making it suitable for electrode materials, and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of inexpensive base metals while maintaining the above-mentioned properties of Ag. Additionally, Cu and Ni treated with oxidation prevention can be used as the metals in the conductive resin layer. Also, metal powders coated with Sn, Ni, or Cu can be used as the metals in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or their alloy powders as the metal powder.

[0051] The metals contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders. Furthermore, the metals contained in the conductive resin layer are primarily responsible for the conductive properties of the layer. Specifically, conductive paths are formed within the conductive resin layer when the conductive fillers (metals contained in the conductive resin layer) come into contact with each other.

[0052] Because the conductive resin layer contains a thermosetting resin, it is more flexible than, for example, the underlying electrode layer made of a plated film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the multilayer ceramic capacitor.

[0053] The thickness of the thickest part of the conductive resin layer is preferably, for example, 10 μm or more and 150 μm or less.

[0054] (In the case of a thin film layer) A thin film layer is a layer of 1 μm or less in thickness in which metal particles are deposited, formed by a thin film formation method such as sputtering or vapor deposition.

[0055] (Plating layer) The plating layer 34 has a first plating layer 34a and a second plating layer 34b. The first plating layer 34a is arranged to cover the first base electrode layer 32a. The second plating layer 34b is arranged to cover the second base electrode layer 32b.

[0056] Furthermore, the plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0057] The plating layer 34 may be formed from multiple layers. Preferably, it is a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the underlying electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic electronic component 100. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic electronic component 100, making mounting easier.

[0058] Furthermore, the thickness of each layer of the plating layer 34 is preferably 2 μm or more and 15 μm or less.

[0059] The external electrode 30 may be formed using only the plating layer 34 without providing the underlayer electrode layer 32. The following describes a structure in which the plating layer 34 is provided without the underlayer electrode layer 32.

[0060] The first external electrode 30a and the second external electrode 30b may each have a plating layer 34 directly formed on the surface of the laminate 12 without providing an underlayment electrode layer 32. That is, the multilayer ceramic capacitor 10 may have a structure that includes a plating layer 34 directly connected to the first internal electrode 16a and the second internal electrode 16b. In such a case, the plating layer 34 may be formed after a catalyst is placed on the surface of the laminate 12 as a pretreatment.

[0061] When a plating layer is formed directly on the laminate 12 without providing a base electrode layer 32, the reduction in the thickness of the base electrode layer 32 can be used to lower the profile, i.e., to make the chip thinner, or to increase the thickness of the laminate 12, i.e., the thickness of the inner layer 18 (effective layer), thereby improving the design flexibility of thin chips.

[0062] Furthermore, it is preferable that the plating layer 34 includes a lower plating electrode formed on the surface of the laminate 12 and an upper plating electrode formed on the surface of the lower plating electrode.

[0063] Preferably, the lower plated electrode and the upper plated electrode each contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such metal.

[0064] The lower plated electrode is preferably formed using Ni, which has solder barrier properties, and the upper plated electrode is preferably formed using Sn or Au, which has good solder wettability.

[0065] Furthermore, for example, when the first internal electrode 16a and the second internal electrode 16b are formed using Ni, it is preferable that the lower layer plating electrode be formed using Cu, which has good bonding properties with Ni. The upper layer plating electrode may be formed as needed, and the first external electrode 30a and the second external electrode 30b may each consist only of the lower layer plating electrode.

[0066] The plating layer 34 may have the upper plating electrode as the outermost layer, or other plating electrodes may be formed on the surface of the upper plating electrode.

[0067] The thickness of each layer of the plating layer 34, which is placed without the underlayer electrode layer 32, is preferably 1 μm or more and 15 μm or less. Furthermore, it is preferable that the plating layer 34 does not contain glass. The metal content per unit volume of the plating layer 34 is preferably 99% by volume or more.

[0068] The dimension of the multilayer ceramic capacitor 10 in the first direction y is defined as dimension L. Dimension L is preferably 0.2 mm or more and 10 mm or less. The dimension of the multilayer ceramic capacitor 10 in the second direction z is defined as dimension W. Dimension W is preferably 0.1 mm or more and 5 mm or less. The dimension of the multilayer ceramic capacitor 10 in the height direction x is defined as dimension T. Dimension T is preferably 0.1 mm or more and 5 mm or less. In this embodiment, the chip size of the multilayer ceramic capacitor 10 is preferably L dimension 1.6 mm, T dimension 0.8 mm, and W dimension 0.8 mm.

[0069] (Spacer) The multilayer ceramic electronic component 100 includes a multilayer ceramic capacitor 10 and a spacer 50. The spacer 50 includes a first spacer 52 that covers at least a portion of the first external electrode 30a, a second spacer 54 that covers at least a portion of the second external electrode 30b, and a third spacer 56 that covers a portion of the laminate 12, a portion of the first spacer 52, and a portion of the second spacer 54.

[0070] As shown in Figure 8, when the multilayer ceramic electronic component 100 is mounted on the mounting substrate 60, the first spacer 52 and the second spacer 54 are electrically and mechanically connected to the land electrodes 64a and 64b, respectively, via solder 62. At this time, the solder 62 forms fillets along the first spacer 52 and the first external electrode 30a, and along the second spacer 54 and the second external electrode 30b. Note that the fillets formed by the solder 62 may be formed only on the first spacer 52 or the second spacer 54. If the fillets are formed only on the first spacer 52 and the second spacer 54, the amount of solder 62 wetting the multilayer ceramic capacitor 10 can be reduced, thereby suppressing noise.

[0071] (First spacer and second spacer) The first spacer 52 is positioned between the first external electrode 30a and the mounting surface S and is connected to the first external electrode 30a. The second spacer 54 is positioned between the second external electrode 30b and the mounting surface S and is connected to the second external electrode 30b.

[0072] The shapes of the first spacer 52 and the second spacer 54 are not particularly limited. In other words, the shapes of the first spacer 52 and the second spacer 54 may be, for example, approximately hexahedral. In the following description, the shapes of the first spacer 52 and the second spacer 54 will be assumed to be hexahedral.

[0073] The first spacer 52 has a first main spacer surface 52a (first surface of the first spacer 52) and a first main spacer surface 52b (second surface of the first spacer 52) that are opposite to the height direction x, a first external electrode side spacer end surface 52c (third surface of the first spacer 52) and a first laminate center side spacer end surface 52d (fourth surface of the first spacer 52) that are perpendicular to the height direction x and opposite to the first direction y, and a first side surface 52e (fifth surface of the first spacer 52) and a first side surface 52f (sixth surface of the first spacer 52) that are perpendicular to the height direction x and the first direction y and opposite to the second direction z. In this case, the first spacer 52 may have a truncated square pyramidal shape such that the area of ​​the first spacer main surface 52b (the second surface of the first spacer 52) is smaller than the area of ​​the first spacer main surface 52a (the first surface of the first spacer 52).

[0074] The first main spacer surface 52b of the first spacer 52 is located on the mounting surface S side. The first main spacer surface 52a of the first spacer 52 is connected to the first external electrode 30a. In addition, in the first spacer 52, the edge portion of the first spacer 52 on the center side of the multilayer ceramic capacitor 10 is located closer to the center than the edge portion of the first external electrode 30a on the center side of the multilayer ceramic capacitor 10. In addition, in the first spacer 52, the ridge portion 52r where the first main spacer surface 52a of the multilayer ceramic capacitor 10 of the first spacer 52 intersects with the central side spacer end surface 52d of the first laminate is located closer to the center than the edge portion of the first external electrode 30a on the center side of the multilayer ceramic capacitor 10. Therefore, the first spacer 52 has a portion on the first main spacer surface 52a that is in contact with the first external electrode 30a and a portion that extends towards the center from the portion in contact with the first external electrode 30a.

[0075] The second spacer 54 has a second main spacer surface 54a (first surface of the second spacer 54) and a second main spacer surface 54b (second surface of the second spacer 54) that are opposite to the height direction x, a second external electrode side spacer end surface 54c (third surface of the second spacer 54) and a second laminate center side spacer end surface 54d (fourth surface of the second spacer 54) that are perpendicular to the height direction x and opposite to the first direction y, and a second side surface 54e (fifth surface of the second spacer 54) and a second side surface 54f (sixth surface of the second spacer 54) that are perpendicular to the height direction x and the first direction y and opposite to the second direction z. In this case, the second spacer 54 may have a truncated square pyramidal shape such that the area of ​​the second spacer main surface 54b (the second surface of the second spacer 54) is smaller than the area of ​​the second spacer main surface 54a (the first surface of the second spacer 54).

[0076] The second main surface 54b of the second spacer 54 is located on the mounting surface S side. The second main surface 54a of the second spacer 54 is connected to the second external electrode 30b. In addition, in the second spacer 54, the edge portion of the second spacer 54 on the center side of the multilayer ceramic capacitor 10 is located closer to the center than the center end portion of the second external electrode 30b on the multilayer ceramic capacitor 10. In addition, in the second spacer 54, the ridge portion 54r where the second main surface 54a of the second spacer 54 on the multilayer ceramic capacitor 10 and the second central side spacer end surface 54d of the second laminate is located closer to the center than the center end portion of the second external electrode 30b on the multilayer ceramic capacitor 10. Therefore, the second spacer 54 has a portion on the second main surface 54a that is in contact with the second external electrode 30b and a portion that extends towards the center from the portion in contact with the second external electrode 30b.

[0077] The placement of the first spacer 52 and the second spacer 54 between the multilayer ceramic capacitor 10 and the mounting surface S increases the distance between the inner layer 18, which is the capacitance forming part of the multilayer ceramic capacitor 10, and the mounting surface S, thereby suppressing "whining."

[0078] At this time, depending on the height dimension L of the multilayer ceramic capacitor 10, the height dimension t of the first spacer 52 and the second spacer 54 s For example, it is preferable that the dimension L in the first direction y of the multilayer ceramic capacitor 10 is 1.6 mm, the dimension W in the second direction z of the multilayer ceramic capacitor 10 is 0.8 mm, and the dimension T in the height direction x of the multilayer ceramic capacitor 10 is 0.8 mm. s The thickness is preferably about 160 μm. Furthermore, the first spacer 52 and the second spacer 54 may have some irregularities. If the first spacer 52 and the second spacer 54 have some irregularities due to their shape, the dimension t in the height direction x of the first spacer 52 and the second spacer 54 is... s It is preferable that the minimum thickness is about 50 μm.

[0079] Furthermore, the dimension t in the first direction y (longitudinal direction) of the first spacer 52 and the second spacer 54 l When the length dimension is 1.0 mm or more, a thickness of 400 μm or more and 450 μm or less is preferable. Furthermore, the area of ​​the first spacer 52 and the area of ​​the second spacer 54 may differ in the cross-section in the height direction x and the first direction y.

[0080] Furthermore, although not shown in the figure, the first spacer 52, when divided into three equal parts in the second direction z (width direction), has a first side region located on the first side surface 12e side, a second side region located on the second side surface 12f side, and a central region located between the first side region and the second side region.

[0081] Similarly, as shown in Figure 4, the second spacer 54, when divided into three equal parts in the second direction z (width direction), has a first side region 54n1 located on the first side surface 12e side, a second side region 54n2 located on the second side surface 12f side, and a central region 54m located between the first side region 54n1 and the second side region 54n2.

[0082] Furthermore, although not shown in the figures, the first spacer 52 includes a first laminated central spacer region which is the region of the laminated body 12 that is on the first direction y (longitudinal direction) side of the first laminated body 12, closer to the center of the first direction y (longitudinal direction) than the first end of the first external electrode 30a in the first direction y (longitudinal direction) (so-called e-dimension end), and a first end face side spacer region which is the region closer to the first end face 12c than the first laminated central spacer region.

[0083] Similarly, as shown in Figure 6, the second spacer 54 has a second laminate central spacer region 54p, which is the region of the laminate 12 that is on the central side of the first direction y (longitudinal direction) of the laminate 12, more than the end of the second external electrode 30b in the first direction y (longitudinal direction) (so-called e-length end), and a second end face spacer region 54q, which is the region of the second end face 12d more than the second laminate central spacer region 54p.

[0084] Furthermore, the end face 52d of the first spacer 52 on the central side of the first laminate has an uneven surface shape, although this is not shown in the figure.

[0085] Similarly, the second spacer 54d on the central side of the second laminate has an uneven surface shape, as shown in Figures 6 and 7.

[0086] Furthermore, it is preferable that the degree of unevenness of the first spacer 52's central-side spacer end face 52d is greater than the degree of unevenness of the first spacer 52's external electrode-side spacer end face 52c.

[0087] Similarly, as shown in Figure 6, it is preferable that the degree of unevenness of the second spacer 54's central-side spacer end face 54d is greater than the degree of unevenness of the second spacer 54's external electrode-side spacer end face 54c.

[0088] This is because the Sn component contained in the external electrodes 30 of the multilayer ceramic capacitor 10 seeps into the vicinity of the first external electrode side spacer end face 52c and the second external electrode side spacer end face 54c during spacer sintering, thereby reducing the degree of unevenness (smoothing the surface).

[0089] The degree of unevenness is measured using the following method. The same method is used for both the first spacer 52 and the second spacer 54, but here we will explain the method for measuring the degree of unevenness of the second spacer 54d on the central side of the second laminate as an example.

[0090] As shown in Figure 7, on the surface of the second spacer 54 whose degree of unevenness is to be measured, in this case, on the end face 54d of the second laminated central spacer, a virtual line I is drawn connecting the ridge portion 54r, which is the intersection point between the end face 54d of the second laminated central spacer and the main surface 54a of the second spacer (the first surface of the second spacer), and the intersection point between the end face 54d of the second laminated central spacer and the main surface 54b of the second spacer (the second surface of the second spacer). The area of ​​the void formed between this virtual line I and the uneven surface of the end face 54d of the second laminated central spacer is measured. This void area is taken as the degree of unevenness of the end face 54d of the second laminated central spacer.

[0091] The first spacer 52 and the second spacer 54 contain metal powder. The metal powder includes, for example, at least one of Cu or Ni as a high-melting-point metal and Sn as a low-melting-point metal. This ensures that the multilayer ceramic electronic component 100 does not melt when soldered onto the substrate and does not deform due to heat, thus allowing the multilayer ceramic electronic component 100 to be mounted while maintaining the desired shape during soldering. Furthermore, the intermetallic compound is preferably an intermetallic compound produced by the reaction of Sn and a Cu-Ni alloy. The high-melting-point metal constituting the intermetallic compound may also include Ag. Because the first spacer 52 and the second spacer 54 contain at least one of Cu or Ni and Sn, metal bonding between the first spacer 52 and the second spacer 54 and the external electrodes 30a and 30b of the multilayer ceramic capacitor 10 is facilitated.

[0092] Furthermore, the first spacer 52 and the second spacer 54 contain a portion of the third spacer 56.

[0093] The first spacer 52, although not shown in the figure, has multiple voids inside. Some of these voids are permeated with components of the third spacer 56.

[0094] Similarly, the second spacer 54 has multiple voids VS inside, as shown in Figures 4 and 6. Some of these voids VS are permeated with components of the third spacer 56.

[0095] (Third Spacer) The third spacer 56 joins the first spacer 52 to the first main surface 12a of the laminate 12, and also joins the second spacer 54 to the first main surface 12a. The third spacer 56 covers a part of the laminate 12, a part of the first spacer 52, and a part of the second spacer 54. More specifically, in a view perpendicular to the mounting surface S, the third spacer 56 covers the first spacer 52. Similarly, in a view perpendicular to the mounting surface S, the third spacer 56 covers the second spacer 54. For example, the third spacer 56 covers the first laminate center-side spacer end face 52d of the first spacer 52, and covers the second laminate center-side spacer end face 54d of the second spacer 54.

[0096] Furthermore, as shown in Figures 6 and 7, the third spacer 56 is positioned (present) so as to fit between the first spacer 52 and the first main surface 12a of the laminate 12, and between the second spacer 54 and the first main surface 12a of the laminate 12. The thickness (length in the height direction x) of the third spacer 56 between the first spacer 52 and the second spacer 54 and the first main surface 12a of the laminate 12 is 1 μm or more and 10 μm or less.

[0097] This makes it possible to suppress delamination between the laminate 12 and the first spacer 52 and the second spacer 54. Furthermore, the flexibility of the third spacer 56 relieves the stress on the laminate 12 (especially the stress around the ends of the external electrodes), and suppresses the occurrence of cracks in the laminate 12 (especially cracks originating from the ends of the external electrodes).

[0098] Furthermore, the third spacer 56 continuously or discontinuously covers the surface of the laminate 12 (the first main surface 12a).

[0099] The third spacer 56 may cover the first spacer side surface 52e and the first spacer side surface 52f of the first spacer 52, and the second spacer side surface 54e and the second spacer side surface 54f of the second spacer 54. Alternatively, it may continuously cover the first spacer side surface 52e and the first spacer side surface 52f of the first spacer 52, and the second spacer side surface 54e and the second spacer side surface 54f of the second spacer 54, up to the first side surface 12e and the second side surface 12f of the multilayer ceramic capacitor 10.

[0100] Furthermore, a portion of the third spacer 56, which is positioned on the first laminate's central end face 52d of the first spacer 52, exists in a shape that conforms to the surface of the first laminate's central end face 52d, which has an uneven shape, although this portion is not shown in the figures.

[0101] Similarly, a portion of the third spacer 56, which is positioned on the second laminate's central end face 54d of the second spacer 54, exists in a shape that conforms to the surface of the second laminate's central end face 54d, which has an uneven shape, as shown in Figure 7.

[0102] As a result, a portion of the third spacer 56 has an uneven shape that is complementary to the central end face 52d of the first laminate and the central end face 54d of the second laminate. This creates an anchoring effect that strengthens the bond between the laminate 12 and the first spacer 52 and the second spacer 54, making it difficult for the first spacer 52 and the second spacer 54 to peel off from the laminate 12.

[0103] Figure 4 is a cross-sectional view taken along the line IV-IV in Figure 2. Specifically, it is an xz cross-sectional view taken 50 μm from the ridge portion 54r of the second spacer 54 toward the second external electrode side spacer end face 54c (the third surface of the second spacer) in the first direction y (longitudinal direction).

[0104] As shown in Figure 4, the amount of the third spacer 56 that has seeped into the second spacer 54 is greater in the central region 54m of the second spacer 54 than in the first side region 54n1 and the second side region 54n2. In other words, the content of the third spacer 56 in the central region 54m of the second spacer 54 is greater than the content of the third spacer 56 in the first side region 54n1 and the second side region 54n2.

[0105] Similarly, although not shown in the diagram, the amount of the third spacer 56 that has seeped into the first spacer 52 is greater in the central region of the first spacer 52 than in the first and second side regions. In other words, the content of the third spacer 56 in the central region of the first spacer 52 is greater than the content of the third spacer 56 in the first and second side regions.

[0106] This produces the following effects. Generally, the region of the laminate 12 corresponding to the central region has more opposing electrode portions 26a and 26b of the internal electrode 16 than the region of the laminate 12 corresponding to the side region. Therefore, the amplitude of vibrations generated during mounting tends to increase as you move towards the region of the laminate 12 corresponding to the central region, and squeaking and cracking are more likely to occur in the region of the laminate 12 corresponding to the central region. However, in the present invention, as described above, by including more third spacers 56 in the central region than in the side region, the third spacers 56 act as a cushion in the central region, and the amplitude of vibrations in the central region, where the amplitude of vibrations during mounting tends to increase, can be mitigated. Thus, a suppressive effect against cracks and squeaking caused by vibration can be obtained.

[0107] Specifically, the content of the third spacer 56 in the central region of the first spacer 52 and the central region 54m of the second spacer 54 (the area of ​​the third spacer 56 relative to the total area of ​​the central regions of the first and second spacers 52 and 54) is 4.9% or more and 9.6% or less.

[0108] The content of the third spacer 56 in the first and second side regions of the first spacer 52 and the first and second side regions 54n1 and 54n2 of the second spacer 54 (the area of ​​the third spacer 56 relative to the total area of ​​the side regions of the first and second spacers 52 and 54) is 1.9% or more and 7.9% or less.

[0109] In other words, (the content of the third spacer 56 in the central region) / (the content of the third spacer 56 in the first and second side regions) is between 0.6 and 5.1.

[0110] If the ratio is less than 0.6, the cushioning effect of the third spacer 56 becomes too small, resulting in a reduced crack reduction effect. If the ratio exceeds 5.1, the ratio of the third spacer 56 in the central region becomes relatively too large, resulting in less solder entering the first and second spacers 52 and 54 during mounting, and a higher fillet height formed by solder on the outside of the external electrode 30, thus reducing the noise reduction effect. When the ratio is between 0.6 and 5.1, the crack and noise reduction effects are more pronounced.

[0111] Figure 6 is a partially enlarged view of the cross-sectional view of the multilayer ceramic electronic component shown in Figure 5, enlarged around the second spacer, and is a partially enlarged view of the xy cross-section cut at the midpoint of the W dimension of the multilayer ceramic electronic component 100. As shown in Figure 6, in the second spacer 54, the amount of the third spacer 56 that has seeped into the second laminate central side spacer region 54p is greater than the amount of the third spacer 56 that has seeped into the second end face side spacer region 54q. That is, the content of the third spacer 56 in the second spacer 54 in the second laminate central side spacer region 54p is greater than the content of the third spacer 56 in the second end face side spacer region 54q.

[0112] Similarly, although not shown in the figures, in the first spacer 52, the amount of third spacer 56 that has seeped into the central spacer region of the first laminate is greater than the amount of third spacer 56 that has seeped into the first end-face spacer region. In other words, the content of third spacer 56 in the central spacer region of the first laminate of the first spacer 52 is greater than the content of third spacer 56 in the first end-face spacer region.

[0113] Specifically, the content of the third spacer 56 in the second spacer 54p on the central side of the second laminate (area of ​​the third spacer 56 relative to the total area of ​​the second spacer 54p on the central side of the second laminate) is 1% or more and 10% or less.

[0114] The content of the third spacer 56 in the second end face side spacer region 54q of the second spacer 54 (area of ​​the third spacer 56 relative to the total area of ​​the second end face side spacer region 54q) is 0% or more and 1% or less.

[0115] Similarly, the content of the third spacer 56 in the central spacer region of the first laminate of the first spacer 52 (area %) of the third spacer 56 relative to the total area of ​​the central spacer region of the first laminate is 1% or more and 10% or less.

[0116] The content of the third spacer 56 in the first end face side spacer region of the first spacer 52 (area %) of the third spacer 56 relative to the total area of ​​the first end face side spacer region is 0% or more and 1% or less.

[0117] This results in the following effects. In general, the bond between the laminate 12 and the first and second spacers 52 and 54, which are mainly composed of metal, is not good, and the laminate 12 and the first and second spacers 52 and 54 sometimes peel off. Because the third spacer 56 is included in the first and second spacers 52 and 54 (especially in large quantities in the central spacer region of the first laminate and the central spacer region 54p of the second laminate), the anchoring effect can suppress the peeling of the first and second spacers 52 and 54 from the laminate 12.

[0118] Furthermore, it is preferable that the hue of the multilayer ceramic electronic component 100 differs when viewed from the bottom (mounting surface S side) and when viewed from the top (non-mounting surface) side. The difference in hue makes it easier to select the orientation when mounting on the substrate, and reduces the amount of multilayer ceramic electronic component 100 mounted on a side other than the side that should be mounted.

[0119] The third spacer 56 contains a thermosetting resin (e.g., phenolic resin, epoxy resin, etc.) as its main component and a silane coupling agent (an organic compound containing Si) as its secondary component. The main component of the third spacer 56 may be a UV-curable resin, etc. By containing these main and secondary components, the third spacer 56 functions as a reinforcing resin that reinforces the first spacer 52 and the second spacer 54. The third spacer 56 may also contain, as an additive, a dyeing substance (a compound or metal complex that absorbs light in the visible light region) such as carbon black, phthalocyanine, hexaammine metal complex (luteo salt), or pentaammine metal complex (purpleo salt). By including a dyeing substance as an additive in the third spacer 56, the surface to which the third spacer 56 is coated is easily visible, which can reduce errors during the mounting of the multilayer ceramic electronic component 100.

[0120] For example, if the third spacer 56 contains a large amount of carbon, the hue of the third spacer can be made closer to black.

[0121] As described above, according to the multilayer ceramic electronic component 100 shown in Figure 1, etc., by setting the "content ratio of the third spacer: central region > first and second side regions," the third spacer 56 included in the central region acts as a cushion, and the amplitude of vibration can be mitigated in the central region, where the amplitude of vibration tends to be large during mounting. Therefore, a suppression effect against cracks and noises caused by vibration can be obtained.

[0122] (Modified Version) The multilayer ceramic electronic component 100 may be configured as follows: That is, as shown in Figure 9, the "content of the third spacer: central region > first and second side region", and a fillet formed by the third spacer 56 may be formed at the outer ends in the second direction z (width direction) of the first and second spacer main surfaces 52a and 54a of the first and second spacers 52 and 54. In other words, a fillet formed by the third spacer 56 may be formed so as to connect the first and second spacer side surfaces 52e, 52f, 54e, and 54f of the first and second spacers 52 and 54 with the first main surface 12a of the laminate 12.

[0123] This strengthens the bond between the first and second spacers 52 and 54 and the laminate 12, making it less likely for the first and second spacers 52 and 54 to come apart from the laminate 12.

[0124] 2. Manufacturing Method of Multilayer Ceramic Electronic Components Next, we will explain the manufacturing method of multilayer ceramic electronic components.

[0125] First, prepare the dielectric sheet and the conductive paste for the internal electrodes. The dielectric sheet and the conductive paste for the internal electrodes contain a binder and a solvent. Known binders and solvents can be used.

[0126] Next, a dielectric sheet without an internal electrode pattern printed on it, and a dielectric sheet with a first internal electrode pattern printed on it and a dielectric sheet with a second internal electrode pattern printed on it are prepared, by printing a conductive paste for internal electrodes in a predetermined pattern on the dielectric sheet, for example, by screen printing or gravure printing.

[0127] Next, a predetermined number of dielectric sheets without printed internal electrode patterns are stacked, and then dielectric sheets with printed first and second internal electrode patterns are sequentially stacked on top of them to form the inner layer portion 18. Furthermore, a predetermined number of dielectric sheets without printed internal electrode patterns are stacked on top of the inner layer portion 18 to produce a laminated sheet.

[0128] Next, the laminated sheets are pressed in the lamination direction using means such as a hydrostatic press to produce a laminated block.

[0129] Next, the laminated block is cut to a predetermined size, and the laminated chips are cut out. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0130] Next, the laminated chips are fired to produce the laminated body 12. The firing temperature depends on the materials of the ceramic layer 14 and the internal electrodes 16, but it is preferably between 900°C and 1400°C.

[0131] Next, a conductive paste that will become the base electrode layer 32 is applied to the first end face 12c and the second end face 12d of the laminate 12 to form the base electrode layer 32. In this embodiment, a baked layer was formed as the base electrode layer 32. When forming the baked layer, a conductive paste containing glass components and metal is applied by a method such as dipping, and then a baking treatment is performed to form the base electrode layer 32. The temperature of the baking treatment at this time is preferably 700°C or higher and 900°C or lower.

[0132] Furthermore, when the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may also be formed on the surface of the baking layer, or the conductive resin layer may be formed directly on the laminate 12 by itself without forming a baking layer.

[0133] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto the baking layer or the laminate 12, and performing heat treatment at a temperature of 250°C to 550°C to heat-cur the thermosetting resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent scattering of the thermosetting resin and oxidation of the various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0134] Furthermore, when the base electrode layer 32 is formed as a thin film layer, the base electrode layer 32 can be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer shall be a layer of 1 μm or less in thickness in which metal particles are deposited.

[0135] Furthermore, a plating layer 34 may be provided on the exposed portion of the internal electrode 16 of the laminate 12 without providing the underlay electrode layer 32. In that case, it can be formed by the following method.

[0136] The first end face 12c and the second end face 12d of the laminate 12 are plated to form a base plated electrode on the exposed portion of the internal electrode 16. While either electrolytic plating or electroless plating may be used for the plating process, electroless plating requires pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is generally preferred. Barrel plating is preferred as the plating method. Additionally, if necessary, the upper plated electrode formed on the surface of the lower plated electrode may be formed similarly.

[0137] Subsequently, a plating layer 34 is formed on the surface of the base electrode layer 32, the surface of the conductive resin layer, or the surface of the lower plated electrode, or the surface of the upper plated electrode. In this embodiment, a Ni plating layer and an Sn plating layer were formed on the baked layer. The Ni plating layer and the Sn plating layer were formed sequentially, for example, by a barrel plating method.

[0138] In this way, the multilayer ceramic capacitor 10 is manufactured.

[0139] Next, a method for arranging the first spacer 52 and the second spacer 54 on the multilayer ceramic capacitor 10 will be described.

[0140] A first spacer manufacturing paste for manufacturing the first spacer 52 and a second spacer manufacturing paste for manufacturing the second spacer 54 are prepared. The first and second spacer manufacturing pastes contain, for example, high-melting-point metals such as Cu, Ni, Sn, and Ag, and low-melting-point metals.

[0141] (Application process of the first and second spacers) Next, the first spacer manufacturing paste and the second spacer manufacturing paste are placed on a holding substrate (e.g., an alumina plate) by screen printing or dispensing. Next, the multilayer ceramic capacitor 10 is placed on the upper surface of the spacer manufacturing paste in a position facing the holding substrate. At this time, the first external electrode 30a and the first spacer manufacturing paste, and the second external electrode 30b and the second spacer manufacturing paste are aligned, and the first spacer manufacturing paste and the second spacer manufacturing paste are attached to the multilayer ceramic capacitor 10.

[0142] Furthermore, the first spacer 52 and the second spacer 54 can also be placed on the multilayer ceramic capacitor 10 by the following method: The multilayer ceramic capacitor 10 is placed on a holding substrate (for example, an alumina plate) using an adhesive. The respective spacer manufacturing pastes are placed on the external electrodes 30 of the multilayer ceramic capacitor 10 placed on the holding substrate by screen printing or dispensing. The first external electrode 30a and the first spacer manufacturing paste, and the second external electrode 30b and the second spacer manufacturing paste are aligned, and the first spacer manufacturing paste and the second spacer manufacturing paste are attached to the multilayer ceramic capacitor 10.

[0143] In the spacer placement process described above, the first spacer 52 and the second spacer 54 can be formed in a desired shape and arrangement by changing the amount of paste or modifying the design of the mask.

[0144] (Baking process for the first and second spacers) The preheating temperature is set to a target temperature of 160°C to 220°C, and the temperature inside the furnace is gradually increased. Then, the metal reaction temperature is set to 250°C to 290°C to promote the metal reaction of the first and second spacers 52 and 54.

[0145] By setting the preheating temperature to a relatively high temperature of 160°C to 220°C, the surface irregularities of the first and second spacers 52 and 54 are realized, and in the subsequent coating process of the third spacer 56, the first and second spacers 52 and 54 become spacer shapes that easily accommodate the third spacer 56.

[0146] Next, a method for placing the third spacer 56 on the multilayer ceramic capacitor 10 will be described.

[0147] The surface of the multilayer ceramic capacitor 10 on which the first spacer 52 and the second spacer 54 are placed is cleaned with a solvent. After cleaning is complete, the multilayer ceramic capacitor 10 on which the first spacer 52 and the second spacer 54 are placed is aligned so that the first spacer 52 and the second spacer 54 are facing upwards.

[0148] Next, a paste for manufacturing the third spacer, to be used in the manufacture of the third spacer 56, is prepared.

[0149] (Application process for the third spacer) Next, the paste for manufacturing the third spacer is uniformly applied to the first main surface 12a of the laminate 12 between the first spacer 52 and the second spacer 54, using a dispenser or squeegee printing on the multilayer ceramic capacitor 10 on which the first spacer 52 and the second spacer 54 are arranged. The paste for manufacturing the third spacer is then permeated into the first spacer 52 and the second spacer 54. One method of permeation is to suction the multilayer ceramic capacitor 10 placed in a container (so-called vacuum drawing) (first application of the third spacer). After that, the paste for manufacturing the third spacer is hardened by heat.

[0150] Next, covers (dummy covers) are placed over the areas connecting the first side region of the first spacer 52 and the first side region 54n1 of the second spacer 54, and the areas connecting the second side region of the first spacer 52 and the second side region 54n2 of the second spacer 54. The third spacer manufacturing paste is then applied to the area connecting the central regions of the first spacer 52 and the second spacer 54. After that, the third spacer manufacturing paste is soaked into the first spacer 52 and the second spacer 54 in the same manner as the first application of the third spacer, and the third spacer manufacturing paste is hardened by heat (second application of the third spacer).

[0151] The multilayer ceramic electronic component 100 of this embodiment is manufactured through the above process.

[0152] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto.

[0153] In other words, various modifications can be made to the embodiments described above with respect to the mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and objectives of the present invention, and these modifications are included in the present invention.

[0154] <1> A laminate comprising a plurality of stacked ceramic layers, the laminate comprising: a first main surface and a second main surface facing each other in the height direction; a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction; a first end surface and a second end surface facing each other in the longitudinal direction perpendicular to the height direction and the width direction; a first internal electrode alternately stacked with the plurality of ceramic layers and exposed on the first end surface; a second internal electrode alternately stacked with the plurality of ceramic layers and exposed on the second end surface; a first external electrode arranged from the first end surface across the first main surface and the second main surface; and a second external electrode arranged from the second end surface across the first main surface and the second main surface, wherein the laminate comprises: a first spacer joined to the first external electrode; and a second spacer joined to the second external electrode. A multilayer ceramic electronic component comprising: a third spacer that joins the first spacer and the first main surface, and joins the second spacer and the first main surface, wherein the third spacer is contained within the first spacer and the second spacer, and the first spacer and the second spacer have: a first side region disposed on the first side side, a second side region disposed on the second side side, and a central region disposed between the first side region and the second side region, wherein the content of the third spacer in the central region is greater than the content of the third spacer in the first side region and the second side region.

[0155] <2> The multilayer ceramic electronic component according to <1>, wherein the third spacer is also present between the first spacer and the first main surface, and the third spacer is also present between the second spacer and the first main surface.

[0156] <3> The first spacer has two first spacer main surfaces facing each other in the height direction, two first spacer side surfaces facing each other in the width direction, a first laminated central side spacer end surface facing each other in the longitudinal direction and being on the longitudinal center side of the laminate, and a first external electrode side spacer end surface facing the first laminated central side spacer end surface in the longitudinal direction, and the second spacer has two second spacer main surfaces facing each other in the height direction, two second spacer side surfaces facing each other in the width direction, a second laminated central side spacer end surface facing each other in the longitudinal direction and being on the longitudinal center side of the laminate, and a second external electrode side spacer end surface facing the second laminated central side spacer end surface in the longitudinal direction, and the first laminated central side spacer end surface and the second laminated central side spacer end surface have an uneven surface shape, The multilayer ceramic electronic component according to <1> or <2>, wherein the third spacer is shaped to conform to the surface of the central end face of the first laminate, and the third spacer is shaped to conform to the surface of the central end face of the second laminate.

[0157] <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein the ratio of the area of ​​the third spacer in the central region to the area of ​​the third spacer in the first side region is 0.6 or more and 5.1 or less, and the ratio of the area of ​​the third spacer in the central region to the area of ​​the third spacer in the second side region is 0.6 or more and 5.1 or less.

[0158] <5> The multilayer ceramic electronic component according to any one of <1> to <4>, wherein the first spacer comprises a first laminated central spacer region which is a region on the longitudinal center side of the laminated body than the longitudinal end of the first external electrode, and a first end face spacer region which is a region on the first end face side of the first laminated central spacer region, and the second spacer comprises a second laminated central spacer region which is a region on the longitudinal center side of the laminated body than the longitudinal end of the second external electrode, and a second end face spacer region which is a region on the second end face side of the second laminated central spacer region, and the content of the third spacer in the first laminated central spacer region is greater than the content of the third spacer in the first end face spacer region, and the content of the third spacer in the second laminated central spacer region is greater than the content of the third spacer in the second end face spacer region.

[0159] 100 Multilayer ceramic electronic component 10 Multilayer ceramic capacitor 12 Laminate 12a First main surface 12b Second main surface 12c First end surface 12d Second end surface 12e First side surface 12f Second side surface 14 Ceramic layer 16 Internal electrode 16a First internal electrode 16b Second internal electrode 18 Inner layer 20a First outer layer 20b Second outer layer 26 Opposing electrode 26a First opposing electrode 26b Second opposing electrode 28 Lead-out electrode 28a First lead-out electrode 28b Second lead-out electrode 30 External electrode 30a First external electrode 30b Second external electrode 32 Underlay electrode layer 32a First underlay electrode layer 32b Second underlay electrode layer 34 Plating layer 34a 34b First plating layer Second plating layer 50 Spacer 52 First spacer 52a Main surface of the first spacer (first surface of the first spacer) 52b Main surface of the first spacer (second surface of the first spacer) 52c End surface of the first external electrode side spacer (third surface of the first spacer) 52d End surface of the first laminate center side spacer (fourth surface of the first spacer) 52e Side surface of the first spacer (fifth surface of the first spacer) 52f Side surface of the first spacer (sixth surface of the first spacer) 52r ​​Edge of the first spacer 54 Second spacer 54a Main surface of the second spacer (first surface of the second spacer) 54b Main surface of the second spacer (second surface of the second spacer) 54c End surface of the second external electrode side spacer (third surface of the second spacer) 54d 54e End face of the second spacer on the central side of the second laminate (fourth face of the second spacer) 54f Side face of the second spacer (sixth face of the second spacer) 54m Central region of the second spacer 54n1 First side region of the second spacer 54n2 Second side region of the second spacer 54p Spacer region on the central side of the second spacer on the laminate 54q End face spacer region of the second spacer 54r Edge portion of the second spacer 56 Third spacer 60 Mounting substrate 62 Solder 64a Land electrode 64b Land electrode x Height direction (lamination direction) y First direction (longitudinal direction)z Second direction (width direction) I Imaginary line connecting the edge of the second spacer and the intersection point between the central end face of the second laminate and the main surface of the second spacer (the second surface of the second spacer) T Height dimension of the multilayer ceramic capacitor W Second dimension of the multilayer ceramic capacitor L First dimension of the multilayer ceramic capacitor T s The height dimension T of the first spacer and the second spacer. l Dimensions of the first and second spacers in the first direction: S - mounting surface, VS - gap

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of stacked ceramic layers, a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, a first end surface and a second end surface facing each other in the longitudinal direction perpendicular to the height direction and the width direction, a first internal electrode alternately stacked with the plurality of ceramic layers and exposed on the first end surface, a second internal electrode alternately stacked with the plurality of ceramic layers and exposed on the second end surface, a first external electrode arranged from the first end surface across the first main surface and the second main surface, and a second external electrode arranged from the second end surface across the first main surface and the second main surface, wherein a first spacer is bonded to the first external electrode, and a second spacer is bonded to the second external electrode, A multilayer ceramic electronic component comprising: a third spacer that joins the first spacer and the first main surface, and joins the second spacer and the first main surface, wherein the third spacer is contained within the first spacer and the second spacer, and the first spacer and the second spacer have: a first side region disposed on the first side side, a second side region disposed on the second side side, and a central region disposed between the first side region and the second side region, wherein the content of the third spacer in the central region is greater than the content of the third spacer in the first side region and the second side region.

2. The multilayer ceramic electronic component according to claim 1, wherein the third spacer is also present between the first spacer and the first main surface, and the third spacer is also present between the second spacer and the first main surface.

3. The first spacer has two first spacer main surfaces facing each other in the height direction, two first spacer side surfaces facing each other in the width direction, a first laminated central side spacer end surface facing each other in the longitudinal direction and being on the longitudinal center side of the laminate, and a first external electrode side spacer end surface facing the first laminated central side spacer end surface in the longitudinal direction, and the second spacer has two second spacer main surfaces facing each other in the height direction, two second spacer side surfaces facing each other in the width direction, a second laminated central side spacer end surface facing each other in the longitudinal direction and being on the longitudinal center side of the laminate, and a second external electrode side spacer end surface facing the second laminated central side spacer end surface in the longitudinal direction, and the first laminated central side spacer end surface and the second laminated central side spacer end surface have an uneven surface shape. The multilayer ceramic electronic component according to claim 1 or claim 2, wherein the third spacer is shaped to conform to the surface of the central end face of the first laminate, and the third spacer is shaped to conform to the surface of the central end face of the second laminate.

4. The ratio of the area of ​​the third spacer in the central region to the area of ​​the third spacer in the first side region is 0.6 or more and 5.1 or less, and the ratio of the area of ​​the third spacer in the central region to the area of ​​the third spacer in the second side region is 0.6 or more and 5.1 or less, according to any one of claims 1 to 3.

5. The multilayer ceramic electronic component according to any one of claims 1 to 4, wherein the first spacer comprises a first central spacer region of the laminate which is a region on the longitudinal center side of the laminate which is a region on the longitudinal center side of the laminate which is a region on the first end face side of the first central spacer region of the laminate, and the second spacer comprises a second central spacer region of the laminate which is a region on the longitudinal center side of the laminate which is a region on the longitudinal center side of the laminate which is a region on the second end face side of the second central spacer region of the laminate, and the content of the third spacer in the first central spacer region is greater than the content of the third spacer in the first end face spacer region, and the content of the third spacer in the second central spacer region is greater than the content of the third spacer in the second end face spacer region.

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